[PATCH v2 0/4] irqchip: lpc32xx: add LPC32xx irqchip driver

[PATCH v2 0/4] irqchip: lpc32xx: add LPC32xx irqchip driver

[Vladimir Zapolskiy]

The change replaces legacy NXP LPC32xx irqchip driver with a new one.

Legacy LPC32xx interrupt controller driver was broken since commit
76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which
requires a private interrupt handler, otherwise any fired SIC1 generated
interrupt (mapped to MIC hwirq 0) breaks the kernel with the message
"unexpected IRQ trap at vector 00".

Summary of changes from v1 to v2:
* 2 of 10 from v1 changes are found in v4.6 and thus skipped from this
  series,
* removed all changes related to optional property 'wakeup-source',
  which will be needed later on to support interrupts as wakeup sources,
* removed introduced optional property 'interrupt-controller-name',
* moved DTS changes after new driver, new driver alone used with
  old DTS allows to boot LPC32xx boards,
* added a change which actually removes legacy driver,
* improvements in the driver based on a review findings from Marc.
* minor improvements all over the code.

v1 of the changeset can be found here:

   http://www.spinics.net/lists/devicetree/msg103231.html

Vladimir Zapolskiy (4):
  dt-bindings: interrupt-controllers: add description of SIC1 and SIC2
  irqchip: add LPC32xx interrupt controller driver
  arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC
  ARM: lpc32xx: remove legacy irq controller driver

 .../interrupt-controller/nxp,lpc3220-mic.txt       |  70 +--
 arch/arm/Kconfig                                   |   2 +
 arch/arm/boot/dts/lpc32xx.dtsi                     |  58 ++-
 arch/arm/mach-lpc32xx/Makefile                     |   2 +-
 arch/arm/mach-lpc32xx/irq.c                        | 477 ---------------------
 arch/arm/mach-lpc32xx/phy3250.c                    |   1 -
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-lpc32xx.c                      | 238 ++++++++++
 8 files changed, 329 insertions(+), 520 deletions(-)
 delete mode 100644 arch/arm/mach-lpc32xx/irq.c
 create mode 100644 drivers/irqchip/irq-lpc32xx.c

-- 
2.1.4

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2 0/4] irqchip: lpc32xx: add LPC32xx irqchip driver

[Vladimir Zapolskiy]

The change replaces legacy NXP LPC32xx irqchip driver with a new one.

Legacy LPC32xx interrupt controller driver was broken since commit
76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which
requires a private interrupt handler, otherwise any fired SIC1 generated
interrupt (mapped to MIC hwirq 0) breaks the kernel with the message
"unexpected IRQ trap at vector 00".

Summary of changes from v1 to v2:
* 2 of 10 from v1 changes are found in v4.6 and thus skipped from this
  series,
* removed all changes related to optional property 'wakeup-source',
  which will be needed later on to support interrupts as wakeup sources,
* removed introduced optional property 'interrupt-controller-name',
* moved DTS changes after new driver, new driver alone used with
  old DTS allows to boot LPC32xx boards,
* added a change which actually removes legacy driver,
* improvements in the driver based on a review findings from Marc.
* minor improvements all over the code.

v1 of the changeset can be found here:

   http://www.spinics.net/lists/devicetree/msg103231.html

Vladimir Zapolskiy (4):
  dt-bindings: interrupt-controllers: add description of SIC1 and SIC2
  irqchip: add LPC32xx interrupt controller driver
  arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC
  ARM: lpc32xx: remove legacy irq controller driver

 .../interrupt-controller/nxp,lpc3220-mic.txt       |  70 +--
 arch/arm/Kconfig                                   |   2 +
 arch/arm/boot/dts/lpc32xx.dtsi                     |  58 ++-
 arch/arm/mach-lpc32xx/Makefile                     |   2 +-
 arch/arm/mach-lpc32xx/irq.c                        | 477 ---------------------
 arch/arm/mach-lpc32xx/phy3250.c                    |   1 -
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-lpc32xx.c                      | 238 ++++++++++
 8 files changed, 329 insertions(+), 520 deletions(-)
 delete mode 100644 arch/arm/mach-lpc32xx/irq.c
 create mode 100644 drivers/irqchip/irq-lpc32xx.c

-- 
2.1.4

[PATCH v2 1/4] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

[Vladimir Zapolskiy]

NXP LPC32xx has three interrupt controllers, namely root Main
Interrupt Controller (MIC) and two supplementary Sub Interrupt
Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
are connected to MIC.

Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
---
Changes from v1 to v2:
* removed introduced optional "interrupt-controller-name" property,
  for users the name of a controller will be constructed from mic/sic
  and controller physical address,
* removed introduced optional "wakeup-sources" property, a list of
  mappings between a hardware interrupt and its correspondent wakeup source
  to exit CPU STOP mode will be discussed later on,
* other negligible changes (rewording, small letters in unit address etc.)

 .../interrupt-controller/nxp,lpc3220-mic.txt       | 70 ++++++++++++++--------
 1 file changed, 46 insertions(+), 24 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
index 539adca..38211f3 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
@@ -1,38 +1,60 @@
-* NXP LPC32xx Main Interrupt Controller
-  (MIC, including SIC1 and SIC2 secondary controllers)
+* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
 
 Required properties:
-- compatible: Should be "nxp,lpc3220-mic"
-- interrupt-controller: Identifies the node as an interrupt controller.
-- interrupt-parent: Empty for the interrupt controller itself
-- #interrupt-cells: The number of cells to define the interrupts. Should be 2.
-  The first cell is the IRQ number
-  The second cell is used to specify mode:
-      1 = low-to-high edge triggered
-      2 = high-to-low edge triggered
-      4 = active high level-sensitive
-      8 = active low level-sensitive
-      Default for internal sources should be set to 4 (active high).
-- reg: Should contain MIC registers location and length
+- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
+- reg: should contain IC registers location and length.
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: the number of cells to define an interrupt, should be 2.
+  The first cell is the IRQ number, the second cell is used to specify
+  one of the supported IRQ types:
+      IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
+      IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
+      IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
+      IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
+  Reset value is IRQ_TYPE_LEVEL_LOW.
+
+Optional properties:
+- interrupt-parent: empty for MIC interrupt controller, link to parent
+  MIC interrupt controller for SIC1 and SIC2
+- interrupts: empty for MIC interrupt controller, cascaded MIC
+  hardware interrupts for SIC1 and SIC2
 
 Examples:
-	/*
-	 * MIC
-	 */
+
+	/* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */
 	mic: interrupt-controller@40008000 {
 		compatible = "nxp,lpc3220-mic";
+		reg = <0x40008000 0x4000>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	sic1: interrupt-controller@4000c000 {
+		compatible = "nxp,lpc3220-sic";
+		reg = <0x4000c000 0x4000>;
 		interrupt-controller;
-		interrupt-parent;
 		#interrupt-cells = <2>;
-		reg = <0x40008000 0xC000>;
+
+		interrupt-parent = <&mic>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+			     <30 IRQ_TYPE_LEVEL_LOW>;
 	};
 
-	/*
-	 * ADC
-	 */
+	sic2: interrupt-controller@40010000 {
+		compatible = "nxp,lpc3220-sic";
+		reg = <0x40010000 0x4000>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupt-parent = <&mic>;
+		interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+			     <31 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	/* ADC */
 	adc@40048000 {
 		compatible = "nxp,lpc3220-adc";
 		reg = <0x40048000 0x1000>;
-		interrupt-parent = <&mic>;
-		interrupts = <39 4>;
+		interrupt-parent = <&sic1>;
+		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 	};
-- 
2.1.4

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2 1/4] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

[Vladimir Zapolskiy]

NXP LPC32xx has three interrupt controllers, namely root Main
Interrupt Controller (MIC) and two supplementary Sub Interrupt
Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
are connected to MIC.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
Changes from v1 to v2:
* removed introduced optional "interrupt-controller-name" property,
  for users the name of a controller will be constructed from mic/sic
  and controller physical address,
* removed introduced optional "wakeup-sources" property, a list of
  mappings between a hardware interrupt and its correspondent wakeup source
  to exit CPU STOP mode will be discussed later on,
* other negligible changes (rewording, small letters in unit address etc.)

 .../interrupt-controller/nxp,lpc3220-mic.txt       | 70 ++++++++++++++--------
 1 file changed, 46 insertions(+), 24 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
index 539adca..38211f3 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
@@ -1,38 +1,60 @@
-* NXP LPC32xx Main Interrupt Controller
-  (MIC, including SIC1 and SIC2 secondary controllers)
+* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
 
 Required properties:
-- compatible: Should be "nxp,lpc3220-mic"
-- interrupt-controller: Identifies the node as an interrupt controller.
-- interrupt-parent: Empty for the interrupt controller itself
-- #interrupt-cells: The number of cells to define the interrupts. Should be 2.
-  The first cell is the IRQ number
-  The second cell is used to specify mode:
-      1 = low-to-high edge triggered
-      2 = high-to-low edge triggered
-      4 = active high level-sensitive
-      8 = active low level-sensitive
-      Default for internal sources should be set to 4 (active high).
-- reg: Should contain MIC registers location and length
+- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
+- reg: should contain IC registers location and length.
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: the number of cells to define an interrupt, should be 2.
+  The first cell is the IRQ number, the second cell is used to specify
+  one of the supported IRQ types:
+      IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
+      IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
+      IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
+      IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
+  Reset value is IRQ_TYPE_LEVEL_LOW.
+
+Optional properties:
+- interrupt-parent: empty for MIC interrupt controller, link to parent
+  MIC interrupt controller for SIC1 and SIC2
+- interrupts: empty for MIC interrupt controller, cascaded MIC
+  hardware interrupts for SIC1 and SIC2
 
 Examples:
-	/*
-	 * MIC
-	 */
+
+	/* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */
 	mic: interrupt-controller at 40008000 {
 		compatible = "nxp,lpc3220-mic";
+		reg = <0x40008000 0x4000>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	sic1: interrupt-controller at 4000c000 {
+		compatible = "nxp,lpc3220-sic";
+		reg = <0x4000c000 0x4000>;
 		interrupt-controller;
-		interrupt-parent;
 		#interrupt-cells = <2>;
-		reg = <0x40008000 0xC000>;
+
+		interrupt-parent = <&mic>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+			     <30 IRQ_TYPE_LEVEL_LOW>;
 	};
 
-	/*
-	 * ADC
-	 */
+	sic2: interrupt-controller at 40010000 {
+		compatible = "nxp,lpc3220-sic";
+		reg = <0x40010000 0x4000>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupt-parent = <&mic>;
+		interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+			     <31 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	/* ADC */
 	adc at 40048000 {
 		compatible = "nxp,lpc3220-adc";
 		reg = <0x40048000 0x1000>;
-		interrupt-parent = <&mic>;
-		interrupts = <39 4>;
+		interrupt-parent = <&sic1>;
+		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 	};
-- 
2.1.4

Re: [PATCH v2 1/4] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

[Rob Herring]

On Mon, Apr 25, 2016 at 04:00:23AM +0300, Vladimir Zapolskiy wrote:
> NXP LPC32xx has three interrupt controllers, namely root Main
> Interrupt Controller (MIC) and two supplementary Sub Interrupt
> Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
> are connected to MIC.
> 
> Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
> ---
> Changes from v1 to v2:
> * removed introduced optional "interrupt-controller-name" property,
>   for users the name of a controller will be constructed from mic/sic
>   and controller physical address,
> * removed introduced optional "wakeup-sources" property, a list of
>   mappings between a hardware interrupt and its correspondent wakeup source
>   to exit CPU STOP mode will be discussed later on,
> * other negligible changes (rewording, small letters in unit address etc.)
> 
>  .../interrupt-controller/nxp,lpc3220-mic.txt       | 70 ++++++++++++++--------
>  1 file changed, 46 insertions(+), 24 deletions(-)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2 1/4] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

[Rob Herring]

On Mon, Apr 25, 2016 at 04:00:23AM +0300, Vladimir Zapolskiy wrote:
> NXP LPC32xx has three interrupt controllers, namely root Main
> Interrupt Controller (MIC) and two supplementary Sub Interrupt
> Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
> are connected to MIC.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> ---
> Changes from v1 to v2:
> * removed introduced optional "interrupt-controller-name" property,
>   for users the name of a controller will be constructed from mic/sic
>   and controller physical address,
> * removed introduced optional "wakeup-sources" property, a list of
>   mappings between a hardware interrupt and its correspondent wakeup source
>   to exit CPU STOP mode will be discussed later on,
> * other negligible changes (rewording, small letters in unit address etc.)
> 
>  .../interrupt-controller/nxp,lpc3220-mic.txt       | 70 ++++++++++++++--------
>  1 file changed, 46 insertions(+), 24 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 1/4] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

[Sylvain Lemieux]

On Mon, 2016-04-25 at 09:51 -0500, Rob Herring wrote:
> On Mon, Apr 25, 2016 at 04:00:23AM +0300, Vladimir Zapolskiy wrote:
> > NXP LPC32xx has three interrupt controllers, namely root Main
> > Interrupt Controller (MIC) and two supplementary Sub Interrupt
> > Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
> > are connected to MIC.
> > 
> > Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
> > ---
> > Changes from v1 to v2:
> > * removed introduced optional "interrupt-controller-name" property,
> >   for users the name of a controller will be constructed from mic/sic
> >   and controller physical address,
> > * removed introduced optional "wakeup-sources" property, a list of
> >   mappings between a hardware interrupt and its correspondent wakeup source
> >   to exit CPU STOP mode will be discussed later on,
> > * other negligible changes (rewording, small letters in unit address etc.)
> > 
> >  .../interrupt-controller/nxp,lpc3220-mic.txt       | 70 ++++++++++++++--------
> >  1 file changed, 46 insertions(+), 24 deletions(-)
> 
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

Acked-by: Sylvain Lemieux <slemieux.tyco-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2 1/4] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2

[Sylvain Lemieux]

On Mon, 2016-04-25 at 09:51 -0500, Rob Herring wrote:
> On Mon, Apr 25, 2016 at 04:00:23AM +0300, Vladimir Zapolskiy wrote:
> > NXP LPC32xx has three interrupt controllers, namely root Main
> > Interrupt Controller (MIC) and two supplementary Sub Interrupt
> > Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2
> > are connected to MIC.
> > 
> > Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> > ---
> > Changes from v1 to v2:
> > * removed introduced optional "interrupt-controller-name" property,
> >   for users the name of a controller will be constructed from mic/sic
> >   and controller physical address,
> > * removed introduced optional "wakeup-sources" property, a list of
> >   mappings between a hardware interrupt and its correspondent wakeup source
> >   to exit CPU STOP mode will be discussed later on,
> > * other negligible changes (rewording, small letters in unit address etc.)
> > 
> >  .../interrupt-controller/nxp,lpc3220-mic.txt       | 70 ++++++++++++++--------
> >  1 file changed, 46 insertions(+), 24 deletions(-)
> 
> Acked-by: Rob Herring <robh@kernel.org>

Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>

> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Vladimir Zapolskiy]

The change adds separate device nodes for SIC1 and SIC2 interrupt
controllers and reparents all defined SIC1 and SIC2 interrupt
producers to the correspondent interrupt controller, this is needed to
perform switching to a new LPC32xx MIC/SIC interrupt controller driver.

Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
---
Changes from v1 to v2:
* squashed two step change in lpc32xx.dtsi - new irqchip driver can be
  used (i.e. board boots with access to userspace) with old DTS file,
  so there is no need to fix DTS firstly and then switch to a new driver,
* removed "interrupt-controller-name" and "wakeup-sources" properties
  from all interrupt controllers,
* removed outdated comment.

 arch/arm/boot/dts/lpc32xx.dtsi | 58 +++++++++++++++++++++++++++++-------------
 1 file changed, 41 insertions(+), 17 deletions(-)

diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 73c4746..4570ddc 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -92,7 +92,8 @@
 			ohci: ohci@0 {
 				compatible = "nxp,ohci-nxp", "usb-ohci";
 				reg = <0x0 0x300>;
-				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
 				status = "disabled";
 			};
@@ -100,10 +101,11 @@
 			usbd: usbd@0 {
 				compatible = "nxp,lpc3220-udc";
 				reg = <0x0 0x300>;
-				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>,
-					     <62 IRQ_TYPE_LEVEL_HIGH>,
-					     <60 IRQ_TYPE_LEVEL_HIGH>,
-					     <58 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
+					     <30 IRQ_TYPE_LEVEL_HIGH>,
+					     <28 IRQ_TYPE_LEVEL_HIGH>,
+					     <26 IRQ_TYPE_LEVEL_LOW>;
 				clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
 				status = "disabled";
 			};
@@ -111,7 +113,8 @@
 			i2cusb: i2c@300 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x300 0x100>;
-				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -263,7 +266,8 @@
 			i2c1: i2c@400A0000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A0000 0x100>;
-				interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;
@@ -273,7 +277,8 @@
 			i2c2: i2c@400A8000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A8000 0x100>;
-				interrupts = <50 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;
@@ -314,12 +319,6 @@
 				};
 			};
 
-			/*
-			 * MIC Interrupt controller includes:
-			 *   MIC @40008000
-			 *   SIC1 @4000C000
-			 *   SIC2 @40010000
-			 */
 			mic: interrupt-controller@40008000 {
 				compatible = "nxp,lpc3220-mic";
 				interrupt-controller;
@@ -327,6 +326,28 @@
 				#interrupt-cells = <2>;
 			};
 
+			sic1: interrupt-controller@4000c000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x4000c000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+					     <30 IRQ_TYPE_LEVEL_LOW>;
+				};
+
+			sic2: interrupt-controller@40010000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x40010000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+					     <31 IRQ_TYPE_LEVEL_LOW>;
+			};
+
 			uart1: serial@40014000 {
 				compatible = "nxp,lpc3220-hsuart";
 				reg = <0x40014000 0x1000>;
@@ -351,7 +372,8 @@
 			rtc: rtc@40024000 {
 				compatible = "nxp,lpc3220-rtc";
 				reg = <0x40024000 0x1000>;
-				interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_RTC>;
 			};
 
@@ -404,7 +426,8 @@
 			adc: adc@40048000 {
 				compatible = "nxp,lpc3220-adc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};
@@ -412,7 +435,8 @@
 			tsc: tsc@40048000 {
 				compatible = "nxp,lpc3220-tsc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};
-- 
2.1.4

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Vladimir Zapolskiy]

The change adds separate device nodes for SIC1 and SIC2 interrupt
controllers and reparents all defined SIC1 and SIC2 interrupt
producers to the correspondent interrupt controller, this is needed to
perform switching to a new LPC32xx MIC/SIC interrupt controller driver.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
Changes from v1 to v2:
* squashed two step change in lpc32xx.dtsi - new irqchip driver can be
  used (i.e. board boots with access to userspace) with old DTS file,
  so there is no need to fix DTS firstly and then switch to a new driver,
* removed "interrupt-controller-name" and "wakeup-sources" properties
  from all interrupt controllers,
* removed outdated comment.

 arch/arm/boot/dts/lpc32xx.dtsi | 58 +++++++++++++++++++++++++++++-------------
 1 file changed, 41 insertions(+), 17 deletions(-)

diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 73c4746..4570ddc 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -92,7 +92,8 @@
 			ohci: ohci at 0 {
 				compatible = "nxp,ohci-nxp", "usb-ohci";
 				reg = <0x0 0x300>;
-				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
 				status = "disabled";
 			};
@@ -100,10 +101,11 @@
 			usbd: usbd at 0 {
 				compatible = "nxp,lpc3220-udc";
 				reg = <0x0 0x300>;
-				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>,
-					     <62 IRQ_TYPE_LEVEL_HIGH>,
-					     <60 IRQ_TYPE_LEVEL_HIGH>,
-					     <58 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
+					     <30 IRQ_TYPE_LEVEL_HIGH>,
+					     <28 IRQ_TYPE_LEVEL_HIGH>,
+					     <26 IRQ_TYPE_LEVEL_LOW>;
 				clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
 				status = "disabled";
 			};
@@ -111,7 +113,8 @@
 			i2cusb: i2c at 300 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x300 0x100>;
-				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -263,7 +266,8 @@
 			i2c1: i2c at 400A0000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A0000 0x100>;
-				interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;
@@ -273,7 +277,8 @@
 			i2c2: i2c at 400A8000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A8000 0x100>;
-				interrupts = <50 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;
@@ -314,12 +319,6 @@
 				};
 			};
 
-			/*
-			 * MIC Interrupt controller includes:
-			 *   MIC @40008000
-			 *   SIC1 @4000C000
-			 *   SIC2 @40010000
-			 */
 			mic: interrupt-controller at 40008000 {
 				compatible = "nxp,lpc3220-mic";
 				interrupt-controller;
@@ -327,6 +326,28 @@
 				#interrupt-cells = <2>;
 			};
 
+			sic1: interrupt-controller at 4000c000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x4000c000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+					     <30 IRQ_TYPE_LEVEL_LOW>;
+				};
+
+			sic2: interrupt-controller at 40010000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x40010000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+					     <31 IRQ_TYPE_LEVEL_LOW>;
+			};
+
 			uart1: serial at 40014000 {
 				compatible = "nxp,lpc3220-hsuart";
 				reg = <0x40014000 0x1000>;
@@ -351,7 +372,8 @@
 			rtc: rtc at 40024000 {
 				compatible = "nxp,lpc3220-rtc";
 				reg = <0x40024000 0x1000>;
-				interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_RTC>;
 			};
 
@@ -404,7 +426,8 @@
 			adc: adc at 40048000 {
 				compatible = "nxp,lpc3220-adc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};
@@ -412,7 +435,8 @@
 			tsc: tsc at 40048000 {
 				compatible = "nxp,lpc3220-tsc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};
-- 
2.1.4

Re: [PATCH v2 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Sylvain Lemieux]

Hi Vladimir,

On Mon, 2016-04-25 at 04:00 +0300, Vladimir Zapolskiy wrote:
> The change adds separate device nodes for SIC1 and SIC2 interrupt
> controllers and reparents all defined SIC1 and SIC2 interrupt
> producers to the correspondent interrupt controller, this is needed to
> perform switching to a new LPC32xx MIC/SIC interrupt controller driver.
> 
> Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
> ---
> Changes from v1 to v2:
> * squashed two step change in lpc32xx.dtsi - new irqchip driver can be
>   used (i.e. board boots with access to userspace) with old DTS file,
>   so there is no need to fix DTS firstly and then switch to a new driver,
> * removed "interrupt-controller-name" and "wakeup-sources" properties
>   from all interrupt controllers,
> * removed outdated comment.
> 
>  arch/arm/boot/dts/lpc32xx.dtsi | 58 +++++++++++++++++++++++++++++-------------
>  1 file changed, 41 insertions(+), 17 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
> index 73c4746..4570ddc 100644
> --- a/arch/arm/boot/dts/lpc32xx.dtsi
> +++ b/arch/arm/boot/dts/lpc32xx.dtsi
> @@ -92,7 +92,8 @@

...
>  
> -			/*
> -			 * MIC Interrupt controller includes:
> -			 *   MIC @40008000
> -			 *   SIC1 @4000C000
> -			 *   SIC2 @40010000
> -			 */
>  			mic: interrupt-controller@40008000 {
>  				compatible = "nxp,lpc3220-mic";
>  				interrupt-controller;
> @@ -327,6 +326,28 @@

I think your are missing one change in your patch,
the mic register range should be 0x4000, not 0xC000.

Everything else is OK.

>  				#interrupt-cells = <2>;
>  			};
>  
> +			sic1: interrupt-controller@4000c000 {
> +				compatible = "nxp,lpc3220-sic";
> +				reg = <0x4000c000 0x4000>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +
> +				interrupt-parent = <&mic>;
> +				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
> +					     <30 IRQ_TYPE_LEVEL_LOW>;
> +				};
> +
> +			sic2: interrupt-controller@40010000 {
> +				compatible = "nxp,lpc3220-sic";
> +				reg = <0x40010000 0x4000>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +
> +				interrupt-parent = <&mic>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
> +					     <31 IRQ_TYPE_LEVEL_LOW>;
> +			};
> +
...

Sylvain


--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Sylvain Lemieux]

Hi Vladimir,

On Mon, 2016-04-25 at 04:00 +0300, Vladimir Zapolskiy wrote:
> The change adds separate device nodes for SIC1 and SIC2 interrupt
> controllers and reparents all defined SIC1 and SIC2 interrupt
> producers to the correspondent interrupt controller, this is needed to
> perform switching to a new LPC32xx MIC/SIC interrupt controller driver.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> ---
> Changes from v1 to v2:
> * squashed two step change in lpc32xx.dtsi - new irqchip driver can be
>   used (i.e. board boots with access to userspace) with old DTS file,
>   so there is no need to fix DTS firstly and then switch to a new driver,
> * removed "interrupt-controller-name" and "wakeup-sources" properties
>   from all interrupt controllers,
> * removed outdated comment.
> 
>  arch/arm/boot/dts/lpc32xx.dtsi | 58 +++++++++++++++++++++++++++++-------------
>  1 file changed, 41 insertions(+), 17 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
> index 73c4746..4570ddc 100644
> --- a/arch/arm/boot/dts/lpc32xx.dtsi
> +++ b/arch/arm/boot/dts/lpc32xx.dtsi
> @@ -92,7 +92,8 @@

...
>  
> -			/*
> -			 * MIC Interrupt controller includes:
> -			 *   MIC @40008000
> -			 *   SIC1 @4000C000
> -			 *   SIC2 @40010000
> -			 */
>  			mic: interrupt-controller at 40008000 {
>  				compatible = "nxp,lpc3220-mic";
>  				interrupt-controller;
> @@ -327,6 +326,28 @@

I think your are missing one change in your patch,
the mic register range should be 0x4000, not 0xC000.

Everything else is OK.

>  				#interrupt-cells = <2>;
>  			};
>  
> +			sic1: interrupt-controller at 4000c000 {
> +				compatible = "nxp,lpc3220-sic";
> +				reg = <0x4000c000 0x4000>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +
> +				interrupt-parent = <&mic>;
> +				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
> +					     <30 IRQ_TYPE_LEVEL_LOW>;
> +				};
> +
> +			sic2: interrupt-controller at 40010000 {
> +				compatible = "nxp,lpc3220-sic";
> +				reg = <0x40010000 0x4000>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +
> +				interrupt-parent = <&mic>;
> +				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
> +					     <31 IRQ_TYPE_LEVEL_LOW>;
> +			};
> +
...

Sylvain

Re: [PATCH v2 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Vladimir Zapolskiy]

Hi Sylvain,

On 25.04.2016 19:05, Sylvain Lemieux wrote:
> Hi Vladimir,
> 
> On Mon, 2016-04-25 at 04:00 +0300, Vladimir Zapolskiy wrote:
>> The change adds separate device nodes for SIC1 and SIC2 interrupt
>> controllers and reparents all defined SIC1 and SIC2 interrupt
>> producers to the correspondent interrupt controller, this is needed to
>> perform switching to a new LPC32xx MIC/SIC interrupt controller driver.
>>
>> Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
>> ---
>> Changes from v1 to v2:
>> * squashed two step change in lpc32xx.dtsi - new irqchip driver can be
>>   used (i.e. board boots with access to userspace) with old DTS file,
>>   so there is no need to fix DTS firstly and then switch to a new driver,
>> * removed "interrupt-controller-name" and "wakeup-sources" properties
>>   from all interrupt controllers,
>> * removed outdated comment.
>>
>>  arch/arm/boot/dts/lpc32xx.dtsi | 58 +++++++++++++++++++++++++++++-------------
>>  1 file changed, 41 insertions(+), 17 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
>> index 73c4746..4570ddc 100644
>> --- a/arch/arm/boot/dts/lpc32xx.dtsi
>> +++ b/arch/arm/boot/dts/lpc32xx.dtsi
>> @@ -92,7 +92,8 @@
> 
> ...
>>  
>> -			/*
>> -			 * MIC Interrupt controller includes:
>> -			 *   MIC @40008000
>> -			 *   SIC1 @4000C000
>> -			 *   SIC2 @40010000
>> -			 */
>>  			mic: interrupt-controller@40008000 {
>>  				compatible = "nxp,lpc3220-mic";
>>  				interrupt-controller;
>> @@ -327,6 +326,28 @@
> 
> I think your are missing one change in your patch,
> the mic register range should be 0x4000, not 0xC000.
> 
> Everything else is OK.

Good catch, thank you for pointing it out, and let me fix it
immediately. Fortunately it is corrected in an example from v2 1/4.

>>  				#interrupt-cells = <2>;
>>  			};
>>  
>> +			sic1: interrupt-controller@4000c000 {
>> +				compatible = "nxp,lpc3220-sic";
>> +				reg = <0x4000c000 0x4000>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +
>> +				interrupt-parent = <&mic>;
>> +				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
>> +					     <30 IRQ_TYPE_LEVEL_LOW>;
>> +				};
>> +
>> +			sic2: interrupt-controller@40010000 {
>> +				compatible = "nxp,lpc3220-sic";
>> +				reg = <0x40010000 0x4000>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +
>> +				interrupt-parent = <&mic>;
>> +				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
>> +					     <31 IRQ_TYPE_LEVEL_LOW>;
>> +			};
>> +
> ...
> 

--
With best wishes,
Vladimir
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Vladimir Zapolskiy]

Hi Sylvain,

On 25.04.2016 19:05, Sylvain Lemieux wrote:
> Hi Vladimir,
> 
> On Mon, 2016-04-25 at 04:00 +0300, Vladimir Zapolskiy wrote:
>> The change adds separate device nodes for SIC1 and SIC2 interrupt
>> controllers and reparents all defined SIC1 and SIC2 interrupt
>> producers to the correspondent interrupt controller, this is needed to
>> perform switching to a new LPC32xx MIC/SIC interrupt controller driver.
>>
>> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
>> ---
>> Changes from v1 to v2:
>> * squashed two step change in lpc32xx.dtsi - new irqchip driver can be
>>   used (i.e. board boots with access to userspace) with old DTS file,
>>   so there is no need to fix DTS firstly and then switch to a new driver,
>> * removed "interrupt-controller-name" and "wakeup-sources" properties
>>   from all interrupt controllers,
>> * removed outdated comment.
>>
>>  arch/arm/boot/dts/lpc32xx.dtsi | 58 +++++++++++++++++++++++++++++-------------
>>  1 file changed, 41 insertions(+), 17 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
>> index 73c4746..4570ddc 100644
>> --- a/arch/arm/boot/dts/lpc32xx.dtsi
>> +++ b/arch/arm/boot/dts/lpc32xx.dtsi
>> @@ -92,7 +92,8 @@
> 
> ...
>>  
>> -			/*
>> -			 * MIC Interrupt controller includes:
>> -			 *   MIC @40008000
>> -			 *   SIC1 @4000C000
>> -			 *   SIC2 @40010000
>> -			 */
>>  			mic: interrupt-controller at 40008000 {
>>  				compatible = "nxp,lpc3220-mic";
>>  				interrupt-controller;
>> @@ -327,6 +326,28 @@
> 
> I think your are missing one change in your patch,
> the mic register range should be 0x4000, not 0xC000.
> 
> Everything else is OK.

Good catch, thank you for pointing it out, and let me fix it
immediately. Fortunately it is corrected in an example from v2 1/4.

>>  				#interrupt-cells = <2>;
>>  			};
>>  
>> +			sic1: interrupt-controller at 4000c000 {
>> +				compatible = "nxp,lpc3220-sic";
>> +				reg = <0x4000c000 0x4000>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +
>> +				interrupt-parent = <&mic>;
>> +				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
>> +					     <30 IRQ_TYPE_LEVEL_LOW>;
>> +				};
>> +
>> +			sic2: interrupt-controller at 40010000 {
>> +				compatible = "nxp,lpc3220-sic";
>> +				reg = <0x40010000 0x4000>;
>> +				interrupt-controller;
>> +				#interrupt-cells = <2>;
>> +
>> +				interrupt-parent = <&mic>;
>> +				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
>> +					     <31 IRQ_TYPE_LEVEL_LOW>;
>> +			};
>> +
> ...
> 

--
With best wishes,
Vladimir

[PATCH v3 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Vladimir Zapolskiy]

The change adds separate device nodes for SIC1 and SIC2 interrupt
controllers and reparents all defined SIC1 and SIC2 interrupt
producers to the correspondent interrupt controller, this is needed to
perform switching to a new LPC32xx MIC/SIC interrupt controller driver.

Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
---
Changes from v2 to v3:
* fix io region size for MIC controller after moving SIC1/SIC2
  controllers out,
* move MIC 'reg' property up to follow 'compatible' property.

Changes from v1 to v2:
* squashed two step change in lpc32xx.dtsi - new irqchip driver can be
  used (i.e. board boots with access to userspace) with old DTS file,
  so there is no need to fix DTS firstly and then switch to a new driver,
* removed "interrupt-controller-name" and "wakeup-sources" properties
  from all interrupt controllers,
* removed outdated comment.

 arch/arm/boot/dts/lpc32xx.dtsi | 60 +++++++++++++++++++++++++++++-------------
 1 file changed, 42 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 73c4746..e295e1e 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -92,7 +92,8 @@
 			ohci: ohci@0 {
 				compatible = "nxp,ohci-nxp", "usb-ohci";
 				reg = <0x0 0x300>;
-				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
 				status = "disabled";
 			};
@@ -100,10 +101,11 @@
 			usbd: usbd@0 {
 				compatible = "nxp,lpc3220-udc";
 				reg = <0x0 0x300>;
-				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>,
-					     <62 IRQ_TYPE_LEVEL_HIGH>,
-					     <60 IRQ_TYPE_LEVEL_HIGH>,
-					     <58 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
+					     <30 IRQ_TYPE_LEVEL_HIGH>,
+					     <28 IRQ_TYPE_LEVEL_HIGH>,
+					     <26 IRQ_TYPE_LEVEL_LOW>;
 				clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
 				status = "disabled";
 			};
@@ -111,7 +113,8 @@
 			i2cusb: i2c@300 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x300 0x100>;
-				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -263,7 +266,8 @@
 			i2c1: i2c@400A0000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A0000 0x100>;
-				interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;
@@ -273,7 +277,8 @@
 			i2c2: i2c@400A8000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A8000 0x100>;
-				interrupts = <50 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;
@@ -314,19 +319,35 @@
 				};
 			};
 
-			/*
-			 * MIC Interrupt controller includes:
-			 *   MIC @40008000
-			 *   SIC1 @4000C000
-			 *   SIC2 @40010000
-			 */
 			mic: interrupt-controller@40008000 {
 				compatible = "nxp,lpc3220-mic";
+				reg = <0x40008000 0x4000>;
 				interrupt-controller;
-				reg = <0x40008000 0xC000>;
 				#interrupt-cells = <2>;
 			};
 
+			sic1: interrupt-controller@4000c000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x4000c000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+					     <30 IRQ_TYPE_LEVEL_LOW>;
+				};
+
+			sic2: interrupt-controller@40010000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x40010000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+					     <31 IRQ_TYPE_LEVEL_LOW>;
+			};
+
 			uart1: serial@40014000 {
 				compatible = "nxp,lpc3220-hsuart";
 				reg = <0x40014000 0x1000>;
@@ -351,7 +372,8 @@
 			rtc: rtc@40024000 {
 				compatible = "nxp,lpc3220-rtc";
 				reg = <0x40024000 0x1000>;
-				interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_RTC>;
 			};
 
@@ -404,7 +426,8 @@
 			adc: adc@40048000 {
 				compatible = "nxp,lpc3220-adc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};
@@ -412,7 +435,8 @@
 			tsc: tsc@40048000 {
 				compatible = "nxp,lpc3220-tsc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};
-- 
2.1.4

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v3 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Vladimir Zapolskiy]

The change adds separate device nodes for SIC1 and SIC2 interrupt
controllers and reparents all defined SIC1 and SIC2 interrupt
producers to the correspondent interrupt controller, this is needed to
perform switching to a new LPC32xx MIC/SIC interrupt controller driver.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
Changes from v2 to v3:
* fix io region size for MIC controller after moving SIC1/SIC2
  controllers out,
* move MIC 'reg' property up to follow 'compatible' property.

Changes from v1 to v2:
* squashed two step change in lpc32xx.dtsi - new irqchip driver can be
  used (i.e. board boots with access to userspace) with old DTS file,
  so there is no need to fix DTS firstly and then switch to a new driver,
* removed "interrupt-controller-name" and "wakeup-sources" properties
  from all interrupt controllers,
* removed outdated comment.

 arch/arm/boot/dts/lpc32xx.dtsi | 60 +++++++++++++++++++++++++++++-------------
 1 file changed, 42 insertions(+), 18 deletions(-)

diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 73c4746..e295e1e 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -92,7 +92,8 @@
 			ohci: ohci at 0 {
 				compatible = "nxp,ohci-nxp", "usb-ohci";
 				reg = <0x0 0x300>;
-				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
 				status = "disabled";
 			};
@@ -100,10 +101,11 @@
 			usbd: usbd at 0 {
 				compatible = "nxp,lpc3220-udc";
 				reg = <0x0 0x300>;
-				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>,
-					     <62 IRQ_TYPE_LEVEL_HIGH>,
-					     <60 IRQ_TYPE_LEVEL_HIGH>,
-					     <58 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
+					     <30 IRQ_TYPE_LEVEL_HIGH>,
+					     <28 IRQ_TYPE_LEVEL_HIGH>,
+					     <26 IRQ_TYPE_LEVEL_LOW>;
 				clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
 				status = "disabled";
 			};
@@ -111,7 +113,8 @@
 			i2cusb: i2c at 300 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x300 0x100>;
-				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -263,7 +266,8 @@
 			i2c1: i2c at 400A0000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A0000 0x100>;
-				interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;
@@ -273,7 +277,8 @@
 			i2c2: i2c at 400A8000 {
 				compatible = "nxp,pnx-i2c";
 				reg = <0x400A8000 0x100>;
-				interrupts = <50 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-parent = <&sic1>;
+				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pnx,timeout = <0x64>;
@@ -314,19 +319,35 @@
 				};
 			};
 
-			/*
-			 * MIC Interrupt controller includes:
-			 *   MIC @40008000
-			 *   SIC1 @4000C000
-			 *   SIC2 @40010000
-			 */
 			mic: interrupt-controller at 40008000 {
 				compatible = "nxp,lpc3220-mic";
+				reg = <0x40008000 0x4000>;
 				interrupt-controller;
-				reg = <0x40008000 0xC000>;
 				#interrupt-cells = <2>;
 			};
 
+			sic1: interrupt-controller at 4000c000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x4000c000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+					     <30 IRQ_TYPE_LEVEL_LOW>;
+				};
+
+			sic2: interrupt-controller at 40010000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x40010000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+					     <31 IRQ_TYPE_LEVEL_LOW>;
+			};
+
 			uart1: serial at 40014000 {
 				compatible = "nxp,lpc3220-hsuart";
 				reg = <0x40014000 0x1000>;
@@ -351,7 +372,8 @@
 			rtc: rtc at 40024000 {
 				compatible = "nxp,lpc3220-rtc";
 				reg = <0x40024000 0x1000>;
-				interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_RTC>;
 			};
 
@@ -404,7 +426,8 @@
 			adc: adc at 40048000 {
 				compatible = "nxp,lpc3220-adc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};
@@ -412,7 +435,8 @@
 			tsc: tsc at 40048000 {
 				compatible = "nxp,lpc3220-tsc";
 				reg = <0x40048000 0x1000>;
-				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&sic1>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk LPC32XX_CLK_ADC>;
 				status = "disabled";
 			};
-- 
2.1.4

Re: [PATCH v3 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Sylvain Lemieux]

Hi Vladimir,

On Tue, 2016-04-26 at 00:02 +0300, Vladimir Zapolskiy wrote:
> The change adds separate device nodes for SIC1 and SIC2 interrupt
> controllers and reparents all defined SIC1 and SIC2 interrupt
> producers to the correspondent interrupt controller, this is needed to
> perform switching to a new LPC32xx MIC/SIC interrupt controller driver.
> 
> Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
> ---
> Changes from v2 to v3:
> * fix io region size for MIC controller after moving SIC1/SIC2
>   controllers out,
> * move MIC 'reg' property up to follow 'compatible' property.
> 
> Changes from v1 to v2:
> * squashed two step change in lpc32xx.dtsi - new irqchip driver can be
>   used (i.e. board boots with access to userspace) with old DTS file,
>   so there is no need to fix DTS firstly and then switch to a new driver,
> * removed "interrupt-controller-name" and "wakeup-sources" properties
>   from all interrupt controllers,
> * removed outdated comment.
> 
>  arch/arm/boot/dts/lpc32xx.dtsi | 60 +++++++++++++++++++++++++++++-------------
>  1 file changed, 42 insertions(+), 18 deletions(-)
> 
Please use capital letter for the word ARM in the patch title.

Acked-by: Sylvain Lemieux <slemieux.tyco-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>





--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v3 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Sylvain Lemieux]

Hi Vladimir,

On Tue, 2016-04-26 at 00:02 +0300, Vladimir Zapolskiy wrote:
> The change adds separate device nodes for SIC1 and SIC2 interrupt
> controllers and reparents all defined SIC1 and SIC2 interrupt
> producers to the correspondent interrupt controller, this is needed to
> perform switching to a new LPC32xx MIC/SIC interrupt controller driver.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> ---
> Changes from v2 to v3:
> * fix io region size for MIC controller after moving SIC1/SIC2
>   controllers out,
> * move MIC 'reg' property up to follow 'compatible' property.
> 
> Changes from v1 to v2:
> * squashed two step change in lpc32xx.dtsi - new irqchip driver can be
>   used (i.e. board boots with access to userspace) with old DTS file,
>   so there is no need to fix DTS firstly and then switch to a new driver,
> * removed "interrupt-controller-name" and "wakeup-sources" properties
>   from all interrupt controllers,
> * removed outdated comment.
> 
>  arch/arm/boot/dts/lpc32xx.dtsi | 60 +++++++++++++++++++++++++++++-------------
>  1 file changed, 42 insertions(+), 18 deletions(-)
> 
Please use capital letter for the word ARM in the patch title.

Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>

Re: [PATCH v3 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Vladimir Zapolskiy]

Hi Sylvain,

On 26.04.2016 15:26, Sylvain Lemieux wrote:
> Hi Vladimir,
> 
> On Tue, 2016-04-26 at 00:02 +0300, Vladimir Zapolskiy wrote:
>> The change adds separate device nodes for SIC1 and SIC2 interrupt
>> controllers and reparents all defined SIC1 and SIC2 interrupt
>> producers to the correspondent interrupt controller, this is needed to
>> perform switching to a new LPC32xx MIC/SIC interrupt controller driver.
>>
>> Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
>> ---
>> Changes from v2 to v3:
>> * fix io region size for MIC controller after moving SIC1/SIC2
>>   controllers out,
>> * move MIC 'reg' property up to follow 'compatible' property.
>>
>> Changes from v1 to v2:
>> * squashed two step change in lpc32xx.dtsi - new irqchip driver can be
>>   used (i.e. board boots with access to userspace) with old DTS file,
>>   so there is no need to fix DTS firstly and then switch to a new driver,
>> * removed "interrupt-controller-name" and "wakeup-sources" properties
>>   from all interrupt controllers,
>> * removed outdated comment.
>>
>>  arch/arm/boot/dts/lpc32xx.dtsi | 60 +++++++++++++++++++++++++++++-------------
>>  1 file changed, 42 insertions(+), 18 deletions(-)
>>
> Please use capital letter for the word ARM in the patch title.

right, I'll change it on application, thank you for review.

> Acked-by: Sylvain Lemieux <slemieux.tyco-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> 

--
With best wishes,
Vladimir
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v3 3/4] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC

[Vladimir Zapolskiy]

Hi Sylvain,

On 26.04.2016 15:26, Sylvain Lemieux wrote:
> Hi Vladimir,
> 
> On Tue, 2016-04-26 at 00:02 +0300, Vladimir Zapolskiy wrote:
>> The change adds separate device nodes for SIC1 and SIC2 interrupt
>> controllers and reparents all defined SIC1 and SIC2 interrupt
>> producers to the correspondent interrupt controller, this is needed to
>> perform switching to a new LPC32xx MIC/SIC interrupt controller driver.
>>
>> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
>> ---
>> Changes from v2 to v3:
>> * fix io region size for MIC controller after moving SIC1/SIC2
>>   controllers out,
>> * move MIC 'reg' property up to follow 'compatible' property.
>>
>> Changes from v1 to v2:
>> * squashed two step change in lpc32xx.dtsi - new irqchip driver can be
>>   used (i.e. board boots with access to userspace) with old DTS file,
>>   so there is no need to fix DTS firstly and then switch to a new driver,
>> * removed "interrupt-controller-name" and "wakeup-sources" properties
>>   from all interrupt controllers,
>> * removed outdated comment.
>>
>>  arch/arm/boot/dts/lpc32xx.dtsi | 60 +++++++++++++++++++++++++++++-------------
>>  1 file changed, 42 insertions(+), 18 deletions(-)
>>
> Please use capital letter for the word ARM in the patch title.

right, I'll change it on application, thank you for review.

> Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
> 

--
With best wishes,
Vladimir

[PATCH v2 2/4] irqchip: add LPC32xx interrupt controller driver

[Vladimir Zapolskiy]

The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2
interrupt controllers.

This is a list of new features in comparison to the legacy driver:
* irq types are taken from device tree settings, no more need to
  hardcode them,
* old driver is based on irq_domain_add_legacy, which causes problems
  with handling MIC hardware interrupt 0 produced by SIC1,
* there is one driver for MIC, SIC1 and SIC2, no more need to handle
  them separately, e.g. have two separate handlers for SIC1 and SIC2,
* the driver does not have any dependencies on hardcoded register
  offsets,
* the driver is much simpler for maintenance,
* SPARSE_IRQS option is supported.

Legacy LPC32xx interrupt controller driver was broken since commit
76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which
requires a private interrupt handler, otherwise any SIC1 generated
interrupt (mapped to MIC hwirq 0) breaks the kernel with the message
"unexpected IRQ trap at vector 00".

The change disables compilation of a legacy driver found at
arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate
commit.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
Changes from v1 to v2:
* added chained_irq_{enter,exit} for SIC chained handler,
* use {writel,readl}_relaxed flavour of io access functions,
* changed anchor data type to access iomem from struct irq_domain
  to private struct lpc32xx_irq_chip,
* do not read irq status register twice on every irq event,
* resource deallocation fixes on error path of irqchip driver init,
* removed handling of "interrupt-controller-name" property, name
  is constructed from mic/sic type and controller's physical address,
* minor improvements (renames, __ffs instead of ffs, etc.)

Many kudos to Marc for review of v1.

 arch/arm/Kconfig                |   2 +
 arch/arm/mach-lpc32xx/phy3250.c |   1 -
 drivers/irqchip/Makefile        |   1 +
 drivers/irqchip/irq-lpc32xx.c   | 238 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 241 insertions(+), 1 deletion(-)
 create mode 100644 drivers/irqchip/irq-lpc32xx.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cdfa6c2..6684af9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -531,6 +531,8 @@ config ARCH_LPC32XX
 	select COMMON_CLK
 	select CPU_ARM926T
 	select GENERIC_CLOCKEVENTS
+	select MULTI_IRQ_HANDLER
+	select SPARSE_IRQ
 	select USE_OF
 	help
 	  Support for the NXP LPC32XX family of processors
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index b2f9e22..f9209d0 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -206,7 +206,6 @@ static const char *const lpc32xx_dt_compat[] __initconst = {
 DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
 	.atag_offset	= 0x100,
 	.map_io		= lpc32xx_map_io,
-	.init_irq	= lpc32xx_init_irq,
 	.init_machine	= lpc3250_machine_init,
 	.dt_compat	= lpc32xx_dt_compat,
 MACHINE_END
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index b03cfcb..5261f10 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2835.o
 obj-$(CONFIG_ARCH_BCM2835)		+= irq-bcm2836.o
 obj-$(CONFIG_ARCH_EXYNOS)		+= exynos-combiner.o
 obj-$(CONFIG_ARCH_HIP04)		+= irq-hip04.o
+obj-$(CONFIG_ARCH_LPC32XX)		+= irq-lpc32xx.o
 obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
 obj-$(CONFIG_IRQ_MXS)			+= irq-mxs.o
 obj-$(CONFIG_ARCH_TEGRA)		+= irq-tegra.o
diff --git a/drivers/irqchip/irq-lpc32xx.c b/drivers/irqchip/irq-lpc32xx.c
new file mode 100644
index 0000000..1034aeb
--- /dev/null
+++ b/drivers/irqchip/irq-lpc32xx.c
@@ -0,0 +1,238 @@
+/*
+ * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include <asm/exception.h>
+
+#define LPC32XX_INTC_MASK		0x00
+#define LPC32XX_INTC_RAW		0x04
+#define LPC32XX_INTC_STAT		0x08
+#define LPC32XX_INTC_POL		0x0C
+#define LPC32XX_INTC_TYPE		0x10
+#define LPC32XX_INTC_FIQ		0x14
+
+#define NR_LPC32XX_IC_IRQS		32
+
+struct lpc32xx_irq_chip {
+	void __iomem *base;
+	struct irq_domain *domain;
+	struct irq_chip chip;
+};
+
+static struct lpc32xx_irq_chip *lpc32xx_mic_irqc;
+
+static inline u32 lpc32xx_ic_read(struct lpc32xx_irq_chip *ic, u32 reg)
+{
+	return readl_relaxed(ic->base + reg);
+}
+
+static inline void lpc32xx_ic_write(struct lpc32xx_irq_chip *ic,
+				    u32 reg, u32 val)
+{
+	writel_relaxed(val, ic->base + reg);
+}
+
+static void lpc32xx_irq_mask(struct irq_data *d)
+{
+	struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
+	u32 val, mask = BIT(d->hwirq);
+
+	val = lpc32xx_ic_read(ic, LPC32XX_INTC_MASK) & ~mask;
+	lpc32xx_ic_write(ic, LPC32XX_INTC_MASK, val);
+}
+
+static void lpc32xx_irq_unmask(struct irq_data *d)
+{
+	struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
+	u32 val, mask = BIT(d->hwirq);
+
+	val = lpc32xx_ic_read(ic, LPC32XX_INTC_MASK) | mask;
+	lpc32xx_ic_write(ic, LPC32XX_INTC_MASK, val);
+}
+
+static void lpc32xx_irq_ack(struct irq_data *d)
+{
+	struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
+	u32 mask = BIT(d->hwirq);
+
+	lpc32xx_ic_write(ic, LPC32XX_INTC_RAW, mask);
+}
+
+static int lpc32xx_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
+	u32 val, mask = BIT(d->hwirq);
+	bool high, edge;
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		edge = true;
+		high = true;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		edge = true;
+		high = false;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		edge = false;
+		high = true;
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		edge = false;
+		high = false;
+		break;
+	default:
+		pr_info("unsupported irq type %d\n", type);
+		return -EINVAL;
+	}
+
+	irqd_set_trigger_type(d, type);
+
+	val = lpc32xx_ic_read(ic, LPC32XX_INTC_POL);
+	if (high)
+		val |= mask;
+	else
+		val &= ~mask;
+	lpc32xx_ic_write(ic, LPC32XX_INTC_POL, val);
+
+	val = lpc32xx_ic_read(ic, LPC32XX_INTC_TYPE);
+	if (edge) {
+		val |= mask;
+		irq_set_handler_locked(d, handle_edge_irq);
+	} else {
+		val &= ~mask;
+		irq_set_handler_locked(d, handle_level_irq);
+	}
+	lpc32xx_ic_write(ic, LPC32XX_INTC_TYPE, val);
+
+	return 0;
+}
+
+static void __exception_irq_entry lpc32xx_handle_irq(struct pt_regs *regs)
+{
+	struct lpc32xx_irq_chip *ic = lpc32xx_mic_irqc;
+	u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq;
+
+	while (hwirq) {
+		irq = __ffs(hwirq);
+		hwirq &= ~BIT(irq);
+		handle_domain_irq(lpc32xx_mic_irqc->domain, irq, regs);
+	}
+}
+
+static void lpc32xx_sic_handler(struct irq_desc *desc)
+{
+	struct lpc32xx_irq_chip *ic = irq_desc_get_handler_data(desc);
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq;
+
+	chained_irq_enter(chip, desc);
+
+	while (hwirq) {
+		irq = __ffs(hwirq);
+		hwirq &= ~BIT(irq);
+		generic_handle_irq(irq_find_mapping(ic->domain, irq));
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
+static int lpc32xx_irq_domain_map(struct irq_domain *id, unsigned int virq,
+				  irq_hw_number_t hw)
+{
+	struct lpc32xx_irq_chip *ic = id->host_data;
+
+	irq_set_chip_data(virq, ic);
+	irq_set_chip_and_handler(virq, &ic->chip, handle_level_irq);
+	irq_set_status_flags(virq, IRQ_LEVEL);
+	irq_set_noprobe(virq);
+
+	return 0;
+}
+
+static void lpc32xx_irq_domain_unmap(struct irq_domain *id, unsigned int virq)
+{
+	irq_set_chip_and_handler(virq, NULL, NULL);
+}
+
+static const struct irq_domain_ops lpc32xx_irq_domain_ops = {
+	.map    = lpc32xx_irq_domain_map,
+	.unmap	= lpc32xx_irq_domain_unmap,
+	.xlate  = irq_domain_xlate_twocell,
+};
+
+static int __init lpc32xx_of_ic_init(struct device_node *node,
+				     struct device_node *parent)
+{
+	struct lpc32xx_irq_chip *irqc;
+	bool is_mic = of_device_is_compatible(node, "nxp,lpc3220-mic");
+	const __be32 *reg = of_get_property(node, "reg", NULL);
+	u32 parent_irq, i, addr = reg ? be32_to_cpu(*reg) : 0;
+
+	irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
+	if (!irqc)
+		return -ENOMEM;
+
+	irqc->base = of_iomap(node, 0);
+	if (!irqc->base) {
+		pr_err("%s: unable to map registers\n", node->full_name);
+		kfree(irqc);
+		return -EINVAL;
+	}
+
+	irqc->chip.irq_ack = lpc32xx_irq_ack;
+	irqc->chip.irq_mask = lpc32xx_irq_mask;
+	irqc->chip.irq_unmask = lpc32xx_irq_unmask;
+	irqc->chip.irq_set_type = lpc32xx_irq_set_type;
+	if (is_mic)
+		irqc->chip.name = kasprintf(GFP_KERNEL, "%08x.mic", addr);
+	else
+		irqc->chip.name = kasprintf(GFP_KERNEL, "%08x.sic", addr);
+
+	irqc->domain = irq_domain_add_linear(node, NR_LPC32XX_IC_IRQS,
+					     &lpc32xx_irq_domain_ops, irqc);
+	if (!irqc->domain) {
+		pr_err("unable to add irq domain\n");
+		iounmap(irqc->base);
+		kfree(irqc->chip.name);
+		kfree(irqc);
+		return -ENODEV;
+	}
+
+	if (is_mic) {
+		lpc32xx_mic_irqc = irqc;
+		set_handle_irq(lpc32xx_handle_irq);
+	} else {
+		for (i = 0; i < of_irq_count(node); i++) {
+			parent_irq = irq_of_parse_and_map(node, i);
+			if (parent_irq)
+				irq_set_chained_handler_and_data(parent_irq,
+						 lpc32xx_sic_handler, irqc);
+		}
+	}
+
+	lpc32xx_ic_write(irqc, LPC32XX_INTC_MASK, 0x00);
+	lpc32xx_ic_write(irqc, LPC32XX_INTC_POL,  0x00);
+	lpc32xx_ic_write(irqc, LPC32XX_INTC_TYPE, 0x00);
+
+	return 0;
+}
+
+IRQCHIP_DECLARE(nxp_lpc32xx_mic, "nxp,lpc3220-mic", lpc32xx_of_ic_init);
+IRQCHIP_DECLARE(nxp_lpc32xx_sic, "nxp,lpc3220-sic", lpc32xx_of_ic_init);
-- 
2.1.4

[PATCH v2 2/4] irqchip: add LPC32xx interrupt controller driver

[Sylvain Lemieux]

Hi Vladimir,

On Mon, 2016-04-25 at 04:00 +0300, Vladimir Zapolskiy wrote:
> The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2
> interrupt controllers.
> 
> This is a list of new features in comparison to the legacy driver:
> * irq types are taken from device tree settings, no more need to
>   hardcode them,
> * old driver is based on irq_domain_add_legacy, which causes problems
>   with handling MIC hardware interrupt 0 produced by SIC1,
> * there is one driver for MIC, SIC1 and SIC2, no more need to handle
>   them separately, e.g. have two separate handlers for SIC1 and SIC2,
> * the driver does not have any dependencies on hardcoded register
>   offsets,
> * the driver is much simpler for maintenance,
> * SPARSE_IRQS option is supported.
> 
> Legacy LPC32xx interrupt controller driver was broken since commit
> 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which
> requires a private interrupt handler, otherwise any SIC1 generated
> interrupt (mapped to MIC hwirq 0) breaks the kernel with the message
> "unexpected IRQ trap at vector 00".
> 
> The change disables compilation of a legacy driver found at
> arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate
> commit.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> ---
> Changes from v1 to v2:
> * added chained_irq_{enter,exit} for SIC chained handler,
> * use {writel,readl}_relaxed flavour of io access functions,
> * changed anchor data type to access iomem from struct irq_domain
>   to private struct lpc32xx_irq_chip,
> * do not read irq status register twice on every irq event,
> * resource deallocation fixes on error path of irqchip driver init,
> * removed handling of "interrupt-controller-name" property, name
>   is constructed from mic/sic type and controller's physical address,
> * minor improvements (renames, __ffs instead of ffs, etc.)
> 
> Many kudos to Marc for review of v1.
> 
>  arch/arm/Kconfig                |   2 +
>  arch/arm/mach-lpc32xx/phy3250.c |   1 -
>  drivers/irqchip/Makefile        |   1 +
>  drivers/irqchip/irq-lpc32xx.c   | 238 ++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 241 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/irqchip/irq-lpc32xx.c
> 
I tested the driver on a custom LPC3250 board; I was having at
least 1 interrupt generated from each source (MIC/SIC1/SIC2).

Tested-by: Sylvain Lemieux <slemieux.tyco@gmail.com>

[PATCH v2 2/4] irqchip: add LPC32xx interrupt controller driver

[Vladimir Zapolskiy]

On 26.04.2016 16:41, Sylvain Lemieux wrote:
> Hi Vladimir,
> 
> On Mon, 2016-04-25 at 04:00 +0300, Vladimir Zapolskiy wrote:
>> The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2
>> interrupt controllers.
>>
>> This is a list of new features in comparison to the legacy driver:
>> * irq types are taken from device tree settings, no more need to
>>   hardcode them,
>> * old driver is based on irq_domain_add_legacy, which causes problems
>>   with handling MIC hardware interrupt 0 produced by SIC1,
>> * there is one driver for MIC, SIC1 and SIC2, no more need to handle
>>   them separately, e.g. have two separate handlers for SIC1 and SIC2,
>> * the driver does not have any dependencies on hardcoded register
>>   offsets,
>> * the driver is much simpler for maintenance,
>> * SPARSE_IRQS option is supported.
>>
>> Legacy LPC32xx interrupt controller driver was broken since commit
>> 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which
>> requires a private interrupt handler, otherwise any SIC1 generated
>> interrupt (mapped to MIC hwirq 0) breaks the kernel with the message
>> "unexpected IRQ trap at vector 00".
>>
>> The change disables compilation of a legacy driver found at
>> arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate
>> commit.
>>
>> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
>> ---
>> Changes from v1 to v2:
>> * added chained_irq_{enter,exit} for SIC chained handler,
>> * use {writel,readl}_relaxed flavour of io access functions,
>> * changed anchor data type to access iomem from struct irq_domain
>>   to private struct lpc32xx_irq_chip,
>> * do not read irq status register twice on every irq event,
>> * resource deallocation fixes on error path of irqchip driver init,
>> * removed handling of "interrupt-controller-name" property, name
>>   is constructed from mic/sic type and controller's physical address,
>> * minor improvements (renames, __ffs instead of ffs, etc.)
>>
>> Many kudos to Marc for review of v1.
>>
>>  arch/arm/Kconfig                |   2 +
>>  arch/arm/mach-lpc32xx/phy3250.c |   1 -
>>  drivers/irqchip/Makefile        |   1 +
>>  drivers/irqchip/irq-lpc32xx.c   | 238 ++++++++++++++++++++++++++++++++++++++++
>>  4 files changed, 241 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/irqchip/irq-lpc32xx.c
>>
> I tested the driver on a custom LPC3250 board; I was having at
> least 1 interrupt generated from each source (MIC/SIC1/SIC2).
> 
> Tested-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
> 

Thomas, Marc, Jason, Russell,

in your opinion would it be still possible to accept this change v2 2/4 for v4.7?

Thank you.

--
With best wishes,
Vladimir

[PATCH v2 2/4] irqchip: add LPC32xx interrupt controller driver

[Marc Zyngier]

On 28/04/16 23:15, Vladimir Zapolskiy wrote:
> On 26.04.2016 16:41, Sylvain Lemieux wrote:
>> Hi Vladimir,
>>
>> On Mon, 2016-04-25 at 04:00 +0300, Vladimir Zapolskiy wrote:
>>> The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2
>>> interrupt controllers.
>>>
>>> This is a list of new features in comparison to the legacy driver:
>>> * irq types are taken from device tree settings, no more need to
>>>   hardcode them,
>>> * old driver is based on irq_domain_add_legacy, which causes problems
>>>   with handling MIC hardware interrupt 0 produced by SIC1,
>>> * there is one driver for MIC, SIC1 and SIC2, no more need to handle
>>>   them separately, e.g. have two separate handlers for SIC1 and SIC2,
>>> * the driver does not have any dependencies on hardcoded register
>>>   offsets,
>>> * the driver is much simpler for maintenance,
>>> * SPARSE_IRQS option is supported.
>>>
>>> Legacy LPC32xx interrupt controller driver was broken since commit
>>> 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which
>>> requires a private interrupt handler, otherwise any SIC1 generated
>>> interrupt (mapped to MIC hwirq 0) breaks the kernel with the message
>>> "unexpected IRQ trap at vector 00".
>>>
>>> The change disables compilation of a legacy driver found at
>>> arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate
>>> commit.
>>>
>>> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
>>> ---
>>> Changes from v1 to v2:
>>> * added chained_irq_{enter,exit} for SIC chained handler,
>>> * use {writel,readl}_relaxed flavour of io access functions,
>>> * changed anchor data type to access iomem from struct irq_domain
>>>   to private struct lpc32xx_irq_chip,
>>> * do not read irq status register twice on every irq event,
>>> * resource deallocation fixes on error path of irqchip driver init,
>>> * removed handling of "interrupt-controller-name" property, name
>>>   is constructed from mic/sic type and controller's physical address,
>>> * minor improvements (renames, __ffs instead of ffs, etc.)
>>>
>>> Many kudos to Marc for review of v1.
>>>
>>>  arch/arm/Kconfig                |   2 +
>>>  arch/arm/mach-lpc32xx/phy3250.c |   1 -
>>>  drivers/irqchip/Makefile        |   1 +
>>>  drivers/irqchip/irq-lpc32xx.c   | 238 ++++++++++++++++++++++++++++++++++++++++
>>>  4 files changed, 241 insertions(+), 1 deletion(-)
>>>  create mode 100644 drivers/irqchip/irq-lpc32xx.c
>>>
>> I tested the driver on a custom LPC3250 board; I was having at
>> least 1 interrupt generated from each source (MIC/SIC1/SIC2).
>>
>> Tested-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
>>
> 
> Thomas, Marc, Jason, Russell,
> 
> in your opinion would it be still possible to accept this change v2 2/4 for v4.7?

I'll queue them.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

[PATCH v2 2/4] irqchip: add LPC32xx interrupt controller driver

[Vladimir Zapolskiy]

On 03.05.2016 11:34, Marc Zyngier wrote:
> On 28/04/16 23:15, Vladimir Zapolskiy wrote:
>> On 26.04.2016 16:41, Sylvain Lemieux wrote:
>>> Hi Vladimir,
>>>
>>> On Mon, 2016-04-25 at 04:00 +0300, Vladimir Zapolskiy wrote:
>>>> The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2
>>>> interrupt controllers.
>>>>
>>>> This is a list of new features in comparison to the legacy driver:
>>>> * irq types are taken from device tree settings, no more need to
>>>>   hardcode them,
>>>> * old driver is based on irq_domain_add_legacy, which causes problems
>>>>   with handling MIC hardware interrupt 0 produced by SIC1,
>>>> * there is one driver for MIC, SIC1 and SIC2, no more need to handle
>>>>   them separately, e.g. have two separate handlers for SIC1 and SIC2,
>>>> * the driver does not have any dependencies on hardcoded register
>>>>   offsets,
>>>> * the driver is much simpler for maintenance,
>>>> * SPARSE_IRQS option is supported.
>>>>
>>>> Legacy LPC32xx interrupt controller driver was broken since commit
>>>> 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which
>>>> requires a private interrupt handler, otherwise any SIC1 generated
>>>> interrupt (mapped to MIC hwirq 0) breaks the kernel with the message
>>>> "unexpected IRQ trap at vector 00".
>>>>
>>>> The change disables compilation of a legacy driver found at
>>>> arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate
>>>> commit.
>>>>
>>>> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
>>>> ---
>>>> Changes from v1 to v2:
>>>> * added chained_irq_{enter,exit} for SIC chained handler,
>>>> * use {writel,readl}_relaxed flavour of io access functions,
>>>> * changed anchor data type to access iomem from struct irq_domain
>>>>   to private struct lpc32xx_irq_chip,
>>>> * do not read irq status register twice on every irq event,
>>>> * resource deallocation fixes on error path of irqchip driver init,
>>>> * removed handling of "interrupt-controller-name" property, name
>>>>   is constructed from mic/sic type and controller's physical address,
>>>> * minor improvements (renames, __ffs instead of ffs, etc.)
>>>>
>>>> Many kudos to Marc for review of v1.
>>>>
>>>>  arch/arm/Kconfig                |   2 +
>>>>  arch/arm/mach-lpc32xx/phy3250.c |   1 -
>>>>  drivers/irqchip/Makefile        |   1 +
>>>>  drivers/irqchip/irq-lpc32xx.c   | 238 ++++++++++++++++++++++++++++++++++++++++
>>>>  4 files changed, 241 insertions(+), 1 deletion(-)
>>>>  create mode 100644 drivers/irqchip/irq-lpc32xx.c
>>>>
>>> I tested the driver on a custom LPC3250 board; I was having at
>>> least 1 interrupt generated from each source (MIC/SIC1/SIC2).
>>>
>>> Tested-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
>>>
>>
>> Thomas, Marc, Jason, Russell,
>>
>> in your opinion would it be still possible to accept this change v2 2/4 for v4.7?
> 
> I'll queue them.
> 

Marc, thank you in advance, please note that I ask to review/pick up
only 2/4 for v4.7 ("irqchip: add LPC32xx interrupt controller driver"),
DT changes are merged through arm-soc and the last 4/4 clean-up can
be deferred till v4.8.

--
With best wishes,
Vladimir

[PATCH v2 2/4] irqchip: add LPC32xx interrupt controller driver

[Marc Zyngier]

On 03/05/16 10:38, Vladimir Zapolskiy wrote:
> On 03.05.2016 11:34, Marc Zyngier wrote:
>> On 28/04/16 23:15, Vladimir Zapolskiy wrote:
>>> On 26.04.2016 16:41, Sylvain Lemieux wrote:
>>>> Hi Vladimir,
>>>>
>>>> On Mon, 2016-04-25 at 04:00 +0300, Vladimir Zapolskiy wrote:
>>>>> The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2
>>>>> interrupt controllers.
>>>>>
>>>>> This is a list of new features in comparison to the legacy driver:
>>>>> * irq types are taken from device tree settings, no more need to
>>>>>   hardcode them,
>>>>> * old driver is based on irq_domain_add_legacy, which causes problems
>>>>>   with handling MIC hardware interrupt 0 produced by SIC1,
>>>>> * there is one driver for MIC, SIC1 and SIC2, no more need to handle
>>>>>   them separately, e.g. have two separate handlers for SIC1 and SIC2,
>>>>> * the driver does not have any dependencies on hardcoded register
>>>>>   offsets,
>>>>> * the driver is much simpler for maintenance,
>>>>> * SPARSE_IRQS option is supported.
>>>>>
>>>>> Legacy LPC32xx interrupt controller driver was broken since commit
>>>>> 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which
>>>>> requires a private interrupt handler, otherwise any SIC1 generated
>>>>> interrupt (mapped to MIC hwirq 0) breaks the kernel with the message
>>>>> "unexpected IRQ trap at vector 00".
>>>>>
>>>>> The change disables compilation of a legacy driver found at
>>>>> arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate
>>>>> commit.
>>>>>
>>>>> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
>>>>> ---
>>>>> Changes from v1 to v2:
>>>>> * added chained_irq_{enter,exit} for SIC chained handler,
>>>>> * use {writel,readl}_relaxed flavour of io access functions,
>>>>> * changed anchor data type to access iomem from struct irq_domain
>>>>>   to private struct lpc32xx_irq_chip,
>>>>> * do not read irq status register twice on every irq event,
>>>>> * resource deallocation fixes on error path of irqchip driver init,
>>>>> * removed handling of "interrupt-controller-name" property, name
>>>>>   is constructed from mic/sic type and controller's physical address,
>>>>> * minor improvements (renames, __ffs instead of ffs, etc.)
>>>>>
>>>>> Many kudos to Marc for review of v1.
>>>>>
>>>>>  arch/arm/Kconfig                |   2 +
>>>>>  arch/arm/mach-lpc32xx/phy3250.c |   1 -
>>>>>  drivers/irqchip/Makefile        |   1 +
>>>>>  drivers/irqchip/irq-lpc32xx.c   | 238 ++++++++++++++++++++++++++++++++++++++++
>>>>>  4 files changed, 241 insertions(+), 1 deletion(-)
>>>>>  create mode 100644 drivers/irqchip/irq-lpc32xx.c
>>>>>
>>>> I tested the driver on a custom LPC3250 board; I was having at
>>>> least 1 interrupt generated from each source (MIC/SIC1/SIC2).
>>>>
>>>> Tested-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
>>>>
>>>
>>> Thomas, Marc, Jason, Russell,
>>>
>>> in your opinion would it be still possible to accept this change v2 2/4 for v4.7?
>>
>> I'll queue them.
>>
> 
> Marc, thank you in advance, please note that I ask to review/pick up
> only 2/4 for v4.7 ("irqchip: add LPC32xx interrupt controller driver"),
> DT changes are merged through arm-soc and the last 4/4 clean-up can
> be deferred till v4.8.

Right. I'll drop patch 1/4 then.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

[PATCH v2 4/4] ARM: lpc32xx: remove legacy irq controller driver

[Vladimir Zapolskiy]

New NXP LPC32xx irq chip driver is used instead of a legacy one.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
Changes from v1 to v2:
* none, this is a new change

 arch/arm/mach-lpc32xx/Makefile |   2 +-
 arch/arm/mach-lpc32xx/irq.c    | 477 -----------------------------------------
 2 files changed, 1 insertion(+), 478 deletions(-)
 delete mode 100644 arch/arm/mach-lpc32xx/irq.c

diff --git a/arch/arm/mach-lpc32xx/Makefile b/arch/arm/mach-lpc32xx/Makefile
index c70709a..79b6b07 100644
--- a/arch/arm/mach-lpc32xx/Makefile
+++ b/arch/arm/mach-lpc32xx/Makefile
@@ -2,6 +2,6 @@
 # Makefile for the linux kernel.
 #
 
-obj-y	:= irq.o common.o serial.o
+obj-y	:= common.o serial.o
 obj-y	+= pm.o suspend.o
 obj-y	+= phy3250.o
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
deleted file mode 100644
index 2ae431e..0000000
--- a/arch/arm/mach-lpc32xx/irq.c
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * arch/arm/mach-lpc32xx/irq.c
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/irqdomain.h>
-#include <linux/module.h>
-
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include "common.h"
-
-/*
- * Default value representing the Activation polarity of all internal
- * interrupt sources
- */
-#define MIC_APR_DEFAULT		0x3FF0EFE0
-#define SIC1_APR_DEFAULT	0xFBD27186
-#define SIC2_APR_DEFAULT	0x801810C0
-
-/*
- * Default value representing the Activation Type of all internal
- * interrupt sources. All are level sensitive.
- */
-#define MIC_ATR_DEFAULT		0x00000000
-#define SIC1_ATR_DEFAULT	0x00026000
-#define SIC2_ATR_DEFAULT	0x00000000
-
-static struct irq_domain *lpc32xx_mic_domain;
-static struct device_node *lpc32xx_mic_np;
-
-struct lpc32xx_event_group_regs {
-	void __iomem *enab_reg;
-	void __iomem *edge_reg;
-	void __iomem *maskstat_reg;
-	void __iomem *rawstat_reg;
-};
-
-static const struct lpc32xx_event_group_regs lpc32xx_event_int_regs = {
-	.enab_reg = LPC32XX_CLKPWR_INT_ER,
-	.edge_reg = LPC32XX_CLKPWR_INT_AP,
-	.maskstat_reg = LPC32XX_CLKPWR_INT_SR,
-	.rawstat_reg = LPC32XX_CLKPWR_INT_RS,
-};
-
-static const struct lpc32xx_event_group_regs lpc32xx_event_pin_regs = {
-	.enab_reg = LPC32XX_CLKPWR_PIN_ER,
-	.edge_reg = LPC32XX_CLKPWR_PIN_AP,
-	.maskstat_reg = LPC32XX_CLKPWR_PIN_SR,
-	.rawstat_reg = LPC32XX_CLKPWR_PIN_RS,
-};
-
-struct lpc32xx_event_info {
-	const struct lpc32xx_event_group_regs *event_group;
-	u32 mask;
-};
-
-/*
- * Maps an IRQ number to and event mask and register
- */
-static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
-	[IRQ_LPC32XX_GPI_08] = {
-		.event_group = &lpc32xx_event_pin_regs,
-		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT,
-	},
-	[IRQ_LPC32XX_GPI_09] = {
-		.event_group = &lpc32xx_event_pin_regs,
-		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT,
-	},
-	[IRQ_LPC32XX_GPI_19] = {
-		.event_group = &lpc32xx_event_pin_regs,
-		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT,
-	},
-	[IRQ_LPC32XX_GPI_07] = {
-		.event_group = &lpc32xx_event_pin_regs,
-		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT,
-	},
-	[IRQ_LPC32XX_GPI_00] = {
-		.event_group = &lpc32xx_event_pin_regs,
-		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT,
-	},
-	[IRQ_LPC32XX_GPI_01] = {
-		.event_group = &lpc32xx_event_pin_regs,
-		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT,
-	},
-	[IRQ_LPC32XX_GPI_02] = {
-		.event_group = &lpc32xx_event_pin_regs,
-		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT,
-	},
-	[IRQ_LPC32XX_GPI_03] = {
-		.event_group = &lpc32xx_event_pin_regs,
-		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT,
-	},
-	[IRQ_LPC32XX_GPI_04] = {
-		.event_group = &lpc32xx_event_pin_regs,
-		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT,
-	},
-	[IRQ_LPC32XX_GPI_05] = {
-		.event_group = &lpc32xx_event_pin_regs,
-		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT,
-	},
-	[IRQ_LPC32XX_GPI_06] = {
-		.event_group = &lpc32xx_event_pin_regs,
-		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
-	},
-	[IRQ_LPC32XX_GPI_28] = {
-		.event_group = &lpc32xx_event_pin_regs,
-		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT,
-	},
-	[IRQ_LPC32XX_GPIO_00] = {
-		.event_group = &lpc32xx_event_int_regs,
-		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
-	},
-	[IRQ_LPC32XX_GPIO_01] = {
-		.event_group = &lpc32xx_event_int_regs,
-		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT,
-	},
-	[IRQ_LPC32XX_GPIO_02] = {
-		.event_group = &lpc32xx_event_int_regs,
-		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT,
-	},
-	[IRQ_LPC32XX_GPIO_03] = {
-		.event_group = &lpc32xx_event_int_regs,
-		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT,
-	},
-	[IRQ_LPC32XX_GPIO_04] = {
-		.event_group = &lpc32xx_event_int_regs,
-		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT,
-	},
-	[IRQ_LPC32XX_GPIO_05] = {
-		.event_group = &lpc32xx_event_int_regs,
-		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT,
-	},
-	[IRQ_LPC32XX_KEY] = {
-		.event_group = &lpc32xx_event_int_regs,
-		.mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
-	},
-	[IRQ_LPC32XX_ETHERNET] = {
-		.event_group = &lpc32xx_event_int_regs,
-		.mask = LPC32XX_CLKPWR_INTSRC_MAC_BIT,
-	},
-	[IRQ_LPC32XX_USB_OTG_ATX] = {
-		.event_group = &lpc32xx_event_int_regs,
-		.mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
-	},
-	[IRQ_LPC32XX_USB_HOST] = {
-		.event_group = &lpc32xx_event_int_regs,
-		.mask = LPC32XX_CLKPWR_INTSRC_USB_BIT,
-	},
-	[IRQ_LPC32XX_RTC] = {
-		.event_group = &lpc32xx_event_int_regs,
-		.mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT,
-	},
-	[IRQ_LPC32XX_MSTIMER] = {
-		.event_group = &lpc32xx_event_int_regs,
-		.mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT,
-	},
-	[IRQ_LPC32XX_TS_AUX] = {
-		.event_group = &lpc32xx_event_int_regs,
-		.mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT,
-	},
-	[IRQ_LPC32XX_TS_P] = {
-		.event_group = &lpc32xx_event_int_regs,
-		.mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT,
-	},
-	[IRQ_LPC32XX_TS_IRQ] = {
-		.event_group = &lpc32xx_event_int_regs,
-		.mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT,
-	},
-};
-
-static void get_controller(unsigned int irq, unsigned int *base,
-	unsigned int *irqbit)
-{
-	if (irq < 32) {
-		*base = LPC32XX_MIC_BASE;
-		*irqbit = 1 << irq;
-	} else if (irq < 64) {
-		*base = LPC32XX_SIC1_BASE;
-		*irqbit = 1 << (irq - 32);
-	} else {
-		*base = LPC32XX_SIC2_BASE;
-		*irqbit = 1 << (irq - 64);
-	}
-}
-
-static void lpc32xx_mask_irq(struct irq_data *d)
-{
-	unsigned int reg, ctrl, mask;
-
-	get_controller(d->hwirq, &ctrl, &mask);
-
-	reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
-	__raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
-}
-
-static void lpc32xx_unmask_irq(struct irq_data *d)
-{
-	unsigned int reg, ctrl, mask;
-
-	get_controller(d->hwirq, &ctrl, &mask);
-
-	reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
-	__raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
-}
-
-static void lpc32xx_ack_irq(struct irq_data *d)
-{
-	unsigned int ctrl, mask;
-
-	get_controller(d->hwirq, &ctrl, &mask);
-
-	__raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
-
-	/* Also need to clear pending wake event */
-	if (lpc32xx_events[d->hwirq].mask != 0)
-		__raw_writel(lpc32xx_events[d->hwirq].mask,
-			lpc32xx_events[d->hwirq].event_group->rawstat_reg);
-}
-
-static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
-	int use_edge)
-{
-	unsigned int reg, ctrl, mask;
-
-	get_controller(irq, &ctrl, &mask);
-
-	/* Activation level, high or low */
-	reg = __raw_readl(LPC32XX_INTC_POLAR(ctrl));
-	if (use_high_level)
-		reg |= mask;
-	else
-		reg &= ~mask;
-	__raw_writel(reg, LPC32XX_INTC_POLAR(ctrl));
-
-	/* Activation type, edge or level */
-	reg = __raw_readl(LPC32XX_INTC_ACT_TYPE(ctrl));
-	if (use_edge)
-		reg |= mask;
-	else
-		reg &= ~mask;
-	__raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl));
-
-	/* Use same polarity for the wake events */
-	if (lpc32xx_events[irq].mask != 0) {
-		reg = __raw_readl(lpc32xx_events[irq].event_group->edge_reg);
-
-		if (use_high_level)
-			reg |= lpc32xx_events[irq].mask;
-		else
-			reg &= ~lpc32xx_events[irq].mask;
-
-		__raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg);
-	}
-}
-
-static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
-{
-	switch (type) {
-	case IRQ_TYPE_EDGE_RISING:
-		/* Rising edge sensitive */
-		__lpc32xx_set_irq_type(d->hwirq, 1, 1);
-		irq_set_handler_locked(d, handle_edge_irq);
-		break;
-
-	case IRQ_TYPE_EDGE_FALLING:
-		/* Falling edge sensitive */
-		__lpc32xx_set_irq_type(d->hwirq, 0, 1);
-		irq_set_handler_locked(d, handle_edge_irq);
-		break;
-
-	case IRQ_TYPE_LEVEL_LOW:
-		/* Low level sensitive */
-		__lpc32xx_set_irq_type(d->hwirq, 0, 0);
-		irq_set_handler_locked(d, handle_level_irq);
-		break;
-
-	case IRQ_TYPE_LEVEL_HIGH:
-		/* High level sensitive */
-		__lpc32xx_set_irq_type(d->hwirq, 1, 0);
-		irq_set_handler_locked(d, handle_level_irq);
-		break;
-
-	/* Other modes are not supported */
-	default:
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
-{
-	unsigned long eventreg;
-
-	if (lpc32xx_events[d->hwirq].mask != 0) {
-		eventreg = __raw_readl(lpc32xx_events[d->hwirq].
-			event_group->enab_reg);
-
-		if (state)
-			eventreg |= lpc32xx_events[d->hwirq].mask;
-		else {
-			eventreg &= ~lpc32xx_events[d->hwirq].mask;
-
-			/*
-			 * When disabling the wakeup, clear the latched
-			 * event
-			 */
-			__raw_writel(lpc32xx_events[d->hwirq].mask,
-				lpc32xx_events[d->hwirq].
-				event_group->rawstat_reg);
-		}
-
-		__raw_writel(eventreg,
-			lpc32xx_events[d->hwirq].event_group->enab_reg);
-
-		return 0;
-	}
-
-	/* Clear event */
-	__raw_writel(lpc32xx_events[d->hwirq].mask,
-		lpc32xx_events[d->hwirq].event_group->rawstat_reg);
-
-	return -ENODEV;
-}
-
-static void __init lpc32xx_set_default_mappings(unsigned int apr,
-	unsigned int atr, unsigned int offset)
-{
-	unsigned int i;
-
-	/* Set activation levels for each interrupt */
-	i = 0;
-	while (i < 32) {
-		__lpc32xx_set_irq_type(offset + i, ((apr >> i) & 0x1),
-			((atr >> i) & 0x1));
-		i++;
-	}
-}
-
-static struct irq_chip lpc32xx_irq_chip = {
-	.name = "MIC",
-	.irq_ack = lpc32xx_ack_irq,
-	.irq_mask = lpc32xx_mask_irq,
-	.irq_unmask = lpc32xx_unmask_irq,
-	.irq_set_type = lpc32xx_set_irq_type,
-	.irq_set_wake = lpc32xx_irq_wake
-};
-
-static void lpc32xx_sic1_handler(struct irq_desc *desc)
-{
-	unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE));
-
-	while (ints != 0) {
-		int irqno = fls(ints) - 1;
-
-		ints &= ~(1 << irqno);
-
-		generic_handle_irq(LPC32XX_SIC1_IRQ(irqno));
-	}
-}
-
-static void lpc32xx_sic2_handler(struct irq_desc *desc)
-{
-	unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE));
-
-	while (ints != 0) {
-		int irqno = fls(ints) - 1;
-
-		ints &= ~(1 << irqno);
-
-		generic_handle_irq(LPC32XX_SIC2_IRQ(irqno));
-	}
-}
-
-static int __init __lpc32xx_mic_of_init(struct device_node *node,
-					struct device_node *parent)
-{
-	lpc32xx_mic_np = node;
-
-	return 0;
-}
-
-static const struct of_device_id mic_of_match[] __initconst = {
-	{ .compatible = "nxp,lpc3220-mic", .data = __lpc32xx_mic_of_init },
-	{ }
-};
-
-void __init lpc32xx_init_irq(void)
-{
-	unsigned int i;
-
-	/* Setup MIC */
-	__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
-	__raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_MIC_BASE));
-	__raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_MIC_BASE));
-
-	/* Setup SIC1 */
-	__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
-	__raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
-	__raw_writel(SIC1_ATR_DEFAULT,
-				LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
-
-	/* Setup SIC2 */
-	__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
-	__raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
-	__raw_writel(SIC2_ATR_DEFAULT,
-				LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
-
-	/* Configure supported IRQ's */
-	for (i = 0; i < NR_IRQS; i++) {
-		irq_set_chip_and_handler(i, &lpc32xx_irq_chip,
-					 handle_level_irq);
-		irq_clear_status_flags(i, IRQ_NOREQUEST);
-	}
-
-	/* Set default mappings */
-	lpc32xx_set_default_mappings(MIC_APR_DEFAULT, MIC_ATR_DEFAULT, 0);
-	lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32);
-	lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64);
-
-	/* Initially disable all wake events */
-	__raw_writel(0, LPC32XX_CLKPWR_P01_ER);
-	__raw_writel(0, LPC32XX_CLKPWR_INT_ER);
-	__raw_writel(0, LPC32XX_CLKPWR_PIN_ER);
-
-	/*
-	 * Default wake activation polarities, all pin sources are low edge
-	 * triggered
-	 */
-	__raw_writel(LPC32XX_CLKPWR_INTSRC_TS_P_BIT |
-		LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT |
-		LPC32XX_CLKPWR_INTSRC_RTC_BIT,
-		LPC32XX_CLKPWR_INT_AP);
-	__raw_writel(0, LPC32XX_CLKPWR_PIN_AP);
-
-	/* Clear latched wake event states */
-	__raw_writel(__raw_readl(LPC32XX_CLKPWR_PIN_RS),
-		LPC32XX_CLKPWR_PIN_RS);
-	__raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS),
-		LPC32XX_CLKPWR_INT_RS);
-
-	of_irq_init(mic_of_match);
-
-	lpc32xx_mic_domain = irq_domain_add_legacy(lpc32xx_mic_np, NR_IRQS,
-						   0, 0, &irq_domain_simple_ops,
-						   NULL);
-	if (!lpc32xx_mic_domain)
-		panic("Unable to add MIC irq domain\n");
-
-	/* MIC SUBIRQx interrupts will route handling to the chain handlers */
-	irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
-	irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
-}
-- 
2.1.4

[PATCH v2 4/4] ARM: lpc32xx: remove legacy irq controller driver

[Sylvain Lemieux]

On Mon, 2016-04-25 at 04:00 +0300, Vladimir Zapolskiy wrote:
> New NXP LPC32xx irq chip driver is used instead of a legacy one.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> ---
> Changes from v1 to v2:
> * none, this is a new change
> 
>  arch/arm/mach-lpc32xx/Makefile |   2 +-
>  arch/arm/mach-lpc32xx/irq.c    | 477 -----------------------------------------
>  2 files changed, 1 insertion(+), 478 deletions(-)
>  delete mode 100644 arch/arm/mach-lpc32xx/irq.c
> 
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>