[PATCHv2 0/8] Addition of Altera Arria10 System Resource Chip

[PATCHv2 0/8] Addition of Altera Arria10 System Resource Chip

[tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx]

From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>

This patch series adds the SPI MultiFunction Device for the Altera System
Resource Chip for the Arria10 Developement Kit. The MFD implements GPIO
expansion on an Altera MAX5. The previous hwmon changes were removed since
they don't fit the hwmon requirements.

Thor Thayer (8):
  dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings
  MAINTAINERS: Add Altera Arria10 System Resource Chip
  mfd: altr_a10sr: Add Altera Arria10 DevKit System Resource Chip
  gpio: altera-a10sr: Add A10 System Resource Chip GPIO support.
  ARM: socfpga: dts: Add SPI Master1 for Arria10 SR chip
  ARM: socfpga: dts: Add Devkit A10-SR fields for Arria10
  ARM: socfpga: dts: Enable GPIO parent for Arria10 SR chip
  ARM: socfpga: dts: Add LED framework to A10-SR GPIO

 .../devicetree/bindings/mfd/altera-a10sr.txt       |   46 ++++++
 MAINTAINERS                                        |    7 +
 arch/arm/boot/dts/socfpga_arria10.dtsi             |   15 ++
 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi       |   49 ++++++
 drivers/gpio/Kconfig                               |    8 +
 drivers/gpio/Makefile                              |    1 +
 drivers/gpio/gpio-altera-a10sr.c                   |  140 ++++++++++++++++
 drivers/mfd/Kconfig                                |   11 ++
 drivers/mfd/Makefile                               |    2 +
 drivers/mfd/altera-a10sr.c                         |  169 ++++++++++++++++++++
 include/linux/mfd/altera-a10sr.h                   |   85 ++++++++++
 11 files changed, 533 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt
 create mode 100644 drivers/gpio/gpio-altera-a10sr.c
 create mode 100644 drivers/mfd/altera-a10sr.c
 create mode 100644 include/linux/mfd/altera-a10sr.h

-- 
1.7.9.5

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[PATCHv2 1/8] dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings

[tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx]

From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>

The Altera Arria10 Devkit System Resource chip is a Multi-Function
Device with a GPIO expander.

This patch adds documentation for the Altera A10-SR DT bindings.

Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
---
v2  Addition of IRQ controller bindings.
    Removal of hw_mon sub-device.
---
 .../devicetree/bindings/mfd/altera-a10sr.txt       |   46 ++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt

diff --git a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
new file mode 100644
index 0000000..ea151f2
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
@@ -0,0 +1,46 @@
+* Altera Arria10 Development Kit System Resource Chip
+
+Required parent device properties:
+- compatible		: "altr,a10sr"
+- spi-max-frequency	: Maximum SPI frequency.
+- reg			: The SPI Chip Select address for the Arria10
+			  System Resource chip
+- interrupt-parent	: The parent interrupt controller.
+- interrupts		: The interrupt line the device is connected to.
+- interrupt-controller	: Marks the device node as an interrupt controller.
+- #interrupt-cells	: The number of cells to describe an IRQ, should be 2.
+			    The first cell is the IRQ number.
+			    The second cell is the flags, encoded as trigger
+			    masks from ../interrupt-controller/interrupts.txt.
+
+The A10SR consists of these sub-devices:
+
+Device                   Description
+------                   ----------
+a10sr_gpio               GPIO Controller
+
+Arria10 GPIO
+Required Properties:
+- compatible        : Should be "altr,a10sr-gpio"
+- gpio-controller   : Marks the device node as a GPIO Controller.
+- #gpio-cells       : Should be two.  The first cell is the pin number and
+                      the second cell is used to specify flags.
+                      See ../gpio/gpio.txt for more information.
+
+Example:
+
+        resource-manager@0 {
+		compatible = "altr,a10sr";
+		reg = <0>;
+		spi-max-frequency = <100000>;
+		interrupt-parent = <&portb>;
+		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		a10sr_gpio: gpio-controller {
+			compatible = "altr,a10sr-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
-- 
1.7.9.5

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[PATCHv2 2/8] MAINTAINERS: Add Altera Arria10 System Resource Chip

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add maintainer for the Altera Arria10 Max5 System Resource chip files.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Lee Jones <lee.jones@linaro.org>i
---
v2  Remove altera-a10sr-hwmon.c file.
---
 MAINTAINERS |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 4f74a5f..7683240 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -607,6 +607,13 @@ L:	linux-gpio@vger.kernel.org
 S:	Maintained
 F:	drivers/gpio/gpio-altera.c
 
+ALTERA SYSTEM RESOURCE DRIVER FOR ARRIA10 DEVKIT
+M:	Thor Thayer <tthayer@opensource.altera.com>
+S:	Maintained
+F:	drivers/gpio/gpio-altera-a10sr.c
+F:	drivers/mfd/altera-a10sr.c
+F:	include/linux/mfd/altera-a10sr.h
+
 ALTERA TRIPLE SPEED ETHERNET DRIVER
 M:	Vince Bridgers <vbridger@opensource.altera.com>
 L:	netdev@vger.kernel.org
-- 
1.7.9.5

[PATCHv2 3/8] mfd: altr_a10sr: Add Altera Arria10 DevKit System Resource Chip

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add support for the Altera Arria10 Development Kit System Resource
chip which is implemented using a MAX5 as a external gpio extender
with the regmap framework over a SPI bus.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2	Remove hwmon from description.
	Change Altera to Intel in copyright header.
	Remove Copyright and Author from attribution
	Use devm_mfd_add_devices() and remove .remove()
	Fix Kconfig spacing.
---
 drivers/mfd/Kconfig              |   11 +++
 drivers/mfd/Makefile             |    2 +
 drivers/mfd/altera-a10sr.c       |  169 ++++++++++++++++++++++++++++++++++++++
 include/linux/mfd/altera-a10sr.h |   85 +++++++++++++++++++
 4 files changed, 267 insertions(+)
 create mode 100644 drivers/mfd/altera-a10sr.c
 create mode 100644 include/linux/mfd/altera-a10sr.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 1bcf601..00ec129 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -18,6 +18,17 @@ config MFD_CS5535
 	  This is the core driver for CS5535/CS5536 MFD functions.  This is
           necessary for using the board's GPIO and MFGPT functionality.
 
+config MFD_ALTERA_A10SR
+	bool "Altera Arria10 DevKit System Resource chip"
+	depends on ARCH_SOCFPGA && SPI_MASTER=y && OF
+	select REGMAP_SPI
+	select MFD_CORE
+	help
+	  Support for the Altera Arria10 DevKit MAX5 System Resource chip
+	  using the SPI interface. This driver provides common support for
+	  accessing the external gpio extender (LEDs & buttons) and
+	  power supply alarms (hwmon).
+
 config MFD_ACT8945A
 	tristate "Active-semi ACT8945A"
 	select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 42a66e1..2ba3ba3 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -205,3 +205,5 @@ intel-soc-pmic-objs		:= intel_soc_pmic_core.o intel_soc_pmic_crc.o
 intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC)	+= intel_soc_pmic_bxtwc.o
 obj-$(CONFIG_INTEL_SOC_PMIC)	+= intel-soc-pmic.o
 obj-$(CONFIG_MFD_MT6397)	+= mt6397-core.o
+
+obj-$(CONFIG_MFD_ALTERA_A10SR)	+= altera-a10sr.o
diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
new file mode 100644
index 0000000..c05aa4f
--- /dev/null
+++ b/drivers/mfd/altera-a10sr.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * SPI access for Altera Arria10 MAX5 System Resource Chip
+ *
+ * Adapted from DA9052
+ */
+
+#include <linux/mfd/altera-a10sr.h>
+#include <linux/mfd/core.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/spi/spi.h>
+
+static const struct mfd_cell altr_a10sr_subdev_info[] = {
+	{
+		.name = "altr_a10sr_gpio",
+		.of_compatible = "altr,a10sr-gpio",
+	},
+};
+
+static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case ALTR_A10SR_VERSION_READ:
+	case ALTR_A10SR_LED_REG:
+	case ALTR_A10SR_PBDSW_REG:
+	case ALTR_A10SR_PBDSW_IRQ_REG:
+	case ALTR_A10SR_PWR_GOOD1_REG:
+	case ALTR_A10SR_PWR_GOOD2_REG:
+	case ALTR_A10SR_PWR_GOOD3_REG:
+	case ALTR_A10SR_FMCAB_REG:
+	case ALTR_A10SR_HPS_RST_REG:
+	case ALTR_A10SR_USB_QSPI_REG:
+	case ALTR_A10SR_SFPA_REG:
+	case ALTR_A10SR_SFPB_REG:
+	case ALTR_A10SR_I2C_M_REG:
+	case ALTR_A10SR_WARM_RST_REG:
+	case ALTR_A10SR_WR_KEY_REG:
+	case ALTR_A10SR_PMBUS_REG:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case ALTR_A10SR_LED_REG:
+	case ALTR_A10SR_PBDSW_IRQ_REG:
+	case ALTR_A10SR_FMCAB_REG:
+	case ALTR_A10SR_HPS_RST_REG:
+	case ALTR_A10SR_USB_QSPI_REG:
+	case ALTR_A10SR_SFPA_REG:
+	case ALTR_A10SR_SFPB_REG:
+	case ALTR_A10SR_WARM_RST_REG:
+	case ALTR_A10SR_WR_KEY_REG:
+	case ALTR_A10SR_PMBUS_REG:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case ALTR_A10SR_PBDSW_REG:
+	case ALTR_A10SR_PBDSW_IRQ_REG:
+	case ALTR_A10SR_PWR_GOOD1_REG:
+	case ALTR_A10SR_PWR_GOOD2_REG:
+	case ALTR_A10SR_PWR_GOOD3_REG:
+	case ALTR_A10SR_HPS_RST_REG:
+	case ALTR_A10SR_I2C_M_REG:
+	case ALTR_A10SR_WARM_RST_REG:
+	case ALTR_A10SR_WR_KEY_REG:
+	case ALTR_A10SR_PMBUS_REG:
+		return true;
+	default:
+		return false;
+	}
+}
+
+const struct regmap_config altr_a10sr_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+
+	.cache_type = REGCACHE_NONE,
+
+	.use_single_rw = true,
+	.read_flag_mask = 1,
+	.write_flag_mask = 0,
+
+	.max_register = ALTR_A10SR_WR_KEY_REG,
+	.readable_reg = altr_a10sr_reg_readable,
+	.writeable_reg = altr_a10sr_reg_writeable,
+	.volatile_reg = altr_a10sr_reg_volatile,
+
+};
+
+static int altr_a10sr_spi_probe(struct spi_device *spi)
+{
+	int ret;
+	struct altr_a10sr *a10sr;
+
+	a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr),
+			     GFP_KERNEL);
+	if (!a10sr)
+		return -ENOMEM;
+
+	spi->mode = SPI_MODE_3;
+	spi->bits_per_word = 8;
+	spi_setup(spi);
+
+	a10sr->dev = &spi->dev;
+
+	spi_set_drvdata(spi, a10sr);
+
+	a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config);
+	if (IS_ERR(a10sr->regmap)) {
+		ret = PTR_ERR(a10sr->regmap);
+		dev_err(&spi->dev, "Failed to allocate register map: %d\n",
+			ret);
+		return ret;
+	}
+
+	ret = devm_mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO,
+				   altr_a10sr_subdev_info,
+				   ARRAY_SIZE(altr_a10sr_subdev_info),
+				   NULL, 0, NULL);
+	if (ret)
+		dev_err(a10sr->dev, "Failed to register sub-devices: %d\n",
+			ret);
+
+	return ret;
+}
+
+static const struct of_device_id altr_a10sr_spi_of_match[] = {
+	{ .compatible = "altr,a10sr" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, altr_a10sr_spi_of_match);
+
+static struct spi_driver altr_a10sr_spi_driver = {
+	.probe = altr_a10sr_spi_probe,
+	.driver = {
+		.name = "altr_a10sr",
+		.of_match_table = of_match_ptr(altr_a10sr_spi_of_match),
+	},
+};
+
+module_spi_driver(altr_a10sr_spi_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>");
+MODULE_DESCRIPTION("Altera Arria10 DevKit System Resource MFD Driver");
diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h
new file mode 100644
index 0000000..45a5e6e
--- /dev/null
+++ b/include/linux/mfd/altera-a10sr.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Declarations for Altera Arria10 MAX5 System Resource Chip
+ *
+ * Adapted from DA9052
+ */
+
+#ifndef __MFD_ALTERA_A10SR_H
+#define __MFD_ALTERA_A10SR_H
+
+#include <linux/completion.h>
+#include <linux/list.h>
+#include <linux/mfd/core.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+/* Write registers are always on even addresses */
+#define  WRITE_REG_MASK              0xFE
+/* Odd registers are always on odd addresses */
+#define  READ_REG_MASK               0x01
+
+#define ALTR_A10SR_BITS_PER_REGISTER  8
+/*
+ * To find the correct register, we divide the input GPIO by
+ * the number of GPIO in each register. We then need to multiply
+ * by 2 because the reads are at odd addresses.
+ */
+#define ALTR_A10SR_REG_OFFSET(X)     (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1)
+#define ALTR_A10SR_REG_BIT(X)        ((X) % ALTR_A10SR_BITS_PER_REGISTER)
+#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y))
+#define ALTR_A10SR_REG_BIT_MASK(X)   (1 << ALTR_A10SR_REG_BIT(X))
+
+/* Arria10 System Controller Register Defines */
+#define ALTR_A10SR_NOP                0x00    /* No Change */
+#define ALTR_A10SR_VERSION_READ       0x00    /* MAX5 Version Read */
+
+#define ALTR_A10SR_LED_REG            0x02    /* LED - Upper 4 bits */
+/* LED register Bit Definitions */
+#define ALTR_A10SR_LED_VALID_SHIFT        4       /* LED - Upper 4 bits valid */
+#define ALTR_A10SR_OUT_VALID_RANGE_LO     ALTR_A10SR_LED_VALID_SHIFT
+#define ALTR_A10SR_OUT_VALID_RANGE_HI     7
+
+#define ALTR_A10SR_PBDSW_REG          0x04    /* PB & DIP SW - Input only */
+#define ALTR_A10SR_PBDSW_IRQ_REG      0x06    /* PB & DIP SW Flag Clear */
+/* Pushbutton & DIP Switch Bit Definitions */
+#define ALTR_A10SR_IN_VALID_RANGE_LO      8
+#define ALTR_A10SR_IN_VALID_RANGE_HI      15
+
+#define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
+#define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
+#define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
+#define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable */
+#define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
+#define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */
+#define ALTR_A10SR_SFPA_REG           0x14    /* SFPA Control Reg */
+#define ALTR_A10SR_SFPB_REG           0x16    /* SFPB Control Reg */
+#define ALTR_A10SR_I2C_M_REG          0x18    /* I2C Master Select */
+#define ALTR_A10SR_WARM_RST_REG       0x1A    /* HPS Warm Reset */
+#define ALTR_A10SR_WR_KEY_REG         0x1C    /* HPS Warm Reset Key */
+#define ALTR_A10SR_PMBUS_REG          0x1E    /* HPS PM Bus */
+
+/**
+ * struct altr_a10sr - Altera Max5 MFD device private data structure
+ * @dev:  : this device
+ * @regmap: the regmap assigned to the parent device.
+ */
+struct altr_a10sr {
+	struct device *dev;
+	struct regmap *regmap;
+};
+
+#endif /* __MFD_ALTERA_A10SR_H */
-- 
1.7.9.5

[PATCHv2 4/8] gpio: altera-a10sr: Add A10 System Resource Chip GPIO support.

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add the GPIO functionality for the Altera Arria10 MAX5 System Resource
Chip. The A10 MAX5 has 12 bits of GPIO assigned to switches, buttons,
and LEDs as a GPIO extender on the SPI bus.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>i
---
v2	Change Altera to Intel in copyright header
---
 drivers/gpio/Kconfig             |    8 +++
 drivers/gpio/Makefile            |    1 +
 drivers/gpio/gpio-altera-a10sr.c |  140 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 149 insertions(+)
 create mode 100644 drivers/gpio/gpio-altera-a10sr.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 9244381..c41c74a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -786,6 +786,14 @@ config GPIO_ADP5520
 	  This option enables support for on-chip GPIO found
 	  on Analog Devices ADP5520 PMICs.
 
+config GPIO_ALTERA_A10SR
+	tristate "Altera Arria10 System Resource GPIO"
+	depends on MFD_ALTERA_A10SR
+	help
+	  Driver for Arria10 Development Kit GPIO expansion which
+	  includes reads of pushbuttons and DIP switches as well
+	  as writes to LEDs.
+
 config GPIO_ARIZONA
 	tristate "Wolfson Microelectronics Arizona class devices"
 	depends on MFD_ARIZONA
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 6e111fc..ac4b09b 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_GPIO_ADNP)		+= gpio-adnp.o
 obj-$(CONFIG_GPIO_ADP5520)	+= gpio-adp5520.o
 obj-$(CONFIG_GPIO_ADP5588)	+= gpio-adp5588.o
 obj-$(CONFIG_GPIO_ALTERA)  	+= gpio-altera.o
+obj-$(CONFIG_GPIO_ALTERA_A10SR)	+= gpio-altera-a10sr.o
 obj-$(CONFIG_GPIO_AMD8111)	+= gpio-amd8111.o
 obj-$(CONFIG_GPIO_AMDPT)	+= gpio-amdpt.o
 obj-$(CONFIG_GPIO_ARIZONA)	+= gpio-arizona.o
diff --git a/drivers/gpio/gpio-altera-a10sr.c b/drivers/gpio/gpio-altera-a10sr.c
new file mode 100644
index 0000000..8274f98
--- /dev/null
+++ b/drivers/gpio/gpio-altera-a10sr.c
@@ -0,0 +1,140 @@
+/*
+ *  Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * GPIO driver for  Altera Arria10 MAX5 System Resource Chip
+ *
+ * Adapted from gpio-tps65910.c
+ */
+
+#include <linux/gpio/driver.h>
+#include <linux/mfd/altera-a10sr.h>
+#include <linux/module.h>
+
+/**
+ * struct altr_a10sr_gpio - Altera Max5 GPIO device private data structure
+ * @gp:   : instance of the gpio_chip
+ * @regmap: the regmap from the parent device.
+ */
+struct altr_a10sr_gpio {
+	struct gpio_chip gp;
+	struct regmap *regmap;
+};
+
+static int altr_a10sr_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+	struct altr_a10sr_gpio *gpio = gpiochip_get_data(chip);
+	int ret, val;
+
+	ret = regmap_read(gpio->regmap, ALTR_A10SR_PBDSW_REG, &val);
+	if (ret < 0)
+		return ret;
+
+	return !!(val & BIT(offset - ALTR_A10SR_LED_VALID_SHIFT));
+}
+
+static void altr_a10sr_gpio_set(struct gpio_chip *chip, unsigned int offset,
+				int value)
+{
+	struct altr_a10sr_gpio *gpio = gpiochip_get_data(chip);
+
+	regmap_update_bits(gpio->regmap, ALTR_A10SR_LED_REG,
+			   BIT(ALTR_A10SR_LED_VALID_SHIFT + offset),
+			   value ? BIT(ALTR_A10SR_LED_VALID_SHIFT + offset)
+			   : 0);
+}
+
+static int altr_a10sr_gpio_direction_input(struct gpio_chip *gc,
+					   unsigned int nr)
+{
+	if (nr >= (ALTR_A10SR_IN_VALID_RANGE_LO - ALTR_A10SR_LED_VALID_SHIFT))
+		return 0;
+	return -EINVAL;
+}
+
+static int altr_a10sr_gpio_direction_output(struct gpio_chip *gc,
+					    unsigned int nr, int value)
+{
+	if (nr <= (ALTR_A10SR_OUT_VALID_RANGE_HI - ALTR_A10SR_LED_VALID_SHIFT))
+		return 0;
+	return -EINVAL;
+}
+
+static struct gpio_chip altr_a10sr_gc = {
+	.label = "altr_a10sr_gpio",
+	.owner = THIS_MODULE,
+	.get = altr_a10sr_gpio_get,
+	.set = altr_a10sr_gpio_set,
+	.direction_input = altr_a10sr_gpio_direction_input,
+	.direction_output = altr_a10sr_gpio_direction_output,
+	.can_sleep = true,
+	.ngpio = 12,
+	.base = -1,
+};
+
+static int altr_a10sr_gpio_probe(struct platform_device *pdev)
+{
+	struct altr_a10sr_gpio *gpio;
+	int ret;
+	struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
+
+	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
+	if (!gpio)
+		return -ENOMEM;
+
+	gpio->regmap = a10sr->regmap;
+
+	gpio->gp = altr_a10sr_gc;
+
+	gpio->gp.of_node = pdev->dev.of_node;
+
+	ret = devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
+		return ret;
+	}
+
+	platform_set_drvdata(pdev, gpio);
+
+	return 0;
+}
+
+static int altr_a10sr_gpio_remove(struct platform_device *pdev)
+{
+	struct altr_a10sr_gpio *gpio = platform_get_drvdata(pdev);
+
+	gpiochip_remove(&gpio->gp);
+
+	return 0;
+}
+
+static const struct of_device_id altr_a10sr_gpio_of_match[] = {
+	{ .compatible = "altr,a10sr-gpio" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, altr_a10sr_gpio_of_match);
+
+static struct platform_driver altr_a10sr_gpio_driver = {
+	.probe = altr_a10sr_gpio_probe,
+	.remove = altr_a10sr_gpio_remove,
+	.driver = {
+		.name	= "altr_a10sr_gpio",
+		.of_match_table = of_match_ptr(altr_a10sr_gpio_of_match),
+	},
+};
+module_platform_driver(altr_a10sr_gpio_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>");
+MODULE_DESCRIPTION("Altera Arria10 System Resource Chip GPIO");
-- 
1.7.9.5

[PATCHv2 5/8] ARM: socfpga: dts: Add SPI Master1 for Arria10 SR chip

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add the Altera Arria10 SPI Master Node in preparation for
the A10SR MFD node.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2:  No change
---
 arch/arm/boot/dts/socfpga_arria10.dtsi |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 17e81dc..e7b6c4a 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -567,6 +567,21 @@
 			status = "disabled";
 		};
 
+		spi1: spi@ffda5000 {
+			compatible = "snps,dw-apb-ssi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xffda5000 0x100>;
+			interrupts = <0 102 4>;
+			num-chipselect = <4>;
+			bus-num = <0>;
+			/*32bit_access;*/
+			tx-dma-channel = <&pdma 16>;
+			rx-dma-channel = <&pdma 17>;
+			clocks = <&spi_m_clk>;
+			status = "disabled";
+		};
+
 		sdr: sdr@ffc25000 {
 			compatible = "syscon";
 			reg = <0xffcfb100 0x80>;
-- 
1.7.9.5

[PATCHv2 6/8] ARM: socfpga: dts: Add Devkit A10-SR fields for Arria10

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add the Altera Arria10 System Resource node. This is a Multi-Function
device with GPIO expander support.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2  Addition of irq controller tags to match with bindings.
---
 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi |   21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 567df98..4638870 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -70,6 +70,27 @@
 	status = "okay";
 };
 
+&spi1 {
+	status = "okay";
+
+	resource-manager@0 {
+		compatible = "altr,a10sr";
+		reg = <0>;
+		spi-max-frequency = <100000>;
+		/* low-level active IRQ at GPIO1_5 */
+		interrupt-parent = <&portb>;
+		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		a10sr_gpio: gpio-controller {
+			compatible = "altr,a10sr-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+};
+
 &i2c1 {
 	speed-mode = <0>;
 	status = "okay";
-- 
1.7.9.5

[PATCHv2 7/8] ARM: socfpga: dts: Enable GPIO parent for Arria10 SR chip

[tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx]

From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>

Enable the Altera Arria10 GPIO parent for MFD operation.

Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
---
v2:  Added this change.
---
 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 4638870..2655fae 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -70,6 +70,10 @@
 	status = "okay";
 };
 
+&gpio1 {
+	status = "okay";
+};
+
 &spi1 {
 	status = "okay";
 
-- 
1.7.9.5

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[PATCHv2 8/8] ARM: socfpga: dts: Add LED framework to A10-SR GPIO

[tthayer]

From: Thor Thayer <tthayer@opensource.altera.com>

Add the LED framework to the Arria10 System Resource chip GPIO hooks.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2  No change
---
 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi |   24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 2655fae..3ff6321 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -31,6 +31,30 @@
 		reg = <0x0 0x40000000>; /* 1GB */
 	};
 
+	a10leds {
+		compatible = "gpio-leds";
+
+		a10sr_led0 {
+			label = "a10sr-led0";
+			gpios = <&a10sr_gpio 0 1>;
+		};
+
+		a10sr_led1 {
+			label = "a10sr-led1";
+			gpios = <&a10sr_gpio 1 1>;
+		};
+
+		a10sr_led2 {
+			label = "a10sr-led2";
+			gpios = <&a10sr_gpio 2 1>;
+		};
+
+		a10sr_led3 {
+			label = "a10sr-led3";
+			gpios = <&a10sr_gpio 3 1>;
+		};
+	};
+
 	soc {
 		clkmgr@ffd04000 {
 			clocks {
-- 
1.7.9.5

Re: [PATCHv2 1/8] dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings

[Rob Herring]

On Thu, Jun 02, 2016 at 12:52:21PM -0500, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
> 
> The Altera Arria10 Devkit System Resource chip is a Multi-Function
> Device with a GPIO expander.
> 
> This patch adds documentation for the Altera A10-SR DT bindings.
> 
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
> v2  Addition of IRQ controller bindings.
>     Removal of hw_mon sub-device.
> ---
>  .../devicetree/bindings/mfd/altera-a10sr.txt       |   46 ++++++++++++++++++++
>  1 file changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCHv2 2/8] MAINTAINERS: Add Altera Arria10 System Resource Chip

[Lee Jones]

On Thu, 02 Jun 2016, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:

> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> 
> Add maintainer for the Altera Arria10 Max5 System Resource chip files.
> 
> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> Acked-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>i
> ---
> v2  Remove altera-a10sr-hwmon.c file.
> ---
>  MAINTAINERS |    7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4f74a5f..7683240 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -607,6 +607,13 @@ L:	linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>  S:	Maintained
>  F:	drivers/gpio/gpio-altera.c
>  
> +ALTERA SYSTEM RESOURCE DRIVER FOR ARRIA10 DEVKIT
> +M:	Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> +S:	Maintained
> +F:	drivers/gpio/gpio-altera-a10sr.c
> +F:	drivers/mfd/altera-a10sr.c
> +F:	include/linux/mfd/altera-a10sr.h

When will you upstream the other drivers?

>  ALTERA TRIPLE SPEED ETHERNET DRIVER
>  M:	Vince Bridgers <vbridger-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>  L:	netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org

-- 
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Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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Re: [PATCHv2 1/8] dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings

[Lee Jones]

On Thu, 02 Jun 2016, tthayer@opensource.altera.com wrote:

> From: Thor Thayer <tthayer@opensource.altera.com>
> 
> The Altera Arria10 Devkit System Resource chip is a Multi-Function
> Device with a GPIO expander.
> 
> This patch adds documentation for the Altera A10-SR DT bindings.
> 
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
> v2  Addition of IRQ controller bindings.
>     Removal of hw_mon sub-device.
> ---
>  .../devicetree/bindings/mfd/altera-a10sr.txt       |   46 ++++++++++++++++++++
>  1 file changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt

Applied, thanks.

> diff --git a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
> new file mode 100644
> index 0000000..ea151f2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
> @@ -0,0 +1,46 @@
> +* Altera Arria10 Development Kit System Resource Chip
> +
> +Required parent device properties:
> +- compatible		: "altr,a10sr"
> +- spi-max-frequency	: Maximum SPI frequency.
> +- reg			: The SPI Chip Select address for the Arria10
> +			  System Resource chip
> +- interrupt-parent	: The parent interrupt controller.
> +- interrupts		: The interrupt line the device is connected to.
> +- interrupt-controller	: Marks the device node as an interrupt controller.
> +- #interrupt-cells	: The number of cells to describe an IRQ, should be 2.
> +			    The first cell is the IRQ number.
> +			    The second cell is the flags, encoded as trigger
> +			    masks from ../interrupt-controller/interrupts.txt.
> +
> +The A10SR consists of these sub-devices:
> +
> +Device                   Description
> +------                   ----------
> +a10sr_gpio               GPIO Controller
> +
> +Arria10 GPIO
> +Required Properties:
> +- compatible        : Should be "altr,a10sr-gpio"
> +- gpio-controller   : Marks the device node as a GPIO Controller.
> +- #gpio-cells       : Should be two.  The first cell is the pin number and
> +                      the second cell is used to specify flags.
> +                      See ../gpio/gpio.txt for more information.
> +
> +Example:
> +
> +        resource-manager@0 {
> +		compatible = "altr,a10sr";
> +		reg = <0>;
> +		spi-max-frequency = <100000>;
> +		interrupt-parent = <&portb>;
> +		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +
> +		a10sr_gpio: gpio-controller {
> +			compatible = "altr,a10sr-gpio";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +	};

-- 
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Linaro STMicroelectronics Landing Team Lead
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Re: [PATCHv2 3/8] mfd: altr_a10sr: Add Altera Arria10 DevKit System Resource Chip

[Lee Jones]

On Thu, 02 Jun 2016, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:

> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> 
> Add support for the Altera Arria10 Development Kit System Resource
> chip which is implemented using a MAX5 as a external gpio extender
> with the regmap framework over a SPI bus.
> 
> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> ---
> v2	Remove hwmon from description.
> 	Change Altera to Intel in copyright header.
> 	Remove Copyright and Author from attribution
> 	Use devm_mfd_add_devices() and remove .remove()
> 	Fix Kconfig spacing.
> ---
>  drivers/mfd/Kconfig              |   11 +++
>  drivers/mfd/Makefile             |    2 +
>  drivers/mfd/altera-a10sr.c       |  169 ++++++++++++++++++++++++++++++++++++++
>  include/linux/mfd/altera-a10sr.h |   85 +++++++++++++++++++
>  4 files changed, 267 insertions(+)
>  create mode 100644 drivers/mfd/altera-a10sr.c
>  create mode 100644 include/linux/mfd/altera-a10sr.h

Applied, thanks.

> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index 1bcf601..00ec129 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -18,6 +18,17 @@ config MFD_CS5535
>  	  This is the core driver for CS5535/CS5536 MFD functions.  This is
>            necessary for using the board's GPIO and MFGPT functionality.
>  
> +config MFD_ALTERA_A10SR
> +	bool "Altera Arria10 DevKit System Resource chip"
> +	depends on ARCH_SOCFPGA && SPI_MASTER=y && OF
> +	select REGMAP_SPI
> +	select MFD_CORE
> +	help
> +	  Support for the Altera Arria10 DevKit MAX5 System Resource chip
> +	  using the SPI interface. This driver provides common support for
> +	  accessing the external gpio extender (LEDs & buttons) and
> +	  power supply alarms (hwmon).
> +
>  config MFD_ACT8945A
>  	tristate "Active-semi ACT8945A"
>  	select MFD_CORE
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 42a66e1..2ba3ba3 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -205,3 +205,5 @@ intel-soc-pmic-objs		:= intel_soc_pmic_core.o intel_soc_pmic_crc.o
>  intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC)	+= intel_soc_pmic_bxtwc.o
>  obj-$(CONFIG_INTEL_SOC_PMIC)	+= intel-soc-pmic.o
>  obj-$(CONFIG_MFD_MT6397)	+= mt6397-core.o
> +
> +obj-$(CONFIG_MFD_ALTERA_A10SR)	+= altera-a10sr.o
> diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
> new file mode 100644
> index 0000000..c05aa4f
> --- /dev/null
> +++ b/drivers/mfd/altera-a10sr.c
> @@ -0,0 +1,169 @@
> +/*
> + * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + * SPI access for Altera Arria10 MAX5 System Resource Chip
> + *
> + * Adapted from DA9052
> + */
> +
> +#include <linux/mfd/altera-a10sr.h>
> +#include <linux/mfd/core.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/spi/spi.h>
> +
> +static const struct mfd_cell altr_a10sr_subdev_info[] = {
> +	{
> +		.name = "altr_a10sr_gpio",
> +		.of_compatible = "altr,a10sr-gpio",
> +	},
> +};
> +
> +static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
> +{
> +	switch (reg) {
> +	case ALTR_A10SR_VERSION_READ:
> +	case ALTR_A10SR_LED_REG:
> +	case ALTR_A10SR_PBDSW_REG:
> +	case ALTR_A10SR_PBDSW_IRQ_REG:
> +	case ALTR_A10SR_PWR_GOOD1_REG:
> +	case ALTR_A10SR_PWR_GOOD2_REG:
> +	case ALTR_A10SR_PWR_GOOD3_REG:
> +	case ALTR_A10SR_FMCAB_REG:
> +	case ALTR_A10SR_HPS_RST_REG:
> +	case ALTR_A10SR_USB_QSPI_REG:
> +	case ALTR_A10SR_SFPA_REG:
> +	case ALTR_A10SR_SFPB_REG:
> +	case ALTR_A10SR_I2C_M_REG:
> +	case ALTR_A10SR_WARM_RST_REG:
> +	case ALTR_A10SR_WR_KEY_REG:
> +	case ALTR_A10SR_PMBUS_REG:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg)
> +{
> +	switch (reg) {
> +	case ALTR_A10SR_LED_REG:
> +	case ALTR_A10SR_PBDSW_IRQ_REG:
> +	case ALTR_A10SR_FMCAB_REG:
> +	case ALTR_A10SR_HPS_RST_REG:
> +	case ALTR_A10SR_USB_QSPI_REG:
> +	case ALTR_A10SR_SFPA_REG:
> +	case ALTR_A10SR_SFPB_REG:
> +	case ALTR_A10SR_WARM_RST_REG:
> +	case ALTR_A10SR_WR_KEY_REG:
> +	case ALTR_A10SR_PMBUS_REG:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg)
> +{
> +	switch (reg) {
> +	case ALTR_A10SR_PBDSW_REG:
> +	case ALTR_A10SR_PBDSW_IRQ_REG:
> +	case ALTR_A10SR_PWR_GOOD1_REG:
> +	case ALTR_A10SR_PWR_GOOD2_REG:
> +	case ALTR_A10SR_PWR_GOOD3_REG:
> +	case ALTR_A10SR_HPS_RST_REG:
> +	case ALTR_A10SR_I2C_M_REG:
> +	case ALTR_A10SR_WARM_RST_REG:
> +	case ALTR_A10SR_WR_KEY_REG:
> +	case ALTR_A10SR_PMBUS_REG:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +const struct regmap_config altr_a10sr_regmap_config = {
> +	.reg_bits = 8,
> +	.val_bits = 8,
> +
> +	.cache_type = REGCACHE_NONE,
> +
> +	.use_single_rw = true,
> +	.read_flag_mask = 1,
> +	.write_flag_mask = 0,
> +
> +	.max_register = ALTR_A10SR_WR_KEY_REG,
> +	.readable_reg = altr_a10sr_reg_readable,
> +	.writeable_reg = altr_a10sr_reg_writeable,
> +	.volatile_reg = altr_a10sr_reg_volatile,
> +
> +};
> +
> +static int altr_a10sr_spi_probe(struct spi_device *spi)
> +{
> +	int ret;
> +	struct altr_a10sr *a10sr;
> +
> +	a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr),
> +			     GFP_KERNEL);
> +	if (!a10sr)
> +		return -ENOMEM;
> +
> +	spi->mode = SPI_MODE_3;
> +	spi->bits_per_word = 8;
> +	spi_setup(spi);
> +
> +	a10sr->dev = &spi->dev;
> +
> +	spi_set_drvdata(spi, a10sr);
> +
> +	a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config);
> +	if (IS_ERR(a10sr->regmap)) {
> +		ret = PTR_ERR(a10sr->regmap);
> +		dev_err(&spi->dev, "Failed to allocate register map: %d\n",
> +			ret);
> +		return ret;
> +	}
> +
> +	ret = devm_mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO,
> +				   altr_a10sr_subdev_info,
> +				   ARRAY_SIZE(altr_a10sr_subdev_info),
> +				   NULL, 0, NULL);
> +	if (ret)
> +		dev_err(a10sr->dev, "Failed to register sub-devices: %d\n",
> +			ret);
> +
> +	return ret;
> +}
> +
> +static const struct of_device_id altr_a10sr_spi_of_match[] = {
> +	{ .compatible = "altr,a10sr" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, altr_a10sr_spi_of_match);
> +
> +static struct spi_driver altr_a10sr_spi_driver = {
> +	.probe = altr_a10sr_spi_probe,
> +	.driver = {
> +		.name = "altr_a10sr",
> +		.of_match_table = of_match_ptr(altr_a10sr_spi_of_match),
> +	},
> +};
> +
> +module_spi_driver(altr_a10sr_spi_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>");
> +MODULE_DESCRIPTION("Altera Arria10 DevKit System Resource MFD Driver");
> diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h
> new file mode 100644
> index 0000000..45a5e6e
> --- /dev/null
> +++ b/include/linux/mfd/altera-a10sr.h
> @@ -0,0 +1,85 @@
> +/*
> + * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + * Declarations for Altera Arria10 MAX5 System Resource Chip
> + *
> + * Adapted from DA9052
> + */
> +
> +#ifndef __MFD_ALTERA_A10SR_H
> +#define __MFD_ALTERA_A10SR_H
> +
> +#include <linux/completion.h>
> +#include <linux/list.h>
> +#include <linux/mfd/core.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +
> +/* Write registers are always on even addresses */
> +#define  WRITE_REG_MASK              0xFE
> +/* Odd registers are always on odd addresses */
> +#define  READ_REG_MASK               0x01
> +
> +#define ALTR_A10SR_BITS_PER_REGISTER  8
> +/*
> + * To find the correct register, we divide the input GPIO by
> + * the number of GPIO in each register. We then need to multiply
> + * by 2 because the reads are at odd addresses.
> + */
> +#define ALTR_A10SR_REG_OFFSET(X)     (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1)
> +#define ALTR_A10SR_REG_BIT(X)        ((X) % ALTR_A10SR_BITS_PER_REGISTER)
> +#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y))
> +#define ALTR_A10SR_REG_BIT_MASK(X)   (1 << ALTR_A10SR_REG_BIT(X))
> +
> +/* Arria10 System Controller Register Defines */
> +#define ALTR_A10SR_NOP                0x00    /* No Change */
> +#define ALTR_A10SR_VERSION_READ       0x00    /* MAX5 Version Read */
> +
> +#define ALTR_A10SR_LED_REG            0x02    /* LED - Upper 4 bits */
> +/* LED register Bit Definitions */
> +#define ALTR_A10SR_LED_VALID_SHIFT        4       /* LED - Upper 4 bits valid */
> +#define ALTR_A10SR_OUT_VALID_RANGE_LO     ALTR_A10SR_LED_VALID_SHIFT
> +#define ALTR_A10SR_OUT_VALID_RANGE_HI     7
> +
> +#define ALTR_A10SR_PBDSW_REG          0x04    /* PB & DIP SW - Input only */
> +#define ALTR_A10SR_PBDSW_IRQ_REG      0x06    /* PB & DIP SW Flag Clear */
> +/* Pushbutton & DIP Switch Bit Definitions */
> +#define ALTR_A10SR_IN_VALID_RANGE_LO      8
> +#define ALTR_A10SR_IN_VALID_RANGE_HI      15
> +
> +#define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
> +#define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
> +#define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
> +#define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable */
> +#define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
> +#define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */
> +#define ALTR_A10SR_SFPA_REG           0x14    /* SFPA Control Reg */
> +#define ALTR_A10SR_SFPB_REG           0x16    /* SFPB Control Reg */
> +#define ALTR_A10SR_I2C_M_REG          0x18    /* I2C Master Select */
> +#define ALTR_A10SR_WARM_RST_REG       0x1A    /* HPS Warm Reset */
> +#define ALTR_A10SR_WR_KEY_REG         0x1C    /* HPS Warm Reset Key */
> +#define ALTR_A10SR_PMBUS_REG          0x1E    /* HPS PM Bus */
> +
> +/**
> + * struct altr_a10sr - Altera Max5 MFD device private data structure
> + * @dev:  : this device
> + * @regmap: the regmap assigned to the parent device.
> + */
> +struct altr_a10sr {
> +	struct device *dev;
> +	struct regmap *regmap;
> +};
> +
> +#endif /* __MFD_ALTERA_A10SR_H */

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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Re: [PATCHv2 2/8] MAINTAINERS: Add Altera Arria10 System Resource Chip

[Thor Thayer]

Hi Lee,

On 06/10/2016 09:47 AM, Lee Jones wrote:
> On Thu, 02 Jun 2016, tthayer@opensource.altera.com wrote:
>
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> Add maintainer for the Altera Arria10 Max5 System Resource chip files.
>>
>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>> Acked-by: Lee Jones <lee.jones@linaro.org>i
>> ---
>> v2  Remove altera-a10sr-hwmon.c file.
>> ---
>>   MAINTAINERS |    7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 4f74a5f..7683240 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -607,6 +607,13 @@ L:	linux-gpio@vger.kernel.org
>>   S:	Maintained
>>   F:	drivers/gpio/gpio-altera.c
>>
>> +ALTERA SYSTEM RESOURCE DRIVER FOR ARRIA10 DEVKIT
>> +M:	Thor Thayer <tthayer@opensource.altera.com>
>> +S:	Maintained
>> +F:	drivers/gpio/gpio-altera-a10sr.c
>> +F:	drivers/mfd/altera-a10sr.c
>> +F:	include/linux/mfd/altera-a10sr.h
>
> When will you upstream the other drivers?
>
I'm finishing up some EDAC drivers right now then I'll start looking at 
adding the other drivers. I should have something in August because of 
vacation interruptions.

Thanks again!

>>   ALTERA TRIPLE SPEED ETHERNET DRIVER
>>   M:	Vince Bridgers <vbridger@opensource.altera.com>
>>   L:	netdev@vger.kernel.org
>

Re: [PATCHv2 4/8] gpio: altera-a10sr: Add A10 System Resource Chip GPIO support.

[Thor Thayer]

Hi Linus,

On 06/02/2016 12:52 PM, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>
> Add the GPIO functionality for the Altera Arria10 MAX5 System Resource
> Chip. The A10 MAX5 has 12 bits of GPIO assigned to switches, buttons,
> and LEDs as a GPIO extender on the SPI bus.
>
> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> Acked-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>i
> ---
> v2	Change Altera to Intel in copyright header
> ---

It appears this patch was not included in the changes upstreamed. You 
had added a note when you ACKed version 1 that Lee could queue this (see 
https://patchwork.kernel.org/patch/8912831/) but I didn't include that 
note in this series.

Can this be added to the GPIO queue now?

Thanks,

Thor
>  drivers/gpio/Kconfig             |    8 +++
>  drivers/gpio/Makefile            |    1 +
>  drivers/gpio/gpio-altera-a10sr.c |  140 ++++++++++++++++++++++++++++++++++++++
>  3 files changed, 149 insertions(+)
>  create mode 100644 drivers/gpio/gpio-altera-a10sr.c
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index 9244381..c41c74a 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -786,6 +786,14 @@ config GPIO_ADP5520
>  	  This option enables support for on-chip GPIO found
>  	  on Analog Devices ADP5520 PMICs.
>
> +config GPIO_ALTERA_A10SR
> +	tristate "Altera Arria10 System Resource GPIO"
> +	depends on MFD_ALTERA_A10SR
> +	help
> +	  Driver for Arria10 Development Kit GPIO expansion which
> +	  includes reads of pushbuttons and DIP switches as well
> +	  as writes to LEDs.
> +
>  config GPIO_ARIZONA
>  	tristate "Wolfson Microelectronics Arizona class devices"
>  	depends on MFD_ARIZONA
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 6e111fc..ac4b09b 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -24,6 +24,7 @@ obj-$(CONFIG_GPIO_ADNP)		+= gpio-adnp.o
>  obj-$(CONFIG_GPIO_ADP5520)	+= gpio-adp5520.o
>  obj-$(CONFIG_GPIO_ADP5588)	+= gpio-adp5588.o
>  obj-$(CONFIG_GPIO_ALTERA)  	+= gpio-altera.o
> +obj-$(CONFIG_GPIO_ALTERA_A10SR)	+= gpio-altera-a10sr.o
>  obj-$(CONFIG_GPIO_AMD8111)	+= gpio-amd8111.o
>  obj-$(CONFIG_GPIO_AMDPT)	+= gpio-amdpt.o
>  obj-$(CONFIG_GPIO_ARIZONA)	+= gpio-arizona.o
> diff --git a/drivers/gpio/gpio-altera-a10sr.c b/drivers/gpio/gpio-altera-a10sr.c
> new file mode 100644
> index 0000000..8274f98
> --- /dev/null
> +++ b/drivers/gpio/gpio-altera-a10sr.c
> @@ -0,0 +1,140 @@
> +/*
> + *  Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + *
> + * GPIO driver for  Altera Arria10 MAX5 System Resource Chip
> + *
> + * Adapted from gpio-tps65910.c
> + */
> +
> +#include <linux/gpio/driver.h>
> +#include <linux/mfd/altera-a10sr.h>
> +#include <linux/module.h>
> +
> +/**
> + * struct altr_a10sr_gpio - Altera Max5 GPIO device private data structure
> + * @gp:   : instance of the gpio_chip
> + * @regmap: the regmap from the parent device.
> + */
> +struct altr_a10sr_gpio {
> +	struct gpio_chip gp;
> +	struct regmap *regmap;
> +};
> +
> +static int altr_a10sr_gpio_get(struct gpio_chip *chip, unsigned int offset)
> +{
> +	struct altr_a10sr_gpio *gpio = gpiochip_get_data(chip);
> +	int ret, val;
> +
> +	ret = regmap_read(gpio->regmap, ALTR_A10SR_PBDSW_REG, &val);
> +	if (ret < 0)
> +		return ret;
> +
> +	return !!(val & BIT(offset - ALTR_A10SR_LED_VALID_SHIFT));
> +}
> +
> +static void altr_a10sr_gpio_set(struct gpio_chip *chip, unsigned int offset,
> +				int value)
> +{
> +	struct altr_a10sr_gpio *gpio = gpiochip_get_data(chip);
> +
> +	regmap_update_bits(gpio->regmap, ALTR_A10SR_LED_REG,
> +			   BIT(ALTR_A10SR_LED_VALID_SHIFT + offset),
> +			   value ? BIT(ALTR_A10SR_LED_VALID_SHIFT + offset)
> +			   : 0);
> +}
> +
> +static int altr_a10sr_gpio_direction_input(struct gpio_chip *gc,
> +					   unsigned int nr)
> +{
> +	if (nr >= (ALTR_A10SR_IN_VALID_RANGE_LO - ALTR_A10SR_LED_VALID_SHIFT))
> +		return 0;
> +	return -EINVAL;
> +}
> +
> +static int altr_a10sr_gpio_direction_output(struct gpio_chip *gc,
> +					    unsigned int nr, int value)
> +{
> +	if (nr <= (ALTR_A10SR_OUT_VALID_RANGE_HI - ALTR_A10SR_LED_VALID_SHIFT))
> +		return 0;
> +	return -EINVAL;
> +}
> +
> +static struct gpio_chip altr_a10sr_gc = {
> +	.label = "altr_a10sr_gpio",
> +	.owner = THIS_MODULE,
> +	.get = altr_a10sr_gpio_get,
> +	.set = altr_a10sr_gpio_set,
> +	.direction_input = altr_a10sr_gpio_direction_input,
> +	.direction_output = altr_a10sr_gpio_direction_output,
> +	.can_sleep = true,
> +	.ngpio = 12,
> +	.base = -1,
> +};
> +
> +static int altr_a10sr_gpio_probe(struct platform_device *pdev)
> +{
> +	struct altr_a10sr_gpio *gpio;
> +	int ret;
> +	struct altr_a10sr *a10sr = dev_get_drvdata(pdev->dev.parent);
> +
> +	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
> +	if (!gpio)
> +		return -ENOMEM;
> +
> +	gpio->regmap = a10sr->regmap;
> +
> +	gpio->gp = altr_a10sr_gc;
> +
> +	gpio->gp.of_node = pdev->dev.of_node;
> +
> +	ret = devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
> +		return ret;
> +	}
> +
> +	platform_set_drvdata(pdev, gpio);
> +
> +	return 0;
> +}
> +
> +static int altr_a10sr_gpio_remove(struct platform_device *pdev)
> +{
> +	struct altr_a10sr_gpio *gpio = platform_get_drvdata(pdev);
> +
> +	gpiochip_remove(&gpio->gp);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id altr_a10sr_gpio_of_match[] = {
> +	{ .compatible = "altr,a10sr-gpio" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, altr_a10sr_gpio_of_match);
> +
> +static struct platform_driver altr_a10sr_gpio_driver = {
> +	.probe = altr_a10sr_gpio_probe,
> +	.remove = altr_a10sr_gpio_remove,
> +	.driver = {
> +		.name	= "altr_a10sr_gpio",
> +		.of_match_table = of_match_ptr(altr_a10sr_gpio_of_match),
> +	},
> +};
> +module_platform_driver(altr_a10sr_gpio_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>");
> +MODULE_DESCRIPTION("Altera Arria10 System Resource Chip GPIO");
>
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Re: [PATCHv2 1/8] dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings

[Thor Thayer]

Hi Lee,

On 06/10/2016 09:47 AM, Lee Jones wrote:
> On Thu, 02 Jun 2016, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
>
>> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>>
>> The Altera Arria10 Devkit System Resource chip is a Multi-Function
>> Device with a GPIO expander.
>>
>> This patch adds documentation for the Altera A10-SR DT bindings.
>>
>> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>> ---
>> v2  Addition of IRQ controller bindings.
>>     Removal of hw_mon sub-device.
>> ---
>>  .../devicetree/bindings/mfd/altera-a10sr.txt       |   46 ++++++++++++++++++++
>>  1 file changed, 46 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt
>
> Applied, thanks.

For some reason, I'm not seeing this in the 4.8 tree with the other mfd 
additions. Do I need to submit it to a different tree?

Thanks,

Thor
>
>> diff --git a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
>> new file mode 100644
>> index 0000000..ea151f2
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
>> @@ -0,0 +1,46 @@
>> +* Altera Arria10 Development Kit System Resource Chip
>> +
>> +Required parent device properties:
>> +- compatible		: "altr,a10sr"
>> +- spi-max-frequency	: Maximum SPI frequency.
>> +- reg			: The SPI Chip Select address for the Arria10
>> +			  System Resource chip
>> +- interrupt-parent	: The parent interrupt controller.
>> +- interrupts		: The interrupt line the device is connected to.
>> +- interrupt-controller	: Marks the device node as an interrupt controller.
>> +- #interrupt-cells	: The number of cells to describe an IRQ, should be 2.
>> +			    The first cell is the IRQ number.
>> +			    The second cell is the flags, encoded as trigger
>> +			    masks from ../interrupt-controller/interrupts.txt.
>> +
>> +The A10SR consists of these sub-devices:
>> +
>> +Device                   Description
>> +------                   ----------
>> +a10sr_gpio               GPIO Controller
>> +
>> +Arria10 GPIO
>> +Required Properties:
>> +- compatible        : Should be "altr,a10sr-gpio"
>> +- gpio-controller   : Marks the device node as a GPIO Controller.
>> +- #gpio-cells       : Should be two.  The first cell is the pin number and
>> +                      the second cell is used to specify flags.
>> +                      See ../gpio/gpio.txt for more information.
>> +
>> +Example:
>> +
>> +        resource-manager@0 {
>> +		compatible = "altr,a10sr";
>> +		reg = <0>;
>> +		spi-max-frequency = <100000>;
>> +		interrupt-parent = <&portb>;
>> +		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
>> +		interrupt-controller;
>> +		#interrupt-cells = <2>;
>> +
>> +		a10sr_gpio: gpio-controller {
>> +			compatible = "altr,a10sr-gpio";
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +		};
>> +	};
>
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Re: [PATCHv2 5/8] ARM: socfpga: dts: Add SPI Master1 for Arria10 SR chip

[Thor Thayer]

Hi Dihn,

On 06/02/2016 12:52 PM, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>
> Add the Altera Arria10 SPI Master Node in preparation for
> the A10SR MFD node.
>
> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> ---
> v2:  No change
> ---
>  arch/arm/boot/dts/socfpga_arria10.dtsi |   15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
> index 17e81dc..e7b6c4a 100644
> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
> @@ -567,6 +567,21 @@
>  			status = "disabled";
>  		};
>
> +		spi1: spi@ffda5000 {
> +			compatible = "snps,dw-apb-ssi";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0xffda5000 0x100>;
> +			interrupts = <0 102 4>;
> +			num-chipselect = <4>;
> +			bus-num = <0>;
> +			/*32bit_access;*/
> +			tx-dma-channel = <&pdma 16>;
> +			rx-dma-channel = <&pdma 17>;
> +			clocks = <&spi_m_clk>;
> +			status = "disabled";
> +		};
> +
>  		sdr: sdr@ffc25000 {
>  			compatible = "syscon";
>  			reg = <0xffcfb100 0x80>;
>
I lost track of this patch. Any comments on this patch?
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Re: [PATCHv2 5/8] ARM: socfpga: dts: Add SPI Master1 for Arria10 SR chip

[Dinh Nguyen]

On Mon, 10 Oct 2016, Thor Thayer wrote:

> Hi Dihn,
> 
> On 06/02/2016 12:52 PM, tthayer@opensource.altera.com wrote:
> > From: Thor Thayer <tthayer@opensource.altera.com>
> > 
> > Add the Altera Arria10 SPI Master Node in preparation for
> > the A10SR MFD node.
> > 
> > Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> > ---
> > v2:  No change
> > ---
> >  arch/arm/boot/dts/socfpga_arria10.dtsi |   15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> > 
> > 
> I lost track of this patch. Any comments on this patch?
> 

Sorry about that, I missed it too.

Applied.

BR,
Dinh

Re: [PATCHv2 6/8] ARM: socfpga: dts: Add Devkit A10-SR fields for Arria10

[Dinh Nguyen]

On Thu, 2 Jun 2016, tthayer@opensource.altera.com wrote:

> From: Thor Thayer <tthayer@opensource.altera.com>
> 
> Add the Altera Arria10 System Resource node. This is a Multi-Function
> device with GPIO expander support.
> 
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
> v2  Addition of irq controller tags to match with bindings.
> ---
>  arch/arm/boot/dts/socfpga_arria10_socdk.dtsi |   21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)

Applied.

BR,
Dinh

Re: [PATCHv2 7/8] ARM: socfpga: dts: Enable GPIO parent for Arria10 SR chip

[Dinh Nguyen]

On Thu, 2 Jun 2016, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:

> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> 
> Enable the Altera Arria10 GPIO parent for MFD operation.
> 
> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> ---
> v2:  Added this change.
> ---
>  arch/arm/boot/dts/socfpga_arria10_socdk.dtsi |    4 ++++
>  1 file changed, 4 insertions(+)

Applied.

BR,
Dinh
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Re: [PATCHv2 8/8] ARM: socfpga: dts: Add LED framework to A10-SR GPIO

[Dinh Nguyen]

On Thu, 2 Jun 2016, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:

> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> 
> Add the LED framework to the Arria10 System Resource chip GPIO hooks.
> 
> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> ---
> v2  No change
> ---
>  arch/arm/boot/dts/socfpga_arria10_socdk.dtsi |   24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
>

Applied.
 
BR,
Dinh
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Re: [PATCHv2 1/8] dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings

[Lee Jones]

On Mon, 10 Oct 2016, Thor Thayer wrote:

> Hi Lee,
> 
> On 06/10/2016 09:47 AM, Lee Jones wrote:
> > On Thu, 02 Jun 2016, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
> > 
> > > From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> > > 
> > > The Altera Arria10 Devkit System Resource chip is a Multi-Function
> > > Device with a GPIO expander.
> > > 
> > > This patch adds documentation for the Altera A10-SR DT bindings.
> > > 
> > > Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> > > ---
> > > v2  Addition of IRQ controller bindings.
> > >     Removal of hw_mon sub-device.
> > > ---
> > >  .../devicetree/bindings/mfd/altera-a10sr.txt       |   46 ++++++++++++++++++++
> > >  1 file changed, 46 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt
> > 
> > Applied, thanks.
> 
> For some reason, I'm not seeing this in the 4.8 tree with the other mfd
> additions. Do I need to submit it to a different tree?

No, it looks like this one was dropped for some reason.

Reapplying now.

> > > diff --git a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
> > > new file mode 100644
> > > index 0000000..ea151f2
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt
> > > @@ -0,0 +1,46 @@
> > > +* Altera Arria10 Development Kit System Resource Chip
> > > +
> > > +Required parent device properties:
> > > +- compatible		: "altr,a10sr"
> > > +- spi-max-frequency	: Maximum SPI frequency.
> > > +- reg			: The SPI Chip Select address for the Arria10
> > > +			  System Resource chip
> > > +- interrupt-parent	: The parent interrupt controller.
> > > +- interrupts		: The interrupt line the device is connected to.
> > > +- interrupt-controller	: Marks the device node as an interrupt controller.
> > > +- #interrupt-cells	: The number of cells to describe an IRQ, should be 2.
> > > +			    The first cell is the IRQ number.
> > > +			    The second cell is the flags, encoded as trigger
> > > +			    masks from ../interrupt-controller/interrupts.txt.
> > > +
> > > +The A10SR consists of these sub-devices:
> > > +
> > > +Device                   Description
> > > +------                   ----------
> > > +a10sr_gpio               GPIO Controller
> > > +
> > > +Arria10 GPIO
> > > +Required Properties:
> > > +- compatible        : Should be "altr,a10sr-gpio"
> > > +- gpio-controller   : Marks the device node as a GPIO Controller.
> > > +- #gpio-cells       : Should be two.  The first cell is the pin number and
> > > +                      the second cell is used to specify flags.
> > > +                      See ../gpio/gpio.txt for more information.
> > > +
> > > +Example:
> > > +
> > > +        resource-manager@0 {
> > > +		compatible = "altr,a10sr";
> > > +		reg = <0>;
> > > +		spi-max-frequency = <100000>;
> > > +		interrupt-parent = <&portb>;
> > > +		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
> > > +		interrupt-controller;
> > > +		#interrupt-cells = <2>;
> > > +
> > > +		a10sr_gpio: gpio-controller {
> > > +			compatible = "altr,a10sr-gpio";
> > > +			gpio-controller;
> > > +			#gpio-cells = <2>;
> > > +		};
> > > +	};
> > 

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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Re: [PATCHv2 4/8] gpio: altera-a10sr: Add A10 System Resource Chip GPIO support.

[Linus Walleij]

On Thu, Jun 2, 2016 at 7:52 PM,  <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org> wrote:

> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>
> Add the GPIO functionality for the Altera Arria10 MAX5 System Resource
> Chip. The A10 MAX5 has 12 bits of GPIO assigned to switches, buttons,
> and LEDs as a GPIO extender on the SPI bus.
>
> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> Acked-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>i
> ---
> v2      Change Altera to Intel in copyright header

Patch applied!

Hey it just worked despite being months old.

Let's see if it builds fine & all.

Yours,
Linus Walleij
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Re: [PATCHv2 4/8] gpio: altera-a10sr: Add A10 System Resource Chip GPIO support.

[Thor Thayer]

Hi Linus,

On 10/21/2016 04:08 AM, Linus Walleij wrote:
> On Thu, Jun 2, 2016 at 7:52 PM,  <tthayer@opensource.altera.com> wrote:
>
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> Add the GPIO functionality for the Altera Arria10 MAX5 System Resource
>> Chip. The A10 MAX5 has 12 bits of GPIO assigned to switches, buttons,
>> and LEDs as a GPIO extender on the SPI bus.
>>
>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>> Acked-by: Linus Walleij <linus.walleij@linaro.org>i
>> ---
>> v2      Change Altera to Intel in copyright header
>
> Patch applied!
>
> Hey it just worked despite being months old.
>
> Let's see if it builds fine & all.
>

Thanks! Yes, it builds properly but to get past a NULL pointer kernel 
panic, I had to revert the recent devprop_gpiochip_set_names() change 
(9427ecbe). Once I did that it worked perfectly.

I'll investigate further and update you.

I apologize for missing this patch earlier. Thank you for your patience.

Thor

> Yours,
> Linus Walleij
>