[PATCH v5 0/5] support rockchip dwc3 driver

[PATCH v5 0/5] support rockchip dwc3 driver

[William Wu]

This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).

William Wu (5):
  usb: dwc3: of-simple: add compatible for rockchip rk3399
  usb: dwc3: add dis_u2_freeclk_exists_quirk
  usb: dwc3: add phyif_utmi_quirk
  usb: dwc3: add dis_del_phy_power_chg_quirk
  usb: dwc3: rockchip: add devicetree bindings documentation

 Documentation/devicetree/bindings/usb/dwc3.txt     |  9 +++++
 .../devicetree/bindings/usb/rockchip,dwc3.txt      | 40 ++++++++++++++++++++++
 drivers/usb/dwc3/core.c                            | 29 ++++++++++++++++
 drivers/usb/dwc3/core.h                            | 20 +++++++++++
 drivers/usb/dwc3/dwc3-of-simple.c                  |  1 +
 5 files changed, 99 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt

-- 
1.9.1

[PATCH v5 0/5] support rockchip dwc3 driver

[William Wu]

This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).

William Wu (5):
  usb: dwc3: of-simple: add compatible for rockchip rk3399
  usb: dwc3: add dis_u2_freeclk_exists_quirk
  usb: dwc3: add phyif_utmi_quirk
  usb: dwc3: add dis_del_phy_power_chg_quirk
  usb: dwc3: rockchip: add devicetree bindings documentation

 Documentation/devicetree/bindings/usb/dwc3.txt     |  9 +++++
 .../devicetree/bindings/usb/rockchip,dwc3.txt      | 40 ++++++++++++++++++++++
 drivers/usb/dwc3/core.c                            | 29 ++++++++++++++++
 drivers/usb/dwc3/core.h                            | 20 +++++++++++
 drivers/usb/dwc3/dwc3-of-simple.c                  |  1 +
 5 files changed, 99 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt

-- 
1.9.1

[PATCH v5 1/5] usb: dwc3: of-simple: add compatible for rockchip rk3399

[William Wu]

Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.

Signed-off-by: William Wu <william.wu@rock-chips.com>
---
Changes in v5:
- change compatible from "rockchip,dwc3" to "rockchip,rk3399-dwc3" (Heiko)

Changes in v4:
- None

Changes in v3:
- None

Changes in v2:
- sort the list of_dwc3_simple_match (Doug)

 drivers/usb/dwc3/dwc3-of-simple.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
index 9743353..05c9349 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -161,6 +161,7 @@ static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = {
 
 static const struct of_device_id of_dwc3_simple_match[] = {
 	{ .compatible = "qcom,dwc3" },
+	{ .compatible = "rockchip,rk3399-dwc3" },
 	{ .compatible = "xlnx,zynqmp-dwc3" },
 	{ /* Sentinel */ }
 };
-- 
1.9.1

[PATCH v5 1/5] usb: dwc3: of-simple: add compatible for rockchip rk3399

[William Wu]

Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.

Signed-off-by: William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v5:
- change compatible from "rockchip,dwc3" to "rockchip,rk3399-dwc3" (Heiko)

Changes in v4:
- None

Changes in v3:
- None

Changes in v2:
- sort the list of_dwc3_simple_match (Doug)

 drivers/usb/dwc3/dwc3-of-simple.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
index 9743353..05c9349 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -161,6 +161,7 @@ static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = {
 
 static const struct of_device_id of_dwc3_simple_match[] = {
 	{ .compatible = "qcom,dwc3" },
+	{ .compatible = "rockchip,rk3399-dwc3" },
 	{ .compatible = "xlnx,zynqmp-dwc3" },
 	{ /* Sentinel */ }
 };
-- 
1.9.1

[PATCH v5 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk

[William Wu]

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.

Signed-off-by: William Wu <william.wu@rock-chips.com>
---
Changes in v5:
- None

Changes in v4:
- rebase on top of balbi testing/next, remove pdata (balbi)

Changes in v3:
- None

Changes in v2:
- None

 Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
 drivers/usb/dwc3/core.c                        | 5 +++++
 drivers/usb/dwc3/core.h                        | 5 +++++
 3 files changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 7d7ce08..1ada121 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -39,6 +39,9 @@ Optional properties:
 			disabling the suspend signal to the PHY.
  - snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection
 			in PHY P3 power state.
+ - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
+			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
+			a free-running PHY clock.
  - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
 			utmi_l1_suspend_n, false when asserts utmi_sleep_n
  - snps,hird-threshold: HIRD threshold
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 9466431..34ab9c3 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -500,6 +500,9 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->dis_enblslpm_quirk)
 		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 
+	if (dwc->dis_u2_freeclk_exists_quirk)
+		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
+
 	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 
 	return 0;
@@ -924,6 +927,8 @@ static int dwc3_probe(struct platform_device *pdev)
 				"snps,dis_enblslpm_quirk");
 	dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
 				"snps,dis_rxdet_inp3_quirk");
+	dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
+				"snps,dis_u2_freeclk_exists_quirk");
 
 	dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
 				"snps,tx_de_emphasis_quirk");
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 45d6de5..f321a5c 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -199,6 +199,7 @@
 
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
+#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS	(1 << 30)
 #define DWC3_GUSB2PHYCFG_SUSPHY		(1 << 6)
 #define DWC3_GUSB2PHYCFG_ULPI_UTMI	(1 << 4)
 #define DWC3_GUSB2PHYCFG_ENBLSLPM	(1 << 8)
@@ -799,6 +800,9 @@ struct dwc3_scratchpad_array {
  * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
  * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
  *                      disabling the suspend signal to the PHY.
+ * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
+ *			in GUSB2PHYCFG, specify that USB2 PHY doesn't
+ *			provide a free-running PHY clock.
  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
  * @tx_de_emphasis: Tx de-emphasis value
  * 	0	- -6dB de-emphasis
@@ -942,6 +946,7 @@ struct dwc3 {
 	unsigned		dis_u2_susphy_quirk:1;
 	unsigned		dis_enblslpm_quirk:1;
 	unsigned		dis_rxdet_inp3_quirk:1;
+	unsigned		dis_u2_freeclk_exists_quirk:1;
 
 	unsigned		tx_de_emphasis_quirk:1;
 	unsigned		tx_de_emphasis:2;
-- 
1.9.1

[PATCH v5 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk

[William Wu]

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.

Signed-off-by: William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v5:
- None

Changes in v4:
- rebase on top of balbi testing/next, remove pdata (balbi)

Changes in v3:
- None

Changes in v2:
- None

 Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
 drivers/usb/dwc3/core.c                        | 5 +++++
 drivers/usb/dwc3/core.h                        | 5 +++++
 3 files changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 7d7ce08..1ada121 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -39,6 +39,9 @@ Optional properties:
 			disabling the suspend signal to the PHY.
  - snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection
 			in PHY P3 power state.
+ - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
+			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
+			a free-running PHY clock.
  - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
 			utmi_l1_suspend_n, false when asserts utmi_sleep_n
  - snps,hird-threshold: HIRD threshold
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 9466431..34ab9c3 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -500,6 +500,9 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->dis_enblslpm_quirk)
 		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 
+	if (dwc->dis_u2_freeclk_exists_quirk)
+		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
+
 	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 
 	return 0;
@@ -924,6 +927,8 @@ static int dwc3_probe(struct platform_device *pdev)
 				"snps,dis_enblslpm_quirk");
 	dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
 				"snps,dis_rxdet_inp3_quirk");
+	dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
+				"snps,dis_u2_freeclk_exists_quirk");
 
 	dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
 				"snps,tx_de_emphasis_quirk");
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 45d6de5..f321a5c 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -199,6 +199,7 @@
 
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
+#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS	(1 << 30)
 #define DWC3_GUSB2PHYCFG_SUSPHY		(1 << 6)
 #define DWC3_GUSB2PHYCFG_ULPI_UTMI	(1 << 4)
 #define DWC3_GUSB2PHYCFG_ENBLSLPM	(1 << 8)
@@ -799,6 +800,9 @@ struct dwc3_scratchpad_array {
  * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
  * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
  *                      disabling the suspend signal to the PHY.
+ * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
+ *			in GUSB2PHYCFG, specify that USB2 PHY doesn't
+ *			provide a free-running PHY clock.
  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
  * @tx_de_emphasis: Tx de-emphasis value
  * 	0	- -6dB de-emphasis
@@ -942,6 +946,7 @@ struct dwc3 {
 	unsigned		dis_u2_susphy_quirk:1;
 	unsigned		dis_enblslpm_quirk:1;
 	unsigned		dis_rxdet_inp3_quirk:1;
+	unsigned		dis_u2_freeclk_exists_quirk:1;
 
 	unsigned		tx_de_emphasis_quirk:1;
 	unsigned		tx_de_emphasis:2;
-- 
1.9.1

Re: [PATCH v5 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk

[Rob Herring]

On Thu, Jun 30, 2016 at 07:12:53PM +0800, William Wu wrote:
> Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
> which specifies whether the USB2.0 PHY provides a free-running
> PHY clock, which is active when the clock control input is active.
> 
> Signed-off-by: William Wu <william.wu@rock-chips.com>
> ---
> Changes in v5:
> - None
> 
> Changes in v4:
> - rebase on top of balbi testing/next, remove pdata (balbi)
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - None
> 
>  Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
>  drivers/usb/dwc3/core.c                        | 5 +++++
>  drivers/usb/dwc3/core.h                        | 5 +++++
>  3 files changed, 13 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index 7d7ce08..1ada121 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -39,6 +39,9 @@ Optional properties:
>  			disabling the suspend signal to the PHY.
>   - snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection
>  			in PHY P3 power state.
> + - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists

Use '-', not '_'.

> +			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
> +			a free-running PHY clock.
>   - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
>  			utmi_l1_suspend_n, false when asserts utmi_sleep_n
>   - snps,hird-threshold: HIRD threshold

Re: [PATCH v5 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk[Involving remittance information, please pay attention to the safety of property]

[William Wu]

Dear Rob,

On 07/01/2016 10:32 AM, Rob Herring wrote:
> On Thu, Jun 30, 2016 at 07:12:53PM +0800, William Wu wrote:
>> Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
>> which specifies whether the USB2.0 PHY provides a free-running
>> PHY clock, which is active when the clock control input is active.
>>
>> Signed-off-by: William Wu <william.wu@rock-chips.com>
>> ---
>> Changes in v5:
>> - None
>>
>> Changes in v4:
>> - rebase on top of balbi testing/next, remove pdata (balbi)
>>
>> Changes in v3:
>> - None
>>
>> Changes in v2:
>> - None
>>
>>   Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
>>   drivers/usb/dwc3/core.c                        | 5 +++++
>>   drivers/usb/dwc3/core.h                        | 5 +++++
>>   3 files changed, 13 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
>> index 7d7ce08..1ada121 100644
>> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> @@ -39,6 +39,9 @@ Optional properties:
>>   			disabling the suspend signal to the PHY.
>>    - snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection
>>   			in PHY P3 power state.
>> + - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
> Use '-', not '_'.
OK, I'll fix them in next patch.
Thanks very much for your help.
>
>> +			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
>> +			a free-running PHY clock.
>>    - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
>>   			utmi_l1_suspend_n, false when asserts utmi_sleep_n
>>    - snps,hird-threshold: HIRD threshold
>
>

Re: [PATCH v5 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk[Involving remittance information, please pay attention to the safety of property]

[William Wu]

Dear Rob,

On 07/01/2016 10:32 AM, Rob Herring wrote:
> On Thu, Jun 30, 2016 at 07:12:53PM +0800, William Wu wrote:
>> Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
>> which specifies whether the USB2.0 PHY provides a free-running
>> PHY clock, which is active when the clock control input is active.
>>
>> Signed-off-by: William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> ---
>> Changes in v5:
>> - None
>>
>> Changes in v4:
>> - rebase on top of balbi testing/next, remove pdata (balbi)
>>
>> Changes in v3:
>> - None
>>
>> Changes in v2:
>> - None
>>
>>   Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
>>   drivers/usb/dwc3/core.c                        | 5 +++++
>>   drivers/usb/dwc3/core.h                        | 5 +++++
>>   3 files changed, 13 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
>> index 7d7ce08..1ada121 100644
>> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> @@ -39,6 +39,9 @@ Optional properties:
>>   			disabling the suspend signal to the PHY.
>>    - snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection
>>   			in PHY P3 power state.
>> + - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
> Use '-', not '_'.
OK, I'll fix them in next patch.
Thanks very much for your help.
>
>> +			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
>> +			a free-running PHY clock.
>>    - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
>>   			utmi_l1_suspend_n, false when asserts utmi_sleep_n
>>    - snps,hird-threshold: HIRD threshold
>
>

[PATCH v5 3/5] usb: dwc3: add phyif_utmi_quirk

[William Wu]

Add a quirk to configure the core to support the
UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY
interface is hardware property, and it's platform
dependent. Normall, the PHYIf can be configured
during coreconsultant. But for some specific usb
cores(e.g. rk3399 soc dwc3), the default PHYIf
configuration value is fault, so we need to
reconfigure it by software.

And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to
the UTMI+ PHY interface.

Signed-off-by: William Wu <william.wu@rock-chips.com>
---
Changes in v5:
- None

Changes in v4:
- rebase on top of balbi testing/next, remove pdata (balbi)

Changes in v3:
- None

Changes in v2:
- add a quirk for phyif_utmi (balbi)

 Documentation/devicetree/bindings/usb/dwc3.txt |  4 ++++
 drivers/usb/dwc3/core.c                        | 19 +++++++++++++++++++
 drivers/usb/dwc3/core.h                        | 12 ++++++++++++
 3 files changed, 35 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 1ada121..34d13a5 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -42,6 +42,10 @@ Optional properties:
  - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
 			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
 			a free-running PHY clock.
+ - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.
+ - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
+			with an 8- or 16-bit interface. Value 0 select 8-bit
+			interface, value 1 select 16-bit interface.
  - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
 			utmi_l1_suspend_n, false when asserts utmi_sleep_n
  - snps,hird-threshold: HIRD threshold
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 34ab9c3..e880686 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -408,6 +408,7 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc)
 static int dwc3_phy_setup(struct dwc3 *dwc)
 {
 	u32 reg;
+	u32 usbtrdtim;
 	int ret;
 
 	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
@@ -503,6 +504,15 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->dis_u2_freeclk_exists_quirk)
 		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 
+	if (dwc->phyif_utmi_quirk) {
+		reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
+		       DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
+		usbtrdtim = dwc->phyif_utmi ? USBTRDTIM_UTMI_16_BIT :
+			    USBTRDTIM_UTMI_8_BIT;
+		reg |= DWC3_GUSB2PHYCFG_PHYIF(dwc->phyif_utmi) |
+		       DWC3_GUSB2PHYCFG_USBTRDTIM(usbtrdtim);
+	}
+
 	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 
 	return 0;
@@ -834,6 +844,7 @@ static int dwc3_probe(struct platform_device *pdev)
 	struct resource		*res;
 	struct dwc3		*dwc;
 	u8			lpm_nyet_threshold;
+	u8			phyif_utmi;
 	u8			tx_de_emphasis;
 	u8			hird_threshold;
 
@@ -880,6 +891,9 @@ static int dwc3_probe(struct platform_device *pdev)
 	/* default to highest possible threshold */
 	lpm_nyet_threshold = 0xff;
 
+	/* default to UTMI+ 8-bit interface */
+	phyif_utmi = 0;
+
 	/* default to -3.5dB de-emphasis */
 	tx_de_emphasis = 1;
 
@@ -929,6 +943,10 @@ static int dwc3_probe(struct platform_device *pdev)
 				"snps,dis_rxdet_inp3_quirk");
 	dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
 				"snps,dis_u2_freeclk_exists_quirk");
+	dwc->phyif_utmi_quirk = device_property_read_bool(dev,
+				"snps,phyif_utmi_quirk");
+	device_property_read_u8(dev, "snps,phyif_utmi",
+				&phyif_utmi);
 
 	dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
 				"snps,tx_de_emphasis_quirk");
@@ -940,6 +958,7 @@ static int dwc3_probe(struct platform_device *pdev)
 				 &dwc->fladj);
 
 	dwc->lpm_nyet_threshold = lpm_nyet_threshold;
+	dwc->phyif_utmi = phyif_utmi;
 	dwc->tx_de_emphasis = tx_de_emphasis;
 
 	dwc->hird_threshold = hird_threshold
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index f321a5c..cf6696c 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -203,6 +203,12 @@
 #define DWC3_GUSB2PHYCFG_SUSPHY		(1 << 6)
 #define DWC3_GUSB2PHYCFG_ULPI_UTMI	(1 << 4)
 #define DWC3_GUSB2PHYCFG_ENBLSLPM	(1 << 8)
+#define DWC3_GUSB2PHYCFG_PHYIF(n)	(n << 3)
+#define DWC3_GUSB2PHYCFG_PHYIF_MASK	DWC3_GUSB2PHYCFG_PHYIF(1)
+#define DWC3_GUSB2PHYCFG_USBTRDTIM(n)	(n << 10)
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK	DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
+#define USBTRDTIM_UTMI_8_BIT		9
+#define USBTRDTIM_UTMI_16_BIT		5
 
 /* Global USB2 PHY Vendor Control Register */
 #define DWC3_GUSB2PHYACC_NEWREGREQ	(1 << 25)
@@ -803,6 +809,10 @@ struct dwc3_scratchpad_array {
  * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
  *			in GUSB2PHYCFG, specify that USB2 PHY doesn't
  *			provide a free-running PHY clock.
+ * @phyif_utmi_quirk: set if we enable phyif UTMI+ quirk
+ * @phyif_utmi: UTMI+ PHY interface value
+ *	0	- 8 bits
+ *	1	- 16 bits
  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
  * @tx_de_emphasis: Tx de-emphasis value
  * 	0	- -6dB de-emphasis
@@ -948,6 +958,8 @@ struct dwc3 {
 	unsigned		dis_rxdet_inp3_quirk:1;
 	unsigned		dis_u2_freeclk_exists_quirk:1;
 
+	unsigned		phyif_utmi_quirk:1;
+	unsigned		phyif_utmi:1;
 	unsigned		tx_de_emphasis_quirk:1;
 	unsigned		tx_de_emphasis:2;
 };
-- 
1.9.1

Re: [PATCH v5 3/5] usb: dwc3: add phyif_utmi_quirk

[Rob Herring]

On Thu, Jun 30, 2016 at 07:12:54PM +0800, William Wu wrote:
> Add a quirk to configure the core to support the
> UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY
> interface is hardware property, and it's platform
> dependent. Normall, the PHYIf can be configured
> during coreconsultant. But for some specific usb
> cores(e.g. rk3399 soc dwc3), the default PHYIf
> configuration value is fault, so we need to
> reconfigure it by software.
> 
> And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
> must be set to the corresponding value according to
> the UTMI+ PHY interface.
> 
> Signed-off-by: William Wu <william.wu@rock-chips.com>
> ---
> Changes in v5:
> - None
> 
> Changes in v4:
> - rebase on top of balbi testing/next, remove pdata (balbi)
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - add a quirk for phyif_utmi (balbi)
> 
>  Documentation/devicetree/bindings/usb/dwc3.txt |  4 ++++
>  drivers/usb/dwc3/core.c                        | 19 +++++++++++++++++++
>  drivers/usb/dwc3/core.h                        | 12 ++++++++++++
>  3 files changed, 35 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index 1ada121..34d13a5 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -42,6 +42,10 @@ Optional properties:
>   - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
>  			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
>  			a free-running PHY clock.
> + - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.

This isn't really what I'd call a quirk.

> + - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
> +			with an 8- or 16-bit interface. Value 0 select 8-bit
> +			interface, value 1 select 16-bit interface.

These seem like they should be standard properties for setting the phy 
type/mode. I think we already have something defined in fact.

Rob

Re: [PATCH v5 3/5] usb: dwc3: add phyif_utmi_quirk

[Rob Herring]

On Thu, Jun 30, 2016 at 07:12:54PM +0800, William Wu wrote:
> Add a quirk to configure the core to support the
> UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY
> interface is hardware property, and it's platform
> dependent. Normall, the PHYIf can be configured
> during coreconsultant. But for some specific usb
> cores(e.g. rk3399 soc dwc3), the default PHYIf
> configuration value is fault, so we need to
> reconfigure it by software.
> 
> And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
> must be set to the corresponding value according to
> the UTMI+ PHY interface.
> 
> Signed-off-by: William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> Changes in v5:
> - None
> 
> Changes in v4:
> - rebase on top of balbi testing/next, remove pdata (balbi)
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - add a quirk for phyif_utmi (balbi)
> 
>  Documentation/devicetree/bindings/usb/dwc3.txt |  4 ++++
>  drivers/usb/dwc3/core.c                        | 19 +++++++++++++++++++
>  drivers/usb/dwc3/core.h                        | 12 ++++++++++++
>  3 files changed, 35 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index 1ada121..34d13a5 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -42,6 +42,10 @@ Optional properties:
>   - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
>  			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
>  			a free-running PHY clock.
> + - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.

This isn't really what I'd call a quirk.

> + - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
> +			with an 8- or 16-bit interface. Value 0 select 8-bit
> +			interface, value 1 select 16-bit interface.

These seem like they should be standard properties for setting the phy 
type/mode. I think we already have something defined in fact.

Rob
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Re: [PATCH v5 3/5] usb: dwc3: add phyif_utmi_quirk[Involving remittance information, please pay attention to the safety of property]

[William Wu]

[-- Attachment #1: Type: text/plain, Size: 3936 bytes --]

Dear Rob,

On 07/01/2016 10:35 AM, Rob Herring wrote:
> On Thu, Jun 30, 2016 at 07:12:54PM +0800, William Wu wrote:
>> Add a quirk to configure the core to support the
>> UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY
>> interface is hardware property, and it's platform
>> dependent. Normall, the PHYIf can be configured
>> during coreconsultant. But for some specific usb
>> cores(e.g. rk3399 soc dwc3), the default PHYIf
>> configuration value is fault, so we need to
>> reconfigure it by software.
>>
>> And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
>> must be set to the corresponding value according to
>> the UTMI+ PHY interface.
>>
>> Signed-off-by: William Wu <william.wu@rock-chips.com>
>> ---
>> Changes in v5:
>> - None
>>
>> Changes in v4:
>> - rebase on top of balbi testing/next, remove pdata (balbi)
>>
>> Changes in v3:
>> - None
>>
>> Changes in v2:
>> - add a quirk for phyif_utmi (balbi)
>>
>>   Documentation/devicetree/bindings/usb/dwc3.txt |  4 ++++
>>   drivers/usb/dwc3/core.c                        | 19 +++++++++++++++++++
>>   drivers/usb/dwc3/core.h                        | 12 ++++++++++++
>>   3 files changed, 35 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
>> index 1ada121..34d13a5 100644
>> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> @@ -42,6 +42,10 @@ Optional properties:
>>    - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
>>   			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
>>   			a free-running PHY clock.
>> + - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.
> This isn't really what I'd call a quirk.
I'm sorry that add you in the review list too late.

Actually, I have discussed the property "snps,phyif_utmi_quirk"
with balbi in patch v2.

As we know, UTMI+ PHY interface is hardware property, and
it can be configured correctly during coreconsulttant according
to dwc3 TRM, section 8.1.1 Table 8-1 where itstates:

|-------------+------------------------------------------------------------|
| GUSB2PHYCFG | Program the following PHY configuration fields: USBTrdTim, |
|             | FSIntf, PHYIf, TOUTCal, or leave the default values if     |
|             | the correct power-on values were selected during           |
|             | coreConsultant configuration.  Note: The PHY must not      |
|             | be enabled for auto-resume in device mode. Hence the       |
|             | field GUSB2PHYCFG[15] (ULPIAutoRes) must be written        |
|             | with '0' during the power-on initialization in case        |
|             | the reset value is '1'.                                    |
|             |                                                            |
|-------------+------------------------------------------------------------|

But for some specific usb cores(e.g. rk3399 soc dwc3),  the default
PHYIf configuration value is fault after core init, ad we need to
reconfigure it by software. so I think maybe a quirk is more proper.

>
>> + - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
>> +			with an 8- or 16-bit interface. Value 0 select 8-bit
>> +			interface, value 1 select 16-bit interface.
> These seem like they should be standard properties for setting the phy
> type/mode. I think we already have something defined in fact.
Yes, it's standard properties for setting the phy interface.
But as I describe above, for most of dwc3 cores designed
by IC vendors, the phy interface can be automatically set
with correct value during coreConsultant configuration,
and don't need to reconfigure it by software. For now,
I haven't found any SoC had this issue except rk3399,
and dwc3 driver also doesn't have any defined similar to
what I defined here.

Best Regards
      William Wu
> Rob
>
>
>


[-- Attachment #2: Type: text/html, Size: 4975 bytes --]

Re: [PATCH v5 3/5] usb: dwc3: add phyif_utmi_quirk[Involving remittance information, please pay attention to the safety of property]

[William Wu]

[-- Attachment #1: Type: text/plain, Size: 3989 bytes --]

Dear Rob,

On 07/01/2016 10:35 AM, Rob Herring wrote:
> On Thu, Jun 30, 2016 at 07:12:54PM +0800, William Wu wrote:
>> Add a quirk to configure the core to support the
>> UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY
>> interface is hardware property, and it's platform
>> dependent. Normall, the PHYIf can be configured
>> during coreconsultant. But for some specific usb
>> cores(e.g. rk3399 soc dwc3), the default PHYIf
>> configuration value is fault, so we need to
>> reconfigure it by software.
>>
>> And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
>> must be set to the corresponding value according to
>> the UTMI+ PHY interface.
>>
>> Signed-off-by: William Wu <william.wu@rock-chips.com>
>> ---
>> Changes in v5:
>> - None
>>
>> Changes in v4:
>> - rebase on top of balbi testing/next, remove pdata (balbi)
>>
>> Changes in v3:
>> - None
>>
>> Changes in v2:
>> - add a quirk for phyif_utmi (balbi)
>>
>>   Documentation/devicetree/bindings/usb/dwc3.txt |  4 ++++
>>   drivers/usb/dwc3/core.c                        | 19 +++++++++++++++++++
>>   drivers/usb/dwc3/core.h                        | 12 ++++++++++++
>>   3 files changed, 35 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
>> index 1ada121..34d13a5 100644
>> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> @@ -42,6 +42,10 @@ Optional properties:
>>    - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
>>   			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
>>   			a free-running PHY clock.
>> + - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.
> This isn't really what I'd call a quirk.
I'm sorry that add you in the review list too late.

Actually, I have discussed the property "snps,phyif_utmi_quirk"
with balbi in patch v2.

As we know, UTMI+ PHY interface is hardware property, and
it can be configured correctly during coreconsulttant according
to dwc3 TRM, section 8.1.1 Table 8-1 where itstates:

|-------------+-------------------------------------------------------------------------------------|
| GUSB2PHYCFG | Program the following PHY configuration fields: USBTrdTim, |
|             | FSIntf, PHYIf, TOUTCal, or leave the default values if  
                        |
|             | the correct power-on values were selected 
during                             |
|             | coreConsultant configuration.  Note: The PHY must 
not                     |
|             | be enabled for auto-resume in device mode. Hence 
the                    |
|             | field GUSB2PHYCFG[15] (ULPIAutoRes) must be 
written                    |
|             | with '0' during the power-on initialization in case     
                          |
|             | the reset value is '1'. |
| | |
|-------------+------------------------------------------------------------------------------------|

But for some specific usb cores(e.g. rk3399 soc dwc3),  the default
PHYIf configuration value is fault after core init, ad we need to
reconfigure it by software. so I think maybe a quirk is more proper.

>
>> + - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
>> +			with an 8- or 16-bit interface. Value 0 select 8-bit
>> +			interface, value 1 select 16-bit interface.
> These seem like they should be standard properties for setting the phy
> type/mode. I think we already have something defined in fact.
Yes, it's standard properties for setting the phy interface.
But as I describe above, for most of dwc3 cores designed
by IC vendors, the phy interface can be automatically set
with correct value during coreConsultant configuration,
and don't need to reconfigure it by software. For now,
I haven't found any SoC had this issue except rk3399,
and dwc3 driver also doesn't have any defined similar to
what I defined here.

Best Regards
      William Wu
>
> Rob
>
>
>


[-- Attachment #2: Type: text/html, Size: 7329 bytes --]

[PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk

[William Wu]

Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.

Signed-off-by: William Wu <william.wu@rock-chips.com>
---
Changes in v5:
- None

Changes in v4:
- rebase on top of balbi testing/next, remove pdata (balbi)

Changes in v3:
- None

Changes in v2:
- None

 Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
 drivers/usb/dwc3/core.c                        | 5 +++++
 drivers/usb/dwc3/core.h                        | 3 +++
 3 files changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 34d13a5..bd5bef0 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -42,6 +42,8 @@ Optional properties:
  - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
 			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
 			a free-running PHY clock.
+ - snps,dis_del_phy_power_chg_quirk: when set core will change PHY power
+			from P0 to P1/P2/P3 without delay.
  - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.
  - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
 			with an 8- or 16-bit interface. Value 0 select 8-bit
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index e880686..320a50f 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -449,6 +449,9 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->dis_u3_susphy_quirk)
 		reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 
+	if (dwc->dis_del_phy_power_chg_quirk)
+		reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
+
 	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 
 	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
@@ -943,6 +946,8 @@ static int dwc3_probe(struct platform_device *pdev)
 				"snps,dis_rxdet_inp3_quirk");
 	dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
 				"snps,dis_u2_freeclk_exists_quirk");
+	dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
+				"snps,dis_del_phy_power_chg_quirk");
 	dwc->phyif_utmi_quirk = device_property_read_bool(dev,
 				"snps,phyif_utmi_quirk");
 	device_property_read_u8(dev, "snps,phyif_utmi",
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index cf6696c..55e136d 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -809,6 +809,8 @@ struct dwc3_scratchpad_array {
  * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
  *			in GUSB2PHYCFG, specify that USB2 PHY doesn't
  *			provide a free-running PHY clock.
+ * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
+ *			change quirk.
  * @phyif_utmi_quirk: set if we enable phyif UTMI+ quirk
  * @phyif_utmi: UTMI+ PHY interface value
  *	0	- 8 bits
@@ -957,6 +959,7 @@ struct dwc3 {
 	unsigned		dis_enblslpm_quirk:1;
 	unsigned		dis_rxdet_inp3_quirk:1;
 	unsigned		dis_u2_freeclk_exists_quirk:1;
+	unsigned		dis_del_phy_power_chg_quirk:1;
 
 	unsigned		phyif_utmi_quirk:1;
 	unsigned		phyif_utmi:1;
-- 
1.9.1

[PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk

[William Wu]

Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.

Signed-off-by: William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v5:
- None

Changes in v4:
- rebase on top of balbi testing/next, remove pdata (balbi)

Changes in v3:
- None

Changes in v2:
- None

 Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
 drivers/usb/dwc3/core.c                        | 5 +++++
 drivers/usb/dwc3/core.h                        | 3 +++
 3 files changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 34d13a5..bd5bef0 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -42,6 +42,8 @@ Optional properties:
  - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
 			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
 			a free-running PHY clock.
+ - snps,dis_del_phy_power_chg_quirk: when set core will change PHY power
+			from P0 to P1/P2/P3 without delay.
  - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.
  - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
 			with an 8- or 16-bit interface. Value 0 select 8-bit
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index e880686..320a50f 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -449,6 +449,9 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->dis_u3_susphy_quirk)
 		reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 
+	if (dwc->dis_del_phy_power_chg_quirk)
+		reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
+
 	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 
 	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
@@ -943,6 +946,8 @@ static int dwc3_probe(struct platform_device *pdev)
 				"snps,dis_rxdet_inp3_quirk");
 	dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
 				"snps,dis_u2_freeclk_exists_quirk");
+	dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
+				"snps,dis_del_phy_power_chg_quirk");
 	dwc->phyif_utmi_quirk = device_property_read_bool(dev,
 				"snps,phyif_utmi_quirk");
 	device_property_read_u8(dev, "snps,phyif_utmi",
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index cf6696c..55e136d 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -809,6 +809,8 @@ struct dwc3_scratchpad_array {
  * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
  *			in GUSB2PHYCFG, specify that USB2 PHY doesn't
  *			provide a free-running PHY clock.
+ * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
+ *			change quirk.
  * @phyif_utmi_quirk: set if we enable phyif UTMI+ quirk
  * @phyif_utmi: UTMI+ PHY interface value
  *	0	- 8 bits
@@ -957,6 +959,7 @@ struct dwc3 {
 	unsigned		dis_enblslpm_quirk:1;
 	unsigned		dis_rxdet_inp3_quirk:1;
 	unsigned		dis_u2_freeclk_exists_quirk:1;
+	unsigned		dis_del_phy_power_chg_quirk:1;
 
 	unsigned		phyif_utmi_quirk:1;
 	unsigned		phyif_utmi:1;
-- 
1.9.1

Re: [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk

[Rob Herring]

On Thu, Jun 30, 2016 at 07:12:55PM +0800, William Wu wrote:
> Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
> which specifies whether disable delay PHY power change
> from P0 to P1/P2/P3 when link state changing from U0
> to U1/U2/U3 respectively.
> 
> Signed-off-by: William Wu <william.wu@rock-chips.com>
> ---
> Changes in v5:
> - None
> 
> Changes in v4:
> - rebase on top of balbi testing/next, remove pdata (balbi)
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - None
> 
>  Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
>  drivers/usb/dwc3/core.c                        | 5 +++++
>  drivers/usb/dwc3/core.h                        | 3 +++
>  3 files changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index 34d13a5..bd5bef0 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -42,6 +42,8 @@ Optional properties:
>   - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
>  			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
>  			a free-running PHY clock.
> + - snps,dis_del_phy_power_chg_quirk: when set core will change PHY power
> +			from P0 to P1/P2/P3 without delay.

Use '-', not '_'.

>   - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.
>   - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
>  			with an 8- or 16-bit interface. Value 0 select 8-bit

Re: [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk

[Rob Herring]

On Thu, Jun 30, 2016 at 07:12:55PM +0800, William Wu wrote:
> Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
> which specifies whether disable delay PHY power change
> from P0 to P1/P2/P3 when link state changing from U0
> to U1/U2/U3 respectively.
> 
> Signed-off-by: William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> Changes in v5:
> - None
> 
> Changes in v4:
> - rebase on top of balbi testing/next, remove pdata (balbi)
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - None
> 
>  Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
>  drivers/usb/dwc3/core.c                        | 5 +++++
>  drivers/usb/dwc3/core.h                        | 3 +++
>  3 files changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index 34d13a5..bd5bef0 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -42,6 +42,8 @@ Optional properties:
>   - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
>  			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
>  			a free-running PHY clock.
> + - snps,dis_del_phy_power_chg_quirk: when set core will change PHY power
> +			from P0 to P1/P2/P3 without delay.

Use '-', not '_'.

>   - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.
>   - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
>  			with an 8- or 16-bit interface. Value 0 select 8-bit

Re: [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk[Involving remittance information, please pay attention to the safety of property]

[William Wu]

Dear Rob,

On 07/01/2016 10:38 AM, Rob Herring wrote:
> On Thu, Jun 30, 2016 at 07:12:55PM +0800, William Wu wrote:
>> Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
>> which specifies whether disable delay PHY power change
>> from P0 to P1/P2/P3 when link state changing from U0
>> to U1/U2/U3 respectively.
>>
>> Signed-off-by: William Wu <william.wu@rock-chips.com>
>> ---
>> Changes in v5:
>> - None
>>
>> Changes in v4:
>> - rebase on top of balbi testing/next, remove pdata (balbi)
>>
>> Changes in v3:
>> - None
>>
>> Changes in v2:
>> - None
>>
>>   Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
>>   drivers/usb/dwc3/core.c                        | 5 +++++
>>   drivers/usb/dwc3/core.h                        | 3 +++
>>   3 files changed, 10 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
>> index 34d13a5..bd5bef0 100644
>> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> @@ -42,6 +42,8 @@ Optional properties:
>>    - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
>>   			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
>>   			a free-running PHY clock.
>> + - snps,dis_del_phy_power_chg_quirk: when set core will change PHY power
>> +			from P0 to P1/P2/P3 without delay.
> Use '-', not '_'.
OK, I'll fix it in next patch.
Thanks~:-)

Best regards,
         William Wu
>
>>    - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.
>>    - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
>>   			with an 8- or 16-bit interface. Value 0 select 8-bit
>
>
>

[PATCH v5 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

[William Wu]

This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.

It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).

Signed-off-by: William Wu <william.wu@rock-chips.com>
---
Changes in v5:
- rename clock-names, and remove unnecessary clocks (Heiko)

Changes in v4:
- modify commit log, and add phy documentation location (Sergei)

Changes in v3:
- add dwc3 address (balbi)

Changes in v2:
- add rockchip,dwc3.txt to Documentation/devicetree/bindings/ (balbi, Brian)

 .../devicetree/bindings/usb/rockchip,dwc3.txt      | 40 ++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt

diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
new file mode 100644
index 0000000..9c85e19
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
@@ -0,0 +1,40 @@
+Rockchip SuperSpeed DWC3 USB SoC controller
+
+Required properties:
+- compatible:	should contain "rockchip,rk3399-dwc3" for rk3399 SoC
+- clocks:	A list of phandle + clock-specifier pairs for the
+		clocks listed in clock-names
+- clock-names:	Should contain the following:
+  "ref_clk"	Controller reference clk, have to be 24 MHz
+  "suspend_clk"	Controller suspend clk, have to be 24 MHz or 32 KHz
+  "bus_clk_otg0"Master/Core clock, have to be >= 62.5 MHz for SS
+		operation and >= 60MHz for HS operation
+  "grf_clk"	Controller grf clk
+
+Required child node:
+A child node must exist to represent the core DWC3 IP block. The name of
+the node is not important. The content of the node is defined in dwc3.txt.
+
+Phy documentation is provided in the following places:
+Documentation/devicetree/bindings/phy/rockchip,dwc3-usb-phy.txt
+
+Example device nodes:
+
+	usbdrd3_0: usb@fe800000 {
+		compatible = "rockchip,rk3399-dwc3";
+		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
+			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk_otg0", "grf_clk";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+		usbdrd_dwc3_0: dwc3@fe800000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xfe800000 0x0 0x100000>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "otg";
+			status = "disabled";
+		};
+	};
-- 
1.9.1

Re: [PATCH v5 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

[Heiko Stuebner]

Hi William,

Am Donnerstag, 30. Juni 2016, 19:16:40 schrieb William Wu:
> This patch adds the devicetree documentation required for Rockchip
> USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
> 
> It supports DRD mode, and could operate in device mode (SS, HS, FS)
> and host mode (SS, HS, FS, LS).
> 
> Signed-off-by: William Wu <william.wu@rock-chips.com>
> ---
> Changes in v5:
> - rename clock-names, and remove unnecessary clocks (Heiko)
> 
> Changes in v4:
> - modify commit log, and add phy documentation location (Sergei)
> 
> Changes in v3:
> - add dwc3 address (balbi)
> 
> Changes in v2:
> - add rockchip,dwc3.txt to Documentation/devicetree/bindings/ (balbi,
> Brian)
> 
>  .../devicetree/bindings/usb/rockchip,dwc3.txt      | 40
> ++++++++++++++++++++++ 1 file changed, 40 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> 
> diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt new file mode
> 100644
> index 0000000..9c85e19
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> @@ -0,0 +1,40 @@
> +Rockchip SuperSpeed DWC3 USB SoC controller
> +
> +Required properties:
> +- compatible:	should contain "rockchip,rk3399-dwc3" for rk3399 SoC
> +- clocks:	A list of phandle + clock-specifier pairs for the
> +		clocks listed in clock-names
> +- clock-names:	Should contain the following:
> +  "ref_clk"	Controller reference clk, have to be 24 MHz
> +  "suspend_clk"	Controller suspend clk, have to be 24 MHz or 32 KHz
> +  "bus_clk_otg0"Master/Core clock, have to be >= 62.5 MHz for SS
> +		operation and >= 60MHz for HS operation

why is it called "bus_clk_otg0" not just simply "bus_clk". As far as I
understand it (and see it in the TRM), you have two dwc3 controllers
(otg0 and otg1) and clock-names are always meant from the perspective of
the individual ip-block. So a devicetree would have:

	usbdrd3_0: usb@fe800000 {
		compatible = "rockchip,rk3399-dwc3";
		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
		clock-names = "ref_clk", "suspend_clk",
			      "bus_clk", "grf_clk";
		...
	};

	usbdrd3_1: usb@fe900000 {
		compatible = "rockchip,rk3399-dwc3";
		clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
			 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
		clock-names = "ref_clk", "suspend_clk",
			      "bus_clk", "grf_clk";
		...
	};


The rest looks really nice now.


Heiko

> +  "grf_clk"	Controller grf clk
> +
> +Required child node:
> +A child node must exist to represent the core DWC3 IP block. The name of
> +the node is not important. The content of the node is defined in
> dwc3.txt. +
> +Phy documentation is provided in the following places:
> +Documentation/devicetree/bindings/phy/rockchip,dwc3-usb-phy.txt
> +
> +Example device nodes:
> +
> +	usbdrd3_0: usb@fe800000 {
> +		compatible = "rockchip,rk3399-dwc3";
> +		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
> +			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
> +		clock-names = "ref_clk", "suspend_clk",
> +			      "bus_clk_otg0", "grf_clk";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		status = "disabled";
> +		usbdrd_dwc3_0: dwc3@fe800000 {
> +			compatible = "snps,dwc3";
> +			reg = <0x0 0xfe800000 0x0 0x100000>;
> +			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> +			dr_mode = "otg";
> +			status = "disabled";
> +		};
> +	};
> --
> 1.9.1

Re: [PATCH v5 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

[William Wu]

Dear Heiko,

On 06/30/2016 08:15 PM, Heiko Stuebner wrote:
> Hi William,
>
> Am Donnerstag, 30. Juni 2016, 19:16:40 schrieb William Wu:
>> This patch adds the devicetree documentation required for Rockchip
>> USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
>>
>> It supports DRD mode, and could operate in device mode (SS, HS, FS)
>> and host mode (SS, HS, FS, LS).
>>
>> Signed-off-by: William Wu <william.wu@rock-chips.com>
>> ---
>> Changes in v5:
>> - rename clock-names, and remove unnecessary clocks (Heiko)
>>
>> Changes in v4:
>> - modify commit log, and add phy documentation location (Sergei)
>>
>> Changes in v3:
>> - add dwc3 address (balbi)
>>
>> Changes in v2:
>> - add rockchip,dwc3.txt to Documentation/devicetree/bindings/ (balbi,
>> Brian)
>>
>>   .../devicetree/bindings/usb/rockchip,dwc3.txt      | 40
>> ++++++++++++++++++++++ 1 file changed, 40 insertions(+)
>>   create mode 100644
>> Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
>>
>> diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
>> b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt new file mode
>> 100644
>> index 0000000..9c85e19
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
>> @@ -0,0 +1,40 @@
>> +Rockchip SuperSpeed DWC3 USB SoC controller
>> +
>> +Required properties:
>> +- compatible:	should contain "rockchip,rk3399-dwc3" for rk3399 SoC
>> +- clocks:	A list of phandle + clock-specifier pairs for the
>> +		clocks listed in clock-names
>> +- clock-names:	Should contain the following:
>> +  "ref_clk"	Controller reference clk, have to be 24 MHz
>> +  "suspend_clk"	Controller suspend clk, have to be 24 MHz or 32 KHz
>> +  "bus_clk_otg0"Master/Core clock, have to be >= 62.5 MHz for SS
>> +		operation and >= 60MHz for HS operation
> why is it called "bus_clk_otg0" not just simply "bus_clk". As far as I
> understand it (and see it in the TRM), you have two dwc3 controllers
> (otg0 and otg1) and clock-names are always meant from the perspective of
> the individual ip-block. So a devicetree would have:
>
> 	usbdrd3_0: usb@fe800000 {
> 		compatible = "rockchip,rk3399-dwc3";
> 		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
> 			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
> 		clock-names = "ref_clk", "suspend_clk",
> 			      "bus_clk", "grf_clk";
> 		...
> 	};
>
> 	usbdrd3_1: usb@fe900000 {
> 		compatible = "rockchip,rk3399-dwc3";
> 		clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
> 			 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
> 		clock-names = "ref_clk", "suspend_clk",
> 			      "bus_clk", "grf_clk";
> 		...
> 	};
>
>
> The rest looks really nice now.
Ah, it looks very goog to me. I'll fix it immediately.
Thank you very much!
>
>
> Heiko
>
>> +  "grf_clk"	Controller grf clk
>> +
>> +Required child node:
>> +A child node must exist to represent the core DWC3 IP block. The name of
>> +the node is not important. The content of the node is defined in
>> dwc3.txt. +
>> +Phy documentation is provided in the following places:
>> +Documentation/devicetree/bindings/phy/rockchip,dwc3-usb-phy.txt
>> +
>> +Example device nodes:
>> +
>> +	usbdrd3_0: usb@fe800000 {
>> +		compatible = "rockchip,rk3399-dwc3";
>> +		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
>> +			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
>> +		clock-names = "ref_clk", "suspend_clk",
>> +			      "bus_clk_otg0", "grf_clk";
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +		status = "disabled";
>> +		usbdrd_dwc3_0: dwc3@fe800000 {
>> +			compatible = "snps,dwc3";
>> +			reg = <0x0 0xfe800000 0x0 0x100000>;
>> +			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
>> +			dr_mode = "otg";
>> +			status = "disabled";
>> +		};
>> +	};
>> --
>> 1.9.1
>
>
>

Re: [PATCH v5 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

[William Wu]

Dear Heiko,

On 06/30/2016 08:15 PM, Heiko Stuebner wrote:
> Hi William,
>
> Am Donnerstag, 30. Juni 2016, 19:16:40 schrieb William Wu:
>> This patch adds the devicetree documentation required for Rockchip
>> USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.
>>
>> It supports DRD mode, and could operate in device mode (SS, HS, FS)
>> and host mode (SS, HS, FS, LS).
>>
>> Signed-off-by: William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> ---
>> Changes in v5:
>> - rename clock-names, and remove unnecessary clocks (Heiko)
>>
>> Changes in v4:
>> - modify commit log, and add phy documentation location (Sergei)
>>
>> Changes in v3:
>> - add dwc3 address (balbi)
>>
>> Changes in v2:
>> - add rockchip,dwc3.txt to Documentation/devicetree/bindings/ (balbi,
>> Brian)
>>
>>   .../devicetree/bindings/usb/rockchip,dwc3.txt      | 40
>> ++++++++++++++++++++++ 1 file changed, 40 insertions(+)
>>   create mode 100644
>> Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
>>
>> diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
>> b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt new file mode
>> 100644
>> index 0000000..9c85e19
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
>> @@ -0,0 +1,40 @@
>> +Rockchip SuperSpeed DWC3 USB SoC controller
>> +
>> +Required properties:
>> +- compatible:	should contain "rockchip,rk3399-dwc3" for rk3399 SoC
>> +- clocks:	A list of phandle + clock-specifier pairs for the
>> +		clocks listed in clock-names
>> +- clock-names:	Should contain the following:
>> +  "ref_clk"	Controller reference clk, have to be 24 MHz
>> +  "suspend_clk"	Controller suspend clk, have to be 24 MHz or 32 KHz
>> +  "bus_clk_otg0"Master/Core clock, have to be >= 62.5 MHz for SS
>> +		operation and >= 60MHz for HS operation
> why is it called "bus_clk_otg0" not just simply "bus_clk". As far as I
> understand it (and see it in the TRM), you have two dwc3 controllers
> (otg0 and otg1) and clock-names are always meant from the perspective of
> the individual ip-block. So a devicetree would have:
>
> 	usbdrd3_0: usb@fe800000 {
> 		compatible = "rockchip,rk3399-dwc3";
> 		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
> 			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
> 		clock-names = "ref_clk", "suspend_clk",
> 			      "bus_clk", "grf_clk";
> 		...
> 	};
>
> 	usbdrd3_1: usb@fe900000 {
> 		compatible = "rockchip,rk3399-dwc3";
> 		clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
> 			 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
> 		clock-names = "ref_clk", "suspend_clk",
> 			      "bus_clk", "grf_clk";
> 		...
> 	};
>
>
> The rest looks really nice now.
Ah, it looks very goog to me. I'll fix it immediately.
Thank you very much!
>
>
> Heiko
>
>> +  "grf_clk"	Controller grf clk
>> +
>> +Required child node:
>> +A child node must exist to represent the core DWC3 IP block. The name of
>> +the node is not important. The content of the node is defined in
>> dwc3.txt. +
>> +Phy documentation is provided in the following places:
>> +Documentation/devicetree/bindings/phy/rockchip,dwc3-usb-phy.txt
>> +
>> +Example device nodes:
>> +
>> +	usbdrd3_0: usb@fe800000 {
>> +		compatible = "rockchip,rk3399-dwc3";
>> +		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
>> +			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
>> +		clock-names = "ref_clk", "suspend_clk",
>> +			      "bus_clk_otg0", "grf_clk";
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +		status = "disabled";
>> +		usbdrd_dwc3_0: dwc3@fe800000 {
>> +			compatible = "snps,dwc3";
>> +			reg = <0x0 0xfe800000 0x0 0x100000>;
>> +			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
>> +			dr_mode = "otg";
>> +			status = "disabled";
>> +		};
>> +	};
>> --
>> 1.9.1
>
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