From: David Long <dave.long@linaro.org> To: Catalin Marinas <catalin.marinas@arm.com>, Huang Shijie <shijie.huang@arm.com>, James Morse <james.morse@arm.com>, Marc Zyngier <marc.zyngier@arm.com>, Pratyush Anand <panand@redhat.com>, Sandeepa Prabhu <sandeepa.s.prabhu@gmail.com>, Will Deacon <will.deacon@arm.com>, William Cohen <wcohen@redhat.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Steve Capper <steve.capper@linaro.org>, Masami Hiramatsu <mhiramat@kernel.org>, Li Bin <huawei.libin@huawei.com> Cc: "Adam Buchbinder" <adam.buchbinder@gmail.com>, "Alex Bennée" <alex.bennee@linaro.org>, "Andrew Morton" <akpm@linux-foundation.org>, "Andrey Ryabinin" <ryabinin.a.a@gmail.com>, "Ard Biesheuvel" <ard.biesheuvel@linaro.org>, "Christoffer Dall" <christoffer.dall@linaro.org>, "Daniel Thompson" <daniel.thompson@linaro.org>, "Dave P Martin" <Dave.Martin@arm.com>, "Jens Wiklander" <jens.wiklander@linaro.org>, "Jisheng Zhang" <jszhang@marvell.com>, "John Blackwood" <john.blackwood@ccur.com>, "Mark Rutland" <mark.rutland@arm.com>, "Petr Mladek" <pmladek@suse.com>, "Robin Murphy" <robin.murphy@arm.com>, "Suzuki K Poulose" <suzuki.poulose@arm.com>, "Vladimir Murzin" <Vladimir.Murzin@arm.com>, "Yang Shi" <yang.shi@linaro.org>, "Zi Shen Lim" <zlim.lnx@gmail.com>, "yalin wang" <yalin.wang2010@gmail.com>, "Mark Brown" <broonie@kernel.org> Subject: [PATCH v15 02/10] arm64: Add more test functions to insn.c Date: Fri, 8 Jul 2016 12:35:46 -0400 [thread overview] Message-ID: <1467995754-32508-3-git-send-email-dave.long@linaro.org> (raw) In-Reply-To: <1467995754-32508-1-git-send-email-dave.long@linaro.org> From: "David A. Long" <dave.long@linaro.org> Certain instructions are hard to execute correctly out-of-line (as in kprobes). Test functions are added to insn.[hc] to identify these. The instructions include any that use PC-relative addressing, change the PC, or change interrupt masking. For efficiency and simplicity test functions are also added for small collections of related instructions. Signed-off-by: David A. Long <dave.long@linaro.org> Acked-by: Masami Hiramatsu <mhiramat@kernel.org> --- arch/arm64/include/asm/insn.h | 36 ++++++++++++++++++++++++++++++++++++ arch/arm64/kernel/insn.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index 30e50eb..497f7a2 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -120,6 +120,29 @@ enum aarch64_insn_register { AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */ }; +enum aarch64_insn_special_register { + AARCH64_INSN_SPCLREG_SPSR_EL1 = 0xC200, + AARCH64_INSN_SPCLREG_ELR_EL1 = 0xC201, + AARCH64_INSN_SPCLREG_SP_EL0 = 0xC208, + AARCH64_INSN_SPCLREG_SPSEL = 0xC210, + AARCH64_INSN_SPCLREG_CURRENTEL = 0xC212, + AARCH64_INSN_SPCLREG_DAIF = 0xDA11, + AARCH64_INSN_SPCLREG_NZCV = 0xDA10, + AARCH64_INSN_SPCLREG_FPCR = 0xDA20, + AARCH64_INSN_SPCLREG_DSPSR_EL0 = 0xDA28, + AARCH64_INSN_SPCLREG_DLR_EL0 = 0xDA29, + AARCH64_INSN_SPCLREG_SPSR_EL2 = 0xE200, + AARCH64_INSN_SPCLREG_ELR_EL2 = 0xE201, + AARCH64_INSN_SPCLREG_SP_EL1 = 0xE208, + AARCH64_INSN_SPCLREG_SPSR_INQ = 0xE218, + AARCH64_INSN_SPCLREG_SPSR_ABT = 0xE219, + AARCH64_INSN_SPCLREG_SPSR_UND = 0xE21A, + AARCH64_INSN_SPCLREG_SPSR_FIQ = 0xE21B, + AARCH64_INSN_SPCLREG_SPSR_EL3 = 0xF200, + AARCH64_INSN_SPCLREG_ELR_EL3 = 0xF201, + AARCH64_INSN_SPCLREG_SP_EL2 = 0xF210 +}; + enum aarch64_insn_variant { AARCH64_INSN_VARIANT_32BIT, AARCH64_INSN_VARIANT_64BIT @@ -223,8 +246,13 @@ static __always_inline bool aarch64_insn_is_##abbr(u32 code) \ static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \ { return (val); } +__AARCH64_INSN_FUNCS(adr_adrp, 0x1F000000, 0x10000000) +__AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000) __AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800) __AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800) +__AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000) +__AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000) +__AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000) __AARCH64_INSN_FUNCS(stp_post, 0x7FC00000, 0x28800000) __AARCH64_INSN_FUNCS(ldp_post, 0x7FC00000, 0x28C00000) __AARCH64_INSN_FUNCS(stp_pre, 0x7FC00000, 0x29800000) @@ -273,10 +301,15 @@ __AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001) __AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002) __AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003) __AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000) +__AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000) __AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F) __AARCH64_INSN_FUNCS(br, 0xFFFFFC1F, 0xD61F0000) __AARCH64_INSN_FUNCS(blr, 0xFFFFFC1F, 0xD63F0000) __AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000) +__AARCH64_INSN_FUNCS(eret, 0xFFFFFFFF, 0xD69F03E0) +__AARCH64_INSN_FUNCS(mrs, 0xFFF00000, 0xD5300000) +__AARCH64_INSN_FUNCS(msr_imm, 0xFFF8F01F, 0xD500401F) +__AARCH64_INSN_FUNCS(msr_reg, 0xFFF00000, 0xD5100000) #undef __AARCH64_INSN_FUNCS @@ -286,6 +319,8 @@ bool aarch64_insn_is_branch_imm(u32 insn); int aarch64_insn_read(void *addr, u32 *insnp); int aarch64_insn_write(void *addr, u32 insn); enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn); +bool aarch64_insn_uses_literal(u32 insn); +bool aarch64_insn_is_branch(u32 insn); u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn); u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type, u32 insn, u64 imm); @@ -367,6 +402,7 @@ bool aarch32_insn_is_wide(u32 insn); #define A32_RT_OFFSET 12 #define A32_RT2_OFFSET 0 +u32 aarch64_insn_extract_system_reg(u32 insn); u32 aarch32_insn_extract_reg_num(u32 insn, int offset); u32 aarch32_insn_mcr_extract_opc2(u32 insn); u32 aarch32_insn_mcr_extract_crm(u32 insn); diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c index 368c082..28c6110f 100644 --- a/arch/arm64/kernel/insn.c +++ b/arch/arm64/kernel/insn.c @@ -162,6 +162,32 @@ static bool __kprobes __aarch64_insn_hotpatch_safe(u32 insn) aarch64_insn_is_nop(insn); } +bool __kprobes aarch64_insn_uses_literal(u32 insn) +{ + /* ldr/ldrsw (literal), prfm */ + + return aarch64_insn_is_ldr_lit(insn) || + aarch64_insn_is_ldrsw_lit(insn) || + aarch64_insn_is_adr_adrp(insn) || + aarch64_insn_is_prfm_lit(insn); +} + +bool __kprobes aarch64_insn_is_branch(u32 insn) +{ + /* b, bl, cb*, tb*, b.cond, br, blr */ + + return aarch64_insn_is_b(insn) || + aarch64_insn_is_bl(insn) || + aarch64_insn_is_cbz(insn) || + aarch64_insn_is_cbnz(insn) || + aarch64_insn_is_tbz(insn) || + aarch64_insn_is_tbnz(insn) || + aarch64_insn_is_ret(insn) || + aarch64_insn_is_br(insn) || + aarch64_insn_is_blr(insn) || + aarch64_insn_is_bcond(insn); +} + /* * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a * Section B2.6.5 "Concurrent modification and execution of instructions": @@ -1175,6 +1201,14 @@ u32 aarch64_set_branch_offset(u32 insn, s32 offset) BUG(); } +/* + * Extract the Op/CR data from a msr/mrs instruction. + */ +u32 aarch64_insn_extract_system_reg(u32 insn) +{ + return (insn & 0x1FFFE0) >> 5; +} + bool aarch32_insn_is_wide(u32 insn) { return insn >= 0xe800; -- 2.5.0
WARNING: multiple messages have this Message-ID (diff)
From: dave.long@linaro.org (David Long) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v15 02/10] arm64: Add more test functions to insn.c Date: Fri, 8 Jul 2016 12:35:46 -0400 [thread overview] Message-ID: <1467995754-32508-3-git-send-email-dave.long@linaro.org> (raw) In-Reply-To: <1467995754-32508-1-git-send-email-dave.long@linaro.org> From: "David A. Long" <dave.long@linaro.org> Certain instructions are hard to execute correctly out-of-line (as in kprobes). Test functions are added to insn.[hc] to identify these. The instructions include any that use PC-relative addressing, change the PC, or change interrupt masking. For efficiency and simplicity test functions are also added for small collections of related instructions. Signed-off-by: David A. Long <dave.long@linaro.org> Acked-by: Masami Hiramatsu <mhiramat@kernel.org> --- arch/arm64/include/asm/insn.h | 36 ++++++++++++++++++++++++++++++++++++ arch/arm64/kernel/insn.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index 30e50eb..497f7a2 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -120,6 +120,29 @@ enum aarch64_insn_register { AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */ }; +enum aarch64_insn_special_register { + AARCH64_INSN_SPCLREG_SPSR_EL1 = 0xC200, + AARCH64_INSN_SPCLREG_ELR_EL1 = 0xC201, + AARCH64_INSN_SPCLREG_SP_EL0 = 0xC208, + AARCH64_INSN_SPCLREG_SPSEL = 0xC210, + AARCH64_INSN_SPCLREG_CURRENTEL = 0xC212, + AARCH64_INSN_SPCLREG_DAIF = 0xDA11, + AARCH64_INSN_SPCLREG_NZCV = 0xDA10, + AARCH64_INSN_SPCLREG_FPCR = 0xDA20, + AARCH64_INSN_SPCLREG_DSPSR_EL0 = 0xDA28, + AARCH64_INSN_SPCLREG_DLR_EL0 = 0xDA29, + AARCH64_INSN_SPCLREG_SPSR_EL2 = 0xE200, + AARCH64_INSN_SPCLREG_ELR_EL2 = 0xE201, + AARCH64_INSN_SPCLREG_SP_EL1 = 0xE208, + AARCH64_INSN_SPCLREG_SPSR_INQ = 0xE218, + AARCH64_INSN_SPCLREG_SPSR_ABT = 0xE219, + AARCH64_INSN_SPCLREG_SPSR_UND = 0xE21A, + AARCH64_INSN_SPCLREG_SPSR_FIQ = 0xE21B, + AARCH64_INSN_SPCLREG_SPSR_EL3 = 0xF200, + AARCH64_INSN_SPCLREG_ELR_EL3 = 0xF201, + AARCH64_INSN_SPCLREG_SP_EL2 = 0xF210 +}; + enum aarch64_insn_variant { AARCH64_INSN_VARIANT_32BIT, AARCH64_INSN_VARIANT_64BIT @@ -223,8 +246,13 @@ static __always_inline bool aarch64_insn_is_##abbr(u32 code) \ static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \ { return (val); } +__AARCH64_INSN_FUNCS(adr_adrp, 0x1F000000, 0x10000000) +__AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000) __AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800) __AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800) +__AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000) +__AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000) +__AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000) __AARCH64_INSN_FUNCS(stp_post, 0x7FC00000, 0x28800000) __AARCH64_INSN_FUNCS(ldp_post, 0x7FC00000, 0x28C00000) __AARCH64_INSN_FUNCS(stp_pre, 0x7FC00000, 0x29800000) @@ -273,10 +301,15 @@ __AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001) __AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002) __AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003) __AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000) +__AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000) __AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F) __AARCH64_INSN_FUNCS(br, 0xFFFFFC1F, 0xD61F0000) __AARCH64_INSN_FUNCS(blr, 0xFFFFFC1F, 0xD63F0000) __AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000) +__AARCH64_INSN_FUNCS(eret, 0xFFFFFFFF, 0xD69F03E0) +__AARCH64_INSN_FUNCS(mrs, 0xFFF00000, 0xD5300000) +__AARCH64_INSN_FUNCS(msr_imm, 0xFFF8F01F, 0xD500401F) +__AARCH64_INSN_FUNCS(msr_reg, 0xFFF00000, 0xD5100000) #undef __AARCH64_INSN_FUNCS @@ -286,6 +319,8 @@ bool aarch64_insn_is_branch_imm(u32 insn); int aarch64_insn_read(void *addr, u32 *insnp); int aarch64_insn_write(void *addr, u32 insn); enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn); +bool aarch64_insn_uses_literal(u32 insn); +bool aarch64_insn_is_branch(u32 insn); u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn); u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type, u32 insn, u64 imm); @@ -367,6 +402,7 @@ bool aarch32_insn_is_wide(u32 insn); #define A32_RT_OFFSET 12 #define A32_RT2_OFFSET 0 +u32 aarch64_insn_extract_system_reg(u32 insn); u32 aarch32_insn_extract_reg_num(u32 insn, int offset); u32 aarch32_insn_mcr_extract_opc2(u32 insn); u32 aarch32_insn_mcr_extract_crm(u32 insn); diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c index 368c082..28c6110f 100644 --- a/arch/arm64/kernel/insn.c +++ b/arch/arm64/kernel/insn.c @@ -162,6 +162,32 @@ static bool __kprobes __aarch64_insn_hotpatch_safe(u32 insn) aarch64_insn_is_nop(insn); } +bool __kprobes aarch64_insn_uses_literal(u32 insn) +{ + /* ldr/ldrsw (literal), prfm */ + + return aarch64_insn_is_ldr_lit(insn) || + aarch64_insn_is_ldrsw_lit(insn) || + aarch64_insn_is_adr_adrp(insn) || + aarch64_insn_is_prfm_lit(insn); +} + +bool __kprobes aarch64_insn_is_branch(u32 insn) +{ + /* b, bl, cb*, tb*, b.cond, br, blr */ + + return aarch64_insn_is_b(insn) || + aarch64_insn_is_bl(insn) || + aarch64_insn_is_cbz(insn) || + aarch64_insn_is_cbnz(insn) || + aarch64_insn_is_tbz(insn) || + aarch64_insn_is_tbnz(insn) || + aarch64_insn_is_ret(insn) || + aarch64_insn_is_br(insn) || + aarch64_insn_is_blr(insn) || + aarch64_insn_is_bcond(insn); +} + /* * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a * Section B2.6.5 "Concurrent modification and execution of instructions": @@ -1175,6 +1201,14 @@ u32 aarch64_set_branch_offset(u32 insn, s32 offset) BUG(); } +/* + * Extract the Op/CR data from a msr/mrs instruction. + */ +u32 aarch64_insn_extract_system_reg(u32 insn) +{ + return (insn & 0x1FFFE0) >> 5; +} + bool aarch32_insn_is_wide(u32 insn) { return insn >= 0xe800; -- 2.5.0
next prev parent reply other threads:[~2016-07-08 16:39 UTC|newest] Thread overview: 147+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-07-08 16:35 [PATCH v15 00/10] arm64: Add kernel probes (kprobes) support David Long 2016-07-08 16:35 ` David Long 2016-07-08 16:35 ` [PATCH v15 01/10] arm64: Add HAVE_REGS_AND_STACK_ACCESS_API feature David Long 2016-07-08 16:35 ` David Long 2016-07-15 10:57 ` Catalin Marinas 2016-07-15 10:57 ` Catalin Marinas 2016-07-15 14:51 ` David Long 2016-07-15 14:51 ` David Long 2016-07-15 15:13 ` Catalin Marinas 2016-07-15 15:13 ` Catalin Marinas 2016-07-15 17:51 ` David Long 2016-07-15 17:51 ` David Long 2016-07-19 14:17 ` Catalin Marinas 2016-07-19 14:17 ` Catalin Marinas 2016-07-08 16:35 ` David Long [this message] 2016-07-08 16:35 ` [PATCH v15 02/10] arm64: Add more test functions to insn.c David Long 2016-07-08 16:35 ` [PATCH v15 03/10] arm64: add conditional instruction simulation support David Long 2016-07-08 16:35 ` David Long 2016-07-08 16:35 ` [PATCH v15 04/10] arm64: Kprobes with single stepping support David Long 2016-07-08 16:35 ` David Long 2016-07-20 9:36 ` Marc Zyngier 2016-07-20 9:36 ` Marc Zyngier 2016-07-20 11:16 ` Catalin Marinas 2016-07-20 11:16 ` Catalin Marinas 2016-07-20 19:08 ` David Long 2016-07-20 19:08 ` David Long 2016-07-21 8:44 ` Marc Zyngier 2016-07-21 8:44 ` Marc Zyngier 2016-07-20 15:49 ` Catalin Marinas 2016-07-20 15:49 ` Catalin Marinas 2016-07-21 14:50 ` David Long 2016-07-21 14:50 ` David Long 2016-07-20 16:09 ` Marc Zyngier 2016-07-20 16:09 ` Marc Zyngier 2016-07-20 16:28 ` Catalin Marinas 2016-07-20 16:28 ` Catalin Marinas 2016-07-20 16:31 ` Marc Zyngier 2016-07-20 16:31 ` Marc Zyngier 2016-07-20 16:46 ` Marc Zyngier 2016-07-20 16:46 ` Marc Zyngier 2016-07-20 17:04 ` Catalin Marinas 2016-07-20 17:04 ` Catalin Marinas 2016-07-21 16:33 ` David Long 2016-07-21 16:33 ` David Long 2016-07-21 17:16 ` Catalin Marinas 2016-07-21 17:16 ` Catalin Marinas 2016-07-21 17:23 ` Marc Zyngier 2016-07-21 17:23 ` Marc Zyngier 2016-07-21 18:33 ` David Long 2016-07-21 18:33 ` David Long 2016-07-22 10:16 ` Catalin Marinas 2016-07-22 10:16 ` Catalin Marinas 2016-07-22 15:51 ` David Long 2016-07-22 15:51 ` David Long 2016-07-25 17:13 ` Catalin Marinas 2016-07-25 17:13 ` Catalin Marinas 2016-07-25 22:27 ` David Long 2016-07-25 22:27 ` David Long 2016-07-27 11:50 ` Daniel Thompson 2016-07-27 11:50 ` Daniel Thompson 2016-07-27 22:13 ` David Long 2016-07-27 22:13 ` David Long 2016-07-28 14:40 ` Catalin Marinas 2016-07-28 14:40 ` Catalin Marinas 2016-07-29 9:01 ` Daniel Thompson 2016-07-29 9:01 ` Daniel Thompson 2016-08-04 4:47 ` David Long 2016-08-04 4:47 ` David Long 2016-08-08 11:13 ` Daniel Thompson 2016-08-08 11:13 ` Daniel Thompson 2016-08-08 11:13 ` Daniel Thompson 2016-08-08 14:29 ` David Long 2016-08-08 14:29 ` David Long 2016-08-08 14:29 ` David Long 2016-08-08 22:49 ` Masami Hiramatsu 2016-08-08 22:49 ` Masami Hiramatsu 2016-08-08 22:49 ` Masami Hiramatsu 2016-08-09 17:23 ` Catalin Marinas 2016-08-09 17:23 ` Catalin Marinas 2016-08-09 17:23 ` Catalin Marinas 2016-08-10 20:41 ` David Long 2016-08-10 20:41 ` David Long 2016-08-10 20:41 ` David Long 2016-08-08 22:19 ` Masami Hiramatsu 2016-08-08 22:19 ` Masami Hiramatsu 2016-07-26 9:50 ` Daniel Thompson 2016-07-26 9:50 ` Daniel Thompson 2016-07-26 16:55 ` Catalin Marinas 2016-07-26 16:55 ` Catalin Marinas 2016-07-27 10:01 ` Dave Martin 2016-07-27 10:01 ` Dave Martin 2016-07-26 17:54 ` Mark Rutland 2016-07-26 17:54 ` Mark Rutland 2016-07-27 11:19 ` Daniel Thompson 2016-07-27 11:19 ` Daniel Thompson 2016-07-27 11:38 ` Dave Martin 2016-07-27 11:38 ` Dave Martin 2016-07-27 11:42 ` Daniel Thompson 2016-07-27 11:42 ` Daniel Thompson 2016-07-27 13:38 ` Mark Rutland 2016-07-27 13:38 ` Mark Rutland 2016-07-08 16:35 ` [PATCH v15 05/10] arm64: Blacklist non-kprobe-able symbol David Long 2016-07-08 16:35 ` David Long 2016-07-08 16:35 ` [PATCH v15 06/10] arm64: Treat all entry code as non-kprobe-able David Long 2016-07-08 16:35 ` David Long 2016-07-15 16:47 ` Catalin Marinas 2016-07-15 16:47 ` Catalin Marinas 2016-07-19 0:53 ` David Long 2016-07-19 0:53 ` David Long 2016-07-08 16:35 ` [PATCH v15 07/10] arm64: kprobes instruction simulation support David Long 2016-07-08 16:35 ` David Long 2016-07-10 22:51 ` Paul Gortmaker 2016-07-10 22:51 ` Paul Gortmaker 2016-07-08 16:35 ` [PATCH v15 08/10] arm64: Add trampoline code for kretprobes David Long 2016-07-08 16:35 ` David Long 2016-07-19 13:46 ` Catalin Marinas 2016-07-19 13:46 ` Catalin Marinas 2016-07-20 18:28 ` David Long 2016-07-20 18:28 ` David Long 2016-07-08 16:35 ` [PATCH v15 09/10] arm64: Add kernel return probes support (kretprobes) David Long 2016-07-08 16:35 ` David Long 2016-07-08 16:35 ` [PATCH v15 10/10] kprobes: Add arm64 case in kprobe example module David Long 2016-07-08 16:35 ` David Long 2016-07-14 16:22 ` [PATCH v15 00/10] arm64: Add kernel probes (kprobes) support Catalin Marinas 2016-07-14 16:22 ` Catalin Marinas 2016-07-14 17:09 ` William Cohen 2016-07-14 17:09 ` William Cohen 2016-07-15 7:50 ` Catalin Marinas 2016-07-15 7:50 ` Catalin Marinas 2016-07-15 8:01 ` Marc Zyngier 2016-07-15 8:01 ` Marc Zyngier 2016-07-15 8:59 ` Alex Bennée 2016-07-15 8:59 ` Alex Bennée 2016-07-15 9:04 ` Marc Zyngier 2016-07-15 9:04 ` Marc Zyngier 2016-07-15 9:53 ` Marc Zyngier 2016-07-15 9:53 ` Marc Zyngier 2016-07-14 17:56 ` David Long 2016-07-14 17:56 ` David Long 2016-07-19 13:57 ` Catalin Marinas 2016-07-19 13:57 ` Catalin Marinas 2016-07-19 14:01 ` David Long 2016-07-19 14:01 ` David Long 2016-07-19 18:27 ` Catalin Marinas 2016-07-19 18:27 ` Catalin Marinas 2016-07-19 19:38 ` David Long 2016-07-19 19:38 ` David Long
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