All of lore.kernel.org
 help / color / mirror / Atom feed
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au
Cc: qemu-devel@nongnu.org, aneesh.kumar@linux.vnet.ibm.com,
	benh@kernel.crashing.org, nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [RFC 4/6] target-ppc: add cmprb instruction
Date: Tue, 12 Jul 2016 23:33:20 +0530	[thread overview]
Message-ID: <1468346602-20700-5-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1468346602-20700-1-git-send-email-nikunj@linux.vnet.ibm.com>

ISA 3.0 Compare Ranged Byte instruction useful for
isupper/islower/isaplha kind of operation.

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 93c7c66..8de217f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -817,6 +817,45 @@ static void gen_cmpli(DisasContext *ctx)
     }
 }
 
+/* cmprb - range comparison: isupper, isaplha, islower*/
+static void gen_cmprb(DisasContext *ctx)
+{
+    TCGLabel *lab1 = gen_new_label();
+    TCGLabel *lab2 = gen_new_label();
+    TCGv src1 = tcg_temp_local_new();
+    TCGv src2 = tcg_temp_local_new();
+    TCGv src2lo = tcg_temp_local_new();
+    TCGv src2hi = tcg_temp_local_new();
+
+    tcg_gen_andi_tl(src1, cpu_gpr[rA(ctx->opcode)], 0xFF);
+    tcg_gen_andi_tl(src2, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF);
+
+    tcg_gen_andi_tl(src2lo, src2, 0xFF);
+    tcg_gen_shri_tl(src2hi, src2, 8);
+    tcg_gen_andi_tl(src2hi, src2hi, 0xFF);
+
+    tcg_gen_brcond_tl(TCG_COND_GTU, src1, src2hi, lab1);
+    tcg_gen_brcond_tl(TCG_COND_LTU, src1, src2lo, lab1);
+    tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 1 << CRF_GT);
+    tcg_gen_br(lab2);
+    gen_set_label(lab1);
+
+    if (ctx->opcode & 0x00200000) {
+        tcg_gen_shri_tl(src2hi, src2, 24);
+        tcg_gen_andi_tl(src2hi, src2hi, 0xFF);
+        tcg_gen_shri_tl(src2lo, src2, 16);
+        tcg_gen_andi_tl(src2lo, src2lo, 0xFF);
+        tcg_gen_brcond_tl(TCG_COND_GTU, src1, src2hi, lab2);
+        tcg_gen_brcond_tl(TCG_COND_LTU, src1, src2lo, lab2);
+        tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 1 << CRF_GT);
+    }
+    gen_set_label(lab2);
+    tcg_temp_free(src1);
+    tcg_temp_free(src2);
+    tcg_temp_free(src2lo);
+    tcg_temp_free(src2hi);
+}
+
 /* isel (PowerPC 2.03 specification) */
 static void gen_isel(DisasContext *ctx)
 {
@@ -9898,6 +9937,7 @@ GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-- 
2.7.4

  parent reply	other threads:[~2016-07-12 18:03 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-12 18:03 [Qemu-devel] [RFC 0/6] POWER9 TCG enablements - part1 Nikunj A Dadhania
2016-07-12 18:03 ` [Qemu-devel] [RFC 1/6] target-ppc: Introduce Power9 family Nikunj A Dadhania
2016-07-14  5:26   ` Bharata B Rao
2016-07-14  6:02     ` Nikunj A Dadhania
2016-07-18  1:48   ` David Gibson
2016-07-18  5:13     ` Nikunj A Dadhania
2016-07-12 18:03 ` [Qemu-devel] [RFC 2/6] target-ppc: Introduce POWER ISA 3.0 flag Nikunj A Dadhania
2016-07-18  1:49   ` David Gibson
2016-07-12 18:03 ` [Qemu-devel] [RFC 3/6] target-ppc: adding addpcis instruction Nikunj A Dadhania
2016-07-18  1:55   ` David Gibson
2016-07-21  5:59   ` Richard Henderson
2016-07-21  8:06     ` Nikunj A Dadhania
2016-07-12 18:03 ` Nikunj A Dadhania [this message]
2016-07-18  2:00   ` [Qemu-devel] [RFC 4/6] target-ppc: add cmprb instruction David Gibson
2016-07-21  6:17   ` Richard Henderson
2016-07-21  8:08     ` Nikunj A Dadhania
2016-08-02  7:02     ` Nikunj A Dadhania
2016-07-12 18:03 ` [Qemu-devel] [RFC 5/6] target-ppc: add modulo word operations Nikunj A Dadhania
2016-07-18  2:04   ` David Gibson
2016-07-18  5:08     ` Nikunj A Dadhania
2016-07-21  6:24       ` Richard Henderson
2016-07-21  8:11         ` Nikunj A Dadhania
2016-07-21 10:24           ` Richard Henderson
2016-07-12 18:03 ` [Qemu-devel] [RFC 6/6] target-ppc: add modulo dword operations Nikunj A Dadhania

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1468346602-20700-5-git-send-email-nikunj@linux.vnet.ibm.com \
    --to=nikunj@linux.vnet.ibm.com \
    --cc=aneesh.kumar@linux.vnet.ibm.com \
    --cc=benh@kernel.crashing.org \
    --cc=david@gibson.dropbear.id.au \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.