Re: [Qemu-devel] [RFC 1/6] target-ppc: Introduce Power9 family

[David Gibson <david@gibson.dropbear.id.au>]

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On Tue, Jul 12, 2016 at 11:33:17PM +0530, Nikunj A Dadhania wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
> 
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> [ rebased and added POWER9 alias ]
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
>  target-ppc/cpu-models.c     |  5 +++
>  target-ppc/cpu-models.h     |  2 ++
>  target-ppc/cpu-qom.h        |  7 ++++
>  target-ppc/mmu_helper.c     |  3 +-
>  target-ppc/translate_init.c | 85 ++++++++++++++++++++++++++++++++++++++++++++-
>  5 files changed, 100 insertions(+), 2 deletions(-)
> 
> diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
> index 5209e63..901cf40 100644
> --- a/target-ppc/cpu-models.c
> +++ b/target-ppc/cpu-models.c
> @@ -1147,6 +1147,10 @@
>                  "POWER8NVL v1.0")
>      POWERPC_DEF("970_v2.2",      CPU_POWERPC_970_v22,                970,
>                  "PowerPC 970 v2.2")
> +
> +    POWERPC_DEF("POWER9_v1.0",   CPU_POWERPC_POWER9_BASE,            POWER9,
> +                "POWER9 v1.0")
> +
>      POWERPC_DEF("970fx_v1.0",    CPU_POWERPC_970FX_v10,              970,
>                  "PowerPC 970FX v1.0 (G5)")
>      POWERPC_DEF("970fx_v2.0",    CPU_POWERPC_970FX_v20,              970,
> @@ -1395,6 +1399,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
>      { "POWER8E", "POWER8E_v2.1" },
>      { "POWER8", "POWER8_v2.0" },
>      { "POWER8NVL", "POWER8NVL_v1.0" },
> +    { "POWER9", "POWER9_v1.0" },
>      { "970", "970_v2.2" },
>      { "970fx", "970fx_v3.1" },
>      { "970mp", "970mp_v1.1" },
> diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h
> index f21a44c..beeaaba 100644
> --- a/target-ppc/cpu-models.h
> +++ b/target-ppc/cpu-models.h
> @@ -562,6 +562,8 @@ enum {
>      CPU_POWERPC_POWER8_v20         = 0x004D0200,
>      CPU_POWERPC_POWER8NVL_BASE     = 0x004C0000,
>      CPU_POWERPC_POWER8NVL_v10      = 0x004C0100,
> +    CPU_POWERPC_POWER9_BASE        = 0x004E0000,
> +    CPU_POWERPC_POWER9_MAM         = 0x004E0100,
>      CPU_POWERPC_970_v22            = 0x00390202,
>      CPU_POWERPC_970FX_v10          = 0x00391100,
>      CPU_POWERPC_970FX_v20          = 0x003C0200,
> diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
> index 2864105..df2fb65 100644
> --- a/target-ppc/cpu-qom.h
> +++ b/target-ppc/cpu-qom.h
> @@ -86,6 +86,13 @@ enum powerpc_mmu_t {
>      POWERPC_MMU_2_07       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
>                               | POWERPC_MMU_64K
>                               | POWERPC_MMU_AMR | 0x00000004,
> +    /* for now , We can add radix later if needed */

I'm guessing this means you're only thinking about the guest-side
presentation of the P9 MMU at this point?  IIUC the host side
presentation is so different that sharing any constants with pre-P9
MMUs probably doesn't make sense.

I'm not immediately sure how we should make this distinction in the
target-ppc code, since these values are supposed to belong to the CPU
regardless of operating mode.


> +    /* POWERPC_MMU_3_00       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> +     * | POWERPC_MMU_AMR | 0x00000005,
> +     */
> +
> +    POWERPC_MMU_3_00       = POWERPC_MMU_64 | POWERPC_MMU_AMR | 0x00000005,
> +
>      /* Architecture 2.07 "degraded" (no 1T segments)           */
>      POWERPC_MMU_2_07a      = POWERPC_MMU_64 | POWERPC_MMU_AMR
>                               | 0x00000004,
> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
> index 485d5b8..6219c4a 100644
> --- a/target-ppc/mmu_helper.c
> +++ b/target-ppc/mmu_helper.c
> @@ -1935,13 +1935,14 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
>      case POWERPC_MMU_2_06a:
>      case POWERPC_MMU_2_07:
>      case POWERPC_MMU_2_07a:
> +    case POWERPC_MMU_3_00:
>  #endif /* defined(TARGET_PPC64) */
>          env->tlb_need_flush = 0;
>          tlb_flush(CPU(cpu), 1);
>          break;
>      default:
>          /* XXX: TODO */
> -        cpu_abort(CPU(cpu), "Unknown MMU model\n");
> +        cpu_abort(CPU(cpu), "Unknown MMU model %d\n", env->mmu_model);
>          break;
>      }
>  }
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 8f257fb..51bab23 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7459,7 +7459,8 @@ enum BOOK3S_CPU_TYPE {
>      BOOK3S_CPU_POWER5PLUS,
>      BOOK3S_CPU_POWER6,
>      BOOK3S_CPU_POWER7,
> -    BOOK3S_CPU_POWER8
> +    BOOK3S_CPU_POWER8,
> +    BOOK3S_CPU_POWER9
>  };
>  
>  static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
> @@ -8241,6 +8242,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>          break;
>      case BOOK3S_CPU_POWER7:
>      case BOOK3S_CPU_POWER8:
> +    case BOOK3S_CPU_POWER9:
>          gen_spr_book3s_ids(env);
>          gen_spr_amr(env, version >= BOOK3S_CPU_POWER8);
>          gen_spr_book3s_purr(env);
> @@ -8293,6 +8295,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>          break;
>      case BOOK3S_CPU_POWER7:
>      case BOOK3S_CPU_POWER8:
> +    case BOOK3S_CPU_POWER9:
>      default:
>          env->slb_nr = 32;
>          break;
> @@ -8310,6 +8313,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>          ppcPOWER7_irq_init(ppc_env_get_cpu(env));
>          break;
>      case BOOK3S_CPU_POWER8:
> +    case BOOK3S_CPU_POWER9:
>          init_excp_POWER8(env);
>          ppcPOWER7_irq_init(ppc_env_get_cpu(env));
>          break;
> @@ -8772,6 +8776,85 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>      pcc->l1_icache_size = 0x8000;
>      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
>  }
> +static void init_proc_POWER9(CPUPPCState *env)
> +{
> +    init_proc_book3s_64(env, BOOK3S_CPU_POWER9);
> +}
> +
> +static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
> +{
> +    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
> +        return true;
> +    }
> +    return false;
> +}
> +
> +POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(oc);
> +    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> +
> +    dc->fw_name = "PowerPC,POWER9";
> +    dc->desc = "POWER9";
> +    dc->props = powerpc_servercpu_properties;
> +    pcc->pvr_match = ppc_pvr_match_power9;
> +    pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
> +    pcc->init_proc = init_proc_POWER9;
> +    pcc->check_pow = check_pow_nocheck;
> +    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
> +                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> +                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> +                       PPC_FLOAT_FRSQRTES |
> +                       PPC_FLOAT_STFIWX |
> +                       PPC_FLOAT_EXT |
> +                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
> +                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
> +                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> +                       PPC_64B | PPC_64BX | PPC_ALTIVEC |
> +                       PPC_SEGMENT_64B | PPC_SLBI |
> +                       PPC_POPCNTB | PPC_POPCNTWD |
> +                       PPC_CILDST;
> +    pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
> +                        PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
> +                        PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
> +                        PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
> +                        PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
> +                        PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
> +                        PPC2_TM | PPC2_PM_ISA206;
> +    pcc->msr_mask = (1ull << MSR_SF) |
> +                    (1ull << MSR_TM) |
> +                    (1ull << MSR_VR) |
> +                    (1ull << MSR_VSX) |
> +                    (1ull << MSR_EE) |
> +                    (1ull << MSR_PR) |
> +                    (1ull << MSR_FP) |
> +                    (1ull << MSR_ME) |
> +                    (1ull << MSR_FE0) |
> +                    (1ull << MSR_SE) |
> +                    (1ull << MSR_DE) |
> +                    (1ull << MSR_FE1) |
> +                    (1ull << MSR_IR) |
> +                    (1ull << MSR_DR) |
> +                    (1ull << MSR_PMM) |
> +                    (1ull << MSR_RI) |
> +                    (1ull << MSR_LE);
> +    pcc->mmu_model = POWERPC_MMU_3_00;
> +#if defined(CONFIG_SOFTMMU)
> +    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> +    /* segment page size remain the same */
> +    pcc->sps = &POWER7_POWER8_sps;
> +#endif
> +    pcc->excp_model = POWERPC_EXCP_POWER8;
> +    pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
> +    pcc->bfd_mach = bfd_mach_ppc64;
> +    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
> +                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
> +                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
> +                 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
> +    pcc->l1_dcache_size = 0x8000;
> +    pcc->l1_icache_size = 0x8000;
> +    pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> +}
>  
>  #if !defined(CONFIG_USER_ONLY)
>  

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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