From: YT Shen <yt.shen@mediatek.com>
To: <dri-devel@lists.freedesktop.org>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Russell King <linux@arm.linux.org.uk>,
David Airlie <airlied@linux.ie>,
Matthias Brugger <matthias.bgg@gmail.com>,
YT Shen <yt.shen@mediatek.com>, CK Hu <ck.hu@mediatek.com>,
Mao Huang <littlecvr@chromium.org>,
Bibby Hsieh <bibby.hsieh@mediatek.com>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>,
Sascha Hauer <kernel@pengutronix.de>, <yingjoe.chen@mediatek.com>,
<emil.l.velikov@gmail.com>, <thierry.reding@gmail.com>,
shaoming chen <shaoming.chen@mediatek.com>
Subject: [PATCH v4 5/8] drm/mediatek: add dsi interrupt control
Date: Fri, 15 Jul 2016 18:07:51 +0800 [thread overview]
Message-ID: <1468577274-6178-6-git-send-email-yt.shen@mediatek.com> (raw)
In-Reply-To: <1468577274-6178-1-git-send-email-yt.shen@mediatek.com>
From: shaoming chen <shaoming.chen@mediatek.com>
add dsi interrupt control
Signed-off-by: shaoming chen <shaoming.chen@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 130 ++++++++++++++++++++++++++++++++++++
1 file changed, 130 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 2d808e5..de5ad7f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -18,6 +18,7 @@
#include <drm/drm_panel.h>
#include <linux/clk.h>
#include <linux/component.h>
+#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_graph.h>
@@ -32,6 +33,13 @@
#define DSI_START 0x00
+#define DSI_INTEN 0x08
+
+#define DSI_INTSTA 0x0c
+#define LPRX_RD_RDY_INT_FLAG BIT(0)
+#define CMD_DONE_INT_FLAG BIT(1)
+#define DSI_BUSY BIT(31)
+
#define DSI_CON_CTRL 0x10
#define DSI_RESET BIT(0)
#define DSI_EN BIT(1)
@@ -74,6 +82,9 @@
#define DSI_HSTX_CKL_WC 0x64
+#define DSI_RACK 0x84
+#define RACK BIT(0)
+
#define DSI_PHY_LCCON 0x104
#define LC_HS_TX_EN BIT(0)
#define LC_ULPM_EN BIT(1)
@@ -134,6 +145,18 @@ struct mtk_dsi {
struct videomode vm;
int refcount;
bool enabled;
+ int irq_num, irq_data;
+};
+
+enum {
+ DSI_INT_SLEEPOUT_DONE_FLAG = BIT(6),
+ DSI_INT_VM_CMD_DONE_FLAG = BIT(5),
+ DSI_INT_EXT_TE_RDY_FLAG = BIT(4),
+ DSI_INT_VM_DONE_FLAG = BIT(3),
+ DSI_INT_TE_RDY_FLAG = BIT(2),
+ DSI_INT_CMD_DONE_FLAG = BIT(1),
+ DSI_INT_LPRX_RD_RDY_FLAG = BIT(0),
+ DSI_INT_ALL_BITS = (0x7f)
};
static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
@@ -440,6 +463,94 @@ static void mtk_dsi_start(struct mtk_dsi *dsi)
writel(1, dsi->regs + DSI_START);
}
+static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
+{
+ u32 inten = DSI_INT_ALL_BITS;
+
+ if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO)
+ inten &= ~(DSI_INT_TE_RDY_FLAG | DSI_INT_EXT_TE_RDY_FLAG);
+
+ writel(inten, dsi->regs + DSI_INTEN);
+}
+
+static void mtk_dsi_irq_wakeup(struct mtk_dsi *dsi, u32 irq_bit)
+{
+ dsi->irq_data |= irq_bit;
+}
+
+static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
+{
+ struct mtk_dsi *dsi = dev_id;
+
+ u32 status, tmp;
+
+ status = readl(dsi->regs + DSI_INTSTA);
+
+ if (status & DSI_INT_LPRX_RD_RDY_FLAG) {
+ /* write clear RD_RDY interrupt */
+ /* write clear RD_RDY interrupt must be before DSI_RACK */
+ /* because CMD_DONE will raise after DSI_RACK, */
+ /* so write clear RD_RDY after that will clear CMD_DONE too */
+ do {
+ /* send read ACK */
+ mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
+ tmp = readl(dsi->regs + DSI_INTSTA);
+ } while (tmp & DSI_BUSY);
+
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_LPRX_RD_RDY_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_LPRX_RD_RDY_FLAG);
+ }
+
+ if (status & DSI_INT_CMD_DONE_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_CMD_DONE_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_CMD_DONE_FLAG);
+ }
+
+ if (status & DSI_INT_TE_RDY_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_TE_RDY_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_TE_RDY_FLAG);
+ }
+
+ if (status & DSI_INT_VM_DONE_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_VM_DONE_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_VM_DONE_FLAG);
+ }
+
+ if (status & DSI_INT_EXT_TE_RDY_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_EXT_TE_RDY_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_EXT_TE_RDY_FLAG);
+ }
+
+ if (status & DSI_INT_VM_CMD_DONE_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_VM_CMD_DONE_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_VM_CMD_DONE_FLAG);
+ }
+
+ if (status & DSI_INT_SLEEPOUT_DONE_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_SLEEPOUT_DONE_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_SLEEPOUT_DONE_FLAG);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static s32 mtk_dsi_wait_for_irq_timeout(struct mtk_dsi *dsi, u32 irq_bit,
+ u32 timeout_ms)
+{
+ while (timeout_ms--) {
+ if (dsi->irq_data & irq_bit) {
+ dsi->irq_data &= ~irq_bit;
+ return 0;
+ }
+
+ usleep_range(1000, 1100);
+ }
+
+ dsi->irq_data = 0;
+
+ return -1;
+}
+
static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
{
if (WARN_ON(dsi->refcount == 0))
@@ -488,6 +599,7 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
dsi_ps_control_vact(dsi);
dsi_config_vdo_timing(dsi);
+ mtk_dsi_set_interrupt_enable(dsi);
dsi_set_mode(dsi);
dsi_clk_hs_mode(dsi, 1);
@@ -883,6 +995,24 @@ static int mtk_dsi_probe(struct platform_device *pdev)
return ret;
}
+ dsi->irq_num = platform_get_irq(pdev, 0);
+ if (dsi->irq_num < 0) {
+ dev_err(&pdev->dev, "failed to request dsi irq resource\n");
+ ret = dsi->irq_num;
+ return -EPROBE_DEFER;
+ }
+
+ irq_set_status_flags(dsi->irq_num, IRQ_TYPE_LEVEL_LOW);
+ ret = devm_request_irq(&pdev->dev, dsi->irq_num, mtk_dsi_irq,
+ IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
+ return -EPROBE_DEFER;
+ }
+
+ dsi->irq_data = 0;
+ dev_info(dev, "dsi irq num is 0x%x\n", dsi->irq_num);
+
platform_set_drvdata(pdev, dsi);
return component_add(&pdev->dev, &mtk_dsi_component_ops);
--
1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: YT Shen <yt.shen@mediatek.com>
To: dri-devel@lists.freedesktop.org, Philipp Zabel <p.zabel@pengutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>,
Russell King <linux@arm.linux.org.uk>,
Mao Huang <littlecvr@chromium.org>,
yingjoe.chen@mediatek.com, devicetree@vger.kernel.org,
Pawel Moll <pawel.moll@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Rob Herring <robh+dt@kernel.org>,
linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
shaoming chen <shaoming.chen@mediatek.com>,
linux-arm-kernel@lists.infradead.org,
srv_heupstream@mediatek.com, emil.l.velikov@gmail.com,
linux-kernel@vger.kernel.org,
Sascha Hauer <kernel@pengutronix.de>,
Kumar Gala <galak@codeaurora.org>
Subject: [PATCH v4 5/8] drm/mediatek: add dsi interrupt control
Date: Fri, 15 Jul 2016 18:07:51 +0800 [thread overview]
Message-ID: <1468577274-6178-6-git-send-email-yt.shen@mediatek.com> (raw)
In-Reply-To: <1468577274-6178-1-git-send-email-yt.shen@mediatek.com>
From: shaoming chen <shaoming.chen@mediatek.com>
add dsi interrupt control
Signed-off-by: shaoming chen <shaoming.chen@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 130 ++++++++++++++++++++++++++++++++++++
1 file changed, 130 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 2d808e5..de5ad7f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -18,6 +18,7 @@
#include <drm/drm_panel.h>
#include <linux/clk.h>
#include <linux/component.h>
+#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_graph.h>
@@ -32,6 +33,13 @@
#define DSI_START 0x00
+#define DSI_INTEN 0x08
+
+#define DSI_INTSTA 0x0c
+#define LPRX_RD_RDY_INT_FLAG BIT(0)
+#define CMD_DONE_INT_FLAG BIT(1)
+#define DSI_BUSY BIT(31)
+
#define DSI_CON_CTRL 0x10
#define DSI_RESET BIT(0)
#define DSI_EN BIT(1)
@@ -74,6 +82,9 @@
#define DSI_HSTX_CKL_WC 0x64
+#define DSI_RACK 0x84
+#define RACK BIT(0)
+
#define DSI_PHY_LCCON 0x104
#define LC_HS_TX_EN BIT(0)
#define LC_ULPM_EN BIT(1)
@@ -134,6 +145,18 @@ struct mtk_dsi {
struct videomode vm;
int refcount;
bool enabled;
+ int irq_num, irq_data;
+};
+
+enum {
+ DSI_INT_SLEEPOUT_DONE_FLAG = BIT(6),
+ DSI_INT_VM_CMD_DONE_FLAG = BIT(5),
+ DSI_INT_EXT_TE_RDY_FLAG = BIT(4),
+ DSI_INT_VM_DONE_FLAG = BIT(3),
+ DSI_INT_TE_RDY_FLAG = BIT(2),
+ DSI_INT_CMD_DONE_FLAG = BIT(1),
+ DSI_INT_LPRX_RD_RDY_FLAG = BIT(0),
+ DSI_INT_ALL_BITS = (0x7f)
};
static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
@@ -440,6 +463,94 @@ static void mtk_dsi_start(struct mtk_dsi *dsi)
writel(1, dsi->regs + DSI_START);
}
+static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
+{
+ u32 inten = DSI_INT_ALL_BITS;
+
+ if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO)
+ inten &= ~(DSI_INT_TE_RDY_FLAG | DSI_INT_EXT_TE_RDY_FLAG);
+
+ writel(inten, dsi->regs + DSI_INTEN);
+}
+
+static void mtk_dsi_irq_wakeup(struct mtk_dsi *dsi, u32 irq_bit)
+{
+ dsi->irq_data |= irq_bit;
+}
+
+static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
+{
+ struct mtk_dsi *dsi = dev_id;
+
+ u32 status, tmp;
+
+ status = readl(dsi->regs + DSI_INTSTA);
+
+ if (status & DSI_INT_LPRX_RD_RDY_FLAG) {
+ /* write clear RD_RDY interrupt */
+ /* write clear RD_RDY interrupt must be before DSI_RACK */
+ /* because CMD_DONE will raise after DSI_RACK, */
+ /* so write clear RD_RDY after that will clear CMD_DONE too */
+ do {
+ /* send read ACK */
+ mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
+ tmp = readl(dsi->regs + DSI_INTSTA);
+ } while (tmp & DSI_BUSY);
+
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_LPRX_RD_RDY_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_LPRX_RD_RDY_FLAG);
+ }
+
+ if (status & DSI_INT_CMD_DONE_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_CMD_DONE_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_CMD_DONE_FLAG);
+ }
+
+ if (status & DSI_INT_TE_RDY_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_TE_RDY_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_TE_RDY_FLAG);
+ }
+
+ if (status & DSI_INT_VM_DONE_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_VM_DONE_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_VM_DONE_FLAG);
+ }
+
+ if (status & DSI_INT_EXT_TE_RDY_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_EXT_TE_RDY_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_EXT_TE_RDY_FLAG);
+ }
+
+ if (status & DSI_INT_VM_CMD_DONE_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_VM_CMD_DONE_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_VM_CMD_DONE_FLAG);
+ }
+
+ if (status & DSI_INT_SLEEPOUT_DONE_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_SLEEPOUT_DONE_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_SLEEPOUT_DONE_FLAG);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static s32 mtk_dsi_wait_for_irq_timeout(struct mtk_dsi *dsi, u32 irq_bit,
+ u32 timeout_ms)
+{
+ while (timeout_ms--) {
+ if (dsi->irq_data & irq_bit) {
+ dsi->irq_data &= ~irq_bit;
+ return 0;
+ }
+
+ usleep_range(1000, 1100);
+ }
+
+ dsi->irq_data = 0;
+
+ return -1;
+}
+
static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
{
if (WARN_ON(dsi->refcount == 0))
@@ -488,6 +599,7 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
dsi_ps_control_vact(dsi);
dsi_config_vdo_timing(dsi);
+ mtk_dsi_set_interrupt_enable(dsi);
dsi_set_mode(dsi);
dsi_clk_hs_mode(dsi, 1);
@@ -883,6 +995,24 @@ static int mtk_dsi_probe(struct platform_device *pdev)
return ret;
}
+ dsi->irq_num = platform_get_irq(pdev, 0);
+ if (dsi->irq_num < 0) {
+ dev_err(&pdev->dev, "failed to request dsi irq resource\n");
+ ret = dsi->irq_num;
+ return -EPROBE_DEFER;
+ }
+
+ irq_set_status_flags(dsi->irq_num, IRQ_TYPE_LEVEL_LOW);
+ ret = devm_request_irq(&pdev->dev, dsi->irq_num, mtk_dsi_irq,
+ IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
+ return -EPROBE_DEFER;
+ }
+
+ dsi->irq_data = 0;
+ dev_info(dev, "dsi irq num is 0x%x\n", dsi->irq_num);
+
platform_set_drvdata(pdev, dsi);
return component_add(&pdev->dev, &mtk_dsi_component_ops);
--
1.7.9.5
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: yt.shen@mediatek.com (YT Shen)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 5/8] drm/mediatek: add dsi interrupt control
Date: Fri, 15 Jul 2016 18:07:51 +0800 [thread overview]
Message-ID: <1468577274-6178-6-git-send-email-yt.shen@mediatek.com> (raw)
In-Reply-To: <1468577274-6178-1-git-send-email-yt.shen@mediatek.com>
From: shaoming chen <shaoming.chen@mediatek.com>
add dsi interrupt control
Signed-off-by: shaoming chen <shaoming.chen@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 130 ++++++++++++++++++++++++++++++++++++
1 file changed, 130 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 2d808e5..de5ad7f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -18,6 +18,7 @@
#include <drm/drm_panel.h>
#include <linux/clk.h>
#include <linux/component.h>
+#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_graph.h>
@@ -32,6 +33,13 @@
#define DSI_START 0x00
+#define DSI_INTEN 0x08
+
+#define DSI_INTSTA 0x0c
+#define LPRX_RD_RDY_INT_FLAG BIT(0)
+#define CMD_DONE_INT_FLAG BIT(1)
+#define DSI_BUSY BIT(31)
+
#define DSI_CON_CTRL 0x10
#define DSI_RESET BIT(0)
#define DSI_EN BIT(1)
@@ -74,6 +82,9 @@
#define DSI_HSTX_CKL_WC 0x64
+#define DSI_RACK 0x84
+#define RACK BIT(0)
+
#define DSI_PHY_LCCON 0x104
#define LC_HS_TX_EN BIT(0)
#define LC_ULPM_EN BIT(1)
@@ -134,6 +145,18 @@ struct mtk_dsi {
struct videomode vm;
int refcount;
bool enabled;
+ int irq_num, irq_data;
+};
+
+enum {
+ DSI_INT_SLEEPOUT_DONE_FLAG = BIT(6),
+ DSI_INT_VM_CMD_DONE_FLAG = BIT(5),
+ DSI_INT_EXT_TE_RDY_FLAG = BIT(4),
+ DSI_INT_VM_DONE_FLAG = BIT(3),
+ DSI_INT_TE_RDY_FLAG = BIT(2),
+ DSI_INT_CMD_DONE_FLAG = BIT(1),
+ DSI_INT_LPRX_RD_RDY_FLAG = BIT(0),
+ DSI_INT_ALL_BITS = (0x7f)
};
static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
@@ -440,6 +463,94 @@ static void mtk_dsi_start(struct mtk_dsi *dsi)
writel(1, dsi->regs + DSI_START);
}
+static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
+{
+ u32 inten = DSI_INT_ALL_BITS;
+
+ if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO)
+ inten &= ~(DSI_INT_TE_RDY_FLAG | DSI_INT_EXT_TE_RDY_FLAG);
+
+ writel(inten, dsi->regs + DSI_INTEN);
+}
+
+static void mtk_dsi_irq_wakeup(struct mtk_dsi *dsi, u32 irq_bit)
+{
+ dsi->irq_data |= irq_bit;
+}
+
+static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
+{
+ struct mtk_dsi *dsi = dev_id;
+
+ u32 status, tmp;
+
+ status = readl(dsi->regs + DSI_INTSTA);
+
+ if (status & DSI_INT_LPRX_RD_RDY_FLAG) {
+ /* write clear RD_RDY interrupt */
+ /* write clear RD_RDY interrupt must be before DSI_RACK */
+ /* because CMD_DONE will raise after DSI_RACK, */
+ /* so write clear RD_RDY after that will clear CMD_DONE too */
+ do {
+ /* send read ACK */
+ mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
+ tmp = readl(dsi->regs + DSI_INTSTA);
+ } while (tmp & DSI_BUSY);
+
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_LPRX_RD_RDY_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_LPRX_RD_RDY_FLAG);
+ }
+
+ if (status & DSI_INT_CMD_DONE_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_CMD_DONE_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_CMD_DONE_FLAG);
+ }
+
+ if (status & DSI_INT_TE_RDY_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_TE_RDY_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_TE_RDY_FLAG);
+ }
+
+ if (status & DSI_INT_VM_DONE_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_VM_DONE_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_VM_DONE_FLAG);
+ }
+
+ if (status & DSI_INT_EXT_TE_RDY_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_EXT_TE_RDY_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_EXT_TE_RDY_FLAG);
+ }
+
+ if (status & DSI_INT_VM_CMD_DONE_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_VM_CMD_DONE_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_VM_CMD_DONE_FLAG);
+ }
+
+ if (status & DSI_INT_SLEEPOUT_DONE_FLAG) {
+ mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_SLEEPOUT_DONE_FLAG, 0);
+ mtk_dsi_irq_wakeup(dsi, DSI_INT_SLEEPOUT_DONE_FLAG);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static s32 mtk_dsi_wait_for_irq_timeout(struct mtk_dsi *dsi, u32 irq_bit,
+ u32 timeout_ms)
+{
+ while (timeout_ms--) {
+ if (dsi->irq_data & irq_bit) {
+ dsi->irq_data &= ~irq_bit;
+ return 0;
+ }
+
+ usleep_range(1000, 1100);
+ }
+
+ dsi->irq_data = 0;
+
+ return -1;
+}
+
static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
{
if (WARN_ON(dsi->refcount == 0))
@@ -488,6 +599,7 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
dsi_ps_control_vact(dsi);
dsi_config_vdo_timing(dsi);
+ mtk_dsi_set_interrupt_enable(dsi);
dsi_set_mode(dsi);
dsi_clk_hs_mode(dsi, 1);
@@ -883,6 +995,24 @@ static int mtk_dsi_probe(struct platform_device *pdev)
return ret;
}
+ dsi->irq_num = platform_get_irq(pdev, 0);
+ if (dsi->irq_num < 0) {
+ dev_err(&pdev->dev, "failed to request dsi irq resource\n");
+ ret = dsi->irq_num;
+ return -EPROBE_DEFER;
+ }
+
+ irq_set_status_flags(dsi->irq_num, IRQ_TYPE_LEVEL_LOW);
+ ret = devm_request_irq(&pdev->dev, dsi->irq_num, mtk_dsi_irq,
+ IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
+ return -EPROBE_DEFER;
+ }
+
+ dsi->irq_data = 0;
+ dev_info(dev, "dsi irq num is 0x%x\n", dsi->irq_num);
+
platform_set_drvdata(pdev, dsi);
return component_add(&pdev->dev, &mtk_dsi_component_ops);
--
1.7.9.5
next prev parent reply other threads:[~2016-07-15 10:09 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-15 10:07 [PATCH v4 0/8] MT2701 DRM support YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-15 10:07 ` [PATCH v4 1/8] drm/mediatek: rename macros, add chip prefix YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-15 10:07 ` [PATCH v4 2/8] drm/mediatek: add *driver_data for different hardware settings YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-15 10:07 ` [PATCH v4 3/8] drm/mediatek: add shadow register support YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-18 6:32 ` CK Hu
2016-07-18 6:32 ` CK Hu
2016-07-18 6:32 ` CK Hu
2016-07-18 8:36 ` Philipp Zabel
2016-07-18 8:36 ` Philipp Zabel
2016-07-18 8:36 ` Philipp Zabel
2016-07-19 11:12 ` YT Shen
2016-07-19 11:12 ` YT Shen
2016-07-19 11:12 ` YT Shen
2016-07-15 10:07 ` [PATCH v4 4/8] drm/mediatek: add support for Mediatek SoC MT2701 YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-18 6:58 ` CK Hu
2016-07-18 6:58 ` CK Hu
2016-07-18 6:58 ` CK Hu
2016-07-19 11:09 ` YT Shen
2016-07-19 11:09 ` YT Shen
2016-07-19 11:09 ` YT Shen
2016-07-20 6:53 ` CK Hu
2016-07-20 6:53 ` CK Hu
2016-07-20 6:53 ` CK Hu
2016-07-26 10:42 ` YT Shen
2016-07-26 10:42 ` YT Shen
2016-07-26 10:42 ` YT Shen
2016-07-27 10:03 ` Philipp Zabel
2016-07-27 10:03 ` Philipp Zabel
2016-07-27 10:03 ` Philipp Zabel
2016-07-28 2:07 ` CK Hu
2016-07-28 2:07 ` CK Hu
2016-07-28 2:07 ` CK Hu
2016-07-28 7:17 ` YT Shen
2016-07-28 7:17 ` YT Shen
2016-07-28 7:17 ` YT Shen
2016-07-28 9:41 ` CK Hu
2016-07-28 9:41 ` CK Hu
2016-07-28 9:41 ` CK Hu
2016-07-15 10:07 ` YT Shen [this message]
2016-07-15 10:07 ` [PATCH v4 5/8] drm/mediatek: add dsi interrupt control YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-19 5:39 ` CK Hu
2016-07-19 5:39 ` CK Hu
2016-07-19 5:39 ` CK Hu
2016-07-19 11:08 ` YT Shen
2016-07-19 11:08 ` YT Shen
2016-07-19 11:08 ` YT Shen
2016-07-15 10:07 ` [PATCH v4 6/8] drm/mediatek: add dsi transfer function YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-20 5:59 ` CK Hu
2016-07-20 5:59 ` CK Hu
2016-07-20 5:59 ` CK Hu
2016-07-26 10:42 ` YT Shen
2016-07-26 10:42 ` YT Shen
2016-07-26 10:42 ` YT Shen
2016-07-15 10:07 ` [PATCH v4 7/8] drm/mediatek: add mipi panel support YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-20 6:27 ` CK Hu
2016-07-20 6:27 ` CK Hu
2016-07-20 6:27 ` CK Hu
2016-07-26 10:42 ` YT Shen
2016-07-26 10:42 ` YT Shen
2016-07-26 10:42 ` YT Shen
2016-07-15 10:07 ` [PATCH v4 8/8] arm: dts: mt2701: Add display subsystem related nodes for MT2701 YT Shen
2016-07-15 10:07 ` YT Shen
2016-07-15 10:07 ` YT Shen
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