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From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com,
	bharata@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com
Subject: [Qemu-devel] [RFC v2 08/13] target-ppc: add cnttzw[.] instruction
Date: Sat, 23 Jul 2016 14:14:45 +0530	[thread overview]
Message-ID: <1469263490-19130-9-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1469263490-19130-1-git-send-email-nikunj@linux.vnet.ibm.com>

Add ISA3.0: Count trailing zeros word instruction.

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/helper.h     |  1 +
 target-ppc/int_helper.c |  5 +++++
 target-ppc/translate.c  | 11 +++++++++++
 3 files changed, 17 insertions(+)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 8a3eb5d..3b3dc36 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -38,6 +38,7 @@ DEF_HELPER_4(divweu, tl, env, tl, tl, i32)
 DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
 
 DEF_HELPER_FLAGS_1(cntlzw, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(cnttzw, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 1d02e8a..ac47230 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -160,6 +160,11 @@ target_ulong helper_cntlzw(target_ulong t)
     return clz32(t);
 }
 
+target_ulong helper_cnttzw(target_ulong t)
+{
+    return ctz32(t);
+}
+
 #if defined(TARGET_PPC64)
 uint64_t helper_modsd(uint64_t rau, uint64_t rbu)
 {
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1fc1922..c28ddff 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1520,6 +1520,16 @@ static void gen_cntlzw(DisasContext *ctx)
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
 }
+
+/* cnttzw */
+static void gen_cnttzw(DisasContext *ctx)
+{
+    gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+    if (unlikely(Rc(ctx->opcode) != 0)) {
+        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
+    }
+}
+
 /* eqv & eqv. */
 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
 /* extsb & extsb. */
@@ -9994,6 +10004,7 @@ GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
+GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-- 
2.7.4

  parent reply	other threads:[~2016-07-23  8:45 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-23  8:44 [Qemu-devel] [RFC v2 00/13] POWER9 TCG enablements - part1 Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 01/13] target-ppc: Introduce Power9 family Nikunj A Dadhania
2016-07-25  1:26   ` David Gibson
2016-07-25  8:48     ` Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 02/13] target-ppc: Introduce POWER ISA 3.0 flag Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 03/13] target-ppc: adding addpcis instruction Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 04/13] target-ppc: add cmprb instruction Nikunj A Dadhania
2016-07-23 16:06   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 05/13] target-ppc: add modulo word operations Nikunj A Dadhania
2016-07-24  1:24   ` Richard Henderson
2016-07-25  5:37     ` Nikunj A Dadhania
2016-07-25  6:07       ` [Qemu-devel] [Qemu-ppc] " Nikunj A Dadhania
2016-07-25 11:14     ` [Qemu-devel] " Nikunj A Dadhania
2016-07-25 14:34       ` Richard Henderson
2016-07-25 16:31     ` Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 06/13] target-ppc: add modulo dword operations Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 07/13] target-ppc: add cnttzd[.] instruction Nikunj A Dadhania
2016-07-24  1:26   ` Richard Henderson
2016-07-23  8:44 ` Nikunj A Dadhania [this message]
2016-07-24  1:26   ` [Qemu-devel] [RFC v2 08/13] target-ppc: add cnttzw[.] instruction Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 09/13] target-ppc: add cmpeqb instruction Nikunj A Dadhania
2016-07-24  1:31   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 10/13] target-ppc: add setb instruction Nikunj A Dadhania
2016-07-24  1:35   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 11/13] target-ppc: add maddld instruction Nikunj A Dadhania
2016-07-24  1:36   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 12/13] target-ppc: add maddhd and maddhdu instruction Nikunj A Dadhania
2016-07-24  1:36   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 13/13] target-ppc: introduce opc4 for Expanded Opcode Nikunj A Dadhania

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