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From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com,
	bharata@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com
Subject: [Qemu-devel] [RFC v2 00/13] POWER9 TCG enablements - part1
Date: Sat, 23 Jul 2016 14:14:37 +0530	[thread overview]
Message-ID: <1469263490-19130-1-git-send-email-nikunj@linux.vnet.ibm.com> (raw)

This set starts adding new instructions for POWER9 described in ISA3.0.

Patches:
  01-02: First two patches adds the required POWER9 cpu model and ISA defines.
  03-12: Adds following instructions:
             addpcis   : Add PC Immediate Shifted
             cmprb     : Compare Ranged Byte
             moduw     : Modulo Unsigned Word
             modsw     : Modulo Signed Word
             modud     : Modulo Unsigned Dword
             modsd     : Modulo Signed Dword
             cnttzd[.] : Count Trailing Zero Dword
             cnttzw[.] : Count Trailing Zero Word
             cmpeqb    : Compare Equal Byte
             setb      : Set Boolean
             maddld    : Multiply-Add Low Dword
             maddhd    : Multiply-Add High Dword
             maddhdu   : Multiply-Add High Dword Unsigned
     13: Adds support for the new Expanded Opcode (EO) added in ISA3.0

Thanks to Richard, David and Bharata for their valuable feedback.

Changelog:
v1:
* addpcis - shift the immediate before adding
* cmprb logic without branches
* mod[su][wd]: use helpers
* cmpeqb - use bit magics in the helpers
* setb - bug fix and branchless
* maddld - discard multiple dword calculation as we need only lower 64-bit
* Expanded opcode - drop pad from 32-bit and free the third level indirect 
  table in unrealize

Aneesh Kumar K.V (1):
  target-ppc: Introduce Power9 family

Nikunj A Dadhania (10):
  target-ppc: Introduce POWER ISA 3.0 flag
  target-ppc: adding addpcis instruction
  target-ppc: add cmprb instruction
  target-ppc: add modulo word operations
  target-ppc: add modulo dword operations
  target-ppc: add cnttzw[.] instruction
  target-ppc: add cmpeqb instruction
  target-ppc: add maddld instruction
  target-ppc: add maddhd and maddhdu instruction
  target-ppc: introduce opc4 for Expanded Opcode

Sandipan Das (1):
  target-ppc: add cnttzd[.] instruction

Vivek Andrew Sha (1):
  target-ppc: add setb instruction

 hw/ppc/spapr_cpu_core.c     |   5 +
 target-ppc/cpu-models.c     |   5 +
 target-ppc/cpu-models.h     |   1 +
 target-ppc/cpu-qom.h        |   7 ++
 target-ppc/cpu.h            |   5 +-
 target-ppc/helper.h         |   7 ++
 target-ppc/int_helper.c     |  63 ++++++++++
 target-ppc/mmu_helper.c     |   3 +-
 target-ppc/translate.c      | 274 ++++++++++++++++++++++++++++++++++++++++----
 target-ppc/translate_init.c | 211 ++++++++++++++++++++++++++++------
 10 files changed, 524 insertions(+), 57 deletions(-)

-- 
2.7.4

             reply	other threads:[~2016-07-23  8:45 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-23  8:44 Nikunj A Dadhania [this message]
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 01/13] target-ppc: Introduce Power9 family Nikunj A Dadhania
2016-07-25  1:26   ` David Gibson
2016-07-25  8:48     ` Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 02/13] target-ppc: Introduce POWER ISA 3.0 flag Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 03/13] target-ppc: adding addpcis instruction Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 04/13] target-ppc: add cmprb instruction Nikunj A Dadhania
2016-07-23 16:06   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 05/13] target-ppc: add modulo word operations Nikunj A Dadhania
2016-07-24  1:24   ` Richard Henderson
2016-07-25  5:37     ` Nikunj A Dadhania
2016-07-25  6:07       ` [Qemu-devel] [Qemu-ppc] " Nikunj A Dadhania
2016-07-25 11:14     ` [Qemu-devel] " Nikunj A Dadhania
2016-07-25 14:34       ` Richard Henderson
2016-07-25 16:31     ` Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 06/13] target-ppc: add modulo dword operations Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 07/13] target-ppc: add cnttzd[.] instruction Nikunj A Dadhania
2016-07-24  1:26   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 08/13] target-ppc: add cnttzw[.] instruction Nikunj A Dadhania
2016-07-24  1:26   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 09/13] target-ppc: add cmpeqb instruction Nikunj A Dadhania
2016-07-24  1:31   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 10/13] target-ppc: add setb instruction Nikunj A Dadhania
2016-07-24  1:35   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 11/13] target-ppc: add maddld instruction Nikunj A Dadhania
2016-07-24  1:36   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 12/13] target-ppc: add maddhd and maddhdu instruction Nikunj A Dadhania
2016-07-24  1:36   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 13/13] target-ppc: introduce opc4 for Expanded Opcode Nikunj A Dadhania

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