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From: Richard Henderson <rth@twiddle.net>
To: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>,
	qemu-ppc@nongnu.org, david@gibson.dropbear.id.au
Cc: qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com,
	aneesh.kumar@linux.vnet.ibm.com
Subject: Re: [Qemu-devel] [RFC v2 05/13] target-ppc: add modulo word operations
Date: Sun, 24 Jul 2016 06:54:00 +0530	[thread overview]
Message-ID: <ec117ce3-81f6-c719-73bf-f65602183c56@twiddle.net> (raw)
In-Reply-To: <1469263490-19130-6-git-send-email-nikunj@linux.vnet.ibm.com>

On 07/23/2016 02:14 PM, Nikunj A Dadhania wrote:
> Adding following instructions:
>
> moduw: Modulo Unsigned Word
> modsw: Modulo Signed Word
>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
>  target-ppc/helper.h     |  2 ++
>  target-ppc/int_helper.c | 15 +++++++++++++++
>  target-ppc/translate.c  | 19 +++++++++++++++++++
>  3 files changed, 36 insertions(+)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 1f5cfd0..76072fd 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -41,6 +41,8 @@ DEF_HELPER_FLAGS_1(cntlzw, TCG_CALL_NO_RWG_SE, tl, tl)
>  DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
>  DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
>  DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> +DEF_HELPER_FLAGS_2(modsw, TCG_CALL_NO_RWG_SE, i32, i32, i32)
> +DEF_HELPER_FLAGS_2(moduw, TCG_CALL_NO_RWG_SE, i32, i32, i32)
>  DEF_HELPER_3(sraw, tl, env, tl, tl)
>  #if defined(TARGET_PPC64)
>  DEF_HELPER_FLAGS_1(cntlzd, TCG_CALL_NO_RWG_SE, tl, tl)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index 7445376..631e0b4 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -139,6 +139,21 @@ uint64_t helper_divde(CPUPPCState *env, uint64_t rau, uint64_t rbu, uint32_t oe)
>
>  #endif
>
> +uint32_t helper_modsw(uint32_t rau, uint32_t rbu)
> +{
> +    int32_t ra = (int32_t) rau;
> +    int32_t rb = (int32_t) rbu;
> +
> +    if ((rb == 0) || (ra == INT32_MIN && rb == -1)) {
> +        return 0;
> +    }
> +    return ra % rb;
> +}
> +
> +uint32_t helper_moduw(uint32_t ra, uint32_t rb)
> +{
> +    return rb ? ra % rb : 0;
> +}

I think, like you, I got distracted by the current div implementation in ppc. 
I've just re-read the spec and seen the "undefined" language.  Which of course 
gives us much more freedom.

With this freedom, we can do the division inline, without branches.  Please see 
target-mips/translate.c, gen_r6_muldiv.

Basically, we check for the offending cases and modify the divisor prior to the 
division.  For unsigned:

	a / (b == 0 ? 1 : b)

For signed:

	a / ((a == INT_MAX & b == -1) | (b == 0) ? : b)


r~

  reply	other threads:[~2016-07-24  1:24 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-23  8:44 [Qemu-devel] [RFC v2 00/13] POWER9 TCG enablements - part1 Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 01/13] target-ppc: Introduce Power9 family Nikunj A Dadhania
2016-07-25  1:26   ` David Gibson
2016-07-25  8:48     ` Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 02/13] target-ppc: Introduce POWER ISA 3.0 flag Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 03/13] target-ppc: adding addpcis instruction Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 04/13] target-ppc: add cmprb instruction Nikunj A Dadhania
2016-07-23 16:06   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 05/13] target-ppc: add modulo word operations Nikunj A Dadhania
2016-07-24  1:24   ` Richard Henderson [this message]
2016-07-25  5:37     ` Nikunj A Dadhania
2016-07-25  6:07       ` [Qemu-devel] [Qemu-ppc] " Nikunj A Dadhania
2016-07-25 11:14     ` [Qemu-devel] " Nikunj A Dadhania
2016-07-25 14:34       ` Richard Henderson
2016-07-25 16:31     ` Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 06/13] target-ppc: add modulo dword operations Nikunj A Dadhania
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 07/13] target-ppc: add cnttzd[.] instruction Nikunj A Dadhania
2016-07-24  1:26   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 08/13] target-ppc: add cnttzw[.] instruction Nikunj A Dadhania
2016-07-24  1:26   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 09/13] target-ppc: add cmpeqb instruction Nikunj A Dadhania
2016-07-24  1:31   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 10/13] target-ppc: add setb instruction Nikunj A Dadhania
2016-07-24  1:35   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 11/13] target-ppc: add maddld instruction Nikunj A Dadhania
2016-07-24  1:36   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 12/13] target-ppc: add maddhd and maddhdu instruction Nikunj A Dadhania
2016-07-24  1:36   ` Richard Henderson
2016-07-23  8:44 ` [Qemu-devel] [RFC v2 13/13] target-ppc: introduce opc4 for Expanded Opcode Nikunj A Dadhania

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