[Qemu-devel] [PULL 0/2] target-mips queue

[Qemu-devel] [PULL 0/2] target-mips queue

[Leon Alrae]

Hi,

Just a couple of bug fixes for rc1.

Thanks,
Leon

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>

The following changes since commit 21a21b853a1bb606358af61e738abfb9aecbd720:

  Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging (2016-07-27 18:18:21 +0100)

are available in the git repository at:

  git://github.com/lalrae/qemu.git tags/mips-20160729

for you to fetch changes up to 701074a6fc7470d0ed54e4a4bcd4d491ad8da22e:

  target-mips: fix EntryHi.EHINV being cleared on TLB exception (2016-07-28 11:24:02 +0100)

----------------------------------------------------------------
MIPS patches 2016-07-29

Changes:
* bug fixes

----------------------------------------------------------------
Leon Alrae (1):
      target-mips: fix EntryHi.EHINV being cleared on TLB exception

Paul Burton (1):
      hw/mips_malta: Fix YAMON API print routine

 hw/mips/mips_malta.c | 2 +-
 target-mips/helper.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

[Qemu-devel] [PULL 1/2] hw/mips_malta: Fix YAMON API print routine

[Leon Alrae]

From: Paul Burton <paul.burton@imgtec.com>

The print routine provided as part of the in-built bootloader had a bug
in that it attempted to use a jump instruction as part of a loop, but
the target has its upper bits zeroed leading to control flow
transferring to 0xb0000814 rather than the intended 0xbfc00814. Fix this
by using a branch instruction instead, which seems more fit for purpose.

A simple way to test this is to build a Linux kernel with EVA enabled &
attempt to boot it in QEMU. It will attempt to print a message
indicating the configuration mismatch but QEMU would previously
incorrectly jump & wind up printing a continuous stream of the letter E.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 hw/mips/mips_malta.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 34d41ef..e90857e 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -727,7 +727,7 @@ static void write_bootloader(uint8_t *base, int64_t run_addr,
     stl_p(p++, 0x00000000);                                     /* nop */
     stl_p(p++, 0x0ff0021c);                                     /* jal 870 */
     stl_p(p++, 0x00000000);                                     /* nop */
-    stl_p(p++, 0x08000205);                                     /* j 814 */
+    stl_p(p++, 0x1000fff9);                                     /* b 814 */
     stl_p(p++, 0x00000000);                                     /* nop */
     stl_p(p++, 0x01a00009);                                     /* jalr t5 */
     stl_p(p++, 0x01602021);                                     /* move a0,t3 */
-- 
2.7.4

[Qemu-devel] [PULL 2/2] target-mips: fix EntryHi.EHINV being cleared on TLB exception

[Leon Alrae]

While implementing TLB invalidation feature we forgot to modify
part of code responsible for updating EntryHi during TLB exception.
Consequently EntryHi.EHINV is unexpectedly cleared on the exception.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target-mips/helper.c b/target-mips/helper.c
index 9fbca26..c864b15 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -396,6 +396,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
                        ((address >> 9) & 0x007ffff0);
     env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
+                       (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
                        (address & (TARGET_PAGE_MASK << 1));
 #if defined(TARGET_MIPS64)
     env->CP0_EntryHi &= env->SEGMask;
-- 
2.7.4

Re: [Qemu-devel] [PULL 0/2] target-mips queue

[Peter Maydell]

On 29 July 2016 at 10:11, Leon Alrae <leon.alrae@imgtec.com> wrote:
> Hi,
>
> Just a couple of bug fixes for rc1.
>
> Thanks,
> Leon
>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
>
> The following changes since commit 21a21b853a1bb606358af61e738abfb9aecbd720:
>
>   Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging (2016-07-27 18:18:21 +0100)
>
> are available in the git repository at:
>
>   git://github.com/lalrae/qemu.git tags/mips-20160729
>
> for you to fetch changes up to 701074a6fc7470d0ed54e4a4bcd4d491ad8da22e:
>
>   target-mips: fix EntryHi.EHINV being cleared on TLB exception (2016-07-28 11:24:02 +0100)
>
> ----------------------------------------------------------------
> MIPS patches 2016-07-29
>
> Changes:
> * bug fixes

Applied, thanks.

-- PMM