From: Kamal Dasu <kdasu.kdev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> To: broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, vigneshr-l0cyMroinI0@public.gmane.org, f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org Cc: bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org, vikram.prakash-dY08KVG/lbpWk0Htik3J/w@public.gmane.org, andy.fung-dY08KVG/lbpWk0Htik3J/w@public.gmane.org, jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org, jchandra-dY08KVG/lbpWk0Htik3J/w@public.gmane.org, Kamal Dasu <kdasu.kdev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Subject: [PATCH v5 5/8] Documentation: dt: spi: Add Broadcom NSP, NS2 SoC bindings Date: Fri, 29 Jul 2016 18:13:10 -0400 [thread overview] Message-ID: <1469830393-13295-6-git-send-email-kdasu.kdev@gmail.com> (raw) In-Reply-To: <1469830393-13295-1-git-send-email-kdasu.kdev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Modify device tree bindings documentation to include NS*, Cygnus and iProc SoCs supported by the new spi-bcm-qspi, spi-nsp-qspi driver. Signed-off-by: Kamal Dasu <kdasu.kdev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> --- .../devicetree/bindings/spi/brcm,spi-bcm-qspi.txt | 96 +++++++++++++++++++++- 1 file changed, 93 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt index bbae763..bc01b73 100644 --- a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt +++ b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt @@ -5,8 +5,8 @@ BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits of : MSPI : SPI master controller can read and write to a SPI slave device BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration - for flash reads and be configured to do single, double, quad lane - io with 3-byte and 4-byte addressing support. + for flash reads and be configured to do single, double, quad lane + io with 3-byte and 4-byte addressing support. Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP. MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance @@ -26,6 +26,8 @@ Required properties: "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI BRCMSTB SoCs + "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : Uses MSPI+BSPI on Cygnus, NSP, + NS2 SoCs - reg: Define the bases and ranges of the associated I/O address spaces. @@ -35,8 +37,10 @@ Required properties: First name does not matter, but must be reserved for the MSPI controller register range as mentioned in 'reg' above, and will typically contain - "bspi_regs": BSPI register range, not required with compatible - "spi-brcmstb-mspi" + "spi-brcmstb-mspi" - "mspi_regs": MSPI register range is required for compatible strings + - "intr_regs", "intr_status_reg" : Interrupt and status register for + NSP, NS2, Cygnus SoC - interrupts The interrupts used by the MSPI and/or BSPI controller. @@ -143,3 +147,89 @@ BRCMSTB SoC Example: interrupt-names = "mspi_done"; }; +iProc SoC Example: + + qspi: spi@18027200 { + compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; + reg = <0x18027200 0x184>, + <0x18027000 0x124>, + <0x1811c408 0x004>, + <0x180273a0 0x01c>; + reg-names = "mspi_regs", "bspi_regs", "intr_regs", "intr_status_reg"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "mspi_done", + "mspi_halted"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + clock-frequency = <12500000>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + + NS2 SoC Example: + + qspi: spi@66470200 { + compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; + reg = <0x66470200 0x184>, + <0x66470000 0x124>, + <0x67017408 0x004>, + <0x664703a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", + "intr_status_reg"; + interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "spi_l1_intr"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + clock-frequency = <12500000>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + + m25p80 node for NSP, NS2 + + &qspi { + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@1 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@2 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@3 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
WARNING: multiple messages have this Message-ID (diff)
From: Kamal Dasu <kdasu.kdev@gmail.com> To: broonie@kernel.org, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, vigneshr@ti.com, f.fainelli@gmail.com Cc: bcm-kernel-feedback-list@broadcom.com, vikram.prakash@broadcom.com, andy.fung@broadcom.com, jon.mason@broadcom.com, jchandra@broadcom.com, Kamal Dasu <kdasu.kdev@gmail.com> Subject: [PATCH v5 5/8] Documentation: dt: spi: Add Broadcom NSP, NS2 SoC bindings Date: Fri, 29 Jul 2016 18:13:10 -0400 [thread overview] Message-ID: <1469830393-13295-6-git-send-email-kdasu.kdev@gmail.com> (raw) In-Reply-To: <1469830393-13295-1-git-send-email-kdasu.kdev@gmail.com> Modify device tree bindings documentation to include NS*, Cygnus and iProc SoCs supported by the new spi-bcm-qspi, spi-nsp-qspi driver. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> --- .../devicetree/bindings/spi/brcm,spi-bcm-qspi.txt | 96 +++++++++++++++++++++- 1 file changed, 93 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt index bbae763..bc01b73 100644 --- a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt +++ b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt @@ -5,8 +5,8 @@ BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits of : MSPI : SPI master controller can read and write to a SPI slave device BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration - for flash reads and be configured to do single, double, quad lane - io with 3-byte and 4-byte addressing support. + for flash reads and be configured to do single, double, quad lane + io with 3-byte and 4-byte addressing support. Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP. MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance @@ -26,6 +26,8 @@ Required properties: "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI BRCMSTB SoCs + "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : Uses MSPI+BSPI on Cygnus, NSP, + NS2 SoCs - reg: Define the bases and ranges of the associated I/O address spaces. @@ -35,8 +37,10 @@ Required properties: First name does not matter, but must be reserved for the MSPI controller register range as mentioned in 'reg' above, and will typically contain - "bspi_regs": BSPI register range, not required with compatible - "spi-brcmstb-mspi" + "spi-brcmstb-mspi" - "mspi_regs": MSPI register range is required for compatible strings + - "intr_regs", "intr_status_reg" : Interrupt and status register for + NSP, NS2, Cygnus SoC - interrupts The interrupts used by the MSPI and/or BSPI controller. @@ -143,3 +147,89 @@ BRCMSTB SoC Example: interrupt-names = "mspi_done"; }; +iProc SoC Example: + + qspi: spi@18027200 { + compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; + reg = <0x18027200 0x184>, + <0x18027000 0x124>, + <0x1811c408 0x004>, + <0x180273a0 0x01c>; + reg-names = "mspi_regs", "bspi_regs", "intr_regs", "intr_status_reg"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "mspi_done", + "mspi_halted"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + clock-frequency = <12500000>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + + NS2 SoC Example: + + qspi: spi@66470200 { + compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; + reg = <0x66470200 0x184>, + <0x66470000 0x124>, + <0x67017408 0x004>, + <0x664703a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", + "intr_status_reg"; + interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "spi_l1_intr"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + clock-frequency = <12500000>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + + m25p80 node for NSP, NS2 + + &qspi { + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@1 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@2 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@3 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; -- 1.9.1
next prev parent reply other threads:[~2016-07-29 22:13 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-07-29 22:13 [PATCH v5 0/8] Broadcom stb, nsp, ns2, cygnus QSPI driver Kamal Dasu 2016-07-29 22:13 ` Kamal Dasu [not found] ` <1469830393-13295-1-git-send-email-kdasu.kdev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2016-07-29 22:13 ` [PATCH v5 1/8] Documentation: dt: spi: Add BRCMSTB SoC bindings Kamal Dasu 2016-07-29 22:13 ` Kamal Dasu [not found] ` <1469830393-13295-2-git-send-email-kdasu.kdev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2016-08-04 21:06 ` Mark Brown 2016-08-04 21:06 ` Mark Brown [not found] ` <20160804210634.GM10383-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> 2016-08-04 22:20 ` Florian Fainelli 2016-08-04 22:20 ` Florian Fainelli [not found] ` <1fddf72d-cbc1-225f-b482-d6ba99dab823-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2016-08-05 11:03 ` Mark Brown 2016-08-05 11:03 ` Mark Brown 2016-08-16 18:19 ` Mark Brown 2016-08-16 18:19 ` Mark Brown [not found] ` <20160816181944.GY9347-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> 2016-08-19 15:07 ` Kamal Dasu 2016-08-19 15:07 ` Kamal Dasu 2016-07-29 22:13 ` [PATCH v5 2/8] spi: bcm-qspi: Add Broadcom MSPI driver Kamal Dasu 2016-07-29 22:13 ` Kamal Dasu [not found] ` <1469830393-13295-3-git-send-email-kdasu.kdev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2016-08-16 18:15 ` Mark Brown 2016-08-16 18:15 ` Mark Brown [not found] ` <20160816181536.GX9347-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> 2016-08-19 15:20 ` Kamal Dasu 2016-08-19 15:20 ` Kamal Dasu 2016-07-29 22:13 ` [PATCH v5 3/8] spi: bcm-qspi: Add BSPI spi-nor flash controller driver Kamal Dasu 2016-07-29 22:13 ` Kamal Dasu [not found] ` <1469830393-13295-4-git-send-email-kdasu.kdev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2016-08-16 18:31 ` Mark Brown 2016-08-16 18:31 ` Mark Brown [not found] ` <20160816183148.GZ9347-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> 2016-08-19 15:33 ` Kamal Dasu 2016-08-19 15:33 ` Kamal Dasu 2016-07-29 22:13 ` [PATCH v5 4/8] mtd: m25p80: Let m25p80_read() fallback to spi transfer Kamal Dasu 2016-07-29 22:13 ` Kamal Dasu [not found] ` <1469830393-13295-5-git-send-email-kdasu.kdev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2016-08-04 21:07 ` Mark Brown 2016-08-04 21:07 ` Mark Brown [not found] ` <20160804210747.GN10383-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> 2016-08-19 14:59 ` Kamal Dasu 2016-08-19 14:59 ` Kamal Dasu 2016-07-29 22:13 ` Kamal Dasu [this message] 2016-07-29 22:13 ` [PATCH v5 5/8] Documentation: dt: spi: Add Broadcom NSP, NS2 SoC bindings Kamal Dasu [not found] ` <1469830393-13295-6-git-send-email-kdasu.kdev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2016-08-16 18:32 ` Mark Brown 2016-08-16 18:32 ` Mark Brown 2016-07-29 22:13 ` [PATCH v5 6/8] arm: dts: Add bcm-nsp and bcm958625k support Kamal Dasu 2016-07-29 22:13 ` Kamal Dasu 2016-08-01 15:09 ` Jonas Gorski 2016-08-01 15:09 ` Jonas Gorski [not found] ` <CAOiHx=n8a64d-2LGGFHuyBQBg3Cz=ALVXEbvPRHxTyzFjWRMXA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2016-08-02 19:51 ` Kamal Dasu 2016-08-02 19:51 ` Kamal Dasu 2016-07-29 22:13 ` [PATCH v5 7/8] arm64: dts: Add ns2 SoC support Kamal Dasu 2016-07-29 22:13 ` Kamal Dasu 2016-07-29 22:13 ` [PATCH v5 8/8] spi: nsp-qspi: Add Broadcom NSP, NS2, Cygnus " Kamal Dasu 2016-07-29 22:13 ` Kamal Dasu [not found] ` <1469830393-13295-9-git-send-email-kdasu.kdev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2016-08-16 18:40 ` Mark Brown 2016-08-16 18:40 ` Mark Brown [not found] ` <20160816184030.GB9347-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> 2016-08-19 15:43 ` Kamal Dasu 2016-08-19 15:43 ` Kamal Dasu [not found] ` <CAC=U0a31LOphD=21-tBtiCxN-JqxSArxqhQ4_=fXwH-vEKnbHA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2016-08-19 16:42 ` Mark Brown 2016-08-19 16:42 ` Mark Brown
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1469830393-13295-6-git-send-email-kdasu.kdev@gmail.com \ --to=kdasu.kdev-re5jqeeqqe8avxtiumwx3w@public.gmane.org \ --cc=andy.fung-dY08KVG/lbpWk0Htik3J/w@public.gmane.org \ --cc=bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org \ --cc=broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org \ --cc=f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org \ --cc=jchandra-dY08KVG/lbpWk0Htik3J/w@public.gmane.org \ --cc=jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org \ --cc=linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org \ --cc=linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \ --cc=vigneshr-l0cyMroinI0@public.gmane.org \ --cc=vikram.prakash-dY08KVG/lbpWk0Htik3J/w@public.gmane.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.