* [PATCH 0/2] Shrink and lock the size static gen6 semaphore init array
@ 2016-08-11 10:43 Tvrtko Ursulin
2016-08-11 10:43 ` [PATCH 1/2] drm/i915: Add enum for hardware engine identifiers Tvrtko Ursulin
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Tvrtko Ursulin @ 2016-08-11 10:43 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Previous attempts to get rid of the static init table using the function
were not too popular so this time round I am trying to do it by chaging the
namespace of the engine identifiers used for indexing.
Going from driver internal engine id to hardware engine id allows us to
keep the table checked in size by limiting to the number of Gen6 engines.
I am not fully happy with the naming of new enums in intel_engine_hw_id so
feel free to suggest something nicer.
Tvrtko Ursulin (2):
drm/i915: Add enum for hardware engine identifiers
drm/i915: Initialize legacy semaphores from engine hw id indexed array
drivers/gpu/drm/i915/intel_engine_cs.c | 14 ++++-----
drivers/gpu/drm/i915/intel_ringbuffer.c | 55 +++++++++++++++++----------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 15 ++++++---
3 files changed, 47 insertions(+), 37 deletions(-)
--
1.9.1
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^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 1/2] drm/i915: Add enum for hardware engine identifiers 2016-08-11 10:43 [PATCH 0/2] Shrink and lock the size static gen6 semaphore init array Tvrtko Ursulin @ 2016-08-11 10:43 ` Tvrtko Ursulin 2016-08-11 10:43 ` [PATCH 2/2] drm/i915: Initialize legacy semaphores from engine hw id indexed array Tvrtko Ursulin ` (2 subsequent siblings) 3 siblings, 0 replies; 12+ messages in thread From: Tvrtko Ursulin @ 2016-08-11 10:43 UTC (permalink / raw) To: Intel-gfx From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Put the engine hardware id in the common header so they are not only associated with the GuC since they are needed for the legacy semaphores implementation. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/intel_engine_cs.c | 14 +++++++------- drivers/gpu/drm/i915/intel_ringbuffer.h | 10 ++++++++-- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 186c12d07f99..ab942de88d9a 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -29,7 +29,7 @@ static const struct engine_info { const char *name; unsigned exec_id; - unsigned guc_id; + enum intel_engine_hw_id hw_id; u32 mmio_base; unsigned irq_shift; int (*init_legacy)(struct intel_engine_cs *engine); @@ -38,7 +38,7 @@ static const struct engine_info { [RCS] = { .name = "render ring", .exec_id = I915_EXEC_RENDER, - .guc_id = GUC_RENDER_ENGINE, + .hw_id = RCS_HW, .mmio_base = RENDER_RING_BASE, .irq_shift = GEN8_RCS_IRQ_SHIFT, .init_execlists = logical_render_ring_init, @@ -47,7 +47,7 @@ static const struct engine_info { [BCS] = { .name = "blitter ring", .exec_id = I915_EXEC_BLT, - .guc_id = GUC_BLITTER_ENGINE, + .hw_id = BCS_HW, .mmio_base = BLT_RING_BASE, .irq_shift = GEN8_BCS_IRQ_SHIFT, .init_execlists = logical_xcs_ring_init, @@ -56,7 +56,7 @@ static const struct engine_info { [VCS] = { .name = "bsd ring", .exec_id = I915_EXEC_BSD, - .guc_id = GUC_VIDEO_ENGINE, + .hw_id = VCS_HW, .mmio_base = GEN6_BSD_RING_BASE, .irq_shift = GEN8_VCS1_IRQ_SHIFT, .init_execlists = logical_xcs_ring_init, @@ -65,7 +65,7 @@ static const struct engine_info { [VCS2] = { .name = "bsd2 ring", .exec_id = I915_EXEC_BSD, - .guc_id = GUC_VIDEO_ENGINE2, + .hw_id = VCS2_HW, .mmio_base = GEN8_BSD2_RING_BASE, .irq_shift = GEN8_VCS2_IRQ_SHIFT, .init_execlists = logical_xcs_ring_init, @@ -74,7 +74,7 @@ static const struct engine_info { [VECS] = { .name = "video enhancement ring", .exec_id = I915_EXEC_VEBOX, - .guc_id = GUC_VIDEOENHANCE_ENGINE, + .hw_id = VECS_HW, .mmio_base = VEBOX_RING_BASE, .irq_shift = GEN8_VECS_IRQ_SHIFT, .init_execlists = logical_xcs_ring_init, @@ -93,7 +93,7 @@ intel_engine_setup(struct drm_i915_private *dev_priv, engine->i915 = dev_priv; engine->name = info->name; engine->exec_id = info->exec_id; - engine->hw_id = engine->guc_id = info->guc_id; + engine->hw_id = engine->guc_id = info->hw_id; engine->mmio_base = info->mmio_base; engine->irq_shift = info->irq_shift; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index ea2735144b2a..ac568808aeb1 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -146,8 +146,14 @@ struct intel_engine_cs { #define I915_NUM_ENGINES 5 #define _VCS(n) (VCS + (n)) unsigned int exec_id; - unsigned int hw_id; - unsigned int guc_id; /* XXX same as hw_id? */ + enum intel_engine_hw_id { + RCS_HW = 0, + VCS_HW, + BCS_HW, + VECS_HW, + VCS2_HW + } hw_id; + enum intel_engine_hw_id guc_id; /* XXX same as hw_id? */ u64 fence_context; u32 mmio_base; unsigned int irq_shift; -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] drm/i915: Initialize legacy semaphores from engine hw id indexed array 2016-08-11 10:43 [PATCH 0/2] Shrink and lock the size static gen6 semaphore init array Tvrtko Ursulin 2016-08-11 10:43 ` [PATCH 1/2] drm/i915: Add enum for hardware engine identifiers Tvrtko Ursulin @ 2016-08-11 10:43 ` Tvrtko Ursulin 2016-08-11 10:53 ` Chris Wilson 2016-08-11 11:58 ` ✗ Ro.CI.BAT: failure for Shrink and lock the size static gen6 semaphore init array (rev2) Patchwork 2016-08-11 15:31 ` ✗ Ro.CI.BAT: failure for Shrink and lock the size static gen6 semaphore init array (rev3) Patchwork 3 siblings, 1 reply; 12+ messages in thread From: Tvrtko Ursulin @ 2016-08-11 10:43 UTC (permalink / raw) To: Intel-gfx From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Build the legacy semaphore initialisation array using the engine hardware ids instead of driver internal ones. This makes the static array size dependent only on the number of gen6 semaphore engines. Also makes the per-engine semaphore wait and signal tables hardware id indexed saving some more space. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 55 +++++++++++++++++---------------- drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +-- 2 files changed, 32 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index ed19868df9c6..a70157a65cfd 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1385,8 +1385,7 @@ static int gen6_signal(struct drm_i915_gem_request *req) { struct intel_ring *ring = req->ring; struct drm_i915_private *dev_priv = req->i915; - struct intel_engine_cs *useless; - enum intel_engine_id id; + struct intel_engine_cs *engine; int ret, num_rings; num_rings = INTEL_INFO(dev_priv)->num_rings; @@ -1394,9 +1393,13 @@ static int gen6_signal(struct drm_i915_gem_request *req) if (ret) return ret; - for_each_engine_id(useless, dev_priv, id) { - i915_reg_t mbox_reg = req->engine->semaphore.mbox.signal[id]; + for_each_engine(engine, dev_priv) { + i915_reg_t mbox_reg; + + if (engine->hw_id >= I915_GEN6_SEMA_ENGINES) + continue; + mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id]; if (i915_mmio_reg_valid(mbox_reg)) { intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); intel_ring_emit_reg(ring, mbox_reg); @@ -1543,7 +1546,7 @@ gen6_ring_sync_to(struct drm_i915_gem_request *req, u32 dw1 = MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER; - u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->id]; + u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id]; int ret; WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); @@ -2671,41 +2674,41 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, * initialized as INVALID. Gen8 will initialize the * sema between VCS2 and RCS later. */ - for (i = 0; i < I915_NUM_ENGINES; i++) { + for (i = 0; i < I915_GEN6_SEMA_ENGINES; i++) { static const struct { u32 wait_mbox; i915_reg_t mbox_reg; - } sem_data[I915_NUM_ENGINES][I915_NUM_ENGINES] = { - [RCS] = { - [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, - [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, - [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, + } sem_data[I915_GEN6_SEMA_ENGINES][I915_GEN6_SEMA_ENGINES] = { + [RCS_HW] = { + [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, + [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, + [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, }, - [VCS] = { - [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, - [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, - [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, + [VCS_HW] = { + [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, + [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, + [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, }, - [BCS] = { - [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, - [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, - [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, + [BCS_HW] = { + [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, + [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, + [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, }, - [VECS] = { - [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, - [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, - [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, + [VECS_HW] = { + [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, + [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, + [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, }, }; u32 wait_mbox; i915_reg_t mbox_reg; - if (i == engine->id || i == VCS2) { + if (i == engine->hw_id) { wait_mbox = MI_SEMAPHORE_SYNC_INVALID; mbox_reg = GEN6_NOSYNC; } else { - wait_mbox = sem_data[engine->id][i].wait_mbox; - mbox_reg = sem_data[engine->id][i].mbox_reg; + wait_mbox = sem_data[engine->hw_id][i].wait_mbox; + mbox_reg = sem_data[engine->hw_id][i].mbox_reg; } engine->semaphore.mbox.wait[i] = wait_mbox; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index ac568808aeb1..d65df94cc95e 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -277,11 +277,12 @@ struct intel_engine_cs { u32 sync_seqno[I915_NUM_ENGINES-1]; union { +#define I915_GEN6_SEMA_ENGINES 4 struct { /* our mbox written by others */ - u32 wait[I915_NUM_ENGINES]; + u32 wait[I915_GEN6_SEMA_ENGINES]; /* mboxes this ring signals to */ - i915_reg_t signal[I915_NUM_ENGINES]; + i915_reg_t signal[I915_GEN6_SEMA_ENGINES]; } mbox; u64 signal_ggtt[I915_NUM_ENGINES]; }; -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915: Initialize legacy semaphores from engine hw id indexed array 2016-08-11 10:43 ` [PATCH 2/2] drm/i915: Initialize legacy semaphores from engine hw id indexed array Tvrtko Ursulin @ 2016-08-11 10:53 ` Chris Wilson 2016-08-11 11:05 ` [PATCH v2] " Tvrtko Ursulin 2016-08-11 11:06 ` [PATCH 2/2] " Tvrtko Ursulin 0 siblings, 2 replies; 12+ messages in thread From: Chris Wilson @ 2016-08-11 10:53 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: Intel-gfx On Thu, Aug 11, 2016 at 11:43:38AM +0100, Tvrtko Ursulin wrote: > +#define I915_GEN6_SEMA_ENGINES 4 #define GEN6_SEMAPHORE_LAST VECS_HW In theory, I915 and GEN6 are part of the same prefix class. With that change and follow through for the inclusive test, Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2] drm/i915: Initialize legacy semaphores from engine hw id indexed array 2016-08-11 10:53 ` Chris Wilson @ 2016-08-11 11:05 ` Tvrtko Ursulin 2016-08-11 11:20 ` Chris Wilson 2016-08-11 11:06 ` [PATCH 2/2] " Tvrtko Ursulin 1 sibling, 1 reply; 12+ messages in thread From: Tvrtko Ursulin @ 2016-08-11 11:05 UTC (permalink / raw) To: Intel-gfx From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Build the legacy semaphore initialisation array using the engine hardware ids instead of driver internal ones. This makes the static array size dependent only on the number of gen6 semaphore engines. Also makes the per-engine semaphore wait and signal tables hardware id indexed saving some more space. v2: Refactor I915_GEN6_NUM_ENGINES to GEN6_SEMAPHORE_LAST. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 55 +++++++++++++++++---------------- drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +-- 2 files changed, 32 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index ed19868df9c6..d38e7b94f728 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1385,8 +1385,7 @@ static int gen6_signal(struct drm_i915_gem_request *req) { struct intel_ring *ring = req->ring; struct drm_i915_private *dev_priv = req->i915; - struct intel_engine_cs *useless; - enum intel_engine_id id; + struct intel_engine_cs *engine; int ret, num_rings; num_rings = INTEL_INFO(dev_priv)->num_rings; @@ -1394,9 +1393,13 @@ static int gen6_signal(struct drm_i915_gem_request *req) if (ret) return ret; - for_each_engine_id(useless, dev_priv, id) { - i915_reg_t mbox_reg = req->engine->semaphore.mbox.signal[id]; + for_each_engine(engine, dev_priv) { + i915_reg_t mbox_reg; + + if (engine->hw_id > GEN6_SEMAPHORE_LAST) + continue; + mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id]; if (i915_mmio_reg_valid(mbox_reg)) { intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); intel_ring_emit_reg(ring, mbox_reg); @@ -1543,7 +1546,7 @@ gen6_ring_sync_to(struct drm_i915_gem_request *req, u32 dw1 = MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER; - u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->id]; + u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id]; int ret; WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); @@ -2671,41 +2674,41 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, * initialized as INVALID. Gen8 will initialize the * sema between VCS2 and RCS later. */ - for (i = 0; i < I915_NUM_ENGINES; i++) { + for (i = 0; i <= GEN6_SEMAPHORE_LAST; i++) { static const struct { u32 wait_mbox; i915_reg_t mbox_reg; - } sem_data[I915_NUM_ENGINES][I915_NUM_ENGINES] = { - [RCS] = { - [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, - [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, - [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, + } sem_data[GEN6_SEMAPHORE_LAST + 1][GEN6_SEMAPHORE_LAST + 1] = { + [RCS_HW] = { + [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, + [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, + [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, }, - [VCS] = { - [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, - [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, - [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, + [VCS_HW] = { + [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, + [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, + [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, }, - [BCS] = { - [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, - [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, - [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, + [BCS_HW] = { + [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, + [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, + [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, }, - [VECS] = { - [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, - [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, - [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, + [VECS_HW] = { + [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, + [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, + [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, }, }; u32 wait_mbox; i915_reg_t mbox_reg; - if (i == engine->id || i == VCS2) { + if (i == engine->hw_id) { wait_mbox = MI_SEMAPHORE_SYNC_INVALID; mbox_reg = GEN6_NOSYNC; } else { - wait_mbox = sem_data[engine->id][i].wait_mbox; - mbox_reg = sem_data[engine->id][i].mbox_reg; + wait_mbox = sem_data[engine->hw_id][i].wait_mbox; + mbox_reg = sem_data[engine->hw_id][i].mbox_reg; } engine->semaphore.mbox.wait[i] = wait_mbox; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index ac568808aeb1..c2d8677b5b9f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -277,11 +277,12 @@ struct intel_engine_cs { u32 sync_seqno[I915_NUM_ENGINES-1]; union { +#define GEN6_SEMAPHORE_LAST VECS_HW struct { /* our mbox written by others */ - u32 wait[I915_NUM_ENGINES]; + u32 wait[GEN6_SEMAPHORE_LAST + 1]; /* mboxes this ring signals to */ - i915_reg_t signal[I915_NUM_ENGINES]; + i915_reg_t signal[GEN6_SEMAPHORE_LAST + 1]; } mbox; u64 signal_ggtt[I915_NUM_ENGINES]; }; -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2] drm/i915: Initialize legacy semaphores from engine hw id indexed array 2016-08-11 11:05 ` [PATCH v2] " Tvrtko Ursulin @ 2016-08-11 11:20 ` Chris Wilson 2016-08-11 14:45 ` Tvrtko Ursulin 2016-08-11 14:50 ` [PATCH v3] " Tvrtko Ursulin 0 siblings, 2 replies; 12+ messages in thread From: Chris Wilson @ 2016-08-11 11:20 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: Intel-gfx On Thu, Aug 11, 2016 at 12:05:58PM +0100, Tvrtko Ursulin wrote: > @@ -1394,9 +1393,13 @@ static int gen6_signal(struct drm_i915_gem_request *req) > if (ret) > return ret; > > - for_each_engine_id(useless, dev_priv, id) { > - i915_reg_t mbox_reg = req->engine->semaphore.mbox.signal[id]; > + for_each_engine(engine, dev_priv) { > + i915_reg_t mbox_reg; > + > + if (engine->hw_id > GEN6_SEMAPHORE_LAST) > + continue; Yeah, this makes more sense to me... > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h > index ac568808aeb1..c2d8677b5b9f 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -277,11 +277,12 @@ struct intel_engine_cs { > u32 sync_seqno[I915_NUM_ENGINES-1]; > > union { > +#define GEN6_SEMAPHORE_LAST VECS_HW > struct { > /* our mbox written by others */ > - u32 wait[I915_NUM_ENGINES]; > + u32 wait[GEN6_SEMAPHORE_LAST + 1]; but I agree with your hesistation here. #define GEN6_SEMAPHORE_LAST VECS_HW #define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST_HW + 1) #define GEN6_MASK_SEMAPHORES GENMASK(GEN6_SEMAPHORE_LAST, 0) if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK)) continue; (can't decide on NUM/MASK_SEM or SEM_COUNT/MASK) would that look better? -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2] drm/i915: Initialize legacy semaphores from engine hw id indexed array 2016-08-11 11:20 ` Chris Wilson @ 2016-08-11 14:45 ` Tvrtko Ursulin 2016-08-11 14:50 ` [PATCH v3] " Tvrtko Ursulin 1 sibling, 0 replies; 12+ messages in thread From: Tvrtko Ursulin @ 2016-08-11 14:45 UTC (permalink / raw) To: Chris Wilson, Intel-gfx On 11/08/16 12:20, Chris Wilson wrote: > On Thu, Aug 11, 2016 at 12:05:58PM +0100, Tvrtko Ursulin wrote: >> @@ -1394,9 +1393,13 @@ static int gen6_signal(struct drm_i915_gem_request *req) >> if (ret) >> return ret; >> >> - for_each_engine_id(useless, dev_priv, id) { >> - i915_reg_t mbox_reg = req->engine->semaphore.mbox.signal[id]; >> + for_each_engine(engine, dev_priv) { >> + i915_reg_t mbox_reg; >> + >> + if (engine->hw_id > GEN6_SEMAPHORE_LAST) >> + continue; > > Yeah, this makes more sense to me... > >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h >> index ac568808aeb1..c2d8677b5b9f 100644 >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h >> @@ -277,11 +277,12 @@ struct intel_engine_cs { >> u32 sync_seqno[I915_NUM_ENGINES-1]; >> >> union { >> +#define GEN6_SEMAPHORE_LAST VECS_HW >> struct { >> /* our mbox written by others */ >> - u32 wait[I915_NUM_ENGINES]; >> + u32 wait[GEN6_SEMAPHORE_LAST + 1]; > > but I agree with your hesistation here. > > #define GEN6_SEMAPHORE_LAST VECS_HW > #define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST_HW + 1) > #define GEN6_MASK_SEMAPHORES GENMASK(GEN6_SEMAPHORE_LAST, 0) > > if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK)) > continue; > > (can't decide on NUM/MASK_SEM or SEM_COUNT/MASK) > > would that look better? Yeah it is better, will do that with NUM/MASK. Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3] drm/i915: Initialize legacy semaphores from engine hw id indexed array 2016-08-11 11:20 ` Chris Wilson 2016-08-11 14:45 ` Tvrtko Ursulin @ 2016-08-11 14:50 ` Tvrtko Ursulin 2016-08-11 15:46 ` Chris Wilson 1 sibling, 1 reply; 12+ messages in thread From: Tvrtko Ursulin @ 2016-08-11 14:50 UTC (permalink / raw) To: Intel-gfx From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Build the legacy semaphore initialisation array using the engine hardware ids instead of driver internal ones. This makes the static array size dependent only on the number of gen6 semaphore engines. Also makes the per-engine semaphore wait and signal tables hardware id indexed saving some more space. v2: Refactor I915_GEN6_NUM_ENGINES to GEN6_SEMAPHORE_LAST. (Chris Wilson) v3: More polish. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 55 +++++++++++++++++---------------- drivers/gpu/drm/i915/intel_ringbuffer.h | 7 +++-- 2 files changed, 34 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index ed19868df9c6..7dd19771dd52 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1385,8 +1385,7 @@ static int gen6_signal(struct drm_i915_gem_request *req) { struct intel_ring *ring = req->ring; struct drm_i915_private *dev_priv = req->i915; - struct intel_engine_cs *useless; - enum intel_engine_id id; + struct intel_engine_cs *engine; int ret, num_rings; num_rings = INTEL_INFO(dev_priv)->num_rings; @@ -1394,9 +1393,13 @@ static int gen6_signal(struct drm_i915_gem_request *req) if (ret) return ret; - for_each_engine_id(useless, dev_priv, id) { - i915_reg_t mbox_reg = req->engine->semaphore.mbox.signal[id]; + for_each_engine(engine, dev_priv) { + i915_reg_t mbox_reg; + + if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK)) + continue; + mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id]; if (i915_mmio_reg_valid(mbox_reg)) { intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); intel_ring_emit_reg(ring, mbox_reg); @@ -1543,7 +1546,7 @@ gen6_ring_sync_to(struct drm_i915_gem_request *req, u32 dw1 = MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER; - u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->id]; + u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id]; int ret; WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); @@ -2671,41 +2674,41 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, * initialized as INVALID. Gen8 will initialize the * sema between VCS2 and RCS later. */ - for (i = 0; i < I915_NUM_ENGINES; i++) { + for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) { static const struct { u32 wait_mbox; i915_reg_t mbox_reg; - } sem_data[I915_NUM_ENGINES][I915_NUM_ENGINES] = { - [RCS] = { - [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, - [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, - [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, + } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = { + [RCS_HW] = { + [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, + [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, + [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, }, - [VCS] = { - [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, - [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, - [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, + [VCS_HW] = { + [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, + [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, + [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, }, - [BCS] = { - [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, - [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, - [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, + [BCS_HW] = { + [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, + [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, + [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, }, - [VECS] = { - [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, - [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, - [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, + [VECS_HW] = { + [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, + [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, + [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, }, }; u32 wait_mbox; i915_reg_t mbox_reg; - if (i == engine->id || i == VCS2) { + if (i == engine->hw_id) { wait_mbox = MI_SEMAPHORE_SYNC_INVALID; mbox_reg = GEN6_NOSYNC; } else { - wait_mbox = sem_data[engine->id][i].wait_mbox; - mbox_reg = sem_data[engine->id][i].mbox_reg; + wait_mbox = sem_data[engine->hw_id][i].wait_mbox; + mbox_reg = sem_data[engine->hw_id][i].mbox_reg; } engine->semaphore.mbox.wait[i] = wait_mbox; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index ac568808aeb1..03bea5baa46a 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -277,11 +277,14 @@ struct intel_engine_cs { u32 sync_seqno[I915_NUM_ENGINES-1]; union { +#define GEN6_SEMAPHORE_LAST VECS_HW +#define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1) +#define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0) struct { /* our mbox written by others */ - u32 wait[I915_NUM_ENGINES]; + u32 wait[GEN6_NUM_SEMAPHORES]; /* mboxes this ring signals to */ - i915_reg_t signal[I915_NUM_ENGINES]; + i915_reg_t signal[GEN6_NUM_SEMAPHORES]; } mbox; u64 signal_ggtt[I915_NUM_ENGINES]; }; -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3] drm/i915: Initialize legacy semaphores from engine hw id indexed array 2016-08-11 14:50 ` [PATCH v3] " Tvrtko Ursulin @ 2016-08-11 15:46 ` Chris Wilson 0 siblings, 0 replies; 12+ messages in thread From: Chris Wilson @ 2016-08-11 15:46 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: Intel-gfx On Thu, Aug 11, 2016 at 03:50:17PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Build the legacy semaphore initialisation array using the engine > hardware ids instead of driver internal ones. This makes the > static array size dependent only on the number of gen6 semaphore > engines. > > Also makes the per-engine semaphore wait and signal tables > hardware id indexed saving some more space. > > v2: Refactor I915_GEN6_NUM_ENGINES to GEN6_SEMAPHORE_LAST. (Chris Wilson) > v3: More polish. (Chris Wilson) > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (and for patch 1/2) -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915: Initialize legacy semaphores from engine hw id indexed array 2016-08-11 10:53 ` Chris Wilson 2016-08-11 11:05 ` [PATCH v2] " Tvrtko Ursulin @ 2016-08-11 11:06 ` Tvrtko Ursulin 1 sibling, 0 replies; 12+ messages in thread From: Tvrtko Ursulin @ 2016-08-11 11:06 UTC (permalink / raw) To: Chris Wilson, Intel-gfx On 11/08/16 11:53, Chris Wilson wrote: > On Thu, Aug 11, 2016 at 11:43:38AM +0100, Tvrtko Ursulin wrote: >> +#define I915_GEN6_SEMA_ENGINES 4 > > #define GEN6_SEMAPHORE_LAST VECS_HW > > In theory, I915 and GEN6 are part of the same prefix class. > > With that change and follow through for the inclusive test, > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Sent v2. Please can you check that it looks like you wanted there, since I did not carry this rb just in case? Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Ro.CI.BAT: failure for Shrink and lock the size static gen6 semaphore init array (rev2) 2016-08-11 10:43 [PATCH 0/2] Shrink and lock the size static gen6 semaphore init array Tvrtko Ursulin 2016-08-11 10:43 ` [PATCH 1/2] drm/i915: Add enum for hardware engine identifiers Tvrtko Ursulin 2016-08-11 10:43 ` [PATCH 2/2] drm/i915: Initialize legacy semaphores from engine hw id indexed array Tvrtko Ursulin @ 2016-08-11 11:58 ` Patchwork 2016-08-11 15:31 ` ✗ Ro.CI.BAT: failure for Shrink and lock the size static gen6 semaphore init array (rev3) Patchwork 3 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2016-08-11 11:58 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx == Series Details == Series: Shrink and lock the size static gen6 semaphore init array (rev2) URL : https://patchwork.freedesktop.org/series/10949/ State : failure == Summary == Series 10949v2 Shrink and lock the size static gen6 semaphore init array http://patchwork.freedesktop.org/api/1.0/series/10949/revisions/2/mbox Test gem_exec_suspend: Subgroup basic-s3: incomplete -> DMESG-WARN (fi-skl-i7-6700k) Test kms_cursor_legacy: Subgroup basic-flip-vs-cursor-legacy: fail -> PASS (ro-hsw-i7-4770r) fail -> PASS (ro-byt-n2820) pass -> FAIL (ro-bdw-i5-5250u) Subgroup basic-flip-vs-cursor-varying-size: pass -> FAIL (ro-hsw-i7-4770r) pass -> FAIL (ro-byt-n2820) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: dmesg-warn -> SKIP (ro-bdw-i5-5250u) Subgroup suspend-read-crc-pipe-b: pass -> DMESG-WARN (ro-bdw-i7-5600u) fi-hsw-i7-4770k total:244 pass:221 dwarn:0 dfail:0 fail:1 skip:22 fi-kbl-qkkr total:244 pass:186 dwarn:28 dfail:0 fail:3 skip:27 fi-skl-i5-6260u total:244 pass:224 dwarn:4 dfail:0 fail:2 skip:14 fi-skl-i7-6700k total:244 pass:208 dwarn:4 dfail:2 fail:2 skip:28 fi-snb-i7-2600 total:244 pass:202 dwarn:0 dfail:0 fail:0 skip:42 ro-bdw-i5-5250u total:240 pass:218 dwarn:3 dfail:0 fail:2 skip:17 ro-bdw-i7-5600u total:240 pass:206 dwarn:1 dfail:0 fail:1 skip:32 ro-bsw-n3050 total:240 pass:195 dwarn:0 dfail:0 fail:3 skip:42 ro-byt-n2820 total:240 pass:198 dwarn:0 dfail:0 fail:2 skip:40 ro-hsw-i3-4010u total:240 pass:214 dwarn:0 dfail:0 fail:0 skip:26 ro-hsw-i7-4770r total:240 pass:213 dwarn:0 dfail:0 fail:1 skip:26 ro-ilk1-i5-650 total:235 pass:173 dwarn:0 dfail:0 fail:2 skip:60 ro-ivb-i7-3770 total:240 pass:205 dwarn:0 dfail:0 fail:0 skip:35 ro-ivb2-i7-3770 total:240 pass:209 dwarn:0 dfail:0 fail:0 skip:31 ro-skl3-i5-6260u total:240 pass:222 dwarn:0 dfail:0 fail:4 skip:14 ro-bdw-i7-5557U failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1836/ 3c6050a drm-intel-nightly: 2016y-08m-11d-10h-34m-38s UTC integration manifest 547ec16 drm/i915: Initialize legacy semaphores from engine hw id indexed array b2f8c29 drm/i915: Add enum for hardware engine identifiers _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Ro.CI.BAT: failure for Shrink and lock the size static gen6 semaphore init array (rev3) 2016-08-11 10:43 [PATCH 0/2] Shrink and lock the size static gen6 semaphore init array Tvrtko Ursulin ` (2 preceding siblings ...) 2016-08-11 11:58 ` ✗ Ro.CI.BAT: failure for Shrink and lock the size static gen6 semaphore init array (rev2) Patchwork @ 2016-08-11 15:31 ` Patchwork 3 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2016-08-11 15:31 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx == Series Details == Series: Shrink and lock the size static gen6 semaphore init array (rev3) URL : https://patchwork.freedesktop.org/series/10949/ State : failure == Summary == Series 10949v3 Shrink and lock the size static gen6 semaphore init array http://patchwork.freedesktop.org/api/1.0/series/10949/revisions/3/mbox Test gem_exec_suspend: Subgroup basic-s3: incomplete -> DMESG-WARN (fi-skl-i7-6700k) Test kms_cursor_legacy: Subgroup basic-cursor-vs-flip-legacy: pass -> SKIP (ro-hsw-i7-4770r) Subgroup basic-cursor-vs-flip-varying-size: pass -> SKIP (ro-hsw-i7-4770r) Subgroup basic-flip-vs-cursor-legacy: fail -> SKIP (ro-hsw-i7-4770r) pass -> FAIL (ro-bdw-i5-5250u) Subgroup basic-flip-vs-cursor-varying-size: pass -> SKIP (ro-hsw-i7-4770r) Test kms_flip: Subgroup basic-flip-vs-dpms: pass -> SKIP (ro-hsw-i7-4770r) Subgroup basic-flip-vs-modeset: pass -> SKIP (ro-hsw-i7-4770r) Subgroup basic-flip-vs-wf_vblank: pass -> SKIP (ro-hsw-i7-4770r) Subgroup basic-plain-flip: pass -> SKIP (ro-hsw-i7-4770r) Test kms_frontbuffer_tracking: Subgroup basic: pass -> SKIP (ro-hsw-i7-4770r) Test kms_pipe_crc_basic: Subgroup hang-read-crc-pipe-a: pass -> SKIP (ro-hsw-i7-4770r) Subgroup hang-read-crc-pipe-b: pass -> SKIP (ro-hsw-i7-4770r) Subgroup hang-read-crc-pipe-c: pass -> SKIP (ro-hsw-i7-4770r) Subgroup nonblocking-crc-pipe-a: pass -> SKIP (ro-hsw-i7-4770r) Subgroup nonblocking-crc-pipe-a-frame-sequence: pass -> SKIP (ro-hsw-i7-4770r) Subgroup nonblocking-crc-pipe-b: pass -> SKIP (ro-hsw-i7-4770r) Subgroup nonblocking-crc-pipe-b-frame-sequence: pass -> SKIP (ro-hsw-i7-4770r) Subgroup nonblocking-crc-pipe-c: pass -> SKIP (ro-hsw-i7-4770r) Subgroup nonblocking-crc-pipe-c-frame-sequence: pass -> SKIP (ro-hsw-i7-4770r) Subgroup read-crc-pipe-a: pass -> SKIP (ro-hsw-i7-4770r) Subgroup read-crc-pipe-a-frame-sequence: pass -> SKIP (ro-hsw-i7-4770r) Subgroup read-crc-pipe-b: pass -> SKIP (ro-hsw-i7-4770r) Subgroup read-crc-pipe-b-frame-sequence: pass -> SKIP (ro-hsw-i7-4770r) Subgroup read-crc-pipe-c: pass -> SKIP (ro-hsw-i7-4770r) Subgroup read-crc-pipe-c-frame-sequence: pass -> SKIP (ro-hsw-i7-4770r) Subgroup suspend-read-crc-pipe-a: pass -> SKIP (ro-hsw-i7-4770r) Subgroup suspend-read-crc-pipe-b: pass -> SKIP (ro-hsw-i7-4770r) Subgroup suspend-read-crc-pipe-c: pass -> SKIP (ro-hsw-i7-4770r) Test pm_rpm: Subgroup basic-pci-d3-state: pass -> SKIP (ro-hsw-i7-4770r) Subgroup basic-rte: pass -> SKIP (ro-hsw-i7-4770r) fi-hsw-i7-4770k total:244 pass:221 dwarn:0 dfail:0 fail:1 skip:22 fi-kbl-qkkr total:244 pass:187 dwarn:28 dfail:0 fail:3 skip:26 fi-skl-i5-6260u total:244 pass:224 dwarn:4 dfail:0 fail:2 skip:14 fi-skl-i7-6700k total:244 pass:208 dwarn:4 dfail:2 fail:2 skip:28 fi-snb-i7-2600 total:244 pass:202 dwarn:0 dfail:0 fail:0 skip:42 ro-bdw-i5-5250u total:240 pass:218 dwarn:4 dfail:0 fail:2 skip:16 ro-bdw-i7-5600u total:240 pass:207 dwarn:0 dfail:0 fail:1 skip:32 ro-bsw-n3050 total:240 pass:194 dwarn:0 dfail:0 fail:4 skip:42 ro-hsw-i3-4010u total:240 pass:214 dwarn:0 dfail:0 fail:0 skip:26 ro-hsw-i7-4770r total:240 pass:185 dwarn:0 dfail:0 fail:0 skip:55 ro-ilk1-i5-650 total:235 pass:173 dwarn:0 dfail:0 fail:2 skip:60 ro-ivb-i7-3770 total:240 pass:205 dwarn:0 dfail:0 fail:0 skip:35 ro-ivb2-i7-3770 total:240 pass:209 dwarn:0 dfail:0 fail:0 skip:31 ro-skl3-i5-6260u total:240 pass:222 dwarn:0 dfail:0 fail:4 skip:14 ro-bdw-i7-5557U failed to connect after reboot ro-byt-n2820 failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1838/ 3c6050a drm-intel-nightly: 2016y-08m-11d-10h-34m-38s UTC integration manifest db642c1 drm/i915: Initialize legacy semaphores from engine hw id indexed array 42f9b20 drm/i915: Add enum for hardware engine identifiers _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2016-08-11 15:46 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-08-11 10:43 [PATCH 0/2] Shrink and lock the size static gen6 semaphore init array Tvrtko Ursulin 2016-08-11 10:43 ` [PATCH 1/2] drm/i915: Add enum for hardware engine identifiers Tvrtko Ursulin 2016-08-11 10:43 ` [PATCH 2/2] drm/i915: Initialize legacy semaphores from engine hw id indexed array Tvrtko Ursulin 2016-08-11 10:53 ` Chris Wilson 2016-08-11 11:05 ` [PATCH v2] " Tvrtko Ursulin 2016-08-11 11:20 ` Chris Wilson 2016-08-11 14:45 ` Tvrtko Ursulin 2016-08-11 14:50 ` [PATCH v3] " Tvrtko Ursulin 2016-08-11 15:46 ` Chris Wilson 2016-08-11 11:06 ` [PATCH 2/2] " Tvrtko Ursulin 2016-08-11 11:58 ` ✗ Ro.CI.BAT: failure for Shrink and lock the size static gen6 semaphore init array (rev2) Patchwork 2016-08-11 15:31 ` ✗ Ro.CI.BAT: failure for Shrink and lock the size static gen6 semaphore init array (rev3) Patchwork
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