[U-Boot] [PATCH 0/5] clean rkpwm driver

[U-Boot] [PATCH 0/5] clean rkpwm driver

[Kever Yang]

This patch set clean the rkpwm driver by using clock API for module
clock instead of hardcode, move the grf setting to soc level init.



Kever Yang (5):
  clk: rk3399: add pmucru controller support
  clk: rk3288: add PWM clock get rate
  rk_pwm: use clock framework API to get module clock
  rk_pwm: remove grf setting code from driver
  rk3288: add arch_cpu_init for rk3288

 arch/arm/mach-rockchip/rk3288/Makefile |   1 +
 arch/arm/mach-rockchip/rk3288/rk3288.c |  19 ++++
 drivers/clk/rockchip/clk_rk3288.c      |   2 +
 drivers/clk/rockchip/clk_rk3399.c      | 177 ++++++++++++++++++++++++++++++++-
 drivers/pwm/rk_pwm.c                   |  26 ++---
 5 files changed, 208 insertions(+), 17 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/rk3288/rk3288.c

-- 
1.9.1

[U-Boot] [PATCH 1/5] clk: rk3399: add pmucru controller support

[Kever Yang]

pmucru is a module like cru which is a clock controller manage some PLL
and module clocks.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 drivers/clk/rockchip/clk_rk3399.c | 177 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 173 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 0b4ea82..ea0ce2a 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -23,6 +23,10 @@ struct rk3399_clk_priv {
 	ulong rate;
 };
 
+struct rk3399_pmuclk_priv {
+	struct rk3399_pmucru *pmucru;
+};
+
 struct pll_div {
 	u32 refdiv;
 	u32 fbdiv;
@@ -95,11 +99,11 @@ enum {
 
 	/* PMUCRU_CLKSEL_CON2 */
 	I2C_DIV_CON_MASK		= 0x7f,
-	I2C8_DIV_CON_SHIFT		= 8,
-	I2C0_DIV_CON_SHIFT		= 0,
+	CLK_I2C8_DIV_CON_SHIFT		= 8,
+	CLK_I2C0_DIV_CON_SHIFT		= 0,
 
 	/* PMUCRU_CLKSEL_CON3 */
-	I2C4_DIV_CON_SHIFT		= 0,
+	CLK_I2C4_DIV_CON_SHIFT		= 0,
 
 	/* CLKSEL_CON0 */
 	ACLKM_CORE_L_DIV_CON_SHIFT	= 8,
@@ -507,6 +511,14 @@ void rk3399_configure_cpu(struct rk3399_cru *cru,
 			(con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
 				I2C_DIV_CON_MASK;
 
+#define I2C_PMUCLK_REG_MASK(bus) \
+			(I2C_DIV_CON_MASK << \
+			 CLK_I2C ##bus## _DIV_CON_SHIFT)
+
+#define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
+				((clk_div - 1) << \
+				CLK_I2C ##bus## _DIV_CON_SHIFT)
+
 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
 {
 	u32 div, con;
@@ -754,7 +766,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 		break;
 	case DCLK_VOP0:
 	case DCLK_VOP1:
-		rate = rk3399_vop_set_clk(priv->cru, clk->id, rate);
+		ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
 		break;
 	default:
 		return -ENOENT;
@@ -830,3 +842,160 @@ U_BOOT_DRIVER(clk_rk3399) = {
 	.bind		= rk3399_clk_bind,
 	.probe		= rk3399_clk_probe,
 };
+
+static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
+{
+	u32 div, con;
+
+	switch (clk_id) {
+	case SCLK_I2C0_PMU:
+		con = readl(&pmucru->pmucru_clksel[2]);
+		div = I2C_CLK_DIV_VALUE(con, 0);
+		break;
+	case SCLK_I2C4_PMU:
+		con = readl(&pmucru->pmucru_clksel[3]);
+		div = I2C_CLK_DIV_VALUE(con, 4);
+		break;
+	case SCLK_I2C8_PMU:
+		con = readl(&pmucru->pmucru_clksel[2]);
+		div = I2C_CLK_DIV_VALUE(con, 8);
+		break;
+	default:
+		printf("do not support this i2c bus\n");
+		return -EINVAL;
+	}
+
+	return DIV_TO_RATE(PPLL_HZ, div);
+}
+
+static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
+				   uint hz)
+{
+	int src_clk_div;
+
+	src_clk_div = PPLL_HZ / hz;
+	assert(src_clk_div - 1 < 127);
+
+	switch (clk_id) {
+	case SCLK_I2C0_PMU:
+		rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
+			     I2C_PMUCLK_REG_VALUE(0, src_clk_div));
+		break;
+	case SCLK_I2C4_PMU:
+		rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
+			     I2C_PMUCLK_REG_VALUE(4, src_clk_div));
+		break;
+	case SCLK_I2C8_PMU:
+		rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
+			     I2C_PMUCLK_REG_VALUE(8, src_clk_div));
+		break;
+	default:
+		printf("do not support this i2c bus\n");
+		return -EINVAL;
+	}
+
+	return DIV_TO_RATE(PPLL_HZ, src_clk_div);
+}
+
+static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
+{
+	u32 div, con;
+
+	/* PWM closk rate is same as pclk_pmu */
+	con = readl(&pmucru->pmucru_clksel[0]);
+	div = con & PMU_PCLK_DIV_CON_MASK;
+
+	return DIV_TO_RATE(PPLL_HZ, div);
+}
+
+static ulong rk3399_pmuclk_get_rate(struct clk *clk)
+{
+	struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
+	ulong rate = 0;
+
+	switch (clk->id) {
+	case PCLK_RKPWM_PMU:
+		rate = rk3399_pwm_get_clk(priv->pmucru);
+		break;
+	case SCLK_I2C0_PMU:
+	case SCLK_I2C4_PMU:
+	case SCLK_I2C8_PMU:
+		rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rate;
+}
+
+static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
+{
+	struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
+	ulong ret = 0;
+
+	switch (clk->id) {
+	case SCLK_I2C0_PMU:
+	case SCLK_I2C4_PMU:
+	case SCLK_I2C8_PMU:
+		ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return ret;
+}
+
+static struct clk_ops rk3399_pmuclk_ops = {
+	.get_rate = rk3399_pmuclk_get_rate,
+	.set_rate = rk3399_pmuclk_set_rate,
+};
+
+static void pmuclk_init(struct rk3399_pmucru *pmucru)
+{
+	u32 pclk_div;
+
+	/*  configure pmu pll(ppll) */
+	rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
+
+	/*  configure pmu pclk */
+	pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
+	assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div < 0x1f);
+	rk_clrsetreg(&pmucru->pmucru_clksel[0],
+		     PMU_PCLK_DIV_CON_MASK,
+		     pclk_div << PMU_PCLK_DIV_CON_SHIFT);
+}
+
+static int rk3399_pmuclk_probe(struct udevice *dev)
+{
+	struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
+
+	pmuclk_init(priv->pmucru);
+
+	return 0;
+}
+
+static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
+{
+	struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
+
+	priv->pmucru = (struct rk3399_pmucru *)dev_get_addr(dev);
+
+	return 0;
+}
+
+static const struct udevice_id rk3399_pmuclk_ids[] = {
+	{ .compatible = "rockchip,rk3399-pmucru" },
+	{ }
+};
+
+U_BOOT_DRIVER(pmuclk_rk3399) = {
+	.name		= "pmuclk_rk3399",
+	.id		= UCLASS_CLK,
+	.of_match	= rk3399_pmuclk_ids,
+	.priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
+	.ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
+	.ops		= &rk3399_pmuclk_ops,
+	.probe		= rk3399_pmuclk_probe,
+};
-- 
1.9.1

[U-Boot] [PATCH 2/5] clk: rk3288: add PWM clock get rate

[Kever Yang]

This patch add clk_get_rate for PWM device.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 drivers/clk/rockchip/clk_rk3288.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index c07203d..bd71a96 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -695,6 +695,8 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
 	case PCLK_I2C4:
 	case PCLK_I2C5:
 		return gclk_rate;
+	case PCLK_PWM:
+		return PD_BUS_PCLK_HZ;
 	default:
 		return -ENOENT;
 	}
-- 
1.9.1

[U-Boot] [PATCH 3/5] rk_pwm: use clock framework API to get module clock

[Kever Yang]

This patch use clock API instead of hardcode for get pwm clock.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 drivers/pwm/rk_pwm.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c
index 2d289a4..d69aab5 100644
--- a/drivers/pwm/rk_pwm.c
+++ b/drivers/pwm/rk_pwm.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <div64.h>
 #include <dm.h>
 #include <pwm.h>
@@ -13,9 +14,9 @@
 #include <syscon.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3288.h>
 #include <asm/arch/grf_rk3288.h>
 #include <asm/arch/pwm.h>
+#include <asm/arch/hardware.h>
 #include <power/regulator.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -23,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 struct rk_pwm_priv {
 	struct rk3288_pwm *regs;
 	struct rk3288_grf *grf;
+	ulong freq;
 };
 
 static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
@@ -38,8 +40,8 @@ static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
 		RK_PWM_DISABLE,
 		&regs->ctrl);
 
-	period = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * period_ns, 1000000);
-	duty = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * duty_ns, 1000000);
+	period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000);
+	duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000);
 
 	writel(period, &regs->period_hpr);
 	writel(duty, &regs->duty_lpr);
@@ -76,9 +78,18 @@ static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
 static int rk_pwm_probe(struct udevice *dev)
 {
 	struct rk_pwm_priv *priv = dev_get_priv(dev);
+	struct clk clk;
+	int ret = 0;
 
 	rk_setreg(&priv->grf->soc_con2, 1 << 0);
 
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret < 0) {
+		printf("%s get clock fail!\n", __func__);
+		return -EINVAL;
+	}
+	priv->freq = clk_get_rate(&clk);
+
 	return 0;
 }
 
-- 
1.9.1

[U-Boot] [PATCH 4/5] rk_pwm: remove grf setting code from driver

[Kever Yang]

We consider the grf setting for pwm controller select as the system
operation instead of driver operation, move it to soc init, let's
remove it from pwm driver first.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 drivers/pwm/rk_pwm.c | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c
index d69aab5..d3de429 100644
--- a/drivers/pwm/rk_pwm.c
+++ b/drivers/pwm/rk_pwm.c
@@ -13,17 +13,13 @@
 #include <regmap.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3288.h>
 #include <asm/arch/pwm.h>
-#include <asm/arch/hardware.h>
 #include <power/regulator.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 struct rk_pwm_priv {
 	struct rk3288_pwm *regs;
-	struct rk3288_grf *grf;
 	ulong freq;
 };
 
@@ -64,13 +60,8 @@ static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
 static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
 {
 	struct rk_pwm_priv *priv = dev_get_priv(dev);
-	struct regmap *map;
 
 	priv->regs = (struct rk3288_pwm *)dev_get_addr(dev);
-	map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_GRF);
-	if (IS_ERR(map))
-		return PTR_ERR(map);
-	priv->grf = regmap_get_range(map, 0);
 
 	return 0;
 }
@@ -81,8 +72,6 @@ static int rk_pwm_probe(struct udevice *dev)
 	struct clk clk;
 	int ret = 0;
 
-	rk_setreg(&priv->grf->soc_con2, 1 << 0);
-
 	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret < 0) {
 		printf("%s get clock fail!\n", __func__);
-- 
1.9.1

[U-Boot] [PATCH 5/5] rk3288: add arch_cpu_init for rk3288

[Kever Yang]

We do some SoC level one time setting initialization in
arch_cpu_init.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rk3288/Makefile |  1 +
 arch/arm/mach-rockchip/rk3288/rk3288.c | 19 +++++++++++++++++++
 2 files changed, 20 insertions(+)
 create mode 100644 arch/arm/mach-rockchip/rk3288/rk3288.c

diff --git a/arch/arm/mach-rockchip/rk3288/Makefile b/arch/arm/mach-rockchip/rk3288/Makefile
index 82b00a1..2e0be74 100644
--- a/arch/arm/mach-rockchip/rk3288/Makefile
+++ b/arch/arm/mach-rockchip/rk3288/Makefile
@@ -6,5 +6,6 @@
 
 obj-y += clk_rk3288.o
 obj-y += reset_rk3288.o
+obj-y += rk3288.o
 obj-y += sdram_rk3288.o
 obj-y += syscon_rk3288.o
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
new file mode 100644
index 0000000..92f34bb
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#define GRF_SOC_CON2 0x24c
+
+int arch_cpu_init(void)
+{
+	/* We do some SoC one time setting here. */
+
+	/* Use rkpwm by default */
+	rk_setreg(GRF_SOC_CON2, 1 << 0);
+
+	return 0;
+}
-- 
1.9.1

[U-Boot] [PATCH 1/5] clk: rk3399: add pmucru controller support

[Simon Glass]

On 12 August 2016 at 03:47, Kever Yang <kever.yang@rock-chips.com> wrote:
> pmucru is a module like cru which is a clock controller manage some PLL
> and module clocks.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  drivers/clk/rockchip/clk_rk3399.c | 177 +++++++++++++++++++++++++++++++++++++-
>  1 file changed, 173 insertions(+), 4 deletions(-)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 3/5] rk_pwm: use clock framework API to get module clock

[Simon Glass]

Hi Kever,

On 12 August 2016 at 03:57, Kever Yang <kever.yang@rock-chips.com> wrote:
> This patch use clock API instead of hardcode for get pwm clock.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  drivers/pwm/rk_pwm.c | 17 ++++++++++++++---
>  1 file changed, 14 insertions(+), 3 deletions(-)

Acked-by: Simon Glass <sjg@chromium.org>

nit below

>
> diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c
> index 2d289a4..d69aab5 100644
> --- a/drivers/pwm/rk_pwm.c
> +++ b/drivers/pwm/rk_pwm.c
> @@ -6,6 +6,7 @@
>   */
>
>  #include <common.h>
> +#include <clk.h>
>  #include <div64.h>
>  #include <dm.h>
>  #include <pwm.h>
> @@ -13,9 +14,9 @@
>  #include <syscon.h>
>  #include <asm/io.h>
>  #include <asm/arch/clock.h>
> -#include <asm/arch/cru_rk3288.h>
>  #include <asm/arch/grf_rk3288.h>
>  #include <asm/arch/pwm.h>
> +#include <asm/arch/hardware.h>
>  #include <power/regulator.h>
>
>  DECLARE_GLOBAL_DATA_PTR;
> @@ -23,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
>  struct rk_pwm_priv {
>         struct rk3288_pwm *regs;
>         struct rk3288_grf *grf;
> +       ulong freq;
>  };
>
>  static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
> @@ -38,8 +40,8 @@ static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
>                 RK_PWM_DISABLE,
>                 &regs->ctrl);
>
> -       period = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * period_ns, 1000000);
> -       duty = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * duty_ns, 1000000);
> +       period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000);
> +       duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000);
>
>         writel(period, &regs->period_hpr);
>         writel(duty, &regs->duty_lpr);
> @@ -76,9 +78,18 @@ static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
>  static int rk_pwm_probe(struct udevice *dev)
>  {
>         struct rk_pwm_priv *priv = dev_get_priv(dev);
> +       struct clk clk;
> +       int ret = 0;
>
>         rk_setreg(&priv->grf->soc_con2, 1 << 0);
>
> +       ret = clk_get_by_index(dev, 0, &clk);
> +       if (ret < 0) {
> +               printf("%s get clock fail!\n", __func__);

debug() please.

> +               return -EINVAL;
> +       }
> +       priv->freq = clk_get_rate(&clk);
> +
>         return 0;
>  }
>
> --
> 1.9.1
>
>

Regards,
Simon

[U-Boot] [PATCH 4/5] rk_pwm: remove grf setting code from driver

[Simon Glass]

On 12 August 2016 at 03:58, Kever Yang <kever.yang@rock-chips.com> wrote:
> We consider the grf setting for pwm controller select as the system
> operation instead of driver operation, move it to soc init, let's
> remove it from pwm driver first.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  drivers/pwm/rk_pwm.c | 11 -----------
>  1 file changed, 11 deletions(-)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 2/5] clk: rk3288: add PWM clock get rate

[Simon Glass]

On 12 August 2016 at 03:57, Kever Yang <kever.yang@rock-chips.com> wrote:
> This patch add clk_get_rate for PWM device.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  drivers/clk/rockchip/clk_rk3288.c | 2 ++
>  1 file changed, 2 insertions(+)
>

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 5/5] rk3288: add arch_cpu_init for rk3288

[Simon Glass]

On 12 August 2016 at 03:58, Kever Yang <kever.yang@rock-chips.com> wrote:
>
> We do some SoC level one time setting initialization in
> arch_cpu_init.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  arch/arm/mach-rockchip/rk3288/Makefile |  1 +
>  arch/arm/mach-rockchip/rk3288/rk3288.c | 19 +++++++++++++++++++
>  2 files changed, 20 insertions(+)
>  create mode 100644 arch/arm/mach-rockchip/rk3288/rk3288.c


Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 3/5] rk_pwm: use clock framework API to get module clock

[Simon Glass]

On 12 August 2016 at 11:21, Simon Glass <sjg@chromium.org> wrote:
> Hi Kever,
>
> On 12 August 2016 at 03:57, Kever Yang <kever.yang@rock-chips.com> wrote:
>> This patch use clock API instead of hardcode for get pwm clock.
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>>  drivers/pwm/rk_pwm.c | 17 ++++++++++++++---
>>  1 file changed, 14 insertions(+), 3 deletions(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> nit below
>
>>
>> diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c
>> index 2d289a4..d69aab5 100644
>> --- a/drivers/pwm/rk_pwm.c
>> +++ b/drivers/pwm/rk_pwm.c
>> @@ -6,6 +6,7 @@
>>   */
>>
>>  #include <common.h>
>> +#include <clk.h>
>>  #include <div64.h>
>>  #include <dm.h>
>>  #include <pwm.h>
>> @@ -13,9 +14,9 @@
>>  #include <syscon.h>
>>  #include <asm/io.h>
>>  #include <asm/arch/clock.h>
>> -#include <asm/arch/cru_rk3288.h>
>>  #include <asm/arch/grf_rk3288.h>
>>  #include <asm/arch/pwm.h>
>> +#include <asm/arch/hardware.h>
>>  #include <power/regulator.h>
>>
>>  DECLARE_GLOBAL_DATA_PTR;
>> @@ -23,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
>>  struct rk_pwm_priv {
>>         struct rk3288_pwm *regs;
>>         struct rk3288_grf *grf;
>> +       ulong freq;
>>  };
>>
>>  static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
>> @@ -38,8 +40,8 @@ static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
>>                 RK_PWM_DISABLE,
>>                 &regs->ctrl);
>>
>> -       period = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * period_ns, 1000000);
>> -       duty = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * duty_ns, 1000000);
>> +       period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000);
>> +       duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000);
>>
>>         writel(period, &regs->period_hpr);
>>         writel(duty, &regs->duty_lpr);
>> @@ -76,9 +78,18 @@ static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
>>  static int rk_pwm_probe(struct udevice *dev)
>>  {
>>         struct rk_pwm_priv *priv = dev_get_priv(dev);
>> +       struct clk clk;
>> +       int ret = 0;
>>
>>         rk_setreg(&priv->grf->soc_con2, 1 << 0);
>>
>> +       ret = clk_get_by_index(dev, 0, &clk);
>> +       if (ret < 0) {
>> +               printf("%s get clock fail!\n", __func__);
>
> debug() please.
>
>> +               return -EINVAL;
>> +       }
>> +       priv->freq = clk_get_rate(&clk);
>> +
>>         return 0;
>>  }
>>
>> --
>> 1.9.1
>>
>>
>
> Regards,
> Simon

Fixed nit and:

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH 4/5] rk_pwm: remove grf setting code from driver

[Simon Glass]

On 12 August 2016 at 11:21, Simon Glass <sjg@chromium.org> wrote:
> On 12 August 2016 at 03:58, Kever Yang <kever.yang@rock-chips.com> wrote:
>> We consider the grf setting for pwm controller select as the system
>> operation instead of driver operation, move it to soc init, let's
>> remove it from pwm driver first.
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>>  drivers/pwm/rk_pwm.c | 11 -----------
>>  1 file changed, 11 deletions(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH 5/5] rk3288: add arch_cpu_init for rk3288

[Simon Glass]

On 15 August 2016 at 22:50, Simon Glass <sjg@chromium.org> wrote:
> On 12 August 2016 at 03:58, Kever Yang <kever.yang@rock-chips.com> wrote:
>>
>> We do some SoC level one time setting initialization in
>> arch_cpu_init.
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>>  arch/arm/mach-rockchip/rk3288/Makefile |  1 +
>>  arch/arm/mach-rockchip/rk3288/rk3288.c | 19 +++++++++++++++++++
>>  2 files changed, 20 insertions(+)
>>  create mode 100644 arch/arm/mach-rockchip/rk3288/rk3288.c
>
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH 1/5] clk: rk3399: add pmucru controller support

[Simon Glass]

On 12 August 2016 at 11:21, Simon Glass <sjg@chromium.org> wrote:
> On 12 August 2016 at 03:47, Kever Yang <kever.yang@rock-chips.com> wrote:
>> pmucru is a module like cru which is a clock controller manage some PLL
>> and module clocks.
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>>  drivers/clk/rockchip/clk_rk3399.c | 177 +++++++++++++++++++++++++++++++++++++-
>>  1 file changed, 173 insertions(+), 4 deletions(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH 2/5] clk: rk3288: add PWM clock get rate

[Simon Glass]

On 12 August 2016 at 11:21, Simon Glass <sjg@chromium.org> wrote:
> On 12 August 2016 at 03:57, Kever Yang <kever.yang@rock-chips.com> wrote:
>> This patch add clk_get_rate for PWM device.
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>>  drivers/clk/rockchip/clk_rk3288.c | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip/next, thanks!