[PATCH V2 0/5] kexec changes for Power ISA 3.0

[PATCH V2 0/5] kexec changes for Power ISA 3.0

[Aneesh Kumar K.V]

Add kexec support with radix page table config.

Changes from v1:
* Rebase to latest kernel
* add tlbflush on MMU cleanup

Aneesh Kumar K.V (1):
  powerpc/mm: Add radix flush all with IS=3

Benjamin Herrenschmidt (4):
  powerpc/64/kexec: NULL check "clear_all" in kexec_sequence
  powerpc/64/kexec: Fix MMU cleanup on radix
  powerpc/64/kexec: Copy image with MMU off when possible
  powerpc/64/kexec: Remove BookE special default_machine_kexec_prepare()

 .../powerpc/include/asm/book3s/64/tlbflush-radix.h |  1 +
 arch/powerpc/include/asm/mmu-book3e.h              |  3 +
 arch/powerpc/include/asm/mmu.h                     |  4 ++
 arch/powerpc/kernel/machine_kexec_64.c             | 74 +++++++---------------
 arch/powerpc/kernel/misc_64.S                      | 25 ++++++--
 arch/powerpc/mm/pgtable-book3s64.c                 |  9 +++
 arch/powerpc/mm/pgtable-radix.c                    | 12 ++++
 arch/powerpc/mm/tlb-radix.c                        | 15 +++++
 8 files changed, 84 insertions(+), 59 deletions(-)

-- 
2.7.4

[PATCH V2 1/5] powerpc/64/kexec: NULL check "clear_all" in kexec_sequence

[Aneesh Kumar K.V]

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

With Radix, it can be NULL even on !BOOKE these days so replace
the ifdef with a NULL check which is cleaner anyway.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/kernel/misc_64.S | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index cb195157b318..7902f4b12d3f 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -659,7 +659,9 @@ _GLOBAL(kexec_sequence)
 	li	r6,1
 	stw	r6,kexec_flag-1b(5)
 
-#ifndef CONFIG_PPC_BOOK3E
+	cmpdi	r27,0
+	beq	1f
+
 	/* clear out hardware hash page table and tlb */
 #ifdef PPC64_ELF_ABI_v1
 	ld	r12,0(r27)		/* deref function descriptor */
@@ -668,7 +670,6 @@ _GLOBAL(kexec_sequence)
 #endif
 	mtctr	r12
 	bctrl				/* mmu_hash_ops.hpte_clear_all(void); */
-#endif /* !CONFIG_PPC_BOOK3E */
 
 /*
  *   kexec image calling is:
@@ -695,7 +696,7 @@ _GLOBAL(kexec_sequence)
  *    are the boot cpu ?????
  *    other device tree differences (prop sizes, va vs pa, etc)...
  */
-	mr	r3,r25	# my phys cpu
+1:	mr	r3,r25	# my phys cpu
 	mr	r4,r30	# start, aka phys mem offset
 	mtlr	4
 	li	r5,0
-- 
2.7.4

Re: [PATCH V2 1/5] powerpc/64/kexec: NULL check "clear_all" in kexec_sequence

[Balbir Singh]

On Fri, Aug 19, 2016 at 02:22:35PM +0530, Aneesh Kumar K.V wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> 
> With Radix, it can be NULL even on !BOOKE these days so replace
> the ifdef with a NULL check which is cleaner anyway.
> 
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
>  arch/powerpc/kernel/misc_64.S | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
> index cb195157b318..7902f4b12d3f 100644
> --- a/arch/powerpc/kernel/misc_64.S
> +++ b/arch/powerpc/kernel/misc_64.S
> @@ -659,7 +659,9 @@ _GLOBAL(kexec_sequence)
>  	li	r6,1
>  	stw	r6,kexec_flag-1b(5)
>  
> -#ifndef CONFIG_PPC_BOOK3E
> +	cmpdi	r27,0
> +	beq	1f
> +

Having a comment inline would help as well. I presume we are not going
to tear down the page tables for radix

Acked-by: Balbir Singh <bsingharora@gmail.com>
 
Balbir Singh

Re: [V2, 1/5] powerpc/64/kexec: NULL check "clear_all" in kexec_sequence

[Michael Ellerman]

On Fri, 2016-19-08 at 08:52:35 UTC, "Aneesh Kumar K.V" wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> 
> With Radix, it can be NULL even on !BOOKE these days so replace
> the ifdef with a NULL check which is cleaner anyway.
> 
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> Acked-by: Balbir Singh <bsingharora@gmail.com>

Series applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/fc48bad53142c991a5280940fd

cheers

[PATCH V2 2/5] powerpc/mm: Add radix flush all with IS=3

[Aneesh Kumar K.V]

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/include/asm/book3s/64/tlbflush-radix.h |  1 +
 arch/powerpc/mm/tlb-radix.c                         | 15 +++++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
index 65037762b120..a9e19cb2f7c5 100644
--- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
+++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
@@ -41,4 +41,5 @@ extern void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmad
 extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
 				     unsigned long page_size);
 extern void radix__flush_tlb_lpid(unsigned long lpid);
+extern void radix__flush_tlb_all(void);
 #endif
diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index 48df05ef5231..517feb47ebe4 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -400,3 +400,18 @@ void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
 	radix__flush_tlb_range_psize(vma->vm_mm, start, end, MMU_PAGE_2M);
 }
 EXPORT_SYMBOL(radix__flush_pmd_tlb_range);
+
+void radix__flush_tlb_all(void)
+{
+	unsigned long rb,prs,r;
+	unsigned long ric = RIC_FLUSH_ALL;
+
+	rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */
+	prs = 0; /* partition scoped */
+	r = 1;   /* raidx format */
+
+	asm volatile("ptesync": : :"memory");
+	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
+		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) : "memory");
+	asm volatile("eieio; tlbsync; ptesync": : :"memory");
+}
-- 
2.7.4

Re: [PATCH V2 2/5] powerpc/mm: Add radix flush all with IS=3

[Benjamin Herrenschmidt]

On Fri, 2016-08-19 at 14:22 +0530, Aneesh Kumar K.V wrote:
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
>  arch/powerpc/include/asm/book3s/64/tlbflush-radix.h |  1 +
>  arch/powerpc/mm/tlb-radix.c                         | 15
> +++++++++++++++
>  2 files changed, 16 insertions(+)

Don't we need two ? One for partition scoped and one for process scoped
?

> diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> index 65037762b120..a9e19cb2f7c5 100644
> --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> @@ -41,4 +41,5 @@ extern void radix__flush_tlb_page_psize(struct
> mm_struct *mm, unsigned long vmad
>  extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned
> long gpa,
>  				     unsigned long page_size);
>  extern void radix__flush_tlb_lpid(unsigned long lpid);
> +extern void radix__flush_tlb_all(void);
>  #endif
> diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-
> radix.c
> index 48df05ef5231..517feb47ebe4 100644
> --- a/arch/powerpc/mm/tlb-radix.c
> +++ b/arch/powerpc/mm/tlb-radix.c
> @@ -400,3 +400,18 @@ void radix__flush_pmd_tlb_range(struct
> vm_area_struct *vma,
>  	radix__flush_tlb_range_psize(vma->vm_mm, start, end,
> MMU_PAGE_2M);
>  }
>  EXPORT_SYMBOL(radix__flush_pmd_tlb_range);
> +
> +void radix__flush_tlb_all(void)
> +{
> +	unsigned long rb,prs,r;
> +	unsigned long ric = RIC_FLUSH_ALL;
> +
> +	rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */
> +	prs = 0; /* partition scoped */
> +	r = 1;   /* raidx format */
> +
> +	asm volatile("ptesync": : :"memory");
> +	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
> +		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0)
> : "memory");
> +	asm volatile("eieio; tlbsync; ptesync": : :"memory");
> +}

Re: [PATCH V2 2/5] powerpc/mm: Add radix flush all with IS=3

[Aneesh Kumar K.V]

Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:

> On Fri, 2016-08-19 at 14:22 +0530, Aneesh Kumar K.V wrote:
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>> =C2=A0arch/powerpc/include/asm/book3s/64/tlbflush-radix.h |=C2=A0=C2=A01=
 +
>> =C2=A0arch/powerpc/mm/tlb-radix.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0| 15
>> +++++++++++++++
>> =C2=A02 files changed, 16 insertions(+)
>
> Don't we need two ? One for partition scoped and one for process scoped
> ?


With invalid selector value 3 (IS =3D 3), we will invalidate all entries
when executed with MSR[HV] =3D 1. I guess that should take out all the
translation cache, including implementation dependent one ?

Also note thar PRS =3D 0. ie, we are partition scoped. ie, we are doing
invalidate with

PRS =3D0, IS =3D 3 HV =3D 1 RIC =3D 2

>
>> diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
>> b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
>> index 65037762b120..a9e19cb2f7c5 100644
>> --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
>> +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
>> @@ -41,4 +41,5 @@ extern void radix__flush_tlb_page_psize(struct
>> mm_struct *mm, unsigned long vmad
>> =C2=A0extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned
>> long gpa,
>> =C2=A0				=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0unsigned long page_size);
>> =C2=A0extern void radix__flush_tlb_lpid(unsigned long lpid);
>> +extern void radix__flush_tlb_all(void);
>> =C2=A0#endif
>> diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-
>> radix.c
>> index 48df05ef5231..517feb47ebe4 100644
>> --- a/arch/powerpc/mm/tlb-radix.c
>> +++ b/arch/powerpc/mm/tlb-radix.c
>> @@ -400,3 +400,18 @@ void radix__flush_pmd_tlb_range(struct
>> vm_area_struct *vma,
>> =C2=A0	radix__flush_tlb_range_psize(vma->vm_mm, start, end,
>> MMU_PAGE_2M);
>> =C2=A0}
>> =C2=A0EXPORT_SYMBOL(radix__flush_pmd_tlb_range);
>> +
>> +void radix__flush_tlb_all(void)
>> +{
>> +	unsigned long rb,prs,r;
>> +	unsigned long ric =3D RIC_FLUSH_ALL;
>> +
>> +	rb =3D 0x3 << PPC_BITLSHIFT(53); /* IS =3D 3 */
>> +	prs =3D 0; /* partition scoped */
>> +	r =3D 1;=C2=A0=C2=A0=C2=A0/* raidx format */
>> +
>> +	asm volatile("ptesync": : :"memory");
>> +	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
>> +		=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0: : "r"(rb), "i"(r), "i"(prs), "i"(ric)=
, "r"(0)
>> : "memory");
>> +	asm volatile("eieio; tlbsync; ptesync": : :"memory");
>> +}

Re: [PATCH V2 2/5] powerpc/mm: Add radix flush all with IS=3

[Balbir Singh]

On Mon, Aug 22, 2016 at 11:41:13AM +0530, Aneesh Kumar K.V wrote:
> Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
> 
> > On Fri, 2016-08-19 at 14:22 +0530, Aneesh Kumar K.V wrote:
> >> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> >> ---
> >>  arch/powerpc/include/asm/book3s/64/tlbflush-radix.h |  1 +
> >>  arch/powerpc/mm/tlb-radix.c                         | 15
> >> +++++++++++++++
> >>  2 files changed, 16 insertions(+)
> >
> > Don't we need two ? One for partition scoped and one for process scoped
> > ?
> 
> 
> With invalid selector value 3 (IS = 3), we will invalidate all entries
> when executed with MSR[HV] = 1. I guess that should take out all the
> translation cache, including implementation dependent one ?
>

I think Ben might be right, we probably need two. We probably want
to invlidate the process scoped ones first followed by partition
scope. I could not find anything in the documentation that said
partition scope flush implied process scope flush.
 
> Also note thar PRS = 0. ie, we are partition scoped. ie, we are doing
> invalidate with
> 
> PRS =0, IS = 3 HV = 1 RIC = 2
> 
> >
> >> diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> >> b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> >> index 65037762b120..a9e19cb2f7c5 100644
> >> --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> >> +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> >> @@ -41,4 +41,5 @@ extern void radix__flush_tlb_page_psize(struct
> >> mm_struct *mm, unsigned long vmad
> >>  extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned
> >> long gpa,
> >>  				     unsigned long page_size);
> >>  extern void radix__flush_tlb_lpid(unsigned long lpid);
> >> +extern void radix__flush_tlb_all(void);
> >>  #endif
> >> diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-
> >> radix.c
> >> index 48df05ef5231..517feb47ebe4 100644
> >> --- a/arch/powerpc/mm/tlb-radix.c
> >> +++ b/arch/powerpc/mm/tlb-radix.c
> >> @@ -400,3 +400,18 @@ void radix__flush_pmd_tlb_range(struct
> >> vm_area_struct *vma,
> >>  	radix__flush_tlb_range_psize(vma->vm_mm, start, end,
> >> MMU_PAGE_2M);
> >>  }
> >>  EXPORT_SYMBOL(radix__flush_pmd_tlb_range);
> >> +
> >> +void radix__flush_tlb_all(void)
> >> +{
> >> +	unsigned long rb,prs,r;
> >> +	unsigned long ric = RIC_FLUSH_ALL;
> >> +
> >> +	rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */
> >> +	prs = 0; /* partition scoped */
> >> +	r = 1;   /* raidx format */
		^^ radix
> >> +
> >> +	asm volatile("ptesync": : :"memory");
> >> +	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
> >> +		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0)
> >> : "memory");
> >> +	asm volatile("eieio; tlbsync; ptesync": : :"memory");
> >> +}
> 


Balbir Singh.

[PATCH V3] powerpc/mm: Add radix flush all with IS=3

[Aneesh Kumar K.V]

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 .../powerpc/include/asm/book3s/64/tlbflush-radix.h |  1 +
 arch/powerpc/mm/tlb-radix.c                        | 24 ++++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
index 65037762b120..a9e19cb2f7c5 100644
--- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
+++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
@@ -41,4 +41,5 @@ extern void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmad
 extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
 				     unsigned long page_size);
 extern void radix__flush_tlb_lpid(unsigned long lpid);
+extern void radix__flush_tlb_all(void);
 #endif
diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index 48df05ef5231..0e49ec541ab5 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -400,3 +400,27 @@ void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
 	radix__flush_tlb_range_psize(vma->vm_mm, start, end, MMU_PAGE_2M);
 }
 EXPORT_SYMBOL(radix__flush_pmd_tlb_range);
+
+void radix__flush_tlb_all(void)
+{
+	unsigned long rb,prs,r,rs;
+	unsigned long ric = RIC_FLUSH_ALL;
+
+	rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */
+	prs = 0; /* partition scoped */
+	r = 1;   /* raidx format */
+	rs = 1 & ((1UL << 32) - 1); /* any LPID value to flush guest mappings */
+
+	asm volatile("ptesync": : :"memory");
+	/*
+	 * now flush guest entries by passing PRS = 1 and LPID != 0
+	 */
+	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
+		     : : "r"(rb), "i"(r), "i"(1), "i"(ric), "r"(rs) : "memory");
+	/*
+	 * now flush host entires by passing PRS = 0 and LPID == 0
+	 */
+	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
+		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) : "memory");
+	asm volatile("eieio; tlbsync; ptesync": : :"memory");
+}
-- 
2.7.4

Re: [PATCH V3] powerpc/mm: Add radix flush all with IS=3

[Balbir Singh]

On 23/08/16 20:57, Aneesh Kumar K.V wrote:
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
>  .../powerpc/include/asm/book3s/64/tlbflush-radix.h |  1 +
>  arch/powerpc/mm/tlb-radix.c                        | 24 ++++++++++++++++++++++
>  2 files changed, 25 insertions(+)
> 
> diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> index 65037762b120..a9e19cb2f7c5 100644
> --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> @@ -41,4 +41,5 @@ extern void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmad
>  extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
>  				     unsigned long page_size);
>  extern void radix__flush_tlb_lpid(unsigned long lpid);
> +extern void radix__flush_tlb_all(void);
>  #endif
> diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
> index 48df05ef5231..0e49ec541ab5 100644
> --- a/arch/powerpc/mm/tlb-radix.c
> +++ b/arch/powerpc/mm/tlb-radix.c
> @@ -400,3 +400,27 @@ void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
>  	radix__flush_tlb_range_psize(vma->vm_mm, start, end, MMU_PAGE_2M);
>  }
>  EXPORT_SYMBOL(radix__flush_pmd_tlb_range);
> +
> +void radix__flush_tlb_all(void)
> +{
> +	unsigned long rb,prs,r,rs;
> +	unsigned long ric = RIC_FLUSH_ALL;
> +
> +	rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */
> +	prs = 0; /* partition scoped */
> +	r = 1;   /* raidx format */

		^^ typo - radix

> +	rs = 1 & ((1UL << 32) - 1); /* any LPID value to flush guest mappings */
> +

For RIC=2 and IS=3, I think RS is ignored.. I don't think we need to
set RS to anything other than 0, please double check


> +	asm volatile("ptesync": : :"memory");
> +	/*
> +	 * now flush guest entries by passing PRS = 1 and LPID != 0
> +	 */
> +	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
> +		     : : "r"(rb), "i"(r), "i"(1), "i"(ric), "r"(rs) : "memory");
> +	/*
> +	 * now flush host entires by passing PRS = 0 and LPID == 0
> +	 */
> +	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
> +		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) : "memory");
> +	asm volatile("eieio; tlbsync; ptesync": : :"memory");
> +}
> 

Otherwise looks good



Balbir Singh.

Re: [V3] powerpc/mm: Add radix flush all with IS=3

[Michael Ellerman]

On Tue, 2016-23-08 at 10:57:48 UTC, "Aneesh Kumar K.V" wrote:
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>

Applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/be34d300597a7a4fb38c6e3f99

cheers

[PATCH V2 3/5] powerpc/64/kexec: Fix MMU cleanup on radix

[Aneesh Kumar K.V]

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Just using the hash ops won't work anymore since radix will have
NULL in there. Instead create an mmu_cleanup_all() function which
will do the right thing based on the MMU mode.

For Radix, for now I clear UPRT and the PTCR, effectively switching
back to Radix with no partition table setup.

Currently set it to NULL on BookE thought it might be a good idea
to wipe the TLB there (Scott ?)

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/include/asm/mmu-book3e.h  |  3 +++
 arch/powerpc/include/asm/mmu.h         |  4 ++++
 arch/powerpc/kernel/machine_kexec_64.c | 13 +++----------
 arch/powerpc/mm/pgtable-book3s64.c     |  9 +++++++++
 arch/powerpc/mm/pgtable-radix.c        | 12 ++++++++++++
 5 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index cd4f04a74802..b62a8d43a06c 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -313,6 +313,9 @@ extern int book3e_htw_mode;
  * return 1, indicating that the tlb requires preloading.
  */
 #define HUGETLB_NEED_PRELOAD
+
+#define mmu_cleanup_all NULL
+
 #endif
 
 #endif /* !__ASSEMBLY__ */
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index e2fb408f8398..79c989a05aa1 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -204,6 +204,10 @@ extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
  * make it match the size our of bolted TLB area
  */
 extern u64 ppc64_rma_size;
+
+/* Cleanup function used by kexec */
+extern void mmu_cleanup_all(void);
+extern void radix__mmu_cleanup_all(void);
 #endif /* CONFIG_PPC64 */
 
 struct mm_struct;
diff --git a/arch/powerpc/kernel/machine_kexec_64.c b/arch/powerpc/kernel/machine_kexec_64.c
index 4c780a342282..8cbd870dd557 100644
--- a/arch/powerpc/kernel/machine_kexec_64.c
+++ b/arch/powerpc/kernel/machine_kexec_64.c
@@ -30,6 +30,7 @@
 #include <asm/smp.h>
 #include <asm/hw_breakpoint.h>
 #include <asm/asm-prototypes.h>
+#include <asm/firmware.h>
 
 #ifdef CONFIG_PPC_BOOK3E
 int default_machine_kexec_prepare(struct kimage *image)
@@ -55,9 +56,6 @@ int default_machine_kexec_prepare(struct kimage *image)
 	const unsigned long *basep;
 	const unsigned int *sizep;
 
-	if (!mmu_hash_ops.hpte_clear_all)
-		return -ENOENT;
-
 	/*
 	 * Since we use the kernel fault handlers and paging code to
 	 * handle the virtual mode, we must make sure no destination
@@ -379,13 +377,8 @@ void default_machine_kexec(struct kimage *image)
 	 * a toc is easier in C, so pass in what we can.
 	 */
 	kexec_sequence(&kexec_stack, image->start, image,
-			page_address(image->control_code_page),
-#ifdef CONFIG_PPC_STD_MMU
-			mmu_hash_ops.hpte_clear_all
-#else
-			NULL
-#endif
-	);
+		       page_address(image->control_code_page),
+		       mmu_cleanup_all);
 	/* NOTREACHED */
 }
 
diff --git a/arch/powerpc/mm/pgtable-book3s64.c b/arch/powerpc/mm/pgtable-book3s64.c
index 7328886bca4c..f4f437cbabf1 100644
--- a/arch/powerpc/mm/pgtable-book3s64.c
+++ b/arch/powerpc/mm/pgtable-book3s64.c
@@ -116,3 +116,12 @@ void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
 	return;
 }
 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
+
+/* For use by kexec */
+void mmu_cleanup_all(void)
+{
+	if (radix_enabled())
+		radix__mmu_cleanup_all();
+	else if (mmu_hash_ops.hpte_clear_all)
+		mmu_hash_ops.hpte_clear_all();
+}
diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
index 035a1a2b1002..790a1e1bb0e5 100644
--- a/arch/powerpc/mm/pgtable-radix.c
+++ b/arch/powerpc/mm/pgtable-radix.c
@@ -395,6 +395,18 @@ void radix__early_init_mmu_secondary(void)
 	}
 }
 
+void radix__mmu_cleanup_all(void)
+{
+	unsigned long lpcr;
+
+	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
+		lpcr = mfspr(SPRN_LPCR);
+		mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
+		mtspr(SPRN_PTCR, 0);
+		radix__flush_tlb_all();
+	}
+}
+
 void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 				phys_addr_t first_memblock_size)
 {
-- 
2.7.4

Re: [PATCH V2 3/5] powerpc/64/kexec: Fix MMU cleanup on radix

[Balbir Singh]

On 19/08/16 18:52, Aneesh Kumar K.V wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> 
> Just using the hash ops won't work anymore since radix will have
> NULL in there. Instead create an mmu_cleanup_all() function which
> will do the right thing based on the MMU mode.
> 
> For Radix, for now I clear UPRT and the PTCR, effectively switching
> back to Radix with no partition table setup.
> 
> Currently set it to NULL on BookE thought it might be a good idea
> to wipe the TLB there (Scott ?)
> 
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
>  arch/powerpc/include/asm/mmu-book3e.h  |  3 +++
>  arch/powerpc/include/asm/mmu.h         |  4 ++++
>  arch/powerpc/kernel/machine_kexec_64.c | 13 +++----------
>  arch/powerpc/mm/pgtable-book3s64.c     |  9 +++++++++
>  arch/powerpc/mm/pgtable-radix.c        | 12 ++++++++++++
>  5 files changed, 31 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
> index cd4f04a74802..b62a8d43a06c 100644
> --- a/arch/powerpc/include/asm/mmu-book3e.h
> +++ b/arch/powerpc/include/asm/mmu-book3e.h
> @@ -313,6 +313,9 @@ extern int book3e_htw_mode;
>   * return 1, indicating that the tlb requires preloading.
>   */
>  #define HUGETLB_NEED_PRELOAD
> +
> +#define mmu_cleanup_all NULL
> +
>  #endif
>  
>  #endif /* !__ASSEMBLY__ */
> diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
> index e2fb408f8398..79c989a05aa1 100644
> --- a/arch/powerpc/include/asm/mmu.h
> +++ b/arch/powerpc/include/asm/mmu.h
> @@ -204,6 +204,10 @@ extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
>   * make it match the size our of bolted TLB area
>   */
>  extern u64 ppc64_rma_size;
> +
> +/* Cleanup function used by kexec */
> +extern void mmu_cleanup_all(void);
> +extern void radix__mmu_cleanup_all(void);
>  #endif /* CONFIG_PPC64 */
>  
>  struct mm_struct;
> diff --git a/arch/powerpc/kernel/machine_kexec_64.c b/arch/powerpc/kernel/machine_kexec_64.c
> index 4c780a342282..8cbd870dd557 100644
> --- a/arch/powerpc/kernel/machine_kexec_64.c
> +++ b/arch/powerpc/kernel/machine_kexec_64.c
> @@ -30,6 +30,7 @@
>  #include <asm/smp.h>
>  #include <asm/hw_breakpoint.h>
>  #include <asm/asm-prototypes.h>
> +#include <asm/firmware.h>
>  
>  #ifdef CONFIG_PPC_BOOK3E
>  int default_machine_kexec_prepare(struct kimage *image)
> @@ -55,9 +56,6 @@ int default_machine_kexec_prepare(struct kimage *image)
>  	const unsigned long *basep;
>  	const unsigned int *sizep;
>  
> -	if (!mmu_hash_ops.hpte_clear_all)
> -		return -ENOENT;
> -
>  	/*
>  	 * Since we use the kernel fault handlers and paging code to
>  	 * handle the virtual mode, we must make sure no destination
> @@ -379,13 +377,8 @@ void default_machine_kexec(struct kimage *image)
>  	 * a toc is easier in C, so pass in what we can.
>  	 */
>  	kexec_sequence(&kexec_stack, image->start, image,
> -			page_address(image->control_code_page),
> -#ifdef CONFIG_PPC_STD_MMU
> -			mmu_hash_ops.hpte_clear_all
> -#else
> -			NULL
> -#endif
> -	);
> +		       page_address(image->control_code_page),
> +		       mmu_cleanup_all);
>  	/* NOTREACHED */
>  }
>  
> diff --git a/arch/powerpc/mm/pgtable-book3s64.c b/arch/powerpc/mm/pgtable-book3s64.c
> index 7328886bca4c..f4f437cbabf1 100644
> --- a/arch/powerpc/mm/pgtable-book3s64.c
> +++ b/arch/powerpc/mm/pgtable-book3s64.c
> @@ -116,3 +116,12 @@ void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
>  	return;
>  }
>  #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
> +
> +/* For use by kexec */
> +void mmu_cleanup_all(void)
> +{
> +	if (radix_enabled())
> +		radix__mmu_cleanup_all();
> +	else if (mmu_hash_ops.hpte_clear_all)
> +		mmu_hash_ops.hpte_clear_all();
> +}
> diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
> index 035a1a2b1002..790a1e1bb0e5 100644
> --- a/arch/powerpc/mm/pgtable-radix.c
> +++ b/arch/powerpc/mm/pgtable-radix.c
> @@ -395,6 +395,18 @@ void radix__early_init_mmu_secondary(void)
>  	}
>  }
>  
> +void radix__mmu_cleanup_all(void)
> +{
> +	unsigned long lpcr;
> +
> +	if (!firmware_has_feature(FW_FEATURE_LPAR)) {
> +		lpcr = mfspr(SPRN_LPCR);
> +		mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);

I suspect the new kernel will do the right thing w.r.t LPCR


> +		mtspr(SPRN_PTCR, 0);

Do we care to free the partition_tb at this point? Probably not since
we are going to reboot soon, but I think it'll help with anyone (read
NMMU) holding stray references.

> +		radix__flush_tlb_all();
> +	}
> +}
> +
>  void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
>  				phys_addr_t first_memblock_size)
>  {
> 


Acked-by: Balbir Singh <bsingharora@gmail.com>

[PATCH V2 4/5] powerpc/64/kexec: Copy image with MMU off when possible

[Aneesh Kumar K.V]

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Currently we turn the MMU off after copying the image, and we make
sure there is no overlap between the hash table and the target pages
in that case.

That doesn't work for Radix however. In that case, the page tables
are scattered and we can't really enforce that the target of the
image isn't overlapping one of them.

So instead, let's turn the MMU off before copying the image in radix
mode. Thankfully, in radix mode, even under a hypervisor, we know we
don't have the same kind of RMA limitations that hash mode has.

While at it, also turn the MMU off early when using hash in non-LPAR
mode, that way we can get rid of the collision check completely.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/kernel/machine_kexec_64.c | 47 +++++++++++++++-------------------
 arch/powerpc/kernel/misc_64.S          | 18 ++++++++++---
 2 files changed, 34 insertions(+), 31 deletions(-)

diff --git a/arch/powerpc/kernel/machine_kexec_64.c b/arch/powerpc/kernel/machine_kexec_64.c
index 8cbd870dd557..98058d13d115 100644
--- a/arch/powerpc/kernel/machine_kexec_64.c
+++ b/arch/powerpc/kernel/machine_kexec_64.c
@@ -65,31 +65,6 @@ int default_machine_kexec_prepare(struct kimage *image)
 		if (image->segment[i].mem < __pa(_end))
 			return -ETXTBSY;
 
-	/*
-	 * For non-LPAR, we absolutely can not overwrite the mmu hash
-	 * table, since we are still using the bolted entries in it to
-	 * do the copy.  Check that here.
-	 *
-	 * It is safe if the end is below the start of the blocked
-	 * region (end <= low), or if the beginning is after the
-	 * end of the blocked region (begin >= high).  Use the
-	 * boolean identity !(a || b)  === (!a && !b).
-	 */
-#ifdef CONFIG_PPC_STD_MMU_64
-	if (htab_address) {
-		low = __pa(htab_address);
-		high = low + htab_size_bytes;
-
-		for (i = 0; i < image->nr_segments; i++) {
-			begin = image->segment[i].mem;
-			end = begin + image->segment[i].memsz;
-
-			if ((begin < high) && (end > low))
-				return -ETXTBSY;
-		}
-	}
-#endif /* CONFIG_PPC_STD_MMU_64 */
-
 	/* We also should not overwrite the tce tables */
 	for_each_node_by_type(node, "pci") {
 		basep = of_get_property(node, "linux,tce-base", NULL);
@@ -330,11 +305,14 @@ struct paca_struct kexec_paca;
 /* Our assembly helper, in misc_64.S */
 extern void kexec_sequence(void *newstack, unsigned long start,
 			   void *image, void *control,
-			   void (*clear_all)(void)) __noreturn;
+			   void (*clear_all)(void),
+			   bool copy_with_mmu_off) __noreturn;
 
 /* too late to fail here */
 void default_machine_kexec(struct kimage *image)
 {
+	bool copy_with_mmu_off;
+
 	/* prepare control code if any */
 
 	/*
@@ -372,13 +350,28 @@ void default_machine_kexec(struct kimage *image)
 	/* XXX: If anyone does 'dynamic lppacas' this will also need to be
 	 * switched to a static version!
 	 */
+	/* On Book3S, the copy must happen with the MMU off if we are either
+	 * using Radix page tables or we are not in an LPAR since we can
+	 * overwrite the page tables while copying.
+	 *
+	 * In an LPAR, we keep the MMU on otherwise we can't access beyond
+	 * the RMA. On BookE there is no real MMU off mode, so we have to
+	 * keep it enabled as well (but then we have bolted TLB entries).
+	 */
+#ifdef CONFIG_PPC_BOOK3E
+	copy_with_mmu_off = false;
+#else
+	copy_with_mmu_off = radix_enabled() ||
+		!(firmware_has_feature(FW_FEATURE_LPAR) ||
+		  firmware_has_feature(FW_FEATURE_PS3_LV1));
+#endif
 
 	/* Some things are best done in assembly.  Finding globals with
 	 * a toc is easier in C, so pass in what we can.
 	 */
 	kexec_sequence(&kexec_stack, image->start, image,
 		       page_address(image->control_code_page),
-		       mmu_cleanup_all);
+		       mmu_cleanup_all, copy_with_mmu_off);
 	/* NOTREACHED */
 }
 
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index 7902f4b12d3f..23b746228d20 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -591,7 +591,8 @@ real_mode:	/* assume normal blr return */
 #endif
 
 /*
- * kexec_sequence(newstack, start, image, control, clear_all())
+ * kexec_sequence(newstack, start, image, control, clear_all(),
+	          copy_with_mmu_off)
  *
  * does the grungy work with stack switching and real mode switches
  * also does simple calls to other code
@@ -627,7 +628,7 @@ _GLOBAL(kexec_sequence)
 	mr	r29,r5			/* image (virt) */
 	mr	r28,r6			/* control, unused */
 	mr	r27,r7			/* clear_all() fn desc */
-	mr	r26,r8			/* spare */
+	mr	r26,r8			/* copy_with_mmu_off */
 	lhz	r25,PACAHWCPUID(r13)	/* get our phys cpu from paca */
 
 	/* disable interrupts, we are overwriting kernel data next */
@@ -639,15 +640,24 @@ _GLOBAL(kexec_sequence)
 	mtmsrd	r3,1
 #endif
 
+	/* We need to turn the MMU off unless we are in hash mode
+	 * under a hypervisor
+	 */
+	cmpdi	r26,0
+	beq	1f
+	bl	real_mode
+1:
 	/* copy dest pages, flush whole dest image */
 	mr	r3,r29
 	bl	kexec_copy_flush	/* (image) */
 
-	/* turn off mmu */
+	/* turn off mmu now if not done earlier */
+	cmpdi	r26,0
+	bne	1f
 	bl	real_mode
 
 	/* copy  0x100 bytes starting at start to 0 */
-	li	r3,0
+1:	li	r3,0
 	mr	r4,r30		/* start, aka phys mem offset */
 	li	r5,0x100
 	li	r6,0
-- 
2.7.4

Re: [PATCH V2 4/5] powerpc/64/kexec: Copy image with MMU off when possible

[Balbir Singh]

On 19/08/16 18:52, Aneesh Kumar K.V wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> 
> Currently we turn the MMU off after copying the image, and we make
> sure there is no overlap between the hash table and the target pages
> in that case.
> 
> That doesn't work for Radix however. In that case, the page tables
> are scattered and we can't really enforce that the target of the
> image isn't overlapping one of them.
> 
> So instead, let's turn the MMU off before copying the image in radix
> mode. Thankfully, in radix mode, even under a hypervisor, we know we
> don't have the same kind of RMA limitations that hash mode has.
> 
> While at it, also turn the MMU off early when using hash in non-LPAR
> mode, that way we can get rid of the collision check completely.
> 
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>

Looks good

Acked-by: Balbir Singh <bsingharora@gmail.com>

[PATCH V2 5/5] powerpc/64/kexec: Remove BookE special default_machine_kexec_prepare()

[Aneesh Kumar K.V]

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

The only difference is now the TCE table check which doesn't need
to be ifdef'ed out, it will basically do nothing on BookE (it is
only useful for ancient IBM machines).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/kernel/machine_kexec_64.c | 16 ----------------
 1 file changed, 16 deletions(-)

diff --git a/arch/powerpc/kernel/machine_kexec_64.c b/arch/powerpc/kernel/machine_kexec_64.c
index 98058d13d115..ae4dafa2a9bd 100644
--- a/arch/powerpc/kernel/machine_kexec_64.c
+++ b/arch/powerpc/kernel/machine_kexec_64.c
@@ -32,21 +32,6 @@
 #include <asm/asm-prototypes.h>
 #include <asm/firmware.h>
 
-#ifdef CONFIG_PPC_BOOK3E
-int default_machine_kexec_prepare(struct kimage *image)
-{
-	int i;
-	/*
-	 * Since we use the kernel fault handlers and paging code to
-	 * handle the virtual mode, we must make sure no destination
-	 * overlaps kernel static data or bss.
-	 */
-	for (i = 0; i < image->nr_segments; i++)
-		if (image->segment[i].mem < __pa(_end))
-			return -ETXTBSY;
-	return 0;
-}
-#else
 int default_machine_kexec_prepare(struct kimage *image)
 {
 	int i;
@@ -86,7 +71,6 @@ int default_machine_kexec_prepare(struct kimage *image)
 
 	return 0;
 }
-#endif /* !CONFIG_PPC_BOOK3E */
 
 static void copy_segments(unsigned long ind)
 {
-- 
2.7.4