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From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 7/8] drm/i915/gen9: fix the watermark res_blocks value
Date: Tue,  6 Sep 2016 21:52:18 -0300	[thread overview]
Message-ID: <1473209539-6689-8-git-send-email-paulo.r.zanoni@intel.com> (raw)
In-Reply-To: <1473209539-6689-1-git-send-email-paulo.r.zanoni@intel.com>

We forgot the "res_blocks += y_tile_minimum" that's described on step
V of our documentation.

Again, this should only affect the Y tiling cases.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 70dc0c4..381c482 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3556,7 +3556,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 	uint8_t cpp;
 	uint32_t width = 0, height = 0;
 	uint32_t plane_pixel_rate;
-	uint32_t y_min_scanlines;
+	uint32_t y_tile_minimum, y_min_scanlines;
 
 	if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
 		*enabled = false;
@@ -3613,10 +3613,10 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 				 latency,
 				 plane_blocks_per_line);
 
+	y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
+
 	if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
 	    fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
-		uint32_t y_tile_minimum = plane_blocks_per_line *
-					  y_min_scanlines;
 		selected_result = max(method2, y_tile_minimum);
 	} else {
 		if ((ddb_allocation / plane_blocks_per_line) >= 1)
@@ -3630,10 +3630,12 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 
 	if (level >= 1 && level <= 7) {
 		if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
-		    fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
+		    fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
+			res_blocks += y_tile_minimum;
 			res_lines += y_min_scanlines;
-		else
+		} else {
 			res_blocks++;
+		}
 	}
 
 	if (res_blocks >= ddb_allocation || res_lines > 31) {
-- 
2.7.4

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  parent reply	other threads:[~2016-09-07  0:52 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-07  0:52 [PATCH 0/8] SKL/KBL watermark fixes Paulo Zanoni
2016-09-07  0:52 ` [PATCH 1/8] drm/i915: SAGV is not SKL-only, so rename a few things Paulo Zanoni
2016-09-07 16:05   ` Lyude
2016-09-09 20:16     ` Zanoni, Paulo R
2016-09-07  0:52 ` [PATCH 2/8] drm/i915: introduce intel_has_sagv() Paulo Zanoni
2016-09-07 16:12   ` Lyude
2016-09-08  8:59     ` Jani Nikula
2016-09-08 14:43       ` Lyude Paul
2016-09-09  8:06         ` Jani Nikula
2016-09-09 19:51           ` Zanoni, Paulo R
2016-09-10 10:49             ` Ville Syrjälä
2016-09-12  9:48               ` Jani Nikula
2016-09-07  0:52 ` [PATCH 3/8] drm/i915/kbl: KBL also needs to run the SAGV code Paulo Zanoni
2016-09-07 16:11   ` Ville Syrjälä
2016-09-07 16:17     ` Lyude
2016-09-13 19:34       ` Zanoni, Paulo R
2016-09-14  9:59         ` Jani Nikula
2016-09-14 13:32           ` Zanoni, Paulo R
2016-09-15  7:15             ` Jani Nikula
2016-09-07  0:52 ` [PATCH 4/8] drm/i915/gen9: fix the WaWmMemoryReadLatency implementation Paulo Zanoni
2016-09-13 12:28   ` Maarten Lankhorst
2016-09-07  0:52 ` [PATCH 5/8] drm/i915/gen9: minimum scanlines for Y tile is not always 4 Paulo Zanoni
2016-09-07 23:03   ` Lyude
2016-09-13 20:22     ` Zanoni, Paulo R
2016-09-07  0:52 ` [PATCH 6/8] drm/i915/gen9: fix plane_blocks_per_line on watermarks calculations Paulo Zanoni
2016-09-07  0:52 ` Paulo Zanoni [this message]
2016-09-07  0:52 ` [PATCH 8/8] drm/i915/gen9: implement missing case for SKL watermarks calculation Paulo Zanoni
2016-09-07  1:24 ` ✗ Fi.CI.BAT: warning for SKL/KBL watermark fixes Patchwork
2016-09-07 23:54 ` [PATCH 0/8] " Lyude

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