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From: Gong Qianyu <Qianyu.Gong@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [Patch v6 3/9] armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency
Date: Wed, 7 Sep 2016 17:56:08 +0800	[thread overview]
Message-ID: <1473242174-5807-4-git-send-email-Qianyu.Gong@nxp.com> (raw)
In-Reply-To: <1473242174-5807-1-git-send-email-Qianyu.Gong@nxp.com>

From: Mingkai Hu <mingkai.hu@nxp.com>

According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
---
v3-v6:
 - No change.
v2:
 - Revise commit message.

 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5af6b73..6451a36 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -179,6 +179,21 @@ ENTRY(lowlevel_init)
 	isb
 	dsb	sy
 #endif
+
+#ifdef CONFIG_LS1046A
+	/* Initialize the L2 RAM latency */
+	mrs   x1, S3_1_c11_c0_2
+	mov   x0, #0x1C7
+	/* Clear L2 Tag RAM latency and L2 Data RAM latency */
+	bic   x1, x1, x0
+	/* Set L2 data ram latency bits [2:0] */
+	orr   x1, x1, #0x2
+	/* set L2 tag ram latency bits [8:6] */
+	orr   x1,  x1, #0x80
+	msr   S3_1_c11_c0_2, x1
+	isb
+#endif
+
 	mov	lr, x29			/* Restore LR */
 	ret
 ENDPROC(lowlevel_init)
-- 
2.1.0.27.g96db324

  parent reply	other threads:[~2016-09-07  9:56 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-07  9:56 [U-Boot] [Patch v6 0/9] Add LS1046ARDB&QDS board support Gong Qianyu
2016-09-07  9:56 ` [U-Boot] [Patch v6 1/9] ddr: fsl: fix a compile issue Gong Qianyu
2016-09-07  9:56 ` [U-Boot] [Patch v6 2/9] Export memset for standalone AQ FW load apps Gong Qianyu
2016-09-07  9:56 ` Gong Qianyu [this message]
2016-09-07  9:56 ` [U-Boot] [Patch v6 4/9] armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for standalone app Gong Qianyu
2016-09-07  9:56 ` [U-Boot] [Patch v6 5/9] armv8: fsl-layerscape: spl: remove BSS clearing and board_init_r Gong Qianyu
2016-09-08 17:06   ` york sun
2016-09-09  6:12     ` Q.Y. Gong
2016-09-13 20:45       ` york sun
2016-09-14  7:32         ` Q.Y. Gong
2016-09-14 15:55           ` york sun
2016-09-07  9:56 ` [U-Boot] [Patch v6 6/9] armv8: ls1046a: Enable DDR erratum for ls1046a Gong Qianyu
2016-09-07  9:56 ` [U-Boot] [Patch v6 7/9] armv8: ls1046a: disable SATA ECC in DCSR Gong Qianyu
2016-09-07  9:56 ` [U-Boot] [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board support Gong Qianyu
2016-09-08 17:21   ` york sun
2016-09-09  0:07     ` Prabhakar Kushwaha
2016-09-09 16:20       ` york sun
2016-09-16 20:14   ` york sun
2016-09-21  3:21     ` Q.Y. Gong
2016-09-21  7:46     ` Mingkai Hu
2016-09-21 15:31       ` york sun
2016-09-07  9:56 ` [U-Boot] [Patch v6 9/9] armv8: ls1046aqds: Add LS1046AQDS " Gong Qianyu
2016-09-20 18:06 ` [U-Boot] [Patch v6 0/9] Add LS1046ARDB&QDS " york sun

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