From: catalin.marinas@arm.com (Catalin Marinas) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 6/7] arm64: xen: Enable user access before a privcmd hvc call Date: Tue, 13 Sep 2016 18:46:36 +0100 [thread overview] Message-ID: <1473788797-10879-7-git-send-email-catalin.marinas@arm.com> (raw) In-Reply-To: <1473788797-10879-1-git-send-email-catalin.marinas@arm.com> Privcmd calls are issued by the userspace. The kernel needs to enable access to TTBR0_EL1 as the hypervisor would issue stage 1 translations to user memory via AT instructions. Since AT instructions are not affected by the PAN bit (ARMv8.1), we only need the explicit uaccess_enable/disable if the TTBR0 PAN option is enabled. Reviewed-by: Julien Grall <julien.grall@arm.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org> Cc: Will Deacon <will.deacon@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Kees Cook <keescook@chromium.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> --- arch/arm64/xen/hypercall.S | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/xen/hypercall.S b/arch/arm64/xen/hypercall.S index 329c8027b0a9..a23b2e8f2647 100644 --- a/arch/arm64/xen/hypercall.S +++ b/arch/arm64/xen/hypercall.S @@ -49,6 +49,7 @@ #include <linux/linkage.h> #include <asm/assembler.h> +#include <asm/uaccess.h> #include <xen/interface/xen.h> @@ -91,6 +92,24 @@ ENTRY(privcmd_call) mov x2, x3 mov x3, x4 mov x4, x5 +#ifdef CONFIG_ARM64_SW_TTBR0_PAN + /* + * Privcmd calls are issued by the userspace. The kernel needs to + * enable access to TTBR0_EL1 as the hypervisor would issue stage 1 + * translations to user memory via AT instructions. Since AT + * instructions are not affected by the PAN bit (ARMv8.1), we only + * need the explicit uaccess_enable/disable if the TTBR0 PAN emulation + * is enabled (it implies that hardware UAO and PAN disabled). + */ + uaccess_enable_not_uao x6, x7 +#endif hvc XEN_IMM + +#ifdef CONFIG_ARM64_SW_TTBR0_PAN + /* + * Disable userspace access from kernel once the hyp call completed. + */ + uaccess_disable_not_uao x6 +#endif ret ENDPROC(privcmd_call);
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: Will Deacon <will.deacon@arm.com>, James Morse <james.morse@arm.com>, Kees Cook <keescook@chromium.org>, Mark Rutland <mark.rutland@arm.com>, Ard Biesheuvel <ard.biesheuvel@linaro.org>, AKASHI Takahiro <takahiro.akashi@linaro.org>, kernel-hardening@lists.openwall.com Subject: [kernel-hardening] [PATCH v3 6/7] arm64: xen: Enable user access before a privcmd hvc call Date: Tue, 13 Sep 2016 18:46:36 +0100 [thread overview] Message-ID: <1473788797-10879-7-git-send-email-catalin.marinas@arm.com> (raw) In-Reply-To: <1473788797-10879-1-git-send-email-catalin.marinas@arm.com> Privcmd calls are issued by the userspace. The kernel needs to enable access to TTBR0_EL1 as the hypervisor would issue stage 1 translations to user memory via AT instructions. Since AT instructions are not affected by the PAN bit (ARMv8.1), we only need the explicit uaccess_enable/disable if the TTBR0 PAN option is enabled. Reviewed-by: Julien Grall <julien.grall@arm.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org> Cc: Will Deacon <will.deacon@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Kees Cook <keescook@chromium.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> --- arch/arm64/xen/hypercall.S | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/xen/hypercall.S b/arch/arm64/xen/hypercall.S index 329c8027b0a9..a23b2e8f2647 100644 --- a/arch/arm64/xen/hypercall.S +++ b/arch/arm64/xen/hypercall.S @@ -49,6 +49,7 @@ #include <linux/linkage.h> #include <asm/assembler.h> +#include <asm/uaccess.h> #include <xen/interface/xen.h> @@ -91,6 +92,24 @@ ENTRY(privcmd_call) mov x2, x3 mov x3, x4 mov x4, x5 +#ifdef CONFIG_ARM64_SW_TTBR0_PAN + /* + * Privcmd calls are issued by the userspace. The kernel needs to + * enable access to TTBR0_EL1 as the hypervisor would issue stage 1 + * translations to user memory via AT instructions. Since AT + * instructions are not affected by the PAN bit (ARMv8.1), we only + * need the explicit uaccess_enable/disable if the TTBR0 PAN emulation + * is enabled (it implies that hardware UAO and PAN disabled). + */ + uaccess_enable_not_uao x6, x7 +#endif hvc XEN_IMM + +#ifdef CONFIG_ARM64_SW_TTBR0_PAN + /* + * Disable userspace access from kernel once the hyp call completed. + */ + uaccess_disable_not_uao x6 +#endif ret ENDPROC(privcmd_call);
next prev parent reply other threads:[~2016-09-13 17:46 UTC|newest] Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-09-13 17:46 [PATCH v3 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Catalin Marinas 2016-09-13 17:46 ` [kernel-hardening] " Catalin Marinas 2016-09-13 17:46 ` [PATCH v3 1/7] arm64: Factor out PAN enabling/disabling into separate uaccess_* macros Catalin Marinas 2016-09-13 17:46 ` [kernel-hardening] " Catalin Marinas 2016-09-15 15:10 ` Mark Rutland 2016-09-15 15:10 ` [kernel-hardening] " Mark Rutland 2016-09-13 17:46 ` [PATCH v3 2/7] arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro Catalin Marinas 2016-09-13 17:46 ` [kernel-hardening] " Catalin Marinas 2016-09-15 15:19 ` Mark Rutland 2016-09-15 15:19 ` [kernel-hardening] " Mark Rutland 2016-09-13 17:46 ` [PATCH v3 3/7] arm64: Introduce uaccess_{disable, enable} functionality based on TTBR0_EL1 Catalin Marinas 2016-09-13 17:46 ` [kernel-hardening] [PATCH v3 3/7] arm64: Introduce uaccess_{disable,enable} " Catalin Marinas 2016-09-13 20:45 ` Kees Cook 2016-09-13 20:45 ` [kernel-hardening] " Kees Cook 2016-09-14 8:52 ` Mark Rutland 2016-09-14 8:52 ` [kernel-hardening] " Mark Rutland 2016-09-14 16:27 ` Kees Cook 2016-09-14 16:27 ` Kees Cook 2016-09-13 17:46 ` [PATCH v3 4/7] arm64: Disable TTBR0_EL1 during normal kernel execution Catalin Marinas 2016-09-13 17:46 ` [kernel-hardening] " Catalin Marinas 2016-09-14 16:45 ` Will Deacon 2016-09-14 16:45 ` [kernel-hardening] " Will Deacon 2016-09-13 17:46 ` [PATCH v3 5/7] arm64: Handle faults caused by inadvertent user access with PAN enabled Catalin Marinas 2016-09-13 17:46 ` [kernel-hardening] " Catalin Marinas 2016-09-16 11:33 ` Mark Rutland 2016-09-16 11:33 ` [kernel-hardening] " Mark Rutland 2016-09-16 15:55 ` Catalin Marinas 2016-09-16 15:55 ` [kernel-hardening] " Catalin Marinas 2016-09-13 17:46 ` Catalin Marinas [this message] 2016-09-13 17:46 ` [kernel-hardening] [PATCH v3 6/7] arm64: xen: Enable user access before a privcmd hvc call Catalin Marinas 2016-09-13 17:46 ` [PATCH v3 7/7] arm64: Enable CONFIG_ARM64_SW_TTBR0_PAN Catalin Marinas 2016-09-13 17:46 ` [kernel-hardening] " Catalin Marinas 2016-09-14 10:13 ` [PATCH v3 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Ard Biesheuvel 2016-09-14 10:13 ` [kernel-hardening] " Ard Biesheuvel 2016-09-14 10:27 ` Mark Rutland 2016-09-14 10:27 ` [kernel-hardening] " Mark Rutland 2016-09-14 10:30 ` Ard Biesheuvel 2016-09-14 10:30 ` [kernel-hardening] " Ard Biesheuvel 2016-09-14 10:36 ` Mark Rutland 2016-09-14 10:36 ` [kernel-hardening] " Mark Rutland 2016-09-14 10:48 ` Mark Rutland 2016-09-14 10:48 ` [kernel-hardening] " Mark Rutland 2016-09-14 20:54 ` [kernel-hardening] " David Brown 2016-09-14 20:54 ` David Brown 2016-09-15 9:52 ` Catalin Marinas 2016-09-15 9:52 ` Catalin Marinas 2016-09-15 16:20 ` Mark Rutland 2016-09-15 16:20 ` [kernel-hardening] " Mark Rutland 2016-09-15 16:41 ` Mark Rutland 2016-09-15 16:41 ` [kernel-hardening] " Mark Rutland 2016-09-29 22:44 ` Sami Tolvanen 2016-09-29 22:44 ` Sami Tolvanen 2016-09-30 18:42 ` Kees Cook 2016-09-30 18:42 ` Kees Cook 2016-10-27 14:54 ` Catalin Marinas 2016-10-27 14:54 ` Catalin Marinas 2016-10-27 21:23 ` Kees Cook 2016-10-27 21:23 ` Kees Cook 2016-10-14 21:44 ` Kees Cook 2016-10-14 21:44 ` [kernel-hardening] " Kees Cook 2016-10-15 14:35 ` Catalin Marinas 2016-10-15 14:35 ` [kernel-hardening] " Catalin Marinas 2016-10-16 2:04 ` Kees Cook 2016-10-16 2:04 ` [kernel-hardening] " Kees Cook
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