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From: Masahiro Yamada <yamada.masahiro@socionext.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 02/15] pinctrl: uniphier: add UniPhier sLD3 pinctrl driver
Date: Sat, 17 Sep 2016 03:32:59 +0900	[thread overview]
Message-ID: <1474050792-23218-3-git-send-email-yamada.masahiro@socionext.com> (raw)
In-Reply-To: <1474050792-23218-1-git-send-email-yamada.masahiro@socionext.com>

Add pin-mux support for UniPhier sLD3 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 drivers/pinctrl/uniphier/Kconfig                 |   6 ++
 drivers/pinctrl/uniphier/Makefile                |   1 +
 drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c | 128 +++++++++++++++++++++++
 3 files changed, 135 insertions(+)
 create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c

diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index 7febea2..689e576 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -3,6 +3,12 @@ if ARCH_UNIPHIER
 config PINCTRL_UNIPHIER
 	bool
 
+config PINCTRL_UNIPHIER_SLD3
+	bool "UniPhier PH1-sLD3 SoC pinctrl driver"
+	depends on ARCH_UNIPHIER_SLD3
+	default y
+	select PINCTRL_UNIPHIER
+
 config PINCTRL_UNIPHIER_LD4
 	bool "UniPhier PH1-LD4 SoC pinctrl driver"
 	depends on ARCH_UNIPHIER_LD4
diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile
index 4de251b..fd003ad 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -4,6 +4,7 @@
 
 obj-y					+= pinctrl-uniphier-core.o
 
+obj-$(CONFIG_PINCTRL_UNIPHIER_SLD3)	+= pinctrl-uniphier-sld3.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_LD4)	+= pinctrl-uniphier-ld4.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4)	+= pinctrl-uniphier-pro4.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8)	+= pinctrl-uniphier-sld8.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c
new file mode 100644
index 0000000..d3a507e
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const unsigned emmc_pins[] = {55, 56, 60};
+static const int emmc_muxvals[] = {1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {57};
+static const int emmc_dat8_muxvals[] = {1};
+static const unsigned ether_mii_pins[] = {35, 107, 108, 109, 110, 111, 112,
+					  113};
+static const int ether_mii_muxvals[] = {1, 2, 2, 2, 2, 2, 2, 2};
+static const unsigned ether_rmii_pins[] = {35};
+static const int ether_rmii_muxvals[] = {1};
+static const unsigned i2c0_pins[] = {36};
+static const int i2c0_muxvals[] = {0};
+static const unsigned nand_pins[] = {38, 39, 40, 58, 59};
+static const int nand_muxvals[] = {1, 1, 1, 1, 1};
+static const unsigned nand_cs1_pins[] = {41};
+static const int nand_cs1_muxvals[] = {1};
+static const unsigned sd_pins[] = {42, 43, 44, 45};
+static const int sd_muxvals[] = {1, 1, 1, 1};
+static const unsigned system_bus_pins[] = {46, 50, 51, 53, 54, 73, 74, 75, 76,
+					   77, 78, 79, 80, 88, 89, 91, 92, 99};
+static const int system_bus_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+					 1, 1, 1, 1, 1};
+static const unsigned system_bus_cs0_pins[] = {93};
+static const int system_bus_cs0_muxvals[] = {1};
+static const unsigned system_bus_cs1_pins[] = {94};
+static const int system_bus_cs1_muxvals[] = {1};
+static const unsigned system_bus_cs2_pins[] = {95};
+static const int system_bus_cs2_muxvals[] = {1};
+static const unsigned system_bus_cs3_pins[] = {96};
+static const int system_bus_cs3_muxvals[] = {1};
+static const unsigned system_bus_cs4_pins[] = {81};
+static const int system_bus_cs4_muxvals[] = {1};
+static const unsigned system_bus_cs5_pins[] = {82};
+static const int system_bus_cs5_muxvals[] = {1};
+static const unsigned uart0_pins[] = {63, 64};
+static const int uart0_muxvals[] = {0, 1};
+static const unsigned uart1_pins[] = {65, 66};
+static const int uart1_muxvals[] = {0, 1};
+static const unsigned uart2_pins[] = {96, 102};
+static const int uart2_muxvals[] = {2, 2};
+static const unsigned usb0_pins[] = {13, 14};
+static const int usb0_muxvals[] = {0, 1};
+static const unsigned usb1_pins[] = {15, 16};
+static const int usb1_muxvals[] = {0, 1};
+static const unsigned usb2_pins[] = {17, 18};
+static const int usb2_muxvals[] = {0, 1};
+static const unsigned usb3_pins[] = {19, 20};
+static const int usb3_muxvals[] = {0, 1};
+
+static const struct uniphier_pinctrl_group uniphier_sld3_groups[] = {
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_mii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
+	UNIPHIER_PINCTRL_GROUP(i2c0),
+	UNIPHIER_PINCTRL_GROUP(nand),
+	UNIPHIER_PINCTRL_GROUP(nand_cs1),
+	UNIPHIER_PINCTRL_GROUP(sd),
+	UNIPHIER_PINCTRL_GROUP(system_bus),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+	UNIPHIER_PINCTRL_GROUP(usb0),
+	UNIPHIER_PINCTRL_GROUP(usb1),
+	UNIPHIER_PINCTRL_GROUP(usb2),
+	UNIPHIER_PINCTRL_GROUP(usb3)
+};
+
+static const char * const uniphier_sld3_functions[] = {
+	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_mii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION(system_bus),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
+	UNIPHIER_PINMUX_FUNCTION(usb3),
+};
+
+static struct uniphier_pinctrl_socdata uniphier_sld3_pinctrl_socdata = {
+	.groups = uniphier_sld3_groups,
+	.groups_count = ARRAY_SIZE(uniphier_sld3_groups),
+	.functions = uniphier_sld3_functions,
+	.functions_count = ARRAY_SIZE(uniphier_sld3_functions),
+	.caps = UNIPHIER_PINCTRL_CAPS_MUX_4BIT,
+};
+
+static int uniphier_sld3_pinctrl_probe(struct udevice *dev)
+{
+	return uniphier_pinctrl_probe(dev, &uniphier_sld3_pinctrl_socdata);
+}
+
+static const struct udevice_id uniphier_sld3_pinctrl_match[] = {
+	{ .compatible = "socionext,uniphier-sld3-pinctrl" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_sld3_pinctrl) = {
+	.name = "uniphier-sld3-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(uniphier_sld3_pinctrl_match),
+	.probe = uniphier_sld3_pinctrl_probe,
+	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+	.ops = &uniphier_pinctrl_ops,
+};
-- 
1.9.1

  parent reply	other threads:[~2016-09-16 18:32 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-16 18:32 [U-Boot] [PATCH 00/15] ARM: uniphier: more updates for UniPhier SoC family for v2016.11-rc1 Masahiro Yamada
2016-09-16 18:32 ` [U-Boot] [PATCH 01/15] pinctrl: uniphier: support 4bit-width pin-mux register capability Masahiro Yamada
2016-09-16 18:32 ` Masahiro Yamada [this message]
2016-09-16 18:33 ` [U-Boot] [PATCH 03/15] ARM: dts: uniphier: add pinctrl device node and pinctrl properties Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 04/15] ARM: uniphier: select PINCTRL and SPL_PINCTRL Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 05/15] ARM: uniphier: remove redundant pin-muxing for EA24 pin of sLD3 SoC Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 06/15] ARM: uniphier: remove ad-hoc pin-mux code for sLD3 Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 07/15] ARM: uniphier: consolidate NAND pin-mux settings Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 08/15] ARM: dts: uniphier: include System Bus pin group node in SPL DT Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 09/15] ARM: uniphier: consolidate System Bus pin-mux settings for LD11/LD20 Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 10/15] ARM: uniphier: move XIRQ pin-mux settings of LD11/LD20 Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 11/15] ARM: uniphier: rename CONFIG_DPLL_SSC_RATE_1PER Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 12/15] ARM: uniphier: move PLL init code to U-Boot proper where possible Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 13/15] ARM: uniphier: collect clock/PLL init code into a single directory Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 14/15] ARM: uniphier: add PLL init code for LD20 SoC Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 15/15] ARM: uniphier: update DRAM " Masahiro Yamada
2016-09-18 15:22 ` [U-Boot] [PATCH 00/15] ARM: uniphier: more updates for UniPhier SoC family for v2016.11-rc1 Masahiro Yamada

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