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From: Masahiro Yamada <yamada.masahiro@socionext.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 03/15] ARM: dts: uniphier: add pinctrl device node and pinctrl properties
Date: Sat, 17 Sep 2016 03:33:00 +0900	[thread overview]
Message-ID: <1474050792-23218-4-git-send-email-yamada.masahiro@socionext.com> (raw)
In-Reply-To: <1474050792-23218-1-git-send-email-yamada.masahiro@socionext.com>

DT-side updates to make pinctrl on sLD3 SoC really available.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm/dts/uniphier-ph1-sld3-ref.dts |  8 ++++++++
 arch/arm/dts/uniphier-ph1-sld3.dtsi    | 35 ++++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
index 0863588..f3e76b3 100644
--- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
@@ -93,3 +93,11 @@
 &emmc {
        u-boot,dm-pre-reloc;
 };
+
+&pinctrl_uart0 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_emmc {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index 6a95541..d8c44b7 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -90,6 +90,8 @@
 			status = "disabled";
 			reg = <0x54006800 0x40>;
 			interrupts = <0 33 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart0>;
 			clocks = <&uart_clk>;
 			clock-frequency = <36864000>;
 		};
@@ -99,6 +101,8 @@
 			status = "disabled";
 			reg = <0x54006900 0x40>;
 			interrupts = <0 35 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart1>;
 			clocks = <&uart_clk>;
 			clock-frequency = <36864000>;
 		};
@@ -108,6 +112,8 @@
 			status = "disabled";
 			reg = <0x54006a00 0x40>;
 			interrupts = <0 37 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_uart2>;
 			clocks = <&uart_clk>;
 			clock-frequency = <36864000>;
 		};
@@ -231,6 +237,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <0 41 1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_i2c0>;
 			clocks = <&iobus_clk>;
 			clock-frequency = <100000>;
 		};
@@ -304,6 +312,9 @@
 			status = "disabled";
 			reg = <0x5a400000 0x200>;
 			interrupts = <0 78 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_emmc>;
+			pinctrl-1 = <&pinctrl_emmc_1v8>;
 			clocks = <&mio 1>;
 			bus-width = <8>;
 			non-removable;
@@ -314,6 +325,9 @@
 			status = "disabled";
 			reg = <0x5a500000 0x200>;
 			interrupts = <0 76 4>;
+			pinctrl-names = "default", "1.8v";
+			pinctrl-0 = <&pinctrl_sd>;
+			pinctrl-1 = <&pinctrl_sd_1v8>;
 			clocks = <&mio 0>;
 			bus-width = <4>;
 		};
@@ -323,6 +337,8 @@
 			status = "disabled";
 			reg = <0x5a800100 0x100>;
 			interrupts = <0 80 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
 			clocks = <&mio 3>, <&mio 6>;
 		};
 
@@ -331,6 +347,8 @@
 			status = "disabled";
 			reg = <0x5a810100 0x100>;
 			interrupts = <0 81 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>;
 			clocks = <&mio 4>, <&mio 6>;
 		};
 
@@ -339,6 +357,8 @@
 			status = "disabled";
 			reg = <0x5a820100 0x100>;
 			interrupts = <0 82 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb2>;
 			clocks = <&mio 5>, <&mio 6>;
 		};
 
@@ -347,9 +367,22 @@
 			status = "disabled";
 			reg = <0x5a830100 0x100>;
 			interrupts = <0 83 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb3>;
 			clocks = <&mio 7>, <&mio 6>;
 		};
 
+		soc-glue at 5f800000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+			u-boot,dm-pre-reloc;
+
+			pinctrl: pinctrl {
+				compatible = "socionext,uniphier-sld3-pinctrl";
+				u-boot,dm-pre-reloc;
+			};
+		};
+
 		aidet at f1830000 {
 			compatible = "simple-mfd", "syscon";
 			reg = <0xf1830000 0x200>;
@@ -370,3 +403,5 @@
 		};
 	};
 };
+
+/include/ "uniphier-pinctrl.dtsi"
-- 
1.9.1

  parent reply	other threads:[~2016-09-16 18:33 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-16 18:32 [U-Boot] [PATCH 00/15] ARM: uniphier: more updates for UniPhier SoC family for v2016.11-rc1 Masahiro Yamada
2016-09-16 18:32 ` [U-Boot] [PATCH 01/15] pinctrl: uniphier: support 4bit-width pin-mux register capability Masahiro Yamada
2016-09-16 18:32 ` [U-Boot] [PATCH 02/15] pinctrl: uniphier: add UniPhier sLD3 pinctrl driver Masahiro Yamada
2016-09-16 18:33 ` Masahiro Yamada [this message]
2016-09-16 18:33 ` [U-Boot] [PATCH 04/15] ARM: uniphier: select PINCTRL and SPL_PINCTRL Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 05/15] ARM: uniphier: remove redundant pin-muxing for EA24 pin of sLD3 SoC Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 06/15] ARM: uniphier: remove ad-hoc pin-mux code for sLD3 Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 07/15] ARM: uniphier: consolidate NAND pin-mux settings Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 08/15] ARM: dts: uniphier: include System Bus pin group node in SPL DT Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 09/15] ARM: uniphier: consolidate System Bus pin-mux settings for LD11/LD20 Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 10/15] ARM: uniphier: move XIRQ pin-mux settings of LD11/LD20 Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 11/15] ARM: uniphier: rename CONFIG_DPLL_SSC_RATE_1PER Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 12/15] ARM: uniphier: move PLL init code to U-Boot proper where possible Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 13/15] ARM: uniphier: collect clock/PLL init code into a single directory Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 14/15] ARM: uniphier: add PLL init code for LD20 SoC Masahiro Yamada
2016-09-16 18:33 ` [U-Boot] [PATCH 15/15] ARM: uniphier: update DRAM " Masahiro Yamada
2016-09-18 15:22 ` [U-Boot] [PATCH 00/15] ARM: uniphier: more updates for UniPhier SoC family for v2016.11-rc1 Masahiro Yamada

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