From: Sean Wang <sean.wang@mediatek.com> To: <andrew@lunn.ch> Cc: <john@phrozen.org>, <davem@davemloft.net>, <nbd@openwrt.org>, <netdev@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, <keyhaede@gmail.com> Subject: Re: [PATCH net-next 3/3] net: ethernet: mediatek: add the dts property to set if TRGMII supported on GMAC0 Date: Wed, 21 Sep 2016 14:16:30 +0800 [thread overview] Message-ID: <1474438590-6855-1-git-send-email-sean.wang@mediatek.com> (raw) In-Reply-To: <1474358360-29901-4-git-send-email-sean.wang@mediatek.com> Date: Tue, 20 Sep 2016 21:37:58 +0200, Andrew Lunn <andrew@lunn.ch> wrote: >On Tue, Sep 20, 2016 at 03:59:20PM +0800, sean.wang@mediatek.com wrote: >> From: Sean Wang <sean.wang@mediatek.com> >> >> Add the dts property for the capability if TRGMII supported on GAMC0 >> >> Signed-off-by: Sean Wang <sean.wang@mediatek.com> >> --- >> Documentation/devicetree/bindings/net/mediatek-net.txt | 5 ++++- >> 1 file changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt >> index 6103e55..32f79d8 100644 >> --- a/Documentation/devicetree/bindings/net/mediatek-net.txt >> +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt >> @@ -31,7 +31,10 @@ Optional properties: >> Required properties: >> - compatible: Should be "mediatek,eth-mac" >> - reg: The number of the MAC >> -- phy-handle: see ethernet.txt file in the same directory. >> +- phy-handle: see ethernet.txt file in the same directory and >> + the additional phy-mode "tgrmii" is provided in order to connect >> + with the internal switch MT7530 which is only applicable when reg >> + is equal to 0. > >Humm. How is the switch connected? Is it on the MDIO bus? the switch is connected to MDIO bus >If it is on the mdio bus, the binding is going to look something like: > >eth: ethernet@1b100000 { > compatible = "mediatek,mt7623-eth"; > reg = <0 0x1b100000 0 0x20000>; > clocks = <&topckgen CLK_TOP_ETHIF_SEL>, > <ðsys CLK_ETHSYS_ESW>, > <ðsys CLK_ETHSYS_GP2>, > <ðsys CLK_ETHSYS_GP1>; > clock-names = "ethif", "esw", "gp2", "gp1"; > interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW > GIC_SPI 199 IRQ_TYPE_LEVEL_LOW > GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; > power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; > resets = <ðsys MT2701_ETHSYS_ETH_RST>; > reset-names = "eth"; > mediatek,ethsys = <ðsys>; > mediatek,pctl = <&syscfg_pctl_a>; > #address-cells = <1>; > #size-cells = <0>; > > gmac1: mac@0 { > compatible = "mediatek,eth-mac"; > reg = <0>; > }; > > gmac2: mac@1 { > compatible = "mediatek,eth-mac"; > reg = <1>; > }; > > mdio-bus { > reg = <1>; > #address-cells = <1>; > #size-cells = <0>; > > switch0: switch0@0 { > compatible = "marvell,mv88e6085"; > #address-cells = <1>; > #size-cells = <0>; > reg = <0>; > dsa,member = <0 0>; > > ports { > #address-cells = <1>; > #size-cells = <0>; > port@0 { > reg = <0>; > label = "lan0"; >... >... >In this case the switch is an MDIO device, not an PHY. It will not >have an phy-mode. It cannot have a phy mode, it is not a PHY. > >Or am i missing something here? > >Thanks > 1) The switch driver is not supported for DSA so far yet but DSA is good thing and I will try make it happen in the near future. And another question about DSA, that is if I use DSA for switch, how to know the relationship between MAC and DSA ? such like I could know relationship between MAC and PHY by phy-handle. The cause I ask is becasue I think it's good if the topology about MAC/PHYs/Switch is known just by dts files. 2) The phy-mode I mention is for fixed-link. For current MAC driver, it just uses fixed phy to adapt into the part of switch, so the device tree looks something like the below. ð { status = "okay"; gmac0: mac@0 { compatible = "mediatek,eth-mac"; reg = <0>; phy-mode = "trgmii"; fixed-link { speed = <1000>; full-duplex; pause; }; }; gmac1: mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; phy-handle = <&phy5>; };
WARNING: multiple messages have this Message-ID (diff)
From: Sean Wang <sean.wang@mediatek.com> To: andrew@lunn.ch Cc: john@phrozen.org, davem@davemloft.net, nbd@openwrt.org, netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, keyhaede@gmail.com Subject: Re: [PATCH net-next 3/3] net: ethernet: mediatek: add the dts property to set if TRGMII supported on GMAC0 Date: Wed, 21 Sep 2016 14:16:30 +0800 [thread overview] Message-ID: <1474438590-6855-1-git-send-email-sean.wang@mediatek.com> (raw) In-Reply-To: <1474358360-29901-4-git-send-email-sean.wang@mediatek.com> Date: Tue, 20 Sep 2016 21:37:58 +0200, Andrew Lunn <andrew@lunn.ch> wrote: >On Tue, Sep 20, 2016 at 03:59:20PM +0800, sean.wang@mediatek.com wrote: >> From: Sean Wang <sean.wang@mediatek.com> >> >> Add the dts property for the capability if TRGMII supported on GAMC0 >> >> Signed-off-by: Sean Wang <sean.wang@mediatek.com> >> --- >> Documentation/devicetree/bindings/net/mediatek-net.txt | 5 ++++- >> 1 file changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt >> index 6103e55..32f79d8 100644 >> --- a/Documentation/devicetree/bindings/net/mediatek-net.txt >> +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt >> @@ -31,7 +31,10 @@ Optional properties: >> Required properties: >> - compatible: Should be "mediatek,eth-mac" >> - reg: The number of the MAC >> -- phy-handle: see ethernet.txt file in the same directory. >> +- phy-handle: see ethernet.txt file in the same directory and >> + the additional phy-mode "tgrmii" is provided in order to connect >> + with the internal switch MT7530 which is only applicable when reg >> + is equal to 0. > >Humm. How is the switch connected? Is it on the MDIO bus? the switch is connected to MDIO bus >If it is on the mdio bus, the binding is going to look something like: > >eth: ethernet@1b100000 { > compatible = "mediatek,mt7623-eth"; > reg = <0 0x1b100000 0 0x20000>; > clocks = <&topckgen CLK_TOP_ETHIF_SEL>, > <ðsys CLK_ETHSYS_ESW>, > <ðsys CLK_ETHSYS_GP2>, > <ðsys CLK_ETHSYS_GP1>; > clock-names = "ethif", "esw", "gp2", "gp1"; > interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW > GIC_SPI 199 IRQ_TYPE_LEVEL_LOW > GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; > power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; > resets = <ðsys MT2701_ETHSYS_ETH_RST>; > reset-names = "eth"; > mediatek,ethsys = <ðsys>; > mediatek,pctl = <&syscfg_pctl_a>; > #address-cells = <1>; > #size-cells = <0>; > > gmac1: mac@0 { > compatible = "mediatek,eth-mac"; > reg = <0>; > }; > > gmac2: mac@1 { > compatible = "mediatek,eth-mac"; > reg = <1>; > }; > > mdio-bus { > reg = <1>; > #address-cells = <1>; > #size-cells = <0>; > > switch0: switch0@0 { > compatible = "marvell,mv88e6085"; > #address-cells = <1>; > #size-cells = <0>; > reg = <0>; > dsa,member = <0 0>; > > ports { > #address-cells = <1>; > #size-cells = <0>; > port@0 { > reg = <0>; > label = "lan0"; >... >... >In this case the switch is an MDIO device, not an PHY. It will not >have an phy-mode. It cannot have a phy mode, it is not a PHY. > >Or am i missing something here? > >Thanks > 1) The switch driver is not supported for DSA so far yet but DSA is good thing and I will try make it happen in the near future. And another question about DSA, that is if I use DSA for switch, how to know the relationship between MAC and DSA ? such like I could know relationship between MAC and PHY by phy-handle. The cause I ask is becasue I think it's good if the topology about MAC/PHYs/Switch is known just by dts files. 2) The phy-mode I mention is for fixed-link. For current MAC driver, it just uses fixed phy to adapt into the part of switch, so the device tree looks something like the below. ð { status = "okay"; gmac0: mac@0 { compatible = "mediatek,eth-mac"; reg = <0>; phy-mode = "trgmii"; fixed-link { speed = <1000>; full-duplex; pause; }; }; gmac1: mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; phy-handle = <&phy5>; };
next prev parent reply other threads:[~2016-09-21 6:16 UTC|newest] Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-09-20 7:59 [PATCH net-next 0/3] add support for RGMII on GMAC0 through TRGMII hardware module sean.wang 2016-09-20 7:59 ` sean.wang [not found] ` <1474358360-29901-1-git-send-email-sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> 2016-09-20 7:59 ` [PATCH net-next 1/3] net: ethernet: mediatek: add extension of phy-mode for TRGMII sean.wang-NuS5LvNUpcJWk0Htik3J/w 2016-09-20 7:59 ` sean.wang-NuS5LvNUpcJWk0Htik3J/w 2016-09-20 21:23 ` Florian Fainelli [not found] ` <064d43fb-2942-efd2-6dc7-09f47a256691-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2016-09-21 7:33 ` Sean Wang 2016-09-21 7:33 ` Sean Wang 2016-09-21 16:59 ` Florian Fainelli 2016-09-20 7:59 ` [PATCH net-next 2/3] net: ethernet: mediatek: add support for GMAC0 connecting with external PHY through TRGMII sean.wang 2016-09-20 7:59 ` sean.wang 2016-09-21 4:50 ` David Miller 2016-09-20 7:59 ` [PATCH net-next 3/3] net: ethernet: mediatek: add the dts property to set if TRGMII supported on GMAC0 sean.wang 2016-09-20 7:59 ` sean.wang 2016-09-20 19:37 ` Andrew Lunn 2016-09-21 6:16 ` Sean Wang [this message] 2016-09-21 6:16 ` Sean Wang 2016-09-21 14:17 ` Andrew Lunn 2016-09-21 15:37 ` Sean Wang 2016-09-21 15:37 ` Sean Wang
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