From: Paulo Zanoni <paulo.r.zanoni@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>, stable@vger.kernel.org Subject: [PATCH 2/9] drm/i915: introduce intel_has_sagv() Date: Thu, 22 Sep 2016 18:00:28 -0300 [thread overview] Message-ID: <1474578035-424-3-git-send-email-paulo.r.zanoni@intel.com> (raw) In-Reply-To: <1474578035-424-1-git-send-email-paulo.r.zanoni@intel.com> And use it to move knowledge about the SAGV-supporting platforms from the callers to the SAGV code. We'll add more platforms to intel_has_sagv(), so IMHO it makes more sense to move all this to a single function instead of patching all the callers every time we add SAGV support to a new platform. v2: Move I915_SAGV_NOT_CONTROLLED to the new function (Lyude). Cc: stable@vger.kernel.org Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 5 ++--- drivers/gpu/drm/i915/intel_pm.c | 22 ++++++++++++++++++---- 2 files changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 45d6183..8e464e0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -14367,7 +14367,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) * SKL workaround: bspec recommends we disable the SAGV when we * have more then one pipe enabled */ - if (IS_SKYLAKE(dev_priv) && !intel_can_enable_sagv(state)) + if (!intel_can_enable_sagv(state)) intel_disable_sagv(dev_priv); intel_modeset_verify_disabled(dev); @@ -14425,8 +14425,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); } - if (IS_SKYLAKE(dev_priv) && intel_state->modeset && - intel_can_enable_sagv(state)) + if (intel_state->modeset && intel_can_enable_sagv(state)) intel_enable_sagv(dev_priv); drm_atomic_helper_commit_hw_done(state); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 4db3b04..13809a3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2877,6 +2877,13 @@ skl_wm_plane_id(const struct intel_plane *plane) } } +static bool +intel_has_sagv(struct drm_i915_private *dev_priv) +{ + return IS_SKYLAKE(dev_priv) && + dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED; +} + /* * SAGV dynamically adjusts the system agent voltage and clock frequencies * depending on power and performance requirements. The display engine access @@ -2893,8 +2900,10 @@ intel_enable_sagv(struct drm_i915_private *dev_priv) { int ret; - if (dev_priv->sagv_status == I915_SAGV_NOT_CONTROLLED || - dev_priv->sagv_status == I915_SAGV_ENABLED) + if (!intel_has_sagv(dev_priv)) + return 0; + + if (dev_priv->sagv_status == I915_SAGV_ENABLED) return 0; DRM_DEBUG_KMS("Enabling the SAGV\n"); @@ -2942,8 +2951,10 @@ intel_disable_sagv(struct drm_i915_private *dev_priv) { int ret, result; - if (dev_priv->sagv_status == I915_SAGV_NOT_CONTROLLED || - dev_priv->sagv_status == I915_SAGV_DISABLED) + if (!intel_has_sagv(dev_priv)) + return 0; + + if (dev_priv->sagv_status == I915_SAGV_DISABLED) return 0; DRM_DEBUG_KMS("Disabling the SAGV\n"); @@ -2984,6 +2995,9 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state) enum pipe pipe; int level, plane; + if (!intel_has_sagv(dev_priv)) + return false; + /* * SKL workaround: bspec recommends we disable the SAGV when we have * more then one pipe enabled -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Paulo Zanoni <paulo.r.zanoni@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>, stable@vger.kernel.org Subject: [PATCH 2/9] drm/i915: introduce intel_has_sagv() Date: Thu, 22 Sep 2016 18:00:28 -0300 [thread overview] Message-ID: <1474578035-424-3-git-send-email-paulo.r.zanoni@intel.com> (raw) In-Reply-To: <1474578035-424-1-git-send-email-paulo.r.zanoni@intel.com> And use it to move knowledge about the SAGV-supporting platforms from the callers to the SAGV code. We'll add more platforms to intel_has_sagv(), so IMHO it makes more sense to move all this to a single function instead of patching all the callers every time we add SAGV support to a new platform. v2: Move I915_SAGV_NOT_CONTROLLED to the new function (Lyude). Cc: stable@vger.kernel.org Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 5 ++--- drivers/gpu/drm/i915/intel_pm.c | 22 ++++++++++++++++++---- 2 files changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 45d6183..8e464e0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -14367,7 +14367,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) * SKL workaround: bspec recommends we disable the SAGV when we * have more then one pipe enabled */ - if (IS_SKYLAKE(dev_priv) && !intel_can_enable_sagv(state)) + if (!intel_can_enable_sagv(state)) intel_disable_sagv(dev_priv); intel_modeset_verify_disabled(dev); @@ -14425,8 +14425,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); } - if (IS_SKYLAKE(dev_priv) && intel_state->modeset && - intel_can_enable_sagv(state)) + if (intel_state->modeset && intel_can_enable_sagv(state)) intel_enable_sagv(dev_priv); drm_atomic_helper_commit_hw_done(state); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 4db3b04..13809a3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2877,6 +2877,13 @@ skl_wm_plane_id(const struct intel_plane *plane) } } +static bool +intel_has_sagv(struct drm_i915_private *dev_priv) +{ + return IS_SKYLAKE(dev_priv) && + dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED; +} + /* * SAGV dynamically adjusts the system agent voltage and clock frequencies * depending on power and performance requirements. The display engine access @@ -2893,8 +2900,10 @@ intel_enable_sagv(struct drm_i915_private *dev_priv) { int ret; - if (dev_priv->sagv_status == I915_SAGV_NOT_CONTROLLED || - dev_priv->sagv_status == I915_SAGV_ENABLED) + if (!intel_has_sagv(dev_priv)) + return 0; + + if (dev_priv->sagv_status == I915_SAGV_ENABLED) return 0; DRM_DEBUG_KMS("Enabling the SAGV\n"); @@ -2942,8 +2951,10 @@ intel_disable_sagv(struct drm_i915_private *dev_priv) { int ret, result; - if (dev_priv->sagv_status == I915_SAGV_NOT_CONTROLLED || - dev_priv->sagv_status == I915_SAGV_DISABLED) + if (!intel_has_sagv(dev_priv)) + return 0; + + if (dev_priv->sagv_status == I915_SAGV_DISABLED) return 0; DRM_DEBUG_KMS("Disabling the SAGV\n"); @@ -2984,6 +2995,9 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state) enum pipe pipe; int level, plane; + if (!intel_has_sagv(dev_priv)) + return false; + /* * SKL workaround: bspec recommends we disable the SAGV when we have * more then one pipe enabled -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2016-09-22 21:00 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-09-22 21:00 [PATCH 0/9] SKL/KBL watermark fixes, v3 Paulo Zanoni 2016-09-22 21:00 ` [PATCH 1/9] drm/i915: SAGV is not SKL-only, so rename a few things Paulo Zanoni 2016-09-22 21:00 ` Paulo Zanoni [this message] 2016-09-22 21:00 ` [PATCH 2/9] drm/i915: introduce intel_has_sagv() Paulo Zanoni 2016-09-22 21:00 ` [PATCH 3/9] drm/i915/kbl: KBL also needs to run the SAGV code Paulo Zanoni 2016-09-22 21:00 ` Paulo Zanoni 2016-09-22 21:00 ` [PATCH 4/9] drm/i915/gen9: fix the WaWmMemoryReadLatency implementation Paulo Zanoni 2016-09-22 21:00 ` Paulo Zanoni 2016-09-22 21:00 ` [PATCH 5/9] drm/i915/gen9: minimum scanlines for Y tile is not always 4 Paulo Zanoni 2016-09-27 7:06 ` [Intel-gfx] " Tvrtko Ursulin 2016-09-27 7:06 ` Tvrtko Ursulin 2016-09-22 21:00 ` [PATCH 6/9] drm/i915/gen9: fix plane_blocks_per_line on watermarks calculations Paulo Zanoni 2016-09-22 21:00 ` Paulo Zanoni 2016-09-27 7:20 ` [Intel-gfx] " Tvrtko Ursulin 2016-09-22 21:00 ` [PATCH 7/9] drm/i915/gen9: fix the watermark res_blocks value Paulo Zanoni 2016-09-22 21:00 ` [PATCH 8/9] drm/i915/gen9: implement missing case for SKL watermarks calculation Paulo Zanoni 2016-09-22 21:00 ` [PATCH 9/9] drm/i915/gen9: fail the modeset instead of WARNing on unsupported config Paulo Zanoni 2016-09-22 21:49 ` ✗ Fi.CI.BAT: warning for SKL/KBL watermark fixes (rev3) Patchwork 2016-09-26 17:57 ` Paulo Zanoni -- strict thread matches above, loose matches on Subject: below -- 2016-09-14 0:38 [PATCH 0/9] SKL/KBL watermark fixes, v2 Paulo Zanoni 2016-09-14 0:38 ` [PATCH 2/9] drm/i915: introduce intel_has_sagv() Paulo Zanoni
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