From: Paulo Zanoni <paulo.r.zanoni@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>, stable@vger.kernel.org, Vandana Kannan <vandana.kannan@intel.com> Subject: [PATCH 4/9] drm/i915/gen9: fix the WaWmMemoryReadLatency implementation Date: Thu, 22 Sep 2016 18:00:30 -0300 [thread overview] Message-ID: <1474578035-424-5-git-send-email-paulo.r.zanoni@intel.com> (raw) In-Reply-To: <1474578035-424-1-git-send-email-paulo.r.zanoni@intel.com> Bspec says: "The mailbox response data may not account for memory read latency. If the mailbox response data for level 0 is 0us, add 2 microseconds to the result for each valid level." This means we should only do the +2 in case wm[0] == 0, not always. So split the sanitizing implementation from the WA implementation and fix the WA implementation. v2: Add Fixes tag (Maarten). Fixes: 367294be7c25 ("drm/i915/gen9: Add 2us read latency to WM level") Cc: stable@vger.kernel.org Cc: Vandana Kannan <vandana.kannan@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 42 +++++++++++++++++++++-------------------- 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f09d912..ee561c2 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2127,32 +2127,34 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) GEN9_MEM_LATENCY_LEVEL_MASK; /* + * If a level n (n > 1) has a 0us latency, all levels m (m >= n) + * need to be disabled. We make sure to sanitize the values out + * of the punit to satisfy this requirement. + */ + for (level = 1; level <= max_level; level++) { + if (wm[level] == 0) { + for (i = level + 1; i <= max_level; i++) + wm[i] = 0; + break; + } + } + + /* * WaWmMemoryReadLatency:skl * * punit doesn't take into account the read latency so we need - * to add 2us to the various latency levels we retrieve from - * the punit. - * - W0 is a bit special in that it's the only level that - * can't be disabled if we want to have display working, so - * we always add 2us there. - * - For levels >=1, punit returns 0us latency when they are - * disabled, so we respect that and don't add 2us then - * - * Additionally, if a level n (n > 1) has a 0us latency, all - * levels m (m >= n) need to be disabled. We make sure to - * sanitize the values out of the punit to satisfy this - * requirement. + * to add 2us to the various latency levels we retrieve from the + * punit when level 0 response data us 0us. */ - wm[0] += 2; - for (level = 1; level <= max_level; level++) - if (wm[level] != 0) + if (wm[0] == 0) { + wm[0] += 2; + for (level = 1; level <= max_level; level++) { + if (wm[level] == 0) + break; wm[level] += 2; - else { - for (i = level + 1; i <= max_level; i++) - wm[i] = 0; - - break; } + } + } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { uint64_t sskpd = I915_READ64(MCH_SSKPD); -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Paulo Zanoni <paulo.r.zanoni@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>, stable@vger.kernel.org, Vandana Kannan <vandana.kannan@intel.com> Subject: [PATCH 4/9] drm/i915/gen9: fix the WaWmMemoryReadLatency implementation Date: Thu, 22 Sep 2016 18:00:30 -0300 [thread overview] Message-ID: <1474578035-424-5-git-send-email-paulo.r.zanoni@intel.com> (raw) In-Reply-To: <1474578035-424-1-git-send-email-paulo.r.zanoni@intel.com> Bspec says: "The mailbox response data may not account for memory read latency. If the mailbox response data for level 0 is 0us, add 2 microseconds to the result for each valid level." This means we should only do the +2 in case wm[0] == 0, not always. So split the sanitizing implementation from the WA implementation and fix the WA implementation. v2: Add Fixes tag (Maarten). Fixes: 367294be7c25 ("drm/i915/gen9: Add 2us read latency to WM level") Cc: stable@vger.kernel.org Cc: Vandana Kannan <vandana.kannan@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 42 +++++++++++++++++++++-------------------- 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f09d912..ee561c2 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2127,32 +2127,34 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) GEN9_MEM_LATENCY_LEVEL_MASK; /* + * If a level n (n > 1) has a 0us latency, all levels m (m >= n) + * need to be disabled. We make sure to sanitize the values out + * of the punit to satisfy this requirement. + */ + for (level = 1; level <= max_level; level++) { + if (wm[level] == 0) { + for (i = level + 1; i <= max_level; i++) + wm[i] = 0; + break; + } + } + + /* * WaWmMemoryReadLatency:skl * * punit doesn't take into account the read latency so we need - * to add 2us to the various latency levels we retrieve from - * the punit. - * - W0 is a bit special in that it's the only level that - * can't be disabled if we want to have display working, so - * we always add 2us there. - * - For levels >=1, punit returns 0us latency when they are - * disabled, so we respect that and don't add 2us then - * - * Additionally, if a level n (n > 1) has a 0us latency, all - * levels m (m >= n) need to be disabled. We make sure to - * sanitize the values out of the punit to satisfy this - * requirement. + * to add 2us to the various latency levels we retrieve from the + * punit when level 0 response data us 0us. */ - wm[0] += 2; - for (level = 1; level <= max_level; level++) - if (wm[level] != 0) + if (wm[0] == 0) { + wm[0] += 2; + for (level = 1; level <= max_level; level++) { + if (wm[level] == 0) + break; wm[level] += 2; - else { - for (i = level + 1; i <= max_level; i++) - wm[i] = 0; - - break; } + } + } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { uint64_t sskpd = I915_READ64(MCH_SSKPD); -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2016-09-22 21:00 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-09-22 21:00 [PATCH 0/9] SKL/KBL watermark fixes, v3 Paulo Zanoni 2016-09-22 21:00 ` [PATCH 1/9] drm/i915: SAGV is not SKL-only, so rename a few things Paulo Zanoni 2016-09-22 21:00 ` [PATCH 2/9] drm/i915: introduce intel_has_sagv() Paulo Zanoni 2016-09-22 21:00 ` Paulo Zanoni 2016-09-22 21:00 ` [PATCH 3/9] drm/i915/kbl: KBL also needs to run the SAGV code Paulo Zanoni 2016-09-22 21:00 ` Paulo Zanoni 2016-09-22 21:00 ` Paulo Zanoni [this message] 2016-09-22 21:00 ` [PATCH 4/9] drm/i915/gen9: fix the WaWmMemoryReadLatency implementation Paulo Zanoni 2016-09-22 21:00 ` [PATCH 5/9] drm/i915/gen9: minimum scanlines for Y tile is not always 4 Paulo Zanoni 2016-09-27 7:06 ` [Intel-gfx] " Tvrtko Ursulin 2016-09-27 7:06 ` Tvrtko Ursulin 2016-09-22 21:00 ` [PATCH 6/9] drm/i915/gen9: fix plane_blocks_per_line on watermarks calculations Paulo Zanoni 2016-09-22 21:00 ` Paulo Zanoni 2016-09-27 7:20 ` [Intel-gfx] " Tvrtko Ursulin 2016-09-22 21:00 ` [PATCH 7/9] drm/i915/gen9: fix the watermark res_blocks value Paulo Zanoni 2016-09-22 21:00 ` [PATCH 8/9] drm/i915/gen9: implement missing case for SKL watermarks calculation Paulo Zanoni 2016-09-22 21:00 ` [PATCH 9/9] drm/i915/gen9: fail the modeset instead of WARNing on unsupported config Paulo Zanoni 2016-09-22 21:49 ` ✗ Fi.CI.BAT: warning for SKL/KBL watermark fixes (rev3) Patchwork 2016-09-26 17:57 ` Paulo Zanoni -- strict thread matches above, loose matches on Subject: below -- 2016-09-14 0:38 [PATCH 0/9] SKL/KBL watermark fixes, v2 Paulo Zanoni 2016-09-14 0:38 ` [PATCH 4/9] drm/i915/gen9: fix the WaWmMemoryReadLatency implementation Paulo Zanoni
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1474578035-424-5-git-send-email-paulo.r.zanoni@intel.com \ --to=paulo.r.zanoni@intel.com \ --cc=intel-gfx@lists.freedesktop.org \ --cc=stable@vger.kernel.org \ --cc=vandana.kannan@intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.