From: Eric Auger <eric.auger@redhat.com> To: eric.auger@redhat.com, eric.auger.pro@gmail.com, christoffer.dall@linaro.org, marc.zyngier@arm.com, robin.murphy@arm.com, alex.williamson@redhat.com, will.deacon@arm.com, joro@8bytes.org, tglx@linutronix.de, jason@lakedaemon.net, linux-arm-kernel@lists.infradead.org Cc: kvm@vger.kernel.org, drjones@redhat.com, linux-kernel@vger.kernel.org, Bharat.Bhushan@freescale.com, pranav.sawargaonkar@gmail.com, p.fedin@samsung.com, iommu@lists.linux-foundation.org, Jean-Philippe.Brucker@arm.com, yehuday@marvell.com, Manish.Jaggi@caviumnetworks.com Subject: [RFC 10/11] iommu/arm-smmu: Do not advertise IOMMU_CAP_INTR_REMAP Date: Tue, 27 Sep 2016 20:48:37 +0000 [thread overview] Message-ID: <1475009318-2617-11-git-send-email-eric.auger@redhat.com> (raw) In-Reply-To: <1475009318-2617-1-git-send-email-eric.auger@redhat.com> Do not advertise IOMMU_CAP_INTR_REMAP for arm-smmu(-v3). Indeed the irq_remapping capability is abstracted on irqchip side for ARM as opposed to Intel IOMMU featuring IRQ remapping HW. So for the time being assignement is considered as unsafe on ARM, until we get an accurate description of whether the MSI controllers are downstream to smmus. This commit affects platform and PCIe device assignment use cases. Signed-off-by: Eric Auger <eric.auger@redhat.com> --- --- drivers/iommu/arm-smmu-v3.c | 3 ++- drivers/iommu/arm-smmu.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index e825679..c86ba84 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -1371,7 +1371,8 @@ static bool arm_smmu_capable(enum iommu_cap cap) case IOMMU_CAP_CACHE_COHERENCY: return true; case IOMMU_CAP_INTR_REMAP: - return true; /* MSIs are just memory writes */ + /* interrupt translation handled at MSI controller level */ + return false; case IOMMU_CAP_NOEXEC: return true; default: diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 707c09b..7af1dd0 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1359,7 +1359,8 @@ static bool arm_smmu_capable(enum iommu_cap cap) */ return true; case IOMMU_CAP_INTR_REMAP: - return true; /* MSIs are just memory writes */ + /* interrupt translation handled at MSI controller level */ + return false; case IOMMU_CAP_NOEXEC: return true; default: -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Eric Auger <eric.auger-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> To: eric.auger-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, eric.auger.pro-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, christoffer.dall-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, marc.zyngier-5wv7dgnIgG8@public.gmane.org, robin.murphy-5wv7dgnIgG8@public.gmane.org, alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org, tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org, jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Cc: drjones-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Manish.Jaggi-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org, p.fedin-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, pranav.sawargaonkar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, yehuday-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org Subject: [RFC 10/11] iommu/arm-smmu: Do not advertise IOMMU_CAP_INTR_REMAP Date: Tue, 27 Sep 2016 20:48:37 +0000 [thread overview] Message-ID: <1475009318-2617-11-git-send-email-eric.auger@redhat.com> (raw) In-Reply-To: <1475009318-2617-1-git-send-email-eric.auger-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> Do not advertise IOMMU_CAP_INTR_REMAP for arm-smmu(-v3). Indeed the irq_remapping capability is abstracted on irqchip side for ARM as opposed to Intel IOMMU featuring IRQ remapping HW. So for the time being assignement is considered as unsafe on ARM, until we get an accurate description of whether the MSI controllers are downstream to smmus. This commit affects platform and PCIe device assignment use cases. Signed-off-by: Eric Auger <eric.auger-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> --- --- drivers/iommu/arm-smmu-v3.c | 3 ++- drivers/iommu/arm-smmu.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index e825679..c86ba84 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -1371,7 +1371,8 @@ static bool arm_smmu_capable(enum iommu_cap cap) case IOMMU_CAP_CACHE_COHERENCY: return true; case IOMMU_CAP_INTR_REMAP: - return true; /* MSIs are just memory writes */ + /* interrupt translation handled at MSI controller level */ + return false; case IOMMU_CAP_NOEXEC: return true; default: diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 707c09b..7af1dd0 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1359,7 +1359,8 @@ static bool arm_smmu_capable(enum iommu_cap cap) */ return true; case IOMMU_CAP_INTR_REMAP: - return true; /* MSIs are just memory writes */ + /* interrupt translation handled at MSI controller level */ + return false; case IOMMU_CAP_NOEXEC: return true; default: -- 1.9.1
next prev parent reply other threads:[~2016-09-27 20:50 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-09-27 20:48 [RFC 00/11] KVM PCIe/MSI passthrough on ARM/ARM64: re-design with transparent MSI mapping Eric Auger 2016-09-27 20:48 ` Eric Auger 2016-09-27 20:48 ` Eric Auger 2016-09-27 20:48 ` [RFC 01/11] iommu: Add iommu_domain_msi_geometry and DOMAIN_ATTR_MSI_GEOMETRY Eric Auger 2016-09-27 20:48 ` Eric Auger 2016-09-27 20:48 ` [RFC 02/11] iommu: Introduce IOMMU_CAP_TRANSLATE_MSI capability Eric Auger 2016-09-27 20:48 ` Eric Auger 2016-09-27 20:48 ` [RFC 03/11] iommu: Introduce IOMMU_DOMAIN_MIXED Eric Auger 2016-09-27 20:48 ` Eric Auger 2016-09-27 20:48 ` [RFC 04/11] iommu/dma: Allow MSI-only cookies Eric Auger 2016-09-27 20:48 ` Eric Auger 2016-09-27 20:48 ` [RFC 05/11] iommu/dma: iommu_dma_(un)map_mixed Eric Auger 2016-09-27 20:48 ` Eric Auger 2016-09-30 13:24 ` Robin Murphy 2016-09-30 13:24 ` Robin Murphy 2016-09-30 13:24 ` Robin Murphy 2016-10-02 9:56 ` Christoffer Dall 2016-10-02 9:56 ` Christoffer Dall 2016-10-02 9:56 ` Christoffer Dall 2016-10-04 17:18 ` Robin Murphy 2016-10-04 17:18 ` Robin Murphy 2016-10-04 17:37 ` Auger Eric 2016-10-04 17:37 ` Auger Eric 2016-10-03 9:38 ` Auger Eric 2016-10-03 9:38 ` Auger Eric 2016-10-03 9:38 ` Auger Eric 2016-09-27 20:48 ` [RFC 06/11] iommu/arm-smmu: Allow IOMMU_DOMAIN_MIXED domain allocation Eric Auger 2016-09-27 20:48 ` Eric Auger 2016-09-27 20:48 ` [RFC 07/11] iommu: Use IOMMU_DOMAIN_MIXED typed domain when IOMMU translates MSI Eric Auger 2016-09-27 20:48 ` Eric Auger 2016-09-27 20:48 ` [RFC 08/11] vfio/type1: Sets the IOVA window in case MSI IOVA need to be allocated Eric Auger 2016-09-27 20:48 ` Eric Auger 2016-09-27 20:48 ` [RFC 09/11] vfio/type1: Reserve IOVAs for IOMMU_DOMAIN_MIXED domains Eric Auger 2016-09-27 20:48 ` Eric Auger 2016-09-27 20:48 ` Eric Auger [this message] 2016-09-27 20:48 ` [RFC 10/11] iommu/arm-smmu: Do not advertise IOMMU_CAP_INTR_REMAP Eric Auger 2016-09-27 20:48 ` [RFC 11/11] iommu/arm-smmu: Advertise IOMMU_CAP_TRANSLATE_MSI Eric Auger 2016-09-27 20:48 ` Eric Auger
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