[PATCH 0/9] Broxton ddi phy refactoring

[PATCH 0/9] Broxton ddi phy refactoring

[Ander Conselvan de Oliveira]

Hi,

This is a small refactoring of the broxton ddi phy code that splits the
knowledge of each phy's configuration from the code itself and makes
the connection between the ports and the channels in the phy more
obvious.

I took the oppurtunity to move the code to intel_dpio_phy.c, since there
are a lot of similarities between the bxt and chv phys, as evidenced by
the documentation.

Thanks,
Ander

Ander Conselvan de Oliveira (9):
  drm/i915: Rename struct i915_power_well field data to id
  drm/i915: Explicitly map broxton DPIO power wells to phys
  drm/i915: Pass lane count to bxt_ddi_phy_calc_lane_optmin_mask()
  drm/i915: Move broxton phy code to intel_dpio_phy.c
  drm/i915: Move DPIO phy documentation section to intel_dpio_phy.c
  drm/i915: Move broxton vswing sequence to intel_dpio_phy.c
  drm/i915: Create a struct to hold information about the broxton phys
  drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_info
  drm/i915: Address broxton phy registers based on phy and channel
    number

 Documentation/gpu/i915.rst              |   2 +-
 drivers/gpu/drm/i915/i915_drv.h         |  23 ++
 drivers/gpu/drm/i915/i915_reg.h         | 303 +++++-----------
 drivers/gpu/drm/i915/intel_ddi.c        | 362 +------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c   | 597 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dpll_mgr.c   |  84 +++--
 drivers/gpu/drm/i915/intel_drv.h        |   6 -
 drivers/gpu/drm/i915/intel_runtime_pm.c | 145 ++++----
 8 files changed, 821 insertions(+), 701 deletions(-)

-- 
2.5.5

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[PATCH 1/9] drm/i915: Rename struct i915_power_well field data to id

[Ander Conselvan de Oliveira]

Calling it data seems to imply arbitrary data can be associated with the
power well. However, that field is used for look ups and expected to be
unique, so rename it.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |   3 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 112 ++++++++++++++++----------------
 2 files changed, 58 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4613f03..5bd3f59 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1316,7 +1316,8 @@ struct i915_power_well {
 	/* cached hw enabled state */
 	bool hw_enabled;
 	unsigned long domains;
-	unsigned long data;
+	/* unique identifier for this power well */
+	unsigned long id;
 	const struct i915_power_well_ops *ops;
 };
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6c11168..4ecaf6a 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -331,7 +331,7 @@ static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 	 * sure vgacon can keep working normally without triggering interrupts
 	 * and error messages.
 	 */
-	if (power_well->data == SKL_DISP_PW_2) {
+	if (power_well->id == SKL_DISP_PW_2) {
 		vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
 		outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 		vga_put(pdev, VGA_RSRC_LEGACY_IO);
@@ -344,7 +344,7 @@ static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 				       struct i915_power_well *power_well)
 {
-	if (power_well->data == SKL_DISP_PW_2)
+	if (power_well->id == SKL_DISP_PW_2)
 		gen8_irq_power_well_pre_disable(dev_priv,
 						1 << PIPE_C | 1 << PIPE_B);
 }
@@ -659,7 +659,7 @@ static void
 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
 				  struct i915_power_well *power_well)
 {
-	enum skl_disp_power_wells power_well_id = power_well->data;
+	enum skl_disp_power_wells power_well_id = power_well->id;
 	u32 val;
 	u32 mask;
 
@@ -704,7 +704,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 	tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 	fuse_status = I915_READ(SKL_FUSE_STATUS);
 
-	switch (power_well->data) {
+	switch (power_well->id) {
 	case SKL_DISP_PW_1:
 		if (intel_wait_for_register(dev_priv,
 					    SKL_FUSE_STATUS,
@@ -728,13 +728,13 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 	case SKL_DISP_PW_MISC_IO:
 		break;
 	default:
-		WARN(1, "Unknown power well %lu\n", power_well->data);
+		WARN(1, "Unknown power well %lu\n", power_well->id);
 		return;
 	}
 
-	req_mask = SKL_POWER_WELL_REQ(power_well->data);
+	req_mask = SKL_POWER_WELL_REQ(power_well->id);
 	enable_requested = tmp & req_mask;
-	state_mask = SKL_POWER_WELL_STATE(power_well->data);
+	state_mask = SKL_POWER_WELL_STATE(power_well->id);
 	is_enabled = tmp & state_mask;
 
 	if (!enable && enable_requested)
@@ -770,14 +770,14 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 			  power_well->name, enable ? "enable" : "disable");
 
 	if (check_fuse_status) {
-		if (power_well->data == SKL_DISP_PW_1) {
+		if (power_well->id == SKL_DISP_PW_1) {
 			if (intel_wait_for_register(dev_priv,
 						    SKL_FUSE_STATUS,
 						    SKL_FUSE_PG1_DIST_STATUS,
 						    SKL_FUSE_PG1_DIST_STATUS,
 						    1))
 				DRM_ERROR("PG1 distributing status timeout\n");
-		} else if (power_well->data == SKL_DISP_PW_2) {
+		} else if (power_well->id == SKL_DISP_PW_2) {
 			if (intel_wait_for_register(dev_priv,
 						    SKL_FUSE_STATUS,
 						    SKL_FUSE_PG2_DIST_STATUS,
@@ -819,8 +819,8 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 					struct i915_power_well *power_well)
 {
-	uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
-		SKL_POWER_WELL_STATE(power_well->data);
+	uint32_t mask = SKL_POWER_WELL_REQ(power_well->id) |
+		SKL_POWER_WELL_STATE(power_well->id);
 
 	return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 }
@@ -848,7 +848,7 @@ static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 
 static enum dpio_phy bxt_power_well_to_phy(struct i915_power_well *power_well)
 {
-	enum skl_disp_power_wells power_well_id = power_well->data;
+	enum skl_disp_power_wells power_well_id = power_well->id;
 
 	return power_well_id == BXT_DPIO_CMN_A ? DPIO_PHY1 : DPIO_PHY0;
 }
@@ -856,7 +856,7 @@ static enum dpio_phy bxt_power_well_to_phy(struct i915_power_well *power_well)
 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 					   struct i915_power_well *power_well)
 {
-	enum skl_disp_power_wells power_well_id = power_well->data;
+	enum skl_disp_power_wells power_well_id = power_well->id;
 	struct i915_power_well *cmn_a_well = NULL;
 
 	if (power_well_id == BXT_DPIO_CMN_BC) {
@@ -976,7 +976,7 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 			       struct i915_power_well *power_well, bool enable)
 {
-	enum punit_power_well power_well_id = power_well->data;
+	enum punit_power_well power_well_id = power_well->id;
 	u32 mask;
 	u32 state;
 	u32 ctrl;
@@ -1030,7 +1030,7 @@ static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 				   struct i915_power_well *power_well)
 {
-	int power_well_id = power_well->data;
+	int power_well_id = power_well->id;
 	bool enabled = false;
 	u32 mask;
 	u32 state;
@@ -1145,7 +1145,7 @@ static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
 					  struct i915_power_well *power_well)
 {
-	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
+	WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D);
 
 	vlv_set_power_well(dev_priv, power_well, true);
 
@@ -1155,7 +1155,7 @@ static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
 					   struct i915_power_well *power_well)
 {
-	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
+	WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DISP2D);
 
 	vlv_display_power_well_deinit(dev_priv);
 
@@ -1165,7 +1165,7 @@ static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 					   struct i915_power_well *power_well)
 {
-	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
+	WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC);
 
 	/* since ref/cri clock was enabled */
 	udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
@@ -1191,7 +1191,7 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 {
 	enum pipe pipe;
 
-	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
+	WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC);
 
 	for_each_pipe(dev_priv, pipe)
 		assert_pll_disabled(dev_priv, pipe);
@@ -1214,7 +1214,7 @@ static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_pr
 		struct i915_power_well *power_well;
 
 		power_well = &power_domains->power_wells[i];
-		if (power_well->data == power_well_id)
+		if (power_well->id == power_well_id)
 			return power_well;
 	}
 
@@ -1338,10 +1338,10 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 	enum pipe pipe;
 	uint32_t tmp;
 
-	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
-		     power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
+	WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
+		     power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D);
 
-	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+	if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
 		pipe = PIPE_A;
 		phy = DPIO_PHY0;
 	} else {
@@ -1369,7 +1369,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 		DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
 
-	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+	if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
 		tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
 		tmp |= DPIO_DYNPWRDOWNEN_CH1;
 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
@@ -1400,10 +1400,10 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 {
 	enum dpio_phy phy;
 
-	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
-		     power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
+	WARN_ON_ONCE(power_well->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
+		     power_well->id != PUNIT_POWER_WELL_DPIO_CMN_D);
 
-	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+	if (power_well->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
 		phy = DPIO_PHY0;
 		assert_pll_disabled(dev_priv, PIPE_A);
 		assert_pll_disabled(dev_priv, PIPE_B);
@@ -1552,7 +1552,7 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
 					struct i915_power_well *power_well)
 {
-	enum pipe pipe = power_well->data;
+	enum pipe pipe = power_well->id;
 	bool enabled;
 	u32 state, ctrl;
 
@@ -1582,7 +1582,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
 				    struct i915_power_well *power_well,
 				    bool enable)
 {
-	enum pipe pipe = power_well->data;
+	enum pipe pipe = power_well->id;
 	u32 state;
 	u32 ctrl;
 
@@ -1615,7 +1615,7 @@ out:
 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
 					struct i915_power_well *power_well)
 {
-	WARN_ON_ONCE(power_well->data != PIPE_A);
+	WARN_ON_ONCE(power_well->id != PIPE_A);
 
 	chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
 }
@@ -1623,7 +1623,7 @@ static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
 				       struct i915_power_well *power_well)
 {
-	WARN_ON_ONCE(power_well->data != PIPE_A);
+	WARN_ON_ONCE(power_well->id != PIPE_A);
 
 	chv_set_pipe_power_well(dev_priv, power_well, true);
 
@@ -1633,7 +1633,7 @@ static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
 					struct i915_power_well *power_well)
 {
-	WARN_ON_ONCE(power_well->data != PIPE_A);
+	WARN_ON_ONCE(power_well->id != PIPE_A);
 
 	vlv_display_power_well_deinit(dev_priv);
 
@@ -1977,12 +1977,12 @@ static struct i915_power_well vlv_power_wells[] = {
 		.always_on = 1,
 		.domains = POWER_DOMAIN_MASK,
 		.ops = &i9xx_always_on_power_well_ops,
-		.data = PUNIT_POWER_WELL_ALWAYS_ON,
+		.id = PUNIT_POWER_WELL_ALWAYS_ON,
 	},
 	{
 		.name = "display",
 		.domains = VLV_DISPLAY_POWER_DOMAINS,
-		.data = PUNIT_POWER_WELL_DISP2D,
+		.id = PUNIT_POWER_WELL_DISP2D,
 		.ops = &vlv_display_power_well_ops,
 	},
 	{
@@ -1992,7 +1992,7 @@ static struct i915_power_well vlv_power_wells[] = {
 			   VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
 			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
 		.ops = &vlv_dpio_power_well_ops,
-		.data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
+		.id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
 	},
 	{
 		.name = "dpio-tx-b-23",
@@ -2001,7 +2001,7 @@ static struct i915_power_well vlv_power_wells[] = {
 			   VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
 			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
 		.ops = &vlv_dpio_power_well_ops,
-		.data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
+		.id = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
 	},
 	{
 		.name = "dpio-tx-c-01",
@@ -2010,7 +2010,7 @@ static struct i915_power_well vlv_power_wells[] = {
 			   VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
 			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
 		.ops = &vlv_dpio_power_well_ops,
-		.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
+		.id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
 	},
 	{
 		.name = "dpio-tx-c-23",
@@ -2019,12 +2019,12 @@ static struct i915_power_well vlv_power_wells[] = {
 			   VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
 			   VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
 		.ops = &vlv_dpio_power_well_ops,
-		.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
+		.id = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
 	},
 	{
 		.name = "dpio-common",
 		.domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
-		.data = PUNIT_POWER_WELL_DPIO_CMN_BC,
+		.id = PUNIT_POWER_WELL_DPIO_CMN_BC,
 		.ops = &vlv_dpio_cmn_power_well_ops,
 	},
 };
@@ -2044,19 +2044,19 @@ static struct i915_power_well chv_power_wells[] = {
 		 * required for any pipe to work.
 		 */
 		.domains = CHV_DISPLAY_POWER_DOMAINS,
-		.data = PIPE_A,
+		.id = PIPE_A,
 		.ops = &chv_pipe_power_well_ops,
 	},
 	{
 		.name = "dpio-common-bc",
 		.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
-		.data = PUNIT_POWER_WELL_DPIO_CMN_BC,
+		.id = PUNIT_POWER_WELL_DPIO_CMN_BC,
 		.ops = &chv_dpio_cmn_power_well_ops,
 	},
 	{
 		.name = "dpio-common-d",
 		.domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
-		.data = PUNIT_POWER_WELL_DPIO_CMN_D,
+		.id = PUNIT_POWER_WELL_DPIO_CMN_D,
 		.ops = &chv_dpio_cmn_power_well_ops,
 	},
 };
@@ -2079,57 +2079,57 @@ static struct i915_power_well skl_power_wells[] = {
 		.always_on = 1,
 		.domains = POWER_DOMAIN_MASK,
 		.ops = &i9xx_always_on_power_well_ops,
-		.data = SKL_DISP_PW_ALWAYS_ON,
+		.id = SKL_DISP_PW_ALWAYS_ON,
 	},
 	{
 		.name = "power well 1",
 		/* Handled by the DMC firmware */
 		.domains = 0,
 		.ops = &skl_power_well_ops,
-		.data = SKL_DISP_PW_1,
+		.id = SKL_DISP_PW_1,
 	},
 	{
 		.name = "MISC IO power well",
 		/* Handled by the DMC firmware */
 		.domains = 0,
 		.ops = &skl_power_well_ops,
-		.data = SKL_DISP_PW_MISC_IO,
+		.id = SKL_DISP_PW_MISC_IO,
 	},
 	{
 		.name = "DC off",
 		.domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
 		.ops = &gen9_dc_off_power_well_ops,
-		.data = SKL_DISP_PW_DC_OFF,
+		.id = SKL_DISP_PW_DC_OFF,
 	},
 	{
 		.name = "power well 2",
 		.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
 		.ops = &skl_power_well_ops,
-		.data = SKL_DISP_PW_2,
+		.id = SKL_DISP_PW_2,
 	},
 	{
 		.name = "DDI A/E power well",
 		.domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
 		.ops = &skl_power_well_ops,
-		.data = SKL_DISP_PW_DDI_A_E,
+		.id = SKL_DISP_PW_DDI_A_E,
 	},
 	{
 		.name = "DDI B power well",
 		.domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
 		.ops = &skl_power_well_ops,
-		.data = SKL_DISP_PW_DDI_B,
+		.id = SKL_DISP_PW_DDI_B,
 	},
 	{
 		.name = "DDI C power well",
 		.domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
 		.ops = &skl_power_well_ops,
-		.data = SKL_DISP_PW_DDI_C,
+		.id = SKL_DISP_PW_DDI_C,
 	},
 	{
 		.name = "DDI D power well",
 		.domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
 		.ops = &skl_power_well_ops,
-		.data = SKL_DISP_PW_DDI_D,
+		.id = SKL_DISP_PW_DDI_D,
 	},
 };
 
@@ -2144,31 +2144,31 @@ static struct i915_power_well bxt_power_wells[] = {
 		.name = "power well 1",
 		.domains = 0,
 		.ops = &skl_power_well_ops,
-		.data = SKL_DISP_PW_1,
+		.id = SKL_DISP_PW_1,
 	},
 	{
 		.name = "DC off",
 		.domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
 		.ops = &gen9_dc_off_power_well_ops,
-		.data = SKL_DISP_PW_DC_OFF,
+		.id = SKL_DISP_PW_DC_OFF,
 	},
 	{
 		.name = "power well 2",
 		.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
 		.ops = &skl_power_well_ops,
-		.data = SKL_DISP_PW_2,
+		.id = SKL_DISP_PW_2,
 	},
 	{
 		.name = "dpio-common-a",
 		.domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
 		.ops = &bxt_dpio_cmn_power_well_ops,
-		.data = BXT_DPIO_CMN_A,
+		.id = BXT_DPIO_CMN_A,
 	},
 	{
 		.name = "dpio-common-bc",
 		.domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
 		.ops = &bxt_dpio_cmn_power_well_ops,
-		.data = BXT_DPIO_CMN_BC,
+		.id = BXT_DPIO_CMN_BC,
 	},
 };
 
-- 
2.5.5

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[PATCH 2/9] drm/i915: Explicitly map broxton DPIO power wells to phys

[Ander Conselvan de Oliveira]

The mapping from the BXT_DPIO_CMN_* power wells to their respective phys
required a detour implemented in the bxt_power_well_to_phy() function.
Instead, embed that information directly into the power_well struct, by
resurrecting the data field.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |  5 +++++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++++++---------------
 2 files changed, 12 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5bd3f59..93c90b9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1318,6 +1318,11 @@ struct i915_power_well {
 	unsigned long domains;
 	/* unique identifier for this power well */
 	unsigned long id;
+	/*
+	 * Arbitraty data associated with this power well. Platform and power
+	 * well specific.
+	 */
+	unsigned long data;
 	const struct i915_power_well_ops *ops;
 };
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 4ecaf6a..d41fd46 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -846,13 +846,6 @@ static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 	skl_set_power_well(dev_priv, power_well, false);
 }
 
-static enum dpio_phy bxt_power_well_to_phy(struct i915_power_well *power_well)
-{
-	enum skl_disp_power_wells power_well_id = power_well->id;
-
-	return power_well_id == BXT_DPIO_CMN_A ? DPIO_PHY1 : DPIO_PHY0;
-}
-
 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 					   struct i915_power_well *power_well)
 {
@@ -868,7 +861,7 @@ static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 		intel_power_well_get(dev_priv, cmn_a_well);
 	}
 
-	bxt_ddi_phy_init(dev_priv, bxt_power_well_to_phy(power_well));
+	bxt_ddi_phy_init(dev_priv, power_well->data);
 
 	if (cmn_a_well)
 		intel_power_well_put(dev_priv, cmn_a_well);
@@ -877,14 +870,13 @@ static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 					    struct i915_power_well *power_well)
 {
-	bxt_ddi_phy_uninit(dev_priv, bxt_power_well_to_phy(power_well));
+	bxt_ddi_phy_uninit(dev_priv, power_well->data);
 }
 
 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
 					    struct i915_power_well *power_well)
 {
-	return bxt_ddi_phy_is_enabled(dev_priv,
-				      bxt_power_well_to_phy(power_well));
+	return bxt_ddi_phy_is_enabled(dev_priv, power_well->data);
 }
 
 static void bxt_dpio_cmn_power_well_sync_hw(struct drm_i915_private *dev_priv,
@@ -903,13 +895,11 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
 
 	power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
 	if (power_well->count > 0)
-		bxt_ddi_phy_verify_state(dev_priv,
-					 bxt_power_well_to_phy(power_well));
+		bxt_ddi_phy_verify_state(dev_priv, power_well->data);
 
 	power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
 	if (power_well->count > 0)
-		bxt_ddi_phy_verify_state(dev_priv,
-					 bxt_power_well_to_phy(power_well));
+		bxt_ddi_phy_verify_state(dev_priv, power_well->data);
 }
 
 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
@@ -2163,12 +2153,14 @@ static struct i915_power_well bxt_power_wells[] = {
 		.domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
 		.ops = &bxt_dpio_cmn_power_well_ops,
 		.id = BXT_DPIO_CMN_A,
+		.data = DPIO_PHY1,
 	},
 	{
 		.name = "dpio-common-bc",
 		.domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
 		.ops = &bxt_dpio_cmn_power_well_ops,
 		.id = BXT_DPIO_CMN_BC,
+		.data = DPIO_PHY0,
 	},
 };
 
-- 
2.5.5

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[PATCH 3/9] drm/i915: Pass lane count to bxt_ddi_phy_calc_lane_optmin_mask()

[Ander Conselvan de Oliveira]

Pass lane count to bxt_ddi_phy_calc_lane_optmin_mask() instead of having
it extract that number from a pipe_config to decouple the phy code from
intel_crtc_state.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 35f0b7c..1dc7543 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2120,9 +2120,9 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
 
 static uint8_t
 bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
-				     struct intel_crtc_state *pipe_config)
+				     uint8_t lane_count)
 {
-	switch (pipe_config->lane_count) {
+	switch (lane_count) {
 	case 1:
 		return 0;
 	case 2:
@@ -2130,7 +2130,7 @@ bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
 	case 4:
 		return BIT(3) | BIT(2) | BIT(0);
 	default:
-		MISSING_CASE(pipe_config->lane_count);
+		MISSING_CASE(lane_count);
 
 		return 0;
 	}
@@ -2347,7 +2347,7 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
 	if (IS_BROXTON(dev_priv) && ret)
 		pipe_config->lane_lat_optim_mask =
 			bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
-							     pipe_config);
+							     pipe_config->lane_count);
 
 	return ret;
 
-- 
2.5.5

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[PATCH 4/9] drm/i915: Move broxton phy code to intel_dpio_phy.c

[Ander Conselvan de Oliveira]

The phy in broxton is also a dpio phy, similar to cherryview but with
programming through MMIO. So move the code together with the other
similar phys.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  12 ++
 drivers/gpu/drm/i915/intel_ddi.c      | 322 +--------------------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 327 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h      |   6 -
 4 files changed, 341 insertions(+), 326 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 93c90b9..8bdbbb5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3735,6 +3735,18 @@ u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 
 /* intel_dpio_phy.c */
+void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
+void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
+bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
+			    enum dpio_phy phy);
+bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
+			      enum dpio_phy phy);
+uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
+					     uint8_t lane_count);
+void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
+				     uint8_t lane_lat_optim_mask);
+uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
+
 void chv_set_phy_signal_level(struct intel_encoder *encoder,
 			      u32 deemph_reg_value, u32 margin_reg_value,
 			      bool uniq_trans_scale);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1dc7543..d69d231 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1853,332 +1853,14 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder,
 	}
 }
 
-bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
-			    enum dpio_phy phy)
-{
-	enum port port;
-
-	if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
-		return false;
-
-	if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
-	     (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
-		DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
-				 phy);
-
-		return false;
-	}
-
-	if (phy == DPIO_PHY1 &&
-	    !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
-		DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
-
-		return false;
-	}
-
-	if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
-		DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
-				 phy);
-
-		return false;
-	}
-
-	for_each_port_masked(port,
-			     phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
-						BIT(PORT_A)) {
-		u32 tmp = I915_READ(BXT_PHY_CTL(port));
-
-		if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
-			DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
-					 "for port %c powered down "
-					 "(PHY_CTL %08x)\n",
-					 phy, port_name(port), tmp);
-
-			return false;
-		}
-	}
-
-	return true;
-}
-
-static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
-{
-	u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
-
-	return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
-}
-
-static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
-				  enum dpio_phy phy)
-{
-	if (intel_wait_for_register(dev_priv,
-				    BXT_PORT_REF_DW3(phy),
-				    GRC_DONE, GRC_DONE,
-				    10))
-		DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
-}
-
-void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
-{
-	u32 val;
-
-	if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
-		/* Still read out the GRC value for state verification */
-		if (phy == DPIO_PHY0)
-			dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
-
-		if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
-			DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
-					 "won't reprogram it\n", phy);
-
-			return;
-		}
-
-		DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
-				 "force reprogramming it\n", phy);
-	}
-
-	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
-	val |= GT_DISPLAY_POWER_ON(phy);
-	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
-
-	/*
-	 * The PHY registers start out inaccessible and respond to reads with
-	 * all 1s.  Eventually they become accessible as they power up, then
-	 * the reserved bit will give the default 0.  Poll on the reserved bit
-	 * becoming 0 to find when the PHY is accessible.
-	 * HW team confirmed that the time to reach phypowergood status is
-	 * anywhere between 50 us and 100us.
-	 */
-	if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
-		(PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
-		DRM_ERROR("timeout during PHY%d power on\n", phy);
-	}
-
-	/* Program PLL Rcomp code offset */
-	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
-	val &= ~IREF0RC_OFFSET_MASK;
-	val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
-	I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
-
-	val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
-	val &= ~IREF1RC_OFFSET_MASK;
-	val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
-	I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
-
-	/* Program power gating */
-	val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
-	val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
-		SUS_CLK_CONFIG;
-	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
-
-	if (phy == DPIO_PHY0) {
-		val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
-		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
-		I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
-	}
-
-	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
-	val &= ~OCL2_LDOFUSE_PWR_DIS;
-	/*
-	 * On PHY1 disable power on the second channel, since no port is
-	 * connected there. On PHY0 both channels have a port, so leave it
-	 * enabled.
-	 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
-	 * power down the second channel on PHY0 as well.
-	 *
-	 * FIXME: Clarify programming of the following, the register is
-	 * read-only with bit 6 fixed at 0 at least in stepping A.
-	 */
-	if (phy == DPIO_PHY1)
-		val |= OCL2_LDOFUSE_PWR_DIS;
-	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
-
-	if (phy == DPIO_PHY0) {
-		uint32_t grc_code;
-		/*
-		 * PHY0 isn't connected to an RCOMP resistor so copy over
-		 * the corresponding calibrated value from PHY1, and disable
-		 * the automatic calibration on PHY0.
-		 */
-		val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
-		grc_code = val << GRC_CODE_FAST_SHIFT |
-			   val << GRC_CODE_SLOW_SHIFT |
-			   val;
-		I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
-
-		val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
-		val |= GRC_DIS | GRC_RDY_OVRD;
-		I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
-	}
-
-	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
-	val |= COMMON_RESET_DIS;
-	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
-
-	if (phy == DPIO_PHY1)
-		bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
-}
-
-void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
-{
-	uint32_t val;
-
-	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
-	val &= ~COMMON_RESET_DIS;
-	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
-
-	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
-	val &= ~GT_DISPLAY_POWER_ON(phy);
-	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
-}
-
-static bool __printf(6, 7)
-__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
-		       i915_reg_t reg, u32 mask, u32 expected,
-		       const char *reg_fmt, ...)
-{
-	struct va_format vaf;
-	va_list args;
-	u32 val;
-
-	val = I915_READ(reg);
-	if ((val & mask) == expected)
-		return true;
-
-	va_start(args, reg_fmt);
-	vaf.fmt = reg_fmt;
-	vaf.va = &args;
-
-	DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
-			 "current %08x, expected %08x (mask %08x)\n",
-			 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
-			 mask);
-
-	va_end(args);
-
-	return false;
-}
-
-bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
-			      enum dpio_phy phy)
-{
-	uint32_t mask;
-	bool ok;
-
-#define _CHK(reg, mask, exp, fmt, ...)					\
-	__phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt,	\
-			       ## __VA_ARGS__)
-
-	if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
-		return false;
-
-	ok = true;
-
-	/* PLL Rcomp code offset */
-	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
-		    IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
-		    "BXT_PORT_CL1CM_DW9(%d)", phy);
-	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
-		    IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
-		    "BXT_PORT_CL1CM_DW10(%d)", phy);
-
-	/* Power gating */
-	mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
-	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
-		    "BXT_PORT_CL1CM_DW28(%d)", phy);
-
-	if (phy == DPIO_PHY0)
-		ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
-			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
-			   "BXT_PORT_CL2CM_DW6_BC");
-
-	/*
-	 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
-	 * at least on stepping A this bit is read-only and fixed at 0.
-	 */
-
-	if (phy == DPIO_PHY0) {
-		u32 grc_code = dev_priv->bxt_phy_grc;
-
-		grc_code = grc_code << GRC_CODE_FAST_SHIFT |
-			   grc_code << GRC_CODE_SLOW_SHIFT |
-			   grc_code;
-		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
-		       GRC_CODE_NOM_MASK;
-		ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
-			    "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
-
-		mask = GRC_DIS | GRC_RDY_OVRD;
-		ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
-			    "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
-	}
-
-	return ok;
-#undef _CHK
-}
-
-static uint8_t
-bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
-				     uint8_t lane_count)
-{
-	switch (lane_count) {
-	case 1:
-		return 0;
-	case 2:
-		return BIT(2) | BIT(0);
-	case 4:
-		return BIT(3) | BIT(2) | BIT(0);
-	default:
-		MISSING_CASE(lane_count);
-
-		return 0;
-	}
-}
-
 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
 				   struct intel_crtc_state *pipe_config,
 				   struct drm_connector_state *conn_state)
 {
-	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
-	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
-	enum port port = dport->port;
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-	int lane;
-
-	for (lane = 0; lane < 4; lane++) {
-		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
-
-		/*
-		 * Note that on CHV this flag is called UPAR, but has
-		 * the same function.
-		 */
-		val &= ~LATENCY_OPTIM;
-		if (intel_crtc->config->lane_lat_optim_mask & BIT(lane))
-			val |= LATENCY_OPTIM;
-
-		I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
-	}
-}
-
-static uint8_t
-bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
-{
-	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
-	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
-	enum port port = dport->port;
-	int lane;
-	uint8_t mask;
-
-	mask = 0;
-	for (lane = 0; lane < 4; lane++) {
-		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
-
-		if (val & LATENCY_OPTIM)
-			mask |= BIT(lane);
-	}
+	uint8_t mask = intel_crtc->config->lane_lat_optim_mask;
 
-	return mask;
+	bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
 }
 
 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 047f487..edf0cfd 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -23,6 +23,333 @@
 
 #include "intel_drv.h"
 
+bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
+			    enum dpio_phy phy)
+{
+	enum port port;
+
+	if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
+		return false;
+
+	if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
+	     (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
+		DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
+				 phy);
+
+		return false;
+	}
+
+	if (phy == DPIO_PHY1 &&
+	    !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
+		DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
+
+		return false;
+	}
+
+	if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
+		DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
+				 phy);
+
+		return false;
+	}
+
+	for_each_port_masked(port,
+			     phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
+						BIT(PORT_A)) {
+		u32 tmp = I915_READ(BXT_PHY_CTL(port));
+
+		if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
+			DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
+					 "for port %c powered down "
+					 "(PHY_CTL %08x)\n",
+					 phy, port_name(port), tmp);
+
+			return false;
+		}
+	}
+
+	return true;
+}
+
+static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+{
+	u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
+
+	return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
+}
+
+static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
+				  enum dpio_phy phy)
+{
+	if (intel_wait_for_register(dev_priv,
+				    BXT_PORT_REF_DW3(phy),
+				    GRC_DONE, GRC_DONE,
+				    10))
+		DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
+}
+
+void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+{
+	u32 val;
+
+	if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
+		/* Still read out the GRC value for state verification */
+		if (phy == DPIO_PHY0)
+			dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
+
+		if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
+			DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
+					 "won't reprogram it\n", phy);
+
+			return;
+		}
+
+		DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
+				 "force reprogramming it\n", phy);
+	}
+
+	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
+	val |= GT_DISPLAY_POWER_ON(phy);
+	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
+
+	/*
+	 * The PHY registers start out inaccessible and respond to reads with
+	 * all 1s.  Eventually they become accessible as they power up, then
+	 * the reserved bit will give the default 0.  Poll on the reserved bit
+	 * becoming 0 to find when the PHY is accessible.
+	 * HW team confirmed that the time to reach phypowergood status is
+	 * anywhere between 50 us and 100us.
+	 */
+	if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
+		(PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
+		DRM_ERROR("timeout during PHY%d power on\n", phy);
+	}
+
+	/* Program PLL Rcomp code offset */
+	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
+	val &= ~IREF0RC_OFFSET_MASK;
+	val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
+	I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
+
+	val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
+	val &= ~IREF1RC_OFFSET_MASK;
+	val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
+	I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
+
+	/* Program power gating */
+	val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
+	val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
+		SUS_CLK_CONFIG;
+	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
+
+	if (phy == DPIO_PHY0) {
+		val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
+		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
+		I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
+	}
+
+	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
+	val &= ~OCL2_LDOFUSE_PWR_DIS;
+	/*
+	 * On PHY1 disable power on the second channel, since no port is
+	 * connected there. On PHY0 both channels have a port, so leave it
+	 * enabled.
+	 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
+	 * power down the second channel on PHY0 as well.
+	 *
+	 * FIXME: Clarify programming of the following, the register is
+	 * read-only with bit 6 fixed at 0 at least in stepping A.
+	 */
+	if (phy == DPIO_PHY1)
+		val |= OCL2_LDOFUSE_PWR_DIS;
+	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
+
+	if (phy == DPIO_PHY0) {
+		uint32_t grc_code;
+		/*
+		 * PHY0 isn't connected to an RCOMP resistor so copy over
+		 * the corresponding calibrated value from PHY1, and disable
+		 * the automatic calibration on PHY0.
+		 */
+		val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
+		grc_code = val << GRC_CODE_FAST_SHIFT |
+			   val << GRC_CODE_SLOW_SHIFT |
+			   val;
+		I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
+
+		val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
+		val |= GRC_DIS | GRC_RDY_OVRD;
+		I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
+	}
+
+	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
+	val |= COMMON_RESET_DIS;
+	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
+
+	if (phy == DPIO_PHY1)
+		bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
+}
+
+void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+{
+	uint32_t val;
+
+	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
+	val &= ~COMMON_RESET_DIS;
+	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
+
+	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
+	val &= ~GT_DISPLAY_POWER_ON(phy);
+	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
+}
+
+static bool __printf(6, 7)
+__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
+		       i915_reg_t reg, u32 mask, u32 expected,
+		       const char *reg_fmt, ...)
+{
+	struct va_format vaf;
+	va_list args;
+	u32 val;
+
+	val = I915_READ(reg);
+	if ((val & mask) == expected)
+		return true;
+
+	va_start(args, reg_fmt);
+	vaf.fmt = reg_fmt;
+	vaf.va = &args;
+
+	DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
+			 "current %08x, expected %08x (mask %08x)\n",
+			 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
+			 mask);
+
+	va_end(args);
+
+	return false;
+}
+
+bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
+			      enum dpio_phy phy)
+{
+	uint32_t mask;
+	bool ok;
+
+#define _CHK(reg, mask, exp, fmt, ...)					\
+	__phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt,	\
+			       ## __VA_ARGS__)
+
+	if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
+		return false;
+
+	ok = true;
+
+	/* PLL Rcomp code offset */
+	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
+		    IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
+		    "BXT_PORT_CL1CM_DW9(%d)", phy);
+	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
+		    IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
+		    "BXT_PORT_CL1CM_DW10(%d)", phy);
+
+	/* Power gating */
+	mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
+	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
+		    "BXT_PORT_CL1CM_DW28(%d)", phy);
+
+	if (phy == DPIO_PHY0)
+		ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
+			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
+			   "BXT_PORT_CL2CM_DW6_BC");
+
+	/*
+	 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
+	 * at least on stepping A this bit is read-only and fixed at 0.
+	 */
+
+	if (phy == DPIO_PHY0) {
+		u32 grc_code = dev_priv->bxt_phy_grc;
+
+		grc_code = grc_code << GRC_CODE_FAST_SHIFT |
+			   grc_code << GRC_CODE_SLOW_SHIFT |
+			   grc_code;
+		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
+		       GRC_CODE_NOM_MASK;
+		ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
+			    "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
+
+		mask = GRC_DIS | GRC_RDY_OVRD;
+		ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
+			    "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
+	}
+
+	return ok;
+#undef _CHK
+}
+
+uint8_t
+bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
+				     uint8_t lane_count)
+{
+	switch (lane_count) {
+	case 1:
+		return 0;
+	case 2:
+		return BIT(2) | BIT(0);
+	case 4:
+		return BIT(3) | BIT(2) | BIT(0);
+	default:
+		MISSING_CASE(lane_count);
+
+		return 0;
+	}
+}
+
+void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
+				     uint8_t lane_lat_optim_mask)
+{
+	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
+	enum port port = dport->port;
+	int lane;
+
+	for (lane = 0; lane < 4; lane++) {
+		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
+
+		/*
+		 * Note that on CHV this flag is called UPAR, but has
+		 * the same function.
+		 */
+		val &= ~LATENCY_OPTIM;
+		if (lane_lat_optim_mask & BIT(lane))
+			val |= LATENCY_OPTIM;
+
+		I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
+	}
+}
+
+uint8_t
+bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
+{
+	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
+	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
+	enum port port = dport->port;
+	int lane;
+	uint8_t mask;
+
+	mask = 0;
+	for (lane = 0; lane < 4; lane++) {
+		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
+
+		if (val & LATENCY_OPTIM)
+			mask |= BIT(lane);
+	}
+
+	return mask;
+}
+
+
 void chv_set_phy_signal_level(struct intel_encoder *encoder,
 			      u32 deemph_reg_value, u32 margin_reg_value,
 			      bool uniq_trans_scale)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f48e79a..c150807 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1328,12 +1328,6 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
-void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
-void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
-bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
-			    enum dpio_phy phy);
-bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
-			      enum dpio_phy phy);
 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
-- 
2.5.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 5/9] drm/i915: Move DPIO phy documentation section to intel_dpio_phy.c

[Ander Conselvan de Oliveira]

Move the DPIO phy documentation section to intel_dpio_phy.c, since that
is a more suitable place now that there is a source file dedicated for
those phys.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 Documentation/gpu/i915.rst            |  2 +-
 drivers/gpu/drm/i915/i915_reg.h       | 91 +----------------------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 91 +++++++++++++++++++++++++++++++++++
 3 files changed, 93 insertions(+), 91 deletions(-)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 87aaffc..8cecae1 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -180,7 +180,7 @@ Display Refresh Rate Switching (DRRS)
 DPIO
 ----
 
-.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
+.. kernel-doc:: drivers/gpu/drm/i915/intel_dpio_phy.c
    :doc: DPIO
 
 CSR firmware support for DMC
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index acc767a..f6d29fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -831,96 +831,7 @@ enum skl_disp_power_wells {
 #define  CCK_FREQUENCY_STATUS_SHIFT		8
 #define  CCK_FREQUENCY_VALUES			(0x1f << 0)
 
-/**
- * DOC: DPIO
- *
- * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
- * ports. DPIO is the name given to such a display PHY. These PHYs
- * don't follow the standard programming model using direct MMIO
- * registers, and instead their registers must be accessed trough IOSF
- * sideband. VLV has one such PHY for driving ports B and C, and CHV
- * adds another PHY for driving port D. Each PHY responds to specific
- * IOSF-SB port.
- *
- * Each display PHY is made up of one or two channels. Each channel
- * houses a common lane part which contains the PLL and other common
- * logic. CH0 common lane also contains the IOSF-SB logic for the
- * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
- * must be running when any DPIO registers are accessed.
- *
- * In addition to having their own registers, the PHYs are also
- * controlled through some dedicated signals from the display
- * controller. These include PLL reference clock enable, PLL enable,
- * and CRI clock selection, for example.
- *
- * Eeach channel also has two splines (also called data lanes), and
- * each spline is made up of one Physical Access Coding Sub-Layer
- * (PCS) block and two TX lanes. So each channel has two PCS blocks
- * and four TX lanes. The TX lanes are used as DP lanes or TMDS
- * data/clock pairs depending on the output type.
- *
- * Additionally the PHY also contains an AUX lane with AUX blocks
- * for each channel. This is used for DP AUX communication, but
- * this fact isn't really relevant for the driver since AUX is
- * controlled from the display controller side. No DPIO registers
- * need to be accessed during AUX communication,
- *
- * Generally on VLV/CHV the common lane corresponds to the pipe and
- * the spline (PCS/TX) corresponds to the port.
- *
- * For dual channel PHY (VLV/CHV):
- *
- *  pipe A == CMN/PLL/REF CH0
- *
- *  pipe B == CMN/PLL/REF CH1
- *
- *  port B == PCS/TX CH0
- *
- *  port C == PCS/TX CH1
- *
- * This is especially important when we cross the streams
- * ie. drive port B with pipe B, or port C with pipe A.
- *
- * For single channel PHY (CHV):
- *
- *  pipe C == CMN/PLL/REF CH0
- *
- *  port D == PCS/TX CH0
- *
- * On BXT the entire PHY channel corresponds to the port. That means
- * the PLL is also now associated with the port rather than the pipe,
- * and so the clock needs to be routed to the appropriate transcoder.
- * Port A PLL is directly connected to transcoder EDP and port B/C
- * PLLs can be routed to any transcoder A/B/C.
- *
- * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
- * digital port D (CHV) or port A (BXT). ::
- *
- *
- *     Dual channel PHY (VLV/CHV/BXT)
- *     ---------------------------------
- *     |      CH0      |      CH1      |
- *     |  CMN/PLL/REF  |  CMN/PLL/REF  |
- *     |---------------|---------------| Display PHY
- *     | PCS01 | PCS23 | PCS01 | PCS23 |
- *     |-------|-------|-------|-------|
- *     |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
- *     ---------------------------------
- *     |     DDI0      |     DDI1      | DP/HDMI ports
- *     ---------------------------------
- *
- *     Single channel PHY (CHV/BXT)
- *     -----------------
- *     |      CH0      |
- *     |  CMN/PLL/REF  |
- *     |---------------| Display PHY
- *     | PCS01 | PCS23 |
- *     |-------|-------|
- *     |TX0|TX1|TX2|TX3|
- *     -----------------
- *     |     DDI2      | DP/HDMI port
- *     -----------------
- */
+/* DPIO registers */
 #define DPIO_DEVFN			0
 
 #define DPIO_CTL			_MMIO(VLV_DISPLAY_BASE + 0x2110)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index edf0cfd..6806296 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -23,6 +23,97 @@
 
 #include "intel_drv.h"
 
+/**
+ * DOC: DPIO
+ *
+ * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
+ * ports. DPIO is the name given to such a display PHY. These PHYs
+ * don't follow the standard programming model using direct MMIO
+ * registers, and instead their registers must be accessed trough IOSF
+ * sideband. VLV has one such PHY for driving ports B and C, and CHV
+ * adds another PHY for driving port D. Each PHY responds to specific
+ * IOSF-SB port.
+ *
+ * Each display PHY is made up of one or two channels. Each channel
+ * houses a common lane part which contains the PLL and other common
+ * logic. CH0 common lane also contains the IOSF-SB logic for the
+ * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
+ * must be running when any DPIO registers are accessed.
+ *
+ * In addition to having their own registers, the PHYs are also
+ * controlled through some dedicated signals from the display
+ * controller. These include PLL reference clock enable, PLL enable,
+ * and CRI clock selection, for example.
+ *
+ * Eeach channel also has two splines (also called data lanes), and
+ * each spline is made up of one Physical Access Coding Sub-Layer
+ * (PCS) block and two TX lanes. So each channel has two PCS blocks
+ * and four TX lanes. The TX lanes are used as DP lanes or TMDS
+ * data/clock pairs depending on the output type.
+ *
+ * Additionally the PHY also contains an AUX lane with AUX blocks
+ * for each channel. This is used for DP AUX communication, but
+ * this fact isn't really relevant for the driver since AUX is
+ * controlled from the display controller side. No DPIO registers
+ * need to be accessed during AUX communication,
+ *
+ * Generally on VLV/CHV the common lane corresponds to the pipe and
+ * the spline (PCS/TX) corresponds to the port.
+ *
+ * For dual channel PHY (VLV/CHV):
+ *
+ *  pipe A == CMN/PLL/REF CH0
+ *
+ *  pipe B == CMN/PLL/REF CH1
+ *
+ *  port B == PCS/TX CH0
+ *
+ *  port C == PCS/TX CH1
+ *
+ * This is especially important when we cross the streams
+ * ie. drive port B with pipe B, or port C with pipe A.
+ *
+ * For single channel PHY (CHV):
+ *
+ *  pipe C == CMN/PLL/REF CH0
+ *
+ *  port D == PCS/TX CH0
+ *
+ * On BXT the entire PHY channel corresponds to the port. That means
+ * the PLL is also now associated with the port rather than the pipe,
+ * and so the clock needs to be routed to the appropriate transcoder.
+ * Port A PLL is directly connected to transcoder EDP and port B/C
+ * PLLs can be routed to any transcoder A/B/C.
+ *
+ * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
+ * digital port D (CHV) or port A (BXT). ::
+ *
+ *
+ *     Dual channel PHY (VLV/CHV/BXT)
+ *     ---------------------------------
+ *     |      CH0      |      CH1      |
+ *     |  CMN/PLL/REF  |  CMN/PLL/REF  |
+ *     |---------------|---------------| Display PHY
+ *     | PCS01 | PCS23 | PCS01 | PCS23 |
+ *     |-------|-------|-------|-------|
+ *     |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
+ *     ---------------------------------
+ *     |     DDI0      |     DDI1      | DP/HDMI ports
+ *     ---------------------------------
+ *
+ *     Single channel PHY (CHV/BXT)
+ *     -----------------
+ *     |      CH0      |
+ *     |  CMN/PLL/REF  |
+ *     |---------------| Display PHY
+ *     | PCS01 | PCS23 |
+ *     |-------|-------|
+ *     |TX0|TX1|TX2|TX3|
+ *     -----------------
+ *     |     DDI2      | DP/HDMI port
+ *     -----------------
+ */
+
 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
 			    enum dpio_phy phy)
 {
-- 
2.5.5

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[PATCH 6/9] drm/i915: Move broxton vswing sequence to intel_dpio_phy.c

[Ander Conselvan de Oliveira]

The vswing sequence is related to the DPIO phy, so move it closer to the
rest of DPIO phy related code.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  3 +++
 drivers/gpu/drm/i915/intel_ddi.c      | 38 +++++-----------------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 39 +++++++++++++++++++++++++++++++++++
 3 files changed, 47 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8bdbbb5..77f1374 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3735,6 +3735,9 @@ u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 
 /* intel_dpio_phy.c */
+void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
+				  enum port port, u32 margin, u32 scale,
+				  u32 enable, u32 deemphasis);
 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index d69d231..f27cd67 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1477,7 +1477,6 @@ static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
 {
 	const struct bxt_ddi_buf_trans *ddi_translations;
 	u32 n_entries, i;
-	uint32_t val;
 
 	if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 		n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
@@ -1506,38 +1505,11 @@ static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
 		}
 	}
 
-	/*
-	 * While we write to the group register to program all lanes at once we
-	 * can read only lane registers and we pick lanes 0/1 for that.
-	 */
-	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
-	val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
-	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
-
-	val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
-	val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
-	val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
-	       ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
-	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
-
-	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
-	val &= ~SCALE_DCOMP_METHOD;
-	if (ddi_translations[level].enable)
-		val |= SCALE_DCOMP_METHOD;
-
-	if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
-		DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
-
-	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
-
-	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
-	val &= ~DE_EMPHASIS;
-	val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
-	I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
-
-	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
-	val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
-	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
+	bxt_ddi_phy_set_signal_level(dev_priv, port,
+				     ddi_translations[level].margin,
+				     ddi_translations[level].scale,
+				     ddi_translations[level].enable,
+				     ddi_translations[level].deemphasis);
 }
 
 static uint32_t translate_signal_level(int signal_levels)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 6806296..2a18724 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -114,6 +114,45 @@
  *     -----------------
  */
 
+void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
+				  enum port port, u32 margin, u32 scale,
+				  u32 enable, u32 deemphasis)
+{
+	u32 val;
+
+	/*
+	 * While we write to the group register to program all lanes at once we
+	 * can read only lane registers and we pick lanes 0/1 for that.
+	 */
+	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
+	val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
+	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
+
+	val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
+	val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
+	val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT;
+	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
+
+	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
+	val &= ~SCALE_DCOMP_METHOD;
+	if (enable)
+		val |= SCALE_DCOMP_METHOD;
+
+	if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
+		DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
+
+	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
+
+	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
+	val &= ~DE_EMPHASIS;
+	val |= deemphasis << DEEMPH_SHIFT;
+	I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
+
+	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
+	val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
+	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
+}
+
 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
 			    enum dpio_phy phy)
 {
-- 
2.5.5

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[PATCH 7/9] drm/i915: Create a struct to hold information about the broxton phys

[Ander Conselvan de Oliveira]

Information about which phy is dual channel is hardcoded in the phy init
sequence. Split that to a separate struct so the init sequence is more
generic.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h       |  9 +++--
 drivers/gpu/drm/i915/intel_dpio_phy.c | 63 +++++++++++++++++++++++++++++------
 2 files changed, 60 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6d29fb..d3802c6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1308,8 +1308,13 @@ enum skl_disp_power_wells {
 #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
 							_PORT_CL1CM_DW30_A)
 
-/* Defined for PHY0 only */
-#define BXT_PORT_CL2CM_DW6_BC		_MMIO(0x6C358)
+/* The spec defines this only for BXT PHY0, but lets assume that this
+ * would exist for PHY1 too if it had a second channel.
+ */
+#define _PORT_CL2CM_DW6_A		0x162358
+#define _PORT_CL2CM_DW6_BC		0x6C358
+#define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC, \
+							_PORT_CL2CM_DW6_A)
 #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
 
 /* BXT PHY Ref registers */
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 2a18724..66d750a 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -114,6 +114,49 @@
  *     -----------------
  */
 
+/**
+ * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
+ */
+struct bxt_ddi_phy_info {
+	/**
+	 * @dual_channel: true if this phy has a second channel.
+	 */
+	bool dual_channel;
+
+	/**
+	 * @channel: struct containing per channel information.
+	 */
+	struct {
+		/**
+		 * @port: which port maps to this channel.
+		 */
+		enum port port;
+	} channel[2];
+};
+
+static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
+	[DPIO_PHY0] = {
+		.dual_channel = true,
+
+		.channel = {
+			[DPIO_CH0] = { .port = PORT_B },
+			[DPIO_CH1] = { .port = PORT_C },
+		}
+	},
+	[DPIO_PHY1] = {
+		.dual_channel = false,
+
+		.channel = {
+			[DPIO_CH0] = { .port = PORT_A },
+		}
+	},
+};
+
+{
+	return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) |
+		BIT(phy_info->channel[DPIO_CH0].port);
+}
+
 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
 				  enum port port, u32 margin, u32 scale,
 				  u32 enable, u32 deemphasis)
@@ -183,9 +226,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
 		return false;
 	}
 
-	for_each_port_masked(port,
-			     phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
-						BIT(PORT_A)) {
+	for_each_port_masked(port, bxt_phy_port_mask(phy_info)) {
 		u32 tmp = I915_READ(BXT_PHY_CTL(port));
 
 		if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
@@ -220,6 +261,7 @@ static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
 
 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 {
+	const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
 	u32 val;
 
 	if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
@@ -272,10 +314,10 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 		SUS_CLK_CONFIG;
 	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
 
-	if (phy == DPIO_PHY0) {
-		val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
+	if (phy_info->dual_channel) {
+		val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
 		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
-		I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
+		I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
 	}
 
 	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
@@ -290,7 +332,7 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 	 * FIXME: Clarify programming of the following, the register is
 	 * read-only with bit 6 fixed at 0 at least in stepping A.
 	 */
-	if (phy == DPIO_PHY1)
+	if (!phy_info->dual_channel)
 		val |= OCL2_LDOFUSE_PWR_DIS;
 	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
 
@@ -363,6 +405,7 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
 			      enum dpio_phy phy)
 {
+	const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
 	uint32_t mask;
 	bool ok;
 
@@ -388,10 +431,10 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
 	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
 		    "BXT_PORT_CL1CM_DW28(%d)", phy);
 
-	if (phy == DPIO_PHY0)
-		ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
+	if (phy_info->dual_channel)
+		ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
 			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
-			   "BXT_PORT_CL2CM_DW6_BC");
+			   "BXT_PORT_CL2CM_DW6(%d)", phy);
 
 	/*
 	 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
-- 
2.5.5

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Re: [PATCH 7/9] drm/i915: Create a struct to hold information about the broxton phys

[Imre Deak]

On ke, 2016-10-05 at 15:09 +0300, Ander Conselvan de Oliveira wrote:
> Information about which phy is dual channel is hardcoded in the phy init
> sequence. Split that to a separate struct so the init sequence is more
> generic.
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> ---
>  drivers/gpu/drm/i915/i915_reg.h       |  9 +++--
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 63 +++++++++++++++++++++++++++++------
>  2 files changed, 60 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f6d29fb..d3802c6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1308,8 +1308,13 @@ enum skl_disp_power_wells {
>  #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
>  							_PORT_CL1CM_DW30_A)
>  
> -/* Defined for PHY0 only */
> -#define BXT_PORT_CL2CM_DW6_BC		_MMIO(0x6C358)
> +/* The spec defines this only for BXT PHY0, but lets assume that this
> + * would exist for PHY1 too if it had a second channel.
> + */
> +#define _PORT_CL2CM_DW6_A		0x162358
> +#define _PORT_CL2CM_DW6_BC		0x6C358
> +#define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC, \
> +							_PORT_CL2CM_DW6_A)
>  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
>  
>  /* BXT PHY Ref registers */
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 2a18724..66d750a 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -114,6 +114,49 @@
>   *     -----------------
>   */
>  
> +/**
> + * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
> + */
> +struct bxt_ddi_phy_info {
> +	/**
> +	 * @dual_channel: true if this phy has a second channel.
> +	 */
> +	bool dual_channel;
> +
> +	/**
> +	 * @channel: struct containing per channel information.
> +	 */
> +	struct {
> +		/**
> +		 * @port: which port maps to this channel.
> +		 */
> +		enum port port;
> +	} channel[2];
> +};
> +
> +static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
> +	[DPIO_PHY0] = {
> +		.dual_channel = true,
> +
> +		.channel = {
> +			[DPIO_CH0] = { .port = PORT_B },
> +			[DPIO_CH1] = { .port = PORT_C },
> +		}
> +	},
> +	[DPIO_PHY1] = {
> +		.dual_channel = false,
> +
> +		.channel = {
> +			[DPIO_CH0] = { .port = PORT_A },
> +		}
> +	},
> +};
> +
> +{

Missing part above, got mangled into the next patch.

> +	return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) |
> +		BIT(phy_info->channel[DPIO_CH0].port);
> +}
> +
>  void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
>  				  enum port port, u32 margin, u32 scale,
>  				  u32 enable, u32 deemphasis)
> @@ -183,9 +226,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
>  		return false;
>  	}
>  
> -	for_each_port_masked(port,
> -			     phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
> -						BIT(PORT_A)) {
> +	for_each_port_masked(port, bxt_phy_port_mask(phy_info)) {
>  		u32 tmp = I915_READ(BXT_PHY_CTL(port));
>  
>  		if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
> @@ -220,6 +261,7 @@ static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
>  
>  void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
>  {
> +	const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
>  	u32 val;
>  
>  	if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
> @@ -272,10 +314,10 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
>  		SUS_CLK_CONFIG;
>  	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
>  
> -	if (phy == DPIO_PHY0) {
> -		val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
> +	if (phy_info->dual_channel) {
> +		val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
>  		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
> -		I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
> +		I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
>  	}
>  
>  	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
> @@ -290,7 +332,7 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
>  	 * FIXME: Clarify programming of the following, the register is
>  	 * read-only with bit 6 fixed at 0 at least in stepping A.
>  	 */
> -	if (phy == DPIO_PHY1)
> +	if (!phy_info->dual_channel)
>  		val |= OCL2_LDOFUSE_PWR_DIS;
>  	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
>  
> @@ -363,6 +405,7 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
>  bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
>  			      enum dpio_phy phy)
>  {
> +	const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
>  	uint32_t mask;
>  	bool ok;
>  
> @@ -388,10 +431,10 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
>  	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
>  		    "BXT_PORT_CL1CM_DW28(%d)", phy);
>  
> -	if (phy == DPIO_PHY0)
> -		ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
> +	if (phy_info->dual_channel)
> +		ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
>  			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
> -			   "BXT_PORT_CL2CM_DW6_BC");
> +			   "BXT_PORT_CL2CM_DW6(%d)", phy);
>  
>  	/*
>  	 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
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Re: [PATCH 7/9] drm/i915: Create a struct to hold information about the broxton phys

[Imre Deak]

On ke, 2016-10-05 at 15:09 +0300, Ander Conselvan de Oliveira wrote:
> Information about which phy is dual channel is hardcoded in the phy init
> sequence. Split that to a separate struct so the init sequence is more
> generic.
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> ---
>  drivers/gpu/drm/i915/i915_reg.h       |  9 +++--
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 63 +++++++++++++++++++++++++++++------
>  2 files changed, 60 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f6d29fb..d3802c6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1308,8 +1308,13 @@ enum skl_disp_power_wells {
>  #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
>  							_PORT_CL1CM_DW30_A)
>  
> -/* Defined for PHY0 only */
> -#define BXT_PORT_CL2CM_DW6_BC		_MMIO(0x6C358)
> +/* The spec defines this only for BXT PHY0, but lets assume that this
> + * would exist for PHY1 too if it had a second channel.
> + */
> +#define _PORT_CL2CM_DW6_A		0x162358
> +#define _PORT_CL2CM_DW6_BC		0x6C358
> +#define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC, \
> +							_PORT_CL2CM_DW6_A)
>  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
>  
>  /* BXT PHY Ref registers */
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 2a18724..66d750a 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -114,6 +114,49 @@
>   *     -----------------
>   */
>  
> +/**
> + * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
> + */
> +struct bxt_ddi_phy_info {
> +	/**
> +	 * @dual_channel: true if this phy has a second channel.
> +	 */
> +	bool dual_channel;
> +
> +	/**
> +	 * @channel: struct containing per channel information.
> +	 */
> +	struct {
> +		/**
> +		 * @port: which port maps to this channel.
> +		 */
> +		enum port port;
> +	} channel[2];

Nitpick: could this be just a port mask?

Patches 1-8 look good to me, with or without the nit changes on those:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +};
> +
> +static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
> +	[DPIO_PHY0] = {
> +		.dual_channel = true,
> +
> +		.channel = {
> +			[DPIO_CH0] = { .port = PORT_B },
> +			[DPIO_CH1] = { .port = PORT_C },
> +		}
> +	},
> +	[DPIO_PHY1] = {
> +		.dual_channel = false,
> +
> +		.channel = {
> +			[DPIO_CH0] = { .port = PORT_A },
> +		}
> +	},
> +};
> +
> +{
> +	return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) |
> +		BIT(phy_info->channel[DPIO_CH0].port);
> +}
> +
>  void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
>  				  enum port port, u32 margin, u32 scale,
>  				  u32 enable, u32 deemphasis)
> @@ -183,9 +226,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
>  		return false;
>  	}
>  
> -	for_each_port_masked(port,
> -			     phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
> -						BIT(PORT_A)) {
> +	for_each_port_masked(port, bxt_phy_port_mask(phy_info)) {
>  		u32 tmp = I915_READ(BXT_PHY_CTL(port));
>  
>  		if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
> @@ -220,6 +261,7 @@ static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
>  
>  void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
>  {
> +	const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
>  	u32 val;
>  
>  	if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
> @@ -272,10 +314,10 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
>  		SUS_CLK_CONFIG;
>  	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
>  
> -	if (phy == DPIO_PHY0) {
> -		val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
> +	if (phy_info->dual_channel) {
> +		val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
>  		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
> -		I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
> +		I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
>  	}
>  
>  	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
> @@ -290,7 +332,7 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
>  	 * FIXME: Clarify programming of the following, the register is
>  	 * read-only with bit 6 fixed at 0 at least in stepping A.
>  	 */
> -	if (phy == DPIO_PHY1)
> +	if (!phy_info->dual_channel)
>  		val |= OCL2_LDOFUSE_PWR_DIS;
>  	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
>  
> @@ -363,6 +405,7 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
>  bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
>  			      enum dpio_phy phy)
>  {
> +	const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
>  	uint32_t mask;
>  	bool ok;
>  
> @@ -388,10 +431,10 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
>  	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
>  		    "BXT_PORT_CL1CM_DW28(%d)", phy);
>  
> -	if (phy == DPIO_PHY0)
> -		ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
> +	if (phy_info->dual_channel)
> +		ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
>  			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
> -			   "BXT_PORT_CL2CM_DW6_BC");
> +			   "BXT_PORT_CL2CM_DW6(%d)", phy);
>  
>  	/*
>  	 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
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Re: [PATCH 7/9] drm/i915: Create a struct to hold information about the broxton phys

[Imre Deak]

On to, 2016-10-06 at 12:56 +0300, Imre Deak wrote:
> On ke, 2016-10-05 at 15:09 +0300, Ander Conselvan de Oliveira wrote:
> > Information about which phy is dual channel is hardcoded in the phy
> > init
> > sequence. Split that to a separate struct so the init sequence is
> > more
> > generic.
> > 
> > Signed-off-by: Ander Conselvan de Oliveira 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h       |  9 +++--
> >  drivers/gpu/drm/i915/intel_dpio_phy.c | 63
> > +++++++++++++++++++++++++++++------
> >  2 files changed, 60 insertions(+), 12 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index f6d29fb..d3802c6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1308,8 +1308,13 @@ enum skl_disp_power_wells {
> >  #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy),
> > _PORT_CL1CM_DW30_BC, \
> >  							_PORT_CL1C
> > M_DW30_A)
> >  
> > -/* Defined for PHY0 only */
> > -#define BXT_PORT_CL2CM_DW6_BC		_MMIO(0x6C358)
> > +/* The spec defines this only for BXT PHY0, but lets assume that
> > this
> > + * would exist for PHY1 too if it had a second channel.
> > + */
> > +#define _PORT_CL2CM_DW6_A		0x162358
> > +#define _PORT_CL2CM_DW6_BC		0x6C358
> > +#define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy),
> > _PORT_CL2CM_DW6_BC, \
> > +							_PORT_CL2C
> > M_DW6_A)
> >  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
> >  
> >  /* BXT PHY Ref registers */
> > diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > index 2a18724..66d750a 100644
> > --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > @@ -114,6 +114,49 @@
> >   *     -----------------
> >   */
> >  
> > +/**
> > + * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
> > + */
> > +struct bxt_ddi_phy_info {
> > +	/**
> > +	 * @dual_channel: true if this phy has a second channel.
> > +	 */
> > +	bool dual_channel;
> > +
> > +	/**
> > +	 * @channel: struct containing per channel information.
> > +	 */
> > +	struct {
> > +		/**
> > +		 * @port: which port maps to this channel.
> > +		 */
> > +		enum port port;
> > +	} channel[2];
> 
> Nitpick: could this be just a port mask?

Ah, just noticed in patch 9 that it cannot, so ignore the above.

> 
> Patches 1-8 look good to me, with or without the nit changes on
> those:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> > +};
> > +
> > +static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
> > +	[DPIO_PHY0] = {
> > +		.dual_channel = true,
> > +
> > +		.channel = {
> > +			[DPIO_CH0] = { .port = PORT_B },
> > +			[DPIO_CH1] = { .port = PORT_C },
> > +		}
> > +	},
> > +	[DPIO_PHY1] = {
> > +		.dual_channel = false,
> > +
> > +		.channel = {
> > +			[DPIO_CH0] = { .port = PORT_A },
> > +		}
> > +	},
> > +};
> > +
> > +{
> > +	return (phy_info->dual_channel * BIT(phy_info-
> > >channel[DPIO_CH1].port)) |
> > +		BIT(phy_info->channel[DPIO_CH0].port);
> > +}
> > +
> >  void bxt_ddi_phy_set_signal_level(struct drm_i915_private
> > *dev_priv,
> >  				  enum port port, u32 margin, u32
> > scale,
> >  				  u32 enable, u32 deemphasis)
> > @@ -183,9 +226,7 @@ bool bxt_ddi_phy_is_enabled(struct
> > drm_i915_private *dev_priv,
> >  		return false;
> >  	}
> >  
> > -	for_each_port_masked(port,
> > -			     phy == DPIO_PHY0 ? BIT(PORT_B) |
> > BIT(PORT_C) :
> > -						BIT(PORT_A)) {
> > +	for_each_port_masked(port, bxt_phy_port_mask(phy_info)) {
> >  		u32 tmp = I915_READ(BXT_PHY_CTL(port));
> >  
> >  		if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
> > @@ -220,6 +261,7 @@ static void bxt_phy_wait_grc_done(struct
> > drm_i915_private *dev_priv,
> >  
> >  void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum
> > dpio_phy phy)
> >  {
> > +	const struct bxt_ddi_phy_info *phy_info =
> > &bxt_ddi_phy_info[phy];
> >  	u32 val;
> >  
> >  	if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
> > @@ -272,10 +314,10 @@ void bxt_ddi_phy_init(struct drm_i915_private
> > *dev_priv, enum dpio_phy phy)
> >  		SUS_CLK_CONFIG;
> >  	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
> >  
> > -	if (phy == DPIO_PHY0) {
> > -		val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
> > +	if (phy_info->dual_channel) {
> > +		val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
> >  		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
> > -		I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
> > +		I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
> >  	}
> >  
> >  	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
> > @@ -290,7 +332,7 @@ void bxt_ddi_phy_init(struct drm_i915_private
> > *dev_priv, enum dpio_phy phy)
> >  	 * FIXME: Clarify programming of the following, the
> > register is
> >  	 * read-only with bit 6 fixed at 0 at least in stepping A.
> >  	 */
> > -	if (phy == DPIO_PHY1)
> > +	if (!phy_info->dual_channel)
> >  		val |= OCL2_LDOFUSE_PWR_DIS;
> >  	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
> >  
> > @@ -363,6 +405,7 @@ __phy_reg_verify_state(struct drm_i915_private
> > *dev_priv, enum dpio_phy phy,
> >  bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
> >  			      enum dpio_phy phy)
> >  {
> > +	const struct bxt_ddi_phy_info *phy_info =
> > &bxt_ddi_phy_info[phy];
> >  	uint32_t mask;
> >  	bool ok;
> >  
> > @@ -388,10 +431,10 @@ bool bxt_ddi_phy_verify_state(struct
> > drm_i915_private *dev_priv,
> >  	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
> >  		    "BXT_PORT_CL1CM_DW28(%d)", phy);
> >  
> > -	if (phy == DPIO_PHY0)
> > -		ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
> > +	if (phy_info->dual_channel)
> > +		ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
> >  			   DW6_OLDO_DYN_PWR_DOWN_EN,
> > DW6_OLDO_DYN_PWR_DOWN_EN,
> > -			   "BXT_PORT_CL2CM_DW6_BC");
> > +			   "BXT_PORT_CL2CM_DW6(%d)", phy);
> >  
> >  	/*
> >  	 * TODO: Verify BXT_PORT_CL1CM_DW30 bit
> > OCL2_LDOFUSE_PWR_DIS,
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[PATCH 8/9] drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_info

[Ander Conselvan de Oliveira]

Use struct bxt_ddi_phy_info to hold information of where the Rcomp
resistor is located, instead of hard coding it in the init sequence.

Note that this moves the enabling of the phy with the Rcomp resistor out
of the power well enable code. That should be safe since
bxt_ddi_phy_init() is called while the power domains lock is held, and
that is the only way that function gets called, so there is no
possibility of a concurrent phy enable caused by a power domain get
call.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_dpio_phy.c   | 76 +++++++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_runtime_pm.c | 15 -------
 2 files changed, 59 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 66d750a..e8a75fd 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -124,6 +124,13 @@ struct bxt_ddi_phy_info {
 	bool dual_channel;
 
 	/**
+	 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
+	 * Otherwise the GRC value will be copied from the phy indicated by
+	 * this field.
+	 */
+	enum dpio_phy rcomp_phy;
+
+	/**
 	 * @channel: struct containing per channel information.
 	 */
 	struct {
@@ -137,6 +144,7 @@ struct bxt_ddi_phy_info {
 static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
 	[DPIO_PHY0] = {
 		.dual_channel = true,
+		.rcomp_phy = DPIO_PHY1,
 
 		.channel = {
 			[DPIO_CH0] = { .port = PORT_B },
@@ -145,6 +153,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
 	},
 	[DPIO_PHY1] = {
 		.dual_channel = false,
+		.rcomp_phy = -1,
 
 		.channel = {
 			[DPIO_CH0] = { .port = PORT_A },
@@ -152,6 +161,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
 	},
 };
 
+static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
 {
 	return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) |
 		BIT(phy_info->channel[DPIO_CH0].port);
@@ -199,6 +209,7 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
 			    enum dpio_phy phy)
 {
+	const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
 	enum port port;
 
 	if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
@@ -212,9 +223,10 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
 		return false;
 	}
 
-	if (phy == DPIO_PHY1 &&
-	    !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
-		DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
+	if (phy_info->rcomp_phy == -1 &&
+	    !(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE)) {
+		DRM_DEBUG_DRIVER("DDI PHY %d powered, but GRC isn't done\n",
+				 phy);
 
 		return false;
 	}
@@ -259,14 +271,15 @@ static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
 		DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
 }
 
-void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
+			      enum dpio_phy phy)
 {
 	const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
 	u32 val;
 
 	if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
 		/* Still read out the GRC value for state verification */
-		if (phy == DPIO_PHY0)
+		if (phy_info->rcomp_phy != -1)
 			dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
 
 		if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
@@ -336,30 +349,32 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 		val |= OCL2_LDOFUSE_PWR_DIS;
 	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
 
-	if (phy == DPIO_PHY0) {
+	if (phy_info->rcomp_phy != -1) {
 		uint32_t grc_code;
 		/*
 		 * PHY0 isn't connected to an RCOMP resistor so copy over
 		 * the corresponding calibrated value from PHY1, and disable
 		 * the automatic calibration on PHY0.
 		 */
-		val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
+		val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
+							  phy_info->rcomp_phy);
 		grc_code = val << GRC_CODE_FAST_SHIFT |
 			   val << GRC_CODE_SLOW_SHIFT |
 			   val;
-		I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
+		I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code);
 
-		val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
+		val = I915_READ(BXT_PORT_REF_DW8(phy));
 		val |= GRC_DIS | GRC_RDY_OVRD;
-		I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
+		I915_WRITE(BXT_PORT_REF_DW8(phy), val);
 	}
 
 	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
 	val |= COMMON_RESET_DIS;
 	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
 
-	if (phy == DPIO_PHY1)
-		bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
+	if (phy_info->rcomp_phy == -1)
+		bxt_phy_wait_grc_done(dev_priv, phy);
+
 }
 
 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
@@ -375,6 +390,33 @@ void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
 }
 
+/* This function assumes it is called from an intel_display_power_get() call,
+ * which would serialize any other attempts to enable the phy with the Rcomp
+ * resistor.
+ */
+void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+{
+	const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
+	enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
+	bool was_enabled;
+
+	if (rcomp_phy != -1) {
+		was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy);
+
+		/*
+		 * We need to copy the GRC calibration value from rcomp_phy,
+		 * so make sure it's powered up.
+		 */
+		if (!was_enabled)
+			_bxt_ddi_phy_init(dev_priv, rcomp_phy);
+	}
+
+	_bxt_ddi_phy_init(dev_priv, phy);
+
+	if (rcomp_phy != -1 && !was_enabled)
+		bxt_ddi_phy_uninit(dev_priv, phy_info->rcomp_phy);
+}
+
 static bool __printf(6, 7)
 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 		       i915_reg_t reg, u32 mask, u32 expected,
@@ -441,7 +483,7 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
 	 * at least on stepping A this bit is read-only and fixed at 0.
 	 */
 
-	if (phy == DPIO_PHY0) {
+	if (phy_info->rcomp_phy != -1) {
 		u32 grc_code = dev_priv->bxt_phy_grc;
 
 		grc_code = grc_code << GRC_CODE_FAST_SHIFT |
@@ -449,12 +491,12 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
 			   grc_code;
 		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
 		       GRC_CODE_NOM_MASK;
-		ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
-			    "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
+		ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
+			    "BXT_PORT_REF_DW6(%d)", phy);
 
 		mask = GRC_DIS | GRC_RDY_OVRD;
-		ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
-			    "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
+		ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
+			    "BXT_PORT_REF_DW8(%d)", phy);
 	}
 
 	return ok;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index d41fd46..3b38998 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -849,22 +849,7 @@ static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 					   struct i915_power_well *power_well)
 {
-	enum skl_disp_power_wells power_well_id = power_well->id;
-	struct i915_power_well *cmn_a_well = NULL;
-
-	if (power_well_id == BXT_DPIO_CMN_BC) {
-		/*
-		 * We need to copy the GRC calibration value from the eDP PHY,
-		 * so make sure it's powered up.
-		 */
-		cmn_a_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
-		intel_power_well_get(dev_priv, cmn_a_well);
-	}
-
 	bxt_ddi_phy_init(dev_priv, power_well->data);
-
-	if (cmn_a_well)
-		intel_power_well_put(dev_priv, cmn_a_well);
 }
 
 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
-- 
2.5.5

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Re: [PATCH 8/9] drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_info

[Imre Deak]

On ke, 2016-10-05 at 15:09 +0300, Ander Conselvan de Oliveira wrote:
> Use struct bxt_ddi_phy_info to hold information of where the Rcomp
> resistor is located, instead of hard coding it in the init sequence.
> 
> Note that this moves the enabling of the phy with the Rcomp resistor out
> of the power well enable code. That should be safe since
> bxt_ddi_phy_init() is called while the power domains lock is held, and
> that is the only way that function gets called, so there is no
> possibility of a concurrent phy enable caused by a power domain get
> call.
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> ---
>  drivers/gpu/drm/i915/intel_dpio_phy.c   | 76 +++++++++++++++++++++++++--------
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 15 -------
>  2 files changed, 59 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 66d750a..e8a75fd 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -124,6 +124,13 @@ struct bxt_ddi_phy_info {
>  	bool dual_channel;
>  
>  	/**
> +	 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
> +	 * Otherwise the GRC value will be copied from the phy indicated by
> +	 * this field.
> +	 */
> +	enum dpio_phy rcomp_phy;
> +
> +	/**
>  	 * @channel: struct containing per channel information.
>  	 */
>  	struct {
> @@ -137,6 +144,7 @@ struct bxt_ddi_phy_info {
>  static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
>  	[DPIO_PHY0] = {
>  		.dual_channel = true,
> +		.rcomp_phy = DPIO_PHY1,
>  
>  		.channel = {
>  			[DPIO_CH0] = { .port = PORT_B },
> @@ -145,6 +153,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
>  	},
>  	[DPIO_PHY1] = {
>  		.dual_channel = false,
> +		.rcomp_phy = -1,
>  
>  		.channel = {
>  			[DPIO_CH0] = { .port = PORT_A },
> @@ -152,6 +161,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
>  	},
>  };
>  
> +static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
>  {
>  	return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) |
>  		BIT(phy_info->channel[DPIO_CH0].port);
> @@ -199,6 +209,7 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
>  bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
>  			    enum dpio_phy phy)
>  {
> +	const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
>  	enum port port;
>  
>  	if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
> @@ -212,9 +223,10 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
>  		return false;
>  	}
>  
> -	if (phy == DPIO_PHY1 &&
> -	    !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
> -		DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
> +	if (phy_info->rcomp_phy == -1 &&
> +	    !(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE)) {
> +		DRM_DEBUG_DRIVER("DDI PHY %d powered, but GRC isn't done\n",
> +				 phy);
>  
>  		return false;
>  	}
> @@ -259,14 +271,15 @@ static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
>  		DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
>  }
>  
> -void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> +static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
> +			      enum dpio_phy phy)
>  {
>  	const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
>  	u32 val;
>  
>  	if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
>  		/* Still read out the GRC value for state verification */
> -		if (phy == DPIO_PHY0)
> +		if (phy_info->rcomp_phy != -1)
>  			dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
>  
>  		if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
> @@ -336,30 +349,32 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
>  		val |= OCL2_LDOFUSE_PWR_DIS;
>  	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
>  
> -	if (phy == DPIO_PHY0) {
> +	if (phy_info->rcomp_phy != -1) {
>  		uint32_t grc_code;
>  		/*
>  		 * PHY0 isn't connected to an RCOMP resistor so copy over
>  		 * the corresponding calibrated value from PHY1, and disable
>  		 * the automatic calibration on PHY0.
>  		 */
> -		val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
> +		val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
> +							  phy_info->rcomp_phy);
>  		grc_code = val << GRC_CODE_FAST_SHIFT |
>  			   val << GRC_CODE_SLOW_SHIFT |
>  			   val;
> -		I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
> +		I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code);
>  
> -		val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
> +		val = I915_READ(BXT_PORT_REF_DW8(phy));
>  		val |= GRC_DIS | GRC_RDY_OVRD;
> -		I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
> +		I915_WRITE(BXT_PORT_REF_DW8(phy), val);
>  	}
>  
>  	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
>  	val |= COMMON_RESET_DIS;
>  	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
>  
> -	if (phy == DPIO_PHY1)
> -		bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
> +	if (phy_info->rcomp_phy == -1)
> +		bxt_phy_wait_grc_done(dev_priv, phy);
> +
>  }
>  
>  void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> @@ -375,6 +390,33 @@ void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
>  	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
>  }
>  
> +/* This function assumes it is called from an intel_display_power_get() call,
> + * which would serialize any other attempts to enable the phy with the Rcomp
> + * resistor.
> + */

You could replace the above with a mutex locked assert.

> +void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> +{
> +	const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
> +	enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
> +	bool was_enabled;
> +
> +	if (rcomp_phy != -1) {
> +		was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy);
> +
> +		/*
> +		 * We need to copy the GRC calibration value from rcomp_phy,
> +		 * so make sure it's powered up.
> +		 */
> +		if (!was_enabled)
> +			_bxt_ddi_phy_init(dev_priv, rcomp_phy);
> +	}
> +
> +	_bxt_ddi_phy_init(dev_priv, phy);
> +
> +	if (rcomp_phy != -1 && !was_enabled)
> +		bxt_ddi_phy_uninit(dev_priv, phy_info->rcomp_phy);
> +}

Nitpick: An alternative would be to add the power well dependency as a
custom power well field for the cmn power wells. We'd avoid the
unnecessary HW access in bxt_ddi_phy_is_enabled().

> +
>  static bool __printf(6, 7)
>  __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
>  		       i915_reg_t reg, u32 mask, u32 expected,
> @@ -441,7 +483,7 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
>  	 * at least on stepping A this bit is read-only and fixed at 0.
>  	 */
>  
> -	if (phy == DPIO_PHY0) {
> +	if (phy_info->rcomp_phy != -1) {
>  		u32 grc_code = dev_priv->bxt_phy_grc;
>  
>  		grc_code = grc_code << GRC_CODE_FAST_SHIFT |
> @@ -449,12 +491,12 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
>  			   grc_code;
>  		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
>  		       GRC_CODE_NOM_MASK;
> -		ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
> -			    "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
> +		ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
> +			    "BXT_PORT_REF_DW6(%d)", phy);
>  
>  		mask = GRC_DIS | GRC_RDY_OVRD;
> -		ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
> -			    "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
> +		ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
> +			    "BXT_PORT_REF_DW8(%d)", phy);
>  	}
>  
>  	return ok;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index d41fd46..3b38998 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -849,22 +849,7 @@ static void skl_power_well_disable(struct drm_i915_private *dev_priv,
>  static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
>  					   struct i915_power_well *power_well)
>  {
> -	enum skl_disp_power_wells power_well_id = power_well->id;
> -	struct i915_power_well *cmn_a_well = NULL;
> -
> -	if (power_well_id == BXT_DPIO_CMN_BC) {
> -		/*
> -		 * We need to copy the GRC calibration value from the eDP PHY,
> -		 * so make sure it's powered up.
> -		 */
> -		cmn_a_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
> -		intel_power_well_get(dev_priv, cmn_a_well);
> -	}
> -
>  	bxt_ddi_phy_init(dev_priv, power_well->data);
> -
> -	if (cmn_a_well)
> -		intel_power_well_put(dev_priv, cmn_a_well);
>  }
>  
>  static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
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Re: [PATCH 8/9] drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_info

[Ander Conselvan De Oliveira]

On Wed, 2016-10-05 at 17:51 +0300, Imre Deak wrote:
> On ke, 2016-10-05 at 15:09 +0300, Ander Conselvan de Oliveira wrote:
> > 
> > Use struct bxt_ddi_phy_info to hold information of where the Rcomp
> > resistor is located, instead of hard coding it in the init sequence.
> > 
> > Note that this moves the enabling of the phy with the Rcomp resistor out
> > of the power well enable code. That should be safe since
> > bxt_ddi_phy_init() is called while the power domains lock is held, and
> > that is the only way that function gets called, so there is no
> > possibility of a concurrent phy enable caused by a power domain get
> > call.
> > 
> > Signed-off-by: Ander Conselvan de Oliveira 
> > ---
> >  drivers/gpu/drm/i915/intel_dpio_phy.c   | 76 +++++++++++++++++++++++++-----
> > ---
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 15 -------
> >  2 files changed, 59 insertions(+), 32 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > index 66d750a..e8a75fd 100644
> > --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > @@ -124,6 +124,13 @@ struct bxt_ddi_phy_info {
> >  	bool dual_channel;
> >  
> >  	/**
> > +	 * @rcomp_phy: If -1, indicates this phy has its own rcomp
> > resistor.
> > +	 * Otherwise the GRC value will be copied from the phy indicated by
> > +	 * this field.
> > +	 */
> > +	enum dpio_phy rcomp_phy;
> > +
> > +	/**
> >  	 * @channel: struct containing per channel information.
> >  	 */
> >  	struct {
> > @@ -137,6 +144,7 @@ struct bxt_ddi_phy_info {
> >  static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
> >  	[DPIO_PHY0] = {
> >  		.dual_channel = true,
> > +		.rcomp_phy = DPIO_PHY1,
> >  
> >  		.channel = {
> >  			[DPIO_CH0] = { .port = PORT_B },
> > @@ -145,6 +153,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[]
> > = {
> >  	},
> >  	[DPIO_PHY1] = {
> >  		.dual_channel = false,
> > +		.rcomp_phy = -1,
> >  
> >  		.channel = {
> >  			[DPIO_CH0] = { .port = PORT_A },
> > @@ -152,6 +161,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[]
> > = {
> >  	},
> >  };
> >  
> > +static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
> >  {
> >  	return (phy_info->dual_channel * BIT(phy_info-
> > >channel[DPIO_CH1].port)) |
> >  		BIT(phy_info->channel[DPIO_CH0].port);
> > @@ -199,6 +209,7 @@ void bxt_ddi_phy_set_signal_level(struct
> > drm_i915_private *dev_priv,
> >  bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
> >  			    enum dpio_phy phy)
> >  {
> > +	const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
> >  	enum port port;
> >  
> >  	if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) &
> > GT_DISPLAY_POWER_ON(phy)))
> > @@ -212,9 +223,10 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private
> > *dev_priv,
> >  		return false;
> >  	}
> >  
> > -	if (phy == DPIO_PHY1 &&
> > -	    !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
> > -		DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't
> > done\n");
> > +	if (phy_info->rcomp_phy == -1 &&
> > +	    !(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE)) {
> > +		DRM_DEBUG_DRIVER("DDI PHY %d powered, but GRC isn't
> > done\n",
> > +				 phy);
> >  
> >  		return false;
> >  	}
> > @@ -259,14 +271,15 @@ static void bxt_phy_wait_grc_done(struct
> > drm_i915_private *dev_priv,
> >  		DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
> >  }
> >  
> > -void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> > +static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
> > +			      enum dpio_phy phy)
> >  {
> >  	const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
> >  	u32 val;
> >  
> >  	if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
> >  		/* Still read out the GRC value for state verification */
> > -		if (phy == DPIO_PHY0)
> > +		if (phy_info->rcomp_phy != -1)
> >  			dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
> >  
> >  		if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
> > @@ -336,30 +349,32 @@ void bxt_ddi_phy_init(struct drm_i915_private
> > *dev_priv, enum dpio_phy phy)
> >  		val |= OCL2_LDOFUSE_PWR_DIS;
> >  	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
> >  
> > -	if (phy == DPIO_PHY0) {
> > +	if (phy_info->rcomp_phy != -1) {
> >  		uint32_t grc_code;
> >  		/*
> >  		 * PHY0 isn't connected to an RCOMP resistor so copy over
> >  		 * the corresponding calibrated value from PHY1, and
> > disable
> >  		 * the automatic calibration on PHY0.
> >  		 */
> > -		val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
> > DPIO_PHY1);
> > +		val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
> > +							  phy_info-
> > >rcomp_phy);
> >  		grc_code = val << GRC_CODE_FAST_SHIFT |
> >  			   val << GRC_CODE_SLOW_SHIFT |
> >  			   val;
> > -		I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
> > +		I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code);
> >  
> > -		val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
> > +		val = I915_READ(BXT_PORT_REF_DW8(phy));
> >  		val |= GRC_DIS | GRC_RDY_OVRD;
> > -		I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
> > +		I915_WRITE(BXT_PORT_REF_DW8(phy), val);
> >  	}
> >  
> >  	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> >  	val |= COMMON_RESET_DIS;
> >  	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
> >  
> > -	if (phy == DPIO_PHY1)
> > -		bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
> > +	if (phy_info->rcomp_phy == -1)
> > +		bxt_phy_wait_grc_done(dev_priv, phy);
> > +
> >  }
> >  
> >  void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy
> > phy)
> > @@ -375,6 +390,33 @@ void bxt_ddi_phy_uninit(struct drm_i915_private
> > *dev_priv, enum dpio_phy phy)
> >  	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
> >  }
> >  
> > +/* This function assumes it is called from an intel_display_power_get()
> > call,
> > + * which would serialize any other attempts to enable the phy with the
> > Rcomp
> > + * resistor.
> > + */
> You could replace the above with a mutex locked assert.

I'll do that and resend.

> > 
> > +void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> > +{
> > +	const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
> > +	enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
> > +	bool was_enabled;
> > +
> > +	if (rcomp_phy != -1) {
> > +		was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy);
> > +
> > +		/*
> > +		 * We need to copy the GRC calibration value from
> > rcomp_phy,
> > +		 * so make sure it's powered up.
> > +		 */
> > +		if (!was_enabled)
> > +			_bxt_ddi_phy_init(dev_priv, rcomp_phy);
> > +	}
> > +
> > +	_bxt_ddi_phy_init(dev_priv, phy);
> > +
> > +	if (rcomp_phy != -1 && !was_enabled)
> > +		bxt_ddi_phy_uninit(dev_priv, phy_info->rcomp_phy);
> > +}
> Nitpick: An alternative would be to add the power well dependency as a
> custom power well field for the cmn power wells. We'd avoid the
> unnecessary HW access in bxt_ddi_phy_is_enabled().

Since you gave me the option, I'll choose to ignore this one. What I like about
the current solution is that the dependency relationship between the phys is
captured in a single place, so I'd like to avoid duplicating that information in
the power well code.

I don't think the extra hardware access is performance critical, but if it were,
maybe we could track whether the phy is enabled in the phy code too?

Ander

> 
> > 
> > +
> >  static bool __printf(6, 7)
> >  __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy
> > phy,
> >  		       i915_reg_t reg, u32 mask, u32 expected,
> > @@ -441,7 +483,7 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private
> > *dev_priv,
> >  	 * at least on stepping A this bit is read-only and fixed at 0.
> >  	 */
> >  
> > -	if (phy == DPIO_PHY0) {
> > +	if (phy_info->rcomp_phy != -1) {
> >  		u32 grc_code = dev_priv->bxt_phy_grc;
> >  
> >  		grc_code = grc_code << GRC_CODE_FAST_SHIFT |
> > @@ -449,12 +491,12 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private
> > *dev_priv,
> >  			   grc_code;
> >  		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
> >  		       GRC_CODE_NOM_MASK;
> > -		ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
> > -			    "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
> > +		ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
> > +			    "BXT_PORT_REF_DW6(%d)", phy);
> >  
> >  		mask = GRC_DIS | GRC_RDY_OVRD;
> > -		ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
> > -			    "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
> > +		ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
> > +			    "BXT_PORT_REF_DW8(%d)", phy);
> >  	}
> >  
> >  	return ok;
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index d41fd46..3b38998 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -849,22 +849,7 @@ static void skl_power_well_disable(struct
> > drm_i915_private *dev_priv,
> >  static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private
> > *dev_priv,
> >  					   struct i915_power_well
> > *power_well)
> >  {
> > -	enum skl_disp_power_wells power_well_id = power_well->id;
> > -	struct i915_power_well *cmn_a_well = NULL;
> > -
> > -	if (power_well_id == BXT_DPIO_CMN_BC) {
> > -		/*
> > -		 * We need to copy the GRC calibration value from the eDP
> > PHY,
> > -		 * so make sure it's powered up.
> > -		 */
> > -		cmn_a_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
> > -		intel_power_well_get(dev_priv, cmn_a_well);
> > -	}
> > -
> >  	bxt_ddi_phy_init(dev_priv, power_well->data);
> > -
> > -	if (cmn_a_well)
> > -		intel_power_well_put(dev_priv, cmn_a_well);
> >  }
> >  
> >  static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private
> > *dev_priv,
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Re: [PATCH 8/9] drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_info

[Imre Deak]

On to, 2016-10-06 at 14:50 +0300, Ander Conselvan De Oliveira wrote:
> On Wed, 2016-10-05 at 17:51 +0300, Imre Deak wrote:
> > On ke, 2016-10-05 at 15:09 +0300, Ander Conselvan de Oliveira
> > wrote:
> > > 
> > > Use struct bxt_ddi_phy_info to hold information of where the
> > > Rcomp
> > > resistor is located, instead of hard coding it in the init
> > > sequence.
> > > 
> > > Note that this moves the enabling of the phy with the Rcomp
> > > resistor out
> > > of the power well enable code. That should be safe since
> > > bxt_ddi_phy_init() is called while the power domains lock is
> > > held, and
> > > that is the only way that function gets called, so there is no
> > > possibility of a concurrent phy enable caused by a power domain
> > > get
> > > call.
> > > 
> > > Signed-off-by: Ander Conselvan de Oliveira 
> > > ---
> > >  drivers/gpu/drm/i915/intel_dpio_phy.c   | 76
> > > +++++++++++++++++++++++++-----
> > > ---
> > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 15 -------
> > >  2 files changed, 59 insertions(+), 32 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > > b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > > index 66d750a..e8a75fd 100644
> > > --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > > +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > > @@ -124,6 +124,13 @@ struct bxt_ddi_phy_info {
> > >  	bool dual_channel;
> > >  
> > >  	/**
> > > +	 * @rcomp_phy: If -1, indicates this phy has its own
> > > rcomp
> > > resistor.
> > > +	 * Otherwise the GRC value will be copied from the phy
> > > indicated by
> > > +	 * this field.
> > > +	 */
> > > +	enum dpio_phy rcomp_phy;
> > > +
> > > +	/**
> > >  	 * @channel: struct containing per channel information.
> > >  	 */
> > >  	struct {
> > > @@ -137,6 +144,7 @@ struct bxt_ddi_phy_info {
> > >  static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
> > >  	[DPIO_PHY0] = {
> > >  		.dual_channel = true,
> > > +		.rcomp_phy = DPIO_PHY1,
> > >  
> > >  		.channel = {
> > >  			[DPIO_CH0] = { .port = PORT_B },
> > > @@ -145,6 +153,7 @@ static const struct bxt_ddi_phy_info
> > > bxt_ddi_phy_info[]
> > > = {
> > >  	},
> > >  	[DPIO_PHY1] = {
> > >  		.dual_channel = false,
> > > +		.rcomp_phy = -1,
> > >  
> > >  		.channel = {
> > >  			[DPIO_CH0] = { .port = PORT_A },
> > > @@ -152,6 +161,7 @@ static const struct bxt_ddi_phy_info
> > > bxt_ddi_phy_info[]
> > > = {
> > >  	},
> > >  };
> > >  
> > > +static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info
> > > *phy_info)
> > >  {
> > >  	return (phy_info->dual_channel * BIT(phy_info-
> > > > channel[DPIO_CH1].port)) |
> > >  		BIT(phy_info->channel[DPIO_CH0].port);
> > > @@ -199,6 +209,7 @@ void bxt_ddi_phy_set_signal_level(struct
> > > drm_i915_private *dev_priv,
> > >  bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
> > >  			    enum dpio_phy phy)
> > >  {
> > > +	const struct bxt_ddi_phy_info *phy_info =
> > > &bxt_ddi_phy_info[phy];
> > >  	enum port port;
> > >  
> > >  	if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) &
> > > GT_DISPLAY_POWER_ON(phy)))
> > > @@ -212,9 +223,10 @@ bool bxt_ddi_phy_is_enabled(struct
> > > drm_i915_private
> > > *dev_priv,
> > >  		return false;
> > >  	}
> > >  
> > > -	if (phy == DPIO_PHY1 &&
> > > -	    !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) &
> > > GRC_DONE)) {
> > > -		DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC
> > > isn't
> > > done\n");
> > > +	if (phy_info->rcomp_phy == -1 &&
> > > +	    !(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE)) {
> > > +		DRM_DEBUG_DRIVER("DDI PHY %d powered, but GRC
> > > isn't
> > > done\n",
> > > +				 phy);
> > >  
> > >  		return false;
> > >  	}
> > > @@ -259,14 +271,15 @@ static void bxt_phy_wait_grc_done(struct
> > > drm_i915_private *dev_priv,
> > >  		DRM_ERROR("timeout waiting for PHY%d GRC\n",
> > > phy);
> > >  }
> > >  
> > > -void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum
> > > dpio_phy phy)
> > > +static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
> > > +			      enum dpio_phy phy)
> > >  {
> > >  	const struct bxt_ddi_phy_info *phy_info =
> > > &bxt_ddi_phy_info[phy];
> > >  	u32 val;
> > >  
> > >  	if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
> > >  		/* Still read out the GRC value for state
> > > verification */
> > > -		if (phy == DPIO_PHY0)
> > > +		if (phy_info->rcomp_phy != -1)
> > >  			dev_priv->bxt_phy_grc =
> > > bxt_get_grc(dev_priv, phy);
> > >  
> > >  		if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
> > > @@ -336,30 +349,32 @@ void bxt_ddi_phy_init(struct
> > > drm_i915_private
> > > *dev_priv, enum dpio_phy phy)
> > >  		val |= OCL2_LDOFUSE_PWR_DIS;
> > >  	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
> > >  
> > > -	if (phy == DPIO_PHY0) {
> > > +	if (phy_info->rcomp_phy != -1) {
> > >  		uint32_t grc_code;
> > >  		/*
> > >  		 * PHY0 isn't connected to an RCOMP resistor so
> > > copy over
> > >  		 * the corresponding calibrated value from PHY1,
> > > and
> > > disable
> > >  		 * the automatic calibration on PHY0.
> > >  		 */
> > > -		val = dev_priv->bxt_phy_grc =
> > > bxt_get_grc(dev_priv,
> > > DPIO_PHY1);
> > > +		val = dev_priv->bxt_phy_grc =
> > > bxt_get_grc(dev_priv,
> > > +							  phy_in
> > > fo-
> > > > rcomp_phy);
> > >  		grc_code = val << GRC_CODE_FAST_SHIFT |
> > >  			   val << GRC_CODE_SLOW_SHIFT |
> > >  			   val;
> > > -		I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0),
> > > grc_code);
> > > +		I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code);
> > >  
> > > -		val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
> > > +		val = I915_READ(BXT_PORT_REF_DW8(phy));
> > >  		val |= GRC_DIS | GRC_RDY_OVRD;
> > > -		I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
> > > +		I915_WRITE(BXT_PORT_REF_DW8(phy), val);
> > >  	}
> > >  
> > >  	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> > >  	val |= COMMON_RESET_DIS;
> > >  	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
> > >  
> > > -	if (phy == DPIO_PHY1)
> > > -		bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
> > > +	if (phy_info->rcomp_phy == -1)
> > > +		bxt_phy_wait_grc_done(dev_priv, phy);
> > > +
> > >  }
> > >  
> > >  void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum
> > > dpio_phy
> > > phy)
> > > @@ -375,6 +390,33 @@ void bxt_ddi_phy_uninit(struct
> > > drm_i915_private
> > > *dev_priv, enum dpio_phy phy)
> > >  	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
> > >  }
> > >  
> > > +/* This function assumes it is called from an
> > > intel_display_power_get()
> > > call,
> > > + * which would serialize any other attempts to enable the phy
> > > with the
> > > Rcomp
> > > + * resistor.
> > > + */
> > You could replace the above with a mutex locked assert.
> 
> I'll do that and resend.
> 
> > > 
> > > +void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum
> > > dpio_phy phy)
> > > +{
> > > +	const struct bxt_ddi_phy_info *phy_info =
> > > &bxt_ddi_phy_info[phy];
> > > +	enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
> > > +	bool was_enabled;
> > > +
> > > +	if (rcomp_phy != -1) {
> > > +		was_enabled = bxt_ddi_phy_is_enabled(dev_priv,
> > > rcomp_phy);
> > > +
> > > +		/*
> > > +		 * We need to copy the GRC calibration value
> > > from
> > > rcomp_phy,
> > > +		 * so make sure it's powered up.
> > > +		 */
> > > +		if (!was_enabled)
> > > +			_bxt_ddi_phy_init(dev_priv, rcomp_phy);
> > > +	}
> > > +
> > > +	_bxt_ddi_phy_init(dev_priv, phy);
> > > +
> > > +	if (rcomp_phy != -1 && !was_enabled)
> > > +		bxt_ddi_phy_uninit(dev_priv, phy_info-
> > > >rcomp_phy);
> > > +}
> > Nitpick: An alternative would be to add the power well dependency
> > as a
> > custom power well field for the cmn power wells. We'd avoid the
> > unnecessary HW access in bxt_ddi_phy_is_enabled().
> 
> Since you gave me the option, I'll choose to ignore this one. What I
> like about
> the current solution is that the dependency relationship between the
> phys is
> captured in a single place, so I'd like to avoid duplicating that
> information in
> the power well code.
> 
> I don't think the extra hardware access is performance critical, but
> if it were,
> maybe we could track whether the phy is enabled in the phy code too?

No, I meant that we already track that in the power well code so
checking for it here again would be redundant. But I'm also fine with
your solution so let's go with that.

--Imre

> 
> Ander
> 
> > 
> > > 
> > > +
> > >  static bool __printf(6, 7)
> > >  __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum
> > > dpio_phy
> > > phy,
> > >  		       i915_reg_t reg, u32 mask, u32 expected,
> > > @@ -441,7 +483,7 @@ bool bxt_ddi_phy_verify_state(struct
> > > drm_i915_private
> > > *dev_priv,
> > >  	 * at least on stepping A this bit is read-only and
> > > fixed at 0.
> > >  	 */
> > >  
> > > -	if (phy == DPIO_PHY0) {
> > > +	if (phy_info->rcomp_phy != -1) {
> > >  		u32 grc_code = dev_priv->bxt_phy_grc;
> > >  
> > >  		grc_code = grc_code << GRC_CODE_FAST_SHIFT |
> > > @@ -449,12 +491,12 @@ bool bxt_ddi_phy_verify_state(struct
> > > drm_i915_private
> > > *dev_priv,
> > >  			   grc_code;
> > >  		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
> > >  		       GRC_CODE_NOM_MASK;
> > > -		ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask,
> > > grc_code,
> > > -			    "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
> > > +		ok &= _CHK(BXT_PORT_REF_DW6(phy), mask,
> > > grc_code,
> > > +			    "BXT_PORT_REF_DW6(%d)", phy);
> > >  
> > >  		mask = GRC_DIS | GRC_RDY_OVRD;
> > > -		ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask,
> > > mask,
> > > -			    "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
> > > +		ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
> > > +			    "BXT_PORT_REF_DW8(%d)", phy);
> > >  	}
> > >  
> > >  	return ok;
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index d41fd46..3b38998 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -849,22 +849,7 @@ static void skl_power_well_disable(struct
> > > drm_i915_private *dev_priv,
> > >  static void bxt_dpio_cmn_power_well_enable(struct
> > > drm_i915_private
> > > *dev_priv,
> > >  					   struct
> > > i915_power_well
> > > *power_well)
> > >  {
> > > -	enum skl_disp_power_wells power_well_id = power_well-
> > > >id;
> > > -	struct i915_power_well *cmn_a_well = NULL;
> > > -
> > > -	if (power_well_id == BXT_DPIO_CMN_BC) {
> > > -		/*
> > > -		 * We need to copy the GRC calibration value
> > > from the eDP
> > > PHY,
> > > -		 * so make sure it's powered up.
> > > -		 */
> > > -		cmn_a_well = lookup_power_well(dev_priv,
> > > BXT_DPIO_CMN_A);
> > > -		intel_power_well_get(dev_priv, cmn_a_well);
> > > -	}
> > > -
> > >  	bxt_ddi_phy_init(dev_priv, power_well->data);
> > > -
> > > -	if (cmn_a_well)
> > > -		intel_power_well_put(dev_priv, cmn_a_well);
> > >  }
> > >  
> > >  static void bxt_dpio_cmn_power_well_disable(struct
> > > drm_i915_private
> > > *dev_priv,
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[PATCH 9/9] drm/i915: Address broxton phy registers based on phy and channel number

[Ander Conselvan de Oliveira]

The port registers related to the phys in broxton map to different
channels and specific phys. Make that mapping explicit.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |   2 +
 drivers/gpu/drm/i915/i915_reg.h       | 211 +++++++++++++---------------------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 131 +++++++++++++++------
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  84 ++++++++------
 4 files changed, 222 insertions(+), 206 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 77f1374..c3fa29a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3735,6 +3735,8 @@ u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 
 /* intel_dpio_phy.c */
+void bxt_port_to_phy_channel(enum port port,
+			     u32 *phy, enum dpio_channel *ch);
 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
 				  enum port port, u32 margin, u32 scale,
 				  u32 enable, u32 deemphasis);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d3802c6..416cbb1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1187,6 +1187,9 @@ enum skl_disp_power_wells {
 #define   DPIO_UPAR_SHIFT		30
 
 /* BXT PHY registers */
+#define BXT_PHY1_BASE			0x162000
+#define BXT_PHY0_BASE			0x6C000
+
 #define _BXT_PHY(phy, a, b)		_MMIO_PIPE((phy), (a), (b))
 
 #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
@@ -1216,31 +1219,26 @@ enum skl_disp_power_wells {
 #define   PORT_PLL_REF_SEL		(1 << 27)
 #define BXT_PORT_PLL_ENABLE(port)	_MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
 
-#define _PORT_PLL_EBB_0_A		0x162034
-#define _PORT_PLL_EBB_0_B		0x6C034
-#define _PORT_PLL_EBB_0_C		0x6C340
+#define _PORT_PLL_EBB_0_CH0		0x34
+#define _PORT_PLL_EBB_0_CH1		0x340
 #define   PORT_PLL_P1_SHIFT		13
 #define   PORT_PLL_P1_MASK		(0x07 << PORT_PLL_P1_SHIFT)
 #define   PORT_PLL_P1(x)		((x)  << PORT_PLL_P1_SHIFT)
 #define   PORT_PLL_P2_SHIFT		8
 #define   PORT_PLL_P2_MASK		(0x1f << PORT_PLL_P2_SHIFT)
 #define   PORT_PLL_P2(x)		((x)  << PORT_PLL_P2_SHIFT)
-#define BXT_PORT_PLL_EBB_0(port)	_MMIO_PORT3(port, _PORT_PLL_EBB_0_A, \
-						_PORT_PLL_EBB_0_B,	\
-						_PORT_PLL_EBB_0_C)
+#define BXT_PORT_PLL_EBB_0(base, ch)	\
+	_MMIO((base) + _PIPE((ch), _PORT_PLL_EBB_0_CH0, _PORT_PLL_EBB_0_CH1))
 
-#define _PORT_PLL_EBB_4_A		0x162038
-#define _PORT_PLL_EBB_4_B		0x6C038
-#define _PORT_PLL_EBB_4_C		0x6C344
+#define _PORT_PLL_EBB_4_CH0		0x38
+#define _PORT_PLL_EBB_4_CH1		0x344
 #define   PORT_PLL_10BIT_CLK_ENABLE	(1 << 13)
 #define   PORT_PLL_RECALIBRATE		(1 << 14)
-#define BXT_PORT_PLL_EBB_4(port)	_MMIO_PORT3(port, _PORT_PLL_EBB_4_A, \
-						_PORT_PLL_EBB_4_B,	\
-						_PORT_PLL_EBB_4_C)
+#define BXT_PORT_PLL_EBB_4(base, ch)	\
+	_MMIO((base) + _PIPE((ch), _PORT_PLL_EBB_4_CH0, _PORT_PLL_EBB_4_CH1))
 
-#define _PORT_PLL_0_A			0x162100
-#define _PORT_PLL_0_B			0x6C100
-#define _PORT_PLL_0_C			0x6C380
+#define _PORT_PLL_0_CH0			0x100
+#define _PORT_PLL_0_CH1			0x380
 /* PORT_PLL_0_A */
 #define   PORT_PLL_M2_MASK		0xFF
 /* PORT_PLL_1_A */
@@ -1267,65 +1265,43 @@ enum skl_disp_power_wells {
 #define  PORT_PLL_DCO_AMP_DEFAULT	15
 #define  PORT_PLL_DCO_AMP_MASK		0x3c00
 #define  PORT_PLL_DCO_AMP(x)		((x)<<10)
-#define _PORT_PLL_BASE(port)		_PORT3(port, _PORT_PLL_0_A,	\
-						_PORT_PLL_0_B,		\
-						_PORT_PLL_0_C)
-#define BXT_PORT_PLL(port, idx)		_MMIO(_PORT_PLL_BASE(port) + (idx) * 4)
+#define _PORT_PLL_BASE(base, ch)	\
+	((base) + _PIPE((ch), _PORT_PLL_0_CH0, _PORT_PLL_0_CH1))
+#define BXT_PORT_PLL(base, ch, idx)	\
+	_MMIO(_PORT_PLL_BASE(base, ch) + (idx) * 4)
 
 /* BXT PHY common lane registers */
-#define _PORT_CL1CM_DW0_A		0x162000
-#define _PORT_CL1CM_DW0_BC		0x6C000
+#define BXT_PORT_CL1CM_DW0(base)	_MMIO((base) + 0x0)
 #define   PHY_POWER_GOOD		(1 << 16)
 #define   PHY_RESERVED			(1 << 7)
-#define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
-							_PORT_CL1CM_DW0_A)
 
-#define _PORT_CL1CM_DW9_A		0x162024
-#define _PORT_CL1CM_DW9_BC		0x6C024
+#define BXT_PORT_CL1CM_DW9(base)	_MMIO((base) + 0x24)
 #define   IREF0RC_OFFSET_SHIFT		8
 #define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
-#define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \
-							_PORT_CL1CM_DW9_A)
 
-#define _PORT_CL1CM_DW10_A		0x162028
-#define _PORT_CL1CM_DW10_BC		0x6C028
+#define BXT_PORT_CL1CM_DW10(base)	_MMIO((base) + 0x28)
 #define   IREF1RC_OFFSET_SHIFT		8
 #define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
-#define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \
-							_PORT_CL1CM_DW10_A)
 
-#define _PORT_CL1CM_DW28_A		0x162070
-#define _PORT_CL1CM_DW28_BC		0x6C070
+#define BXT_PORT_CL1CM_DW28(base)	_MMIO((base) + 0x70)
 #define   OCL1_POWER_DOWN_EN		(1 << 23)
 #define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
 #define   SUS_CLK_CONFIG		0x3
-#define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \
-							_PORT_CL1CM_DW28_A)
 
-#define _PORT_CL1CM_DW30_A		0x162078
-#define _PORT_CL1CM_DW30_BC		0x6C078
+#define BXT_PORT_CL1CM_DW30(base)	_MMIO((base) + 0x78)
 #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
-#define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
-							_PORT_CL1CM_DW30_A)
 
 /* The spec defines this only for BXT PHY0, but lets assume that this
  * would exist for PHY1 too if it had a second channel.
  */
-#define _PORT_CL2CM_DW6_A		0x162358
-#define _PORT_CL2CM_DW6_BC		0x6C358
-#define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC, \
-							_PORT_CL2CM_DW6_A)
+#define BXT_PORT_CL2CM_DW6(base)	_MMIO((base) + 0x358)
 #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
 
 /* BXT PHY Ref registers */
-#define _PORT_REF_DW3_A			0x16218C
-#define _PORT_REF_DW3_BC		0x6C18C
+#define BXT_PORT_REF_DW3(base)		_MMIO((base) + 0x18c)
 #define   GRC_DONE			(1 << 22)
-#define BXT_PORT_REF_DW3(phy)		_BXT_PHY((phy), _PORT_REF_DW3_BC, \
-							_PORT_REF_DW3_A)
 
-#define _PORT_REF_DW6_A			0x162198
-#define _PORT_REF_DW6_BC		0x6C198
+#define BXT_PORT_REF_DW6(base)		_MMIO((base) + 0x198)
 #define   GRC_CODE_SHIFT		24
 #define   GRC_CODE_MASK			(0xFF << GRC_CODE_SHIFT)
 #define   GRC_CODE_FAST_SHIFT		16
@@ -1333,113 +1309,88 @@ enum skl_disp_power_wells {
 #define   GRC_CODE_SLOW_SHIFT		8
 #define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
 #define   GRC_CODE_NOM_MASK		0xFF
-#define BXT_PORT_REF_DW6(phy)		_BXT_PHY((phy), _PORT_REF_DW6_BC,	\
-						      _PORT_REF_DW6_A)
 
-#define _PORT_REF_DW8_A			0x1621A0
-#define _PORT_REF_DW8_BC		0x6C1A0
+#define BXT_PORT_REF_DW8(base)		_MMIO((base) + 0x1a0)
 #define   GRC_DIS			(1 << 15)
 #define   GRC_RDY_OVRD			(1 << 1)
-#define BXT_PORT_REF_DW8(phy)		_BXT_PHY((phy), _PORT_REF_DW8_BC,	\
-						      _PORT_REF_DW8_A)
 
 /* BXT PHY PCS registers */
-#define _PORT_PCS_DW10_LN01_A		0x162428
-#define _PORT_PCS_DW10_LN01_B		0x6C428
-#define _PORT_PCS_DW10_LN01_C		0x6C828
-#define _PORT_PCS_DW10_GRP_A		0x162C28
-#define _PORT_PCS_DW10_GRP_B		0x6CC28
-#define _PORT_PCS_DW10_GRP_C		0x6CE28
-#define BXT_PORT_PCS_DW10_LN01(port)	_MMIO_PORT3(port, _PORT_PCS_DW10_LN01_A, \
-						     _PORT_PCS_DW10_LN01_B, \
-						     _PORT_PCS_DW10_LN01_C)
-#define BXT_PORT_PCS_DW10_GRP(port)	_MMIO_PORT3(port, _PORT_PCS_DW10_GRP_A,  \
-						     _PORT_PCS_DW10_GRP_B,  \
-						     _PORT_PCS_DW10_GRP_C)
+#define _PORT_PCS_DW10_LN01_CH0		0x428
+#define _PORT_PCS_DW10_LN01_CH1		0x828
+#define _PORT_PCS_DW10_GRP_CH0		0xC28
+#define _PORT_PCS_DW10_GRP_CH1		0xE28
 #define   TX2_SWING_CALC_INIT		(1 << 31)
 #define   TX1_SWING_CALC_INIT		(1 << 30)
-
-#define _PORT_PCS_DW12_LN01_A		0x162430
-#define _PORT_PCS_DW12_LN01_B		0x6C430
-#define _PORT_PCS_DW12_LN01_C		0x6C830
-#define _PORT_PCS_DW12_LN23_A		0x162630
-#define _PORT_PCS_DW12_LN23_B		0x6C630
-#define _PORT_PCS_DW12_LN23_C		0x6CA30
-#define _PORT_PCS_DW12_GRP_A		0x162c30
-#define _PORT_PCS_DW12_GRP_B		0x6CC30
-#define _PORT_PCS_DW12_GRP_C		0x6CE30
+#define BXT_PORT_PCS_DW10_LN01(base, ch)	\
+	_MMIO((base) + _PIPE(ch, _PORT_PCS_DW10_LN01_CH0,		\
+			     _PORT_PCS_DW10_LN01_CH1))
+#define BXT_PORT_PCS_DW10_GRP(base, ch)	\
+	_MMIO((base) + _PIPE(ch, _PORT_PCS_DW10_GRP_CH0,		\
+			     _PORT_PCS_DW10_GRP_CH1))
+
+#define _PORT_PCS_DW12_LN01_CH0		0x430
+#define _PORT_PCS_DW12_LN01_CH1		0x830
+#define _PORT_PCS_DW12_LN23_CH0		0x630
+#define _PORT_PCS_DW12_LN23_CH1		0xA30
+#define _PORT_PCS_DW12_GRP_CH0		0xC30
+#define _PORT_PCS_DW12_GRP_CH1		0xE30
 #define   LANESTAGGER_STRAP_OVRD	(1 << 6)
 #define   LANE_STAGGER_MASK		0x1F
-#define BXT_PORT_PCS_DW12_LN01(port)	_MMIO_PORT3(port, _PORT_PCS_DW12_LN01_A, \
-						     _PORT_PCS_DW12_LN01_B, \
-						     _PORT_PCS_DW12_LN01_C)
-#define BXT_PORT_PCS_DW12_LN23(port)	_MMIO_PORT3(port, _PORT_PCS_DW12_LN23_A, \
-						     _PORT_PCS_DW12_LN23_B, \
-						     _PORT_PCS_DW12_LN23_C)
-#define BXT_PORT_PCS_DW12_GRP(port)	_MMIO_PORT3(port, _PORT_PCS_DW12_GRP_A, \
-						     _PORT_PCS_DW12_GRP_B, \
-						     _PORT_PCS_DW12_GRP_C)
+#define BXT_PORT_PCS_DW12_LN01(base, ch)	\
+	_MMIO((base) + _PIPE(ch, _PORT_PCS_DW12_LN01_CH0, _PORT_PCS_DW12_LN01_CH1))
+#define BXT_PORT_PCS_DW12_LN23(base, ch)	\
+	_MMIO((base) + _PIPE(ch, _PORT_PCS_DW12_LN23_CH0, _PORT_PCS_DW12_LN23_CH1))
+#define BXT_PORT_PCS_DW12_GRP(base, ch)	\
+	_MMIO((base) + _PIPE(ch, _PORT_PCS_DW12_GRP_CH0, _PORT_PCS_DW12_GRP_CH1))
 
 /* BXT PHY TX registers */
 #define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
 					  ((lane) & 1) * 0x80)
 
-#define _PORT_TX_DW2_LN0_A		0x162508
-#define _PORT_TX_DW2_LN0_B		0x6C508
-#define _PORT_TX_DW2_LN0_C		0x6C908
-#define _PORT_TX_DW2_GRP_A		0x162D08
-#define _PORT_TX_DW2_GRP_B		0x6CD08
-#define _PORT_TX_DW2_GRP_C		0x6CF08
-#define BXT_PORT_TX_DW2_GRP(port)	_MMIO_PORT3(port, _PORT_TX_DW2_GRP_A,  \
-						     _PORT_TX_DW2_GRP_B,  \
-						     _PORT_TX_DW2_GRP_C)
-#define BXT_PORT_TX_DW2_LN0(port)	_MMIO_PORT3(port, _PORT_TX_DW2_LN0_A,  \
-						     _PORT_TX_DW2_LN0_B,  \
-						     _PORT_TX_DW2_LN0_C)
+#define _PORT_TX_DW2_LN0_CH0		0x508
+#define _PORT_TX_DW2_LN0_CH1		0x908
+#define _PORT_TX_DW2_GRP_CH0		0xD08
+#define _PORT_TX_DW2_GRP_CH1		0xF08
 #define   MARGIN_000_SHIFT		16
 #define   MARGIN_000			(0xFF << MARGIN_000_SHIFT)
 #define   UNIQ_TRANS_SCALE_SHIFT	8
 #define   UNIQ_TRANS_SCALE		(0xFF << UNIQ_TRANS_SCALE_SHIFT)
-
-#define _PORT_TX_DW3_LN0_A		0x16250C
-#define _PORT_TX_DW3_LN0_B		0x6C50C
-#define _PORT_TX_DW3_LN0_C		0x6C90C
-#define _PORT_TX_DW3_GRP_A		0x162D0C
-#define _PORT_TX_DW3_GRP_B		0x6CD0C
-#define _PORT_TX_DW3_GRP_C		0x6CF0C
-#define BXT_PORT_TX_DW3_GRP(port)	_MMIO_PORT3(port, _PORT_TX_DW3_GRP_A,  \
-						     _PORT_TX_DW3_GRP_B,  \
-						     _PORT_TX_DW3_GRP_C)
-#define BXT_PORT_TX_DW3_LN0(port)	_MMIO_PORT3(port, _PORT_TX_DW3_LN0_A,  \
-						     _PORT_TX_DW3_LN0_B,  \
-						     _PORT_TX_DW3_LN0_C)
+#define BXT_PORT_TX_DW2_GRP(base, ch)	\
+	_MMIO((base) + _PIPE((ch), _PORT_TX_DW2_GRP_CH0, _PORT_TX_DW2_GRP_CH1))
+#define BXT_PORT_TX_DW2_LN0(base, ch)	\
+	_MMIO((base) + _PIPE((ch), _PORT_TX_DW2_LN0_CH0, _PORT_TX_DW2_LN0_CH1))
+
+#define _PORT_TX_DW3_LN0_CH0		0x50C
+#define _PORT_TX_DW3_LN0_CH1		0x90C
+#define _PORT_TX_DW3_GRP_CH0		0xD0C
+#define _PORT_TX_DW3_GRP_CH1		0xF0C
 #define   SCALE_DCOMP_METHOD		(1 << 26)
 #define   UNIQUE_TRANGE_EN_METHOD	(1 << 27)
+#define BXT_PORT_TX_DW3_GRP(base, ch)	\
+	_MMIO((base) + _PIPE((ch), _PORT_TX_DW3_GRP_CH0, _PORT_TX_DW3_GRP_CH1))
+#define BXT_PORT_TX_DW3_LN0(base, ch)	\
+	_MMIO((base) + _PIPE((ch), _PORT_TX_DW3_LN0_CH0, _PORT_TX_DW3_LN0_CH1))
+
 
-#define _PORT_TX_DW4_LN0_A		0x162510
-#define _PORT_TX_DW4_LN0_B		0x6C510
-#define _PORT_TX_DW4_LN0_C		0x6C910
-#define _PORT_TX_DW4_GRP_A		0x162D10
-#define _PORT_TX_DW4_GRP_B		0x6CD10
-#define _PORT_TX_DW4_GRP_C		0x6CF10
-#define BXT_PORT_TX_DW4_LN0(port)	_MMIO_PORT3(port, _PORT_TX_DW4_LN0_A,  \
-						     _PORT_TX_DW4_LN0_B,  \
-						     _PORT_TX_DW4_LN0_C)
-#define BXT_PORT_TX_DW4_GRP(port)	_MMIO_PORT3(port, _PORT_TX_DW4_GRP_A,  \
-						     _PORT_TX_DW4_GRP_B,  \
-						     _PORT_TX_DW4_GRP_C)
+#define _PORT_TX_DW4_LN0_CH0		0x510
+#define _PORT_TX_DW4_LN0_CH1		0x910
+#define _PORT_TX_DW4_GRP_CH0		0xD10
+#define _PORT_TX_DW4_GRP_CH1		0xF10
 #define   DEEMPH_SHIFT			24
 #define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)
+#define BXT_PORT_TX_DW4_GRP(base, ch)	\
+	_MMIO((base) + _PIPE((ch), _PORT_TX_DW4_GRP_CH0, _PORT_TX_DW4_GRP_CH1))
+#define BXT_PORT_TX_DW4_LN0(base, ch)	\
+	_MMIO((base) + _PIPE((ch), _PORT_TX_DW4_LN0_CH0, _PORT_TX_DW4_LN0_CH1))
 
-#define _PORT_TX_DW14_LN0_A		0x162538
-#define _PORT_TX_DW14_LN0_B		0x6C538
-#define _PORT_TX_DW14_LN0_C		0x6C938
+#define _PORT_TX_DW14_LN0_CH0		0x538
+#define _PORT_TX_DW14_LN0_CH1		0x938
 #define   LATENCY_OPTIM_SHIFT		30
 #define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
-#define BXT_PORT_TX_DW14_LN(port, lane)	_MMIO(_PORT3((port), _PORT_TX_DW14_LN0_A,   \
-							_PORT_TX_DW14_LN0_B,   \
-							_PORT_TX_DW14_LN0_C) + \
-					 _BXT_LANE_OFFSET(lane))
+#define BXT_PORT_TX_DW14_LN(base, ch, lane)	\
+	_MMIO((base) + _PIPE((ch), _PORT_TX_DW14_LN0_CH0,	\
+				   _PORT_TX_DW14_LN0_CH1) + 	\
+	      _BXT_LANE_OFFSET(lane))
 
 /* UAIMI scratch pad register 1 */
 #define UAIMI_SPR1			_MMIO(0x4F074)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index e8a75fd..07ef154 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -124,6 +124,11 @@ struct bxt_ddi_phy_info {
 	bool dual_channel;
 
 	/**
+	 * @mmio_base: base addess for accessing this PHY through mmio.
+	 */
+	u32 mmio_base;
+
+	/**
 	 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
 	 * Otherwise the GRC value will be copied from the phy indicated by
 	 * this field.
@@ -143,6 +148,7 @@ struct bxt_ddi_phy_info {
 
 static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
 	[DPIO_PHY0] = {
+		.mmio_base = BXT_PHY0_BASE,
 		.dual_channel = true,
 		.rcomp_phy = DPIO_PHY1,
 
@@ -152,6 +158,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
 		}
 	},
 	[DPIO_PHY1] = {
+		.mmio_base = BXT_PHY1_BASE,
 		.dual_channel = false,
 		.rcomp_phy = -1,
 
@@ -167,26 +174,58 @@ static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
 		BIT(phy_info->channel[DPIO_CH0].port);
 }
 
+void bxt_port_to_phy_channel(enum port port,
+			     u32 *mmio_base, enum dpio_channel *ch)
+{
+	const struct bxt_ddi_phy_info *phy_info;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(bxt_ddi_phy_info); i++) {
+		phy_info = &bxt_ddi_phy_info[i];
+
+		if (port == phy_info->channel[DPIO_CH0].port) {
+			*mmio_base = phy_info->mmio_base;
+			*ch = DPIO_CH0;
+			return;
+		}
+
+		if (phy_info->dual_channel &&
+		    port == phy_info->channel[DPIO_CH1].port) {
+			*mmio_base = phy_info->mmio_base;
+			*ch = DPIO_CH1;
+			return;
+		}
+	}
+
+	WARN(1, "PHY not found for PORT %c", port_name(port));
+	*mmio_base = BXT_PHY0_BASE;
+	*ch = DPIO_CH0;
+}
+
 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
 				  enum port port, u32 margin, u32 scale,
 				  u32 enable, u32 deemphasis)
 {
 	u32 val;
+	u32 phy;
+	enum dpio_channel ch;
+
+	bxt_port_to_phy_channel(port, &phy, &ch);
 
 	/*
 	 * While we write to the group register to program all lanes at once we
 	 * can read only lane registers and we pick lanes 0/1 for that.
 	 */
-	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
+	val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
 	val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
-	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
+	I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
 
-	val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
+	val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch));
 	val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
 	val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT;
-	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
+	I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val);
 
-	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
+	val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch));
 	val &= ~SCALE_DCOMP_METHOD;
 	if (enable)
 		val |= SCALE_DCOMP_METHOD;
@@ -194,16 +233,16 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
 	if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
 		DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
 
-	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
+	I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val);
 
-	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
+	val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch));
 	val &= ~DE_EMPHASIS;
 	val |= deemphasis << DEEMPH_SHIFT;
-	I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
+	I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val);
 
-	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
+	val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
 	val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
-	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
+	I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
 }
 
 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
@@ -215,7 +254,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
 	if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
 		return false;
 
-	if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
+	if ((I915_READ(BXT_PORT_CL1CM_DW0(phy_info->mmio_base)) &
 	     (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
 		DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
 				 phy);
@@ -224,7 +263,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
 	}
 
 	if (phy_info->rcomp_phy == -1 &&
-	    !(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE)) {
+	    !(I915_READ(BXT_PORT_REF_DW3(phy_info->mmio_base)) & GRC_DONE)) {
 		DRM_DEBUG_DRIVER("DDI PHY %d powered, but GRC isn't done\n",
 				 phy);
 
@@ -256,7 +295,11 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
 
 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 {
-	u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
+	const struct bxt_ddi_phy_info *phy_info;
+	u32 val;
+
+	phy_info = &bxt_ddi_phy_info[phy];
+	val = I915_READ(BXT_PORT_REF_DW6(phy_info->mmio_base));
 
 	return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
 }
@@ -264,8 +307,12 @@ static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
 				  enum dpio_phy phy)
 {
+	const struct bxt_ddi_phy_info *phy_info;
+
+	phy_info = &bxt_ddi_phy_info[phy];
+
 	if (intel_wait_for_register(dev_priv,
-				    BXT_PORT_REF_DW3(phy),
+				    BXT_PORT_REF_DW3(phy_info->mmio_base),
 				    GRC_DONE, GRC_DONE,
 				    10))
 		DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
@@ -305,35 +352,35 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
 	 * HW team confirmed that the time to reach phypowergood status is
 	 * anywhere between 50 us and 100us.
 	 */
-	if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
+	if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy_info->mmio_base)) &
 		(PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
 		DRM_ERROR("timeout during PHY%d power on\n", phy);
 	}
 
 	/* Program PLL Rcomp code offset */
-	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
+	val = I915_READ(BXT_PORT_CL1CM_DW9(phy_info->mmio_base));
 	val &= ~IREF0RC_OFFSET_MASK;
 	val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
-	I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
+	I915_WRITE(BXT_PORT_CL1CM_DW9(phy_info->mmio_base), val);
 
-	val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
+	val = I915_READ(BXT_PORT_CL1CM_DW10(phy_info->mmio_base));
 	val &= ~IREF1RC_OFFSET_MASK;
 	val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
-	I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
+	I915_WRITE(BXT_PORT_CL1CM_DW10(phy_info->mmio_base), val);
 
 	/* Program power gating */
-	val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
+	val = I915_READ(BXT_PORT_CL1CM_DW28(phy_info->mmio_base));
 	val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
 		SUS_CLK_CONFIG;
-	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
+	I915_WRITE(BXT_PORT_CL1CM_DW28(phy_info->mmio_base), val);
 
 	if (phy_info->dual_channel) {
-		val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
+		val = I915_READ(BXT_PORT_CL2CM_DW6(phy_info->mmio_base));
 		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
-		I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
+		I915_WRITE(BXT_PORT_CL2CM_DW6(phy_info->mmio_base), val);
 	}
 
-	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
+	val = I915_READ(BXT_PORT_CL1CM_DW30(phy_info->mmio_base));
 	val &= ~OCL2_LDOFUSE_PWR_DIS;
 	/*
 	 * On PHY1 disable power on the second channel, since no port is
@@ -347,7 +394,7 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
 	 */
 	if (!phy_info->dual_channel)
 		val |= OCL2_LDOFUSE_PWR_DIS;
-	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
+	I915_WRITE(BXT_PORT_CL1CM_DW30(phy_info->mmio_base), val);
 
 	if (phy_info->rcomp_phy != -1) {
 		uint32_t grc_code;
@@ -361,11 +408,11 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
 		grc_code = val << GRC_CODE_FAST_SHIFT |
 			   val << GRC_CODE_SLOW_SHIFT |
 			   val;
-		I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code);
+		I915_WRITE(BXT_PORT_REF_DW6(phy_info->mmio_base), grc_code);
 
-		val = I915_READ(BXT_PORT_REF_DW8(phy));
+		val = I915_READ(BXT_PORT_REF_DW8(phy_info->mmio_base));
 		val |= GRC_DIS | GRC_RDY_OVRD;
-		I915_WRITE(BXT_PORT_REF_DW8(phy), val);
+		I915_WRITE(BXT_PORT_REF_DW8(phy_info->mmio_base), val);
 	}
 
 	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
@@ -461,20 +508,20 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
 	ok = true;
 
 	/* PLL Rcomp code offset */
-	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
+	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy_info->mmio_base),
 		    IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
 		    "BXT_PORT_CL1CM_DW9(%d)", phy);
-	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
+	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy_info->mmio_base),
 		    IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
 		    "BXT_PORT_CL1CM_DW10(%d)", phy);
 
 	/* Power gating */
 	mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
-	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
+	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy_info->mmio_base), mask, mask,
 		    "BXT_PORT_CL1CM_DW28(%d)", phy);
 
 	if (phy_info->dual_channel)
-		ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
+		ok &= _CHK(BXT_PORT_CL2CM_DW6(phy_info->mmio_base),
 			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
 			   "BXT_PORT_CL2CM_DW6(%d)", phy);
 
@@ -491,11 +538,11 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
 			   grc_code;
 		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
 		       GRC_CODE_NOM_MASK;
-		ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
-			    "BXT_PORT_REF_DW6(%d)", phy);
+		ok &= _CHK(BXT_PORT_REF_DW6(phy_info->mmio_base), mask,
+			   grc_code, "BXT_PORT_REF_DW6(%d)", phy);
 
 		mask = GRC_DIS | GRC_RDY_OVRD;
-		ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
+		ok &= _CHK(BXT_PORT_REF_DW8(phy_info->mmio_base), mask, mask,
 			    "BXT_PORT_REF_DW8(%d)", phy);
 	}
 
@@ -527,10 +574,14 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
 	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
 	enum port port = dport->port;
+	u32 phy;
+	enum dpio_channel ch;
 	int lane;
 
+	bxt_port_to_phy_channel(port, &phy, &ch);
+
 	for (lane = 0; lane < 4; lane++) {
-		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
+		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
 
 		/*
 		 * Note that on CHV this flag is called UPAR, but has
@@ -540,7 +591,7 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
 		if (lane_lat_optim_mask & BIT(lane))
 			val |= LATENCY_OPTIM;
 
-		I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
+		I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val);
 	}
 }
 
@@ -550,12 +601,16 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
 	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
 	enum port port = dport->port;
+	u32 phy;
+	enum dpio_channel ch;
 	int lane;
 	uint8_t mask;
 
+	bxt_port_to_phy_channel(port, &phy, &ch);
+
 	mask = 0;
 	for (lane = 0; lane < 4; lane++) {
-		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
+		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
 
 		if (val & LATENCY_OPTIM)
 			mask |= BIT(lane);
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 1c59ca5..a4a9f05 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1371,6 +1371,10 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
 {
 	uint32_t temp;
 	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
+	u32 phy;
+	enum dpio_channel ch;
+
+	bxt_port_to_phy_channel(port, &phy, &ch);
 
 	/* Non-SSC reference */
 	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
@@ -1378,72 +1382,72 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
 	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
 
 	/* Disable 10 bit clock */
-	temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
+	temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
 	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
-	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
+	I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
 
 	/* Write P1 & P2 */
-	temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
+	temp = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
 	temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
 	temp |= pll->config.hw_state.ebb0;
-	I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
+	I915_WRITE(BXT_PORT_PLL_EBB_0(phy, ch), temp);
 
 	/* Write M2 integer */
-	temp = I915_READ(BXT_PORT_PLL(port, 0));
+	temp = I915_READ(BXT_PORT_PLL(phy, ch, 0));
 	temp &= ~PORT_PLL_M2_MASK;
 	temp |= pll->config.hw_state.pll0;
-	I915_WRITE(BXT_PORT_PLL(port, 0), temp);
+	I915_WRITE(BXT_PORT_PLL(phy, ch, 0), temp);
 
 	/* Write N */
-	temp = I915_READ(BXT_PORT_PLL(port, 1));
+	temp = I915_READ(BXT_PORT_PLL(phy, ch, 1));
 	temp &= ~PORT_PLL_N_MASK;
 	temp |= pll->config.hw_state.pll1;
-	I915_WRITE(BXT_PORT_PLL(port, 1), temp);
+	I915_WRITE(BXT_PORT_PLL(phy, ch, 1), temp);
 
 	/* Write M2 fraction */
-	temp = I915_READ(BXT_PORT_PLL(port, 2));
+	temp = I915_READ(BXT_PORT_PLL(phy, ch, 2));
 	temp &= ~PORT_PLL_M2_FRAC_MASK;
 	temp |= pll->config.hw_state.pll2;
-	I915_WRITE(BXT_PORT_PLL(port, 2), temp);
+	I915_WRITE(BXT_PORT_PLL(phy, ch, 2), temp);
 
 	/* Write M2 fraction enable */
-	temp = I915_READ(BXT_PORT_PLL(port, 3));
+	temp = I915_READ(BXT_PORT_PLL(phy, ch, 3));
 	temp &= ~PORT_PLL_M2_FRAC_ENABLE;
 	temp |= pll->config.hw_state.pll3;
-	I915_WRITE(BXT_PORT_PLL(port, 3), temp);
+	I915_WRITE(BXT_PORT_PLL(phy, ch, 3), temp);
 
 	/* Write coeff */
-	temp = I915_READ(BXT_PORT_PLL(port, 6));
+	temp = I915_READ(BXT_PORT_PLL(phy, ch, 6));
 	temp &= ~PORT_PLL_PROP_COEFF_MASK;
 	temp &= ~PORT_PLL_INT_COEFF_MASK;
 	temp &= ~PORT_PLL_GAIN_CTL_MASK;
 	temp |= pll->config.hw_state.pll6;
-	I915_WRITE(BXT_PORT_PLL(port, 6), temp);
+	I915_WRITE(BXT_PORT_PLL(phy, ch, 6), temp);
 
 	/* Write calibration val */
-	temp = I915_READ(BXT_PORT_PLL(port, 8));
+	temp = I915_READ(BXT_PORT_PLL(phy, ch, 8));
 	temp &= ~PORT_PLL_TARGET_CNT_MASK;
 	temp |= pll->config.hw_state.pll8;
-	I915_WRITE(BXT_PORT_PLL(port, 8), temp);
+	I915_WRITE(BXT_PORT_PLL(phy, ch, 8), temp);
 
-	temp = I915_READ(BXT_PORT_PLL(port, 9));
+	temp = I915_READ(BXT_PORT_PLL(phy, ch, 9));
 	temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
 	temp |= pll->config.hw_state.pll9;
-	I915_WRITE(BXT_PORT_PLL(port, 9), temp);
+	I915_WRITE(BXT_PORT_PLL(phy, ch, 9), temp);
 
-	temp = I915_READ(BXT_PORT_PLL(port, 10));
+	temp = I915_READ(BXT_PORT_PLL(phy, ch, 10));
 	temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
 	temp &= ~PORT_PLL_DCO_AMP_MASK;
 	temp |= pll->config.hw_state.pll10;
-	I915_WRITE(BXT_PORT_PLL(port, 10), temp);
+	I915_WRITE(BXT_PORT_PLL(phy, ch, 10), temp);
 
 	/* Recalibrate with new settings */
-	temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
+	temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
 	temp |= PORT_PLL_RECALIBRATE;
-	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
+	I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
 	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
 	temp |= pll->config.hw_state.ebb4;
-	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
+	I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
 
 	/* Enable PLL */
 	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
@@ -1459,11 +1463,11 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
 	 * While we write to the group register to program all lanes at once we
 	 * can read only lane registers and we pick lanes 0/1 for that.
 	 */
-	temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
+	temp = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
 	temp &= ~LANE_STAGGER_MASK;
 	temp &= ~LANESTAGGER_STRAP_OVRD;
 	temp |= pll->config.hw_state.pcsdw12;
-	I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
+	I915_WRITE(BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
 }
 
 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
@@ -1485,6 +1489,10 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
 	uint32_t val;
 	bool ret;
+	u32 phy;
+	enum dpio_channel ch;
+
+	bxt_port_to_phy_channel(port, &phy, &ch);
 
 	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
 		return false;
@@ -1495,36 +1503,36 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	if (!(val & PORT_PLL_ENABLE))
 		goto out;
 
-	hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
+	hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
 	hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
 
-	hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
+	hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
 	hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
 
-	hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
+	hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0));
 	hw_state->pll0 &= PORT_PLL_M2_MASK;
 
-	hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
+	hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1));
 	hw_state->pll1 &= PORT_PLL_N_MASK;
 
-	hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
+	hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2));
 	hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
 
-	hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
+	hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3));
 	hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
 
-	hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
+	hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6));
 	hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
 			  PORT_PLL_INT_COEFF_MASK |
 			  PORT_PLL_GAIN_CTL_MASK;
 
-	hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
+	hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8));
 	hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
 
-	hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
+	hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9));
 	hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
 
-	hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
+	hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10));
 	hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
 			   PORT_PLL_DCO_AMP_MASK;
 
@@ -1533,11 +1541,11 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	 * can read only lane registers. We configure all lanes the same way, so
 	 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
 	 */
-	hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
-	if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
+	hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
+	if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
 		DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
 				 hw_state->pcsdw12,
-				 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
+				 I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)));
 	hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
 
 	ret = true;
-- 
2.5.5

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Re: [PATCH 9/9] drm/i915: Address broxton phy registers based on phy and channel number

[Imre Deak]

On ke, 2016-10-05 at 15:09 +0300, Ander Conselvan de Oliveira wrote:
> The port registers related to the phys in broxton map to different
> channels and specific phys. Make that mapping explicit.
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |   2 +
>  drivers/gpu/drm/i915/i915_reg.h       | 211 +++++++++++++---------------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 131 +++++++++++++++------
>  drivers/gpu/drm/i915/intel_dpll_mgr.c |  84 ++++++++------
>  4 files changed, 222 insertions(+), 206 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 77f1374..c3fa29a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3735,6 +3735,8 @@ u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
>  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>  
>  /* intel_dpio_phy.c */
> +void bxt_port_to_phy_channel(enum port port,
> +			     u32 *phy, enum dpio_channel *ch);
>  void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
>  				  enum port port, u32 margin, u32 scale,
>  				  u32 enable, u32 deemphasis);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d3802c6..416cbb1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1187,6 +1187,9 @@ enum skl_disp_power_wells {
>  #define   DPIO_UPAR_SHIFT		30
>  
>  /* BXT PHY registers */
> +#define BXT_PHY1_BASE			0x162000
> +#define BXT_PHY0_BASE			0x6C000
> +
>  #define _BXT_PHY(phy, a, b)		_MMIO_PIPE((phy), (a), (b))
>  
>  #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
> @@ -1216,31 +1219,26 @@ enum skl_disp_power_wells {
>  #define   PORT_PLL_REF_SEL		(1 << 27)
>  #define BXT_PORT_PLL_ENABLE(port)	_MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
>  
> -#define _PORT_PLL_EBB_0_A		0x162034
> -#define _PORT_PLL_EBB_0_B		0x6C034
> -#define _PORT_PLL_EBB_0_C		0x6C340
> +#define _PORT_PLL_EBB_0_CH0		0x34
> +#define _PORT_PLL_EBB_0_CH1		0x340
>  #define   PORT_PLL_P1_SHIFT		13
>  #define   PORT_PLL_P1_MASK		(0x07 << PORT_PLL_P1_SHIFT)
>  #define   PORT_PLL_P1(x)		((x)  << PORT_PLL_P1_SHIFT)
>  #define   PORT_PLL_P2_SHIFT		8
>  #define   PORT_PLL_P2_MASK		(0x1f << PORT_PLL_P2_SHIFT)
>  #define   PORT_PLL_P2(x)		((x)  << PORT_PLL_P2_SHIFT)
> -#define BXT_PORT_PLL_EBB_0(port)	_MMIO_PORT3(port, _PORT_PLL_EBB_0_A, \
> -						_PORT_PLL_EBB_0_B,	\
> -						_PORT_PLL_EBB_0_C)
> +#define BXT_PORT_PLL_EBB_0(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_PLL_EBB_0_CH0, _PORT_PLL_EBB_0_CH1))

Passing the phy and calculating the base here would be more natural.
Also we should try to preserve bspec reg names and addresses to make
lookup easier. You could do that by using _PORT_PLL_EBB_0_B
and _PORT_PLL_EBB_0_C here and adjusting the base by -BXT_PHY0_BASE.
I'd also leave _PORT_PLL_EBB_0_A around for reference.

>  
> -#define _PORT_PLL_EBB_4_A		0x162038
> -#define _PORT_PLL_EBB_4_B		0x6C038
> -#define _PORT_PLL_EBB_4_C		0x6C344
> +#define _PORT_PLL_EBB_4_CH0		0x38
> +#define _PORT_PLL_EBB_4_CH1		0x344
>  #define   PORT_PLL_10BIT_CLK_ENABLE	(1 << 13)
>  #define   PORT_PLL_RECALIBRATE		(1 << 14)
> -#define BXT_PORT_PLL_EBB_4(port)	_MMIO_PORT3(port, _PORT_PLL_EBB_4_A, \
> -						_PORT_PLL_EBB_4_B,	\
> -						_PORT_PLL_EBB_4_C)
> +#define BXT_PORT_PLL_EBB_4(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_PLL_EBB_4_CH0, _PORT_PLL_EBB_4_CH1))
>  
> -#define _PORT_PLL_0_A			0x162100
> -#define _PORT_PLL_0_B			0x6C100
> -#define _PORT_PLL_0_C			0x6C380
> +#define _PORT_PLL_0_CH0			0x100
> +#define _PORT_PLL_0_CH1			0x380
>  /* PORT_PLL_0_A */
>  #define   PORT_PLL_M2_MASK		0xFF
>  /* PORT_PLL_1_A */
> @@ -1267,65 +1265,43 @@ enum skl_disp_power_wells {
>  #define  PORT_PLL_DCO_AMP_DEFAULT	15
>  #define  PORT_PLL_DCO_AMP_MASK		0x3c00
>  #define  PORT_PLL_DCO_AMP(x)		((x)<<10)
> -#define _PORT_PLL_BASE(port)		_PORT3(port, _PORT_PLL_0_A,	\
> -						_PORT_PLL_0_B,		\
> -						_PORT_PLL_0_C)
> -#define BXT_PORT_PLL(port, idx)		_MMIO(_PORT_PLL_BASE(port) + (idx) * 4)
> +#define _PORT_PLL_BASE(base, ch)	\
> +	((base) + _PIPE((ch), _PORT_PLL_0_CH0, _PORT_PLL_0_CH1))
> +#define BXT_PORT_PLL(base, ch, idx)	\
> +	_MMIO(_PORT_PLL_BASE(base, ch) + (idx) * 4)
>  
>  /* BXT PHY common lane registers */
> -#define _PORT_CL1CM_DW0_A		0x162000
> -#define _PORT_CL1CM_DW0_BC		0x6C000
> +#define BXT_PORT_CL1CM_DW0(base)	_MMIO((base) + 0x0)
>  #define   PHY_POWER_GOOD		(1 << 16)
>  #define   PHY_RESERVED			(1 << 7)
> -#define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
> -							_PORT_CL1CM_DW0_A)
>  
> -#define _PORT_CL1CM_DW9_A		0x162024
> -#define _PORT_CL1CM_DW9_BC		0x6C024
> +#define BXT_PORT_CL1CM_DW9(base)	_MMIO((base) + 0x24)
>  #define   IREF0RC_OFFSET_SHIFT		8
>  #define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
> -#define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \
> -							_PORT_CL1CM_DW9_A)
>  
> -#define _PORT_CL1CM_DW10_A		0x162028
> -#define _PORT_CL1CM_DW10_BC		0x6C028
> +#define BXT_PORT_CL1CM_DW10(base)	_MMIO((base) + 0x28)
>  #define   IREF1RC_OFFSET_SHIFT		8
>  #define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
> -#define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \
> -							_PORT_CL1CM_DW10_A)
>  
> -#define _PORT_CL1CM_DW28_A		0x162070
> -#define _PORT_CL1CM_DW28_BC		0x6C070
> +#define BXT_PORT_CL1CM_DW28(base)	_MMIO((base) + 0x70)
>  #define   OCL1_POWER_DOWN_EN		(1 << 23)
>  #define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
>  #define   SUS_CLK_CONFIG		0x3
> -#define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \
> -							_PORT_CL1CM_DW28_A)
>  
> -#define _PORT_CL1CM_DW30_A		0x162078
> -#define _PORT_CL1CM_DW30_BC		0x6C078
> +#define BXT_PORT_CL1CM_DW30(base)	_MMIO((base) + 0x78)
>  #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
> -#define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
> -							_PORT_CL1CM_DW30_A)
>  
>  /* The spec defines this only for BXT PHY0, but lets assume that this
>   * would exist for PHY1 too if it had a second channel.
>   */
> -#define _PORT_CL2CM_DW6_A		0x162358
> -#define _PORT_CL2CM_DW6_BC		0x6C358
> -#define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC, \
> -							_PORT_CL2CM_DW6_A)
> +#define BXT_PORT_CL2CM_DW6(base)	_MMIO((base) + 0x358)
>  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
>  
>  /* BXT PHY Ref registers */
> -#define _PORT_REF_DW3_A			0x16218C
> -#define _PORT_REF_DW3_BC		0x6C18C
> +#define BXT_PORT_REF_DW3(base)		_MMIO((base) + 0x18c)
>  #define   GRC_DONE			(1 << 22)
> -#define BXT_PORT_REF_DW3(phy)		_BXT_PHY((phy), _PORT_REF_DW3_BC, \
> -							_PORT_REF_DW3_A)
>  
> -#define _PORT_REF_DW6_A			0x162198
> -#define _PORT_REF_DW6_BC		0x6C198
> +#define BXT_PORT_REF_DW6(base)		_MMIO((base) + 0x198)
>  #define   GRC_CODE_SHIFT		24
>  #define   GRC_CODE_MASK			(0xFF << GRC_CODE_SHIFT)
>  #define   GRC_CODE_FAST_SHIFT		16
> @@ -1333,113 +1309,88 @@ enum skl_disp_power_wells {
>  #define   GRC_CODE_SLOW_SHIFT		8
>  #define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
>  #define   GRC_CODE_NOM_MASK		0xFF
> -#define BXT_PORT_REF_DW6(phy)		_BXT_PHY((phy), _PORT_REF_DW6_BC,	\
> -						      _PORT_REF_DW6_A)
>  
> -#define _PORT_REF_DW8_A			0x1621A0
> -#define _PORT_REF_DW8_BC		0x6C1A0
> +#define BXT_PORT_REF_DW8(base)		_MMIO((base) + 0x1a0)
>  #define   GRC_DIS			(1 << 15)
>  #define   GRC_RDY_OVRD			(1 << 1)
> -#define BXT_PORT_REF_DW8(phy)		_BXT_PHY((phy), _PORT_REF_DW8_BC,	\
> -						      _PORT_REF_DW8_A)
>  
>  /* BXT PHY PCS registers */
> -#define _PORT_PCS_DW10_LN01_A		0x162428
> -#define _PORT_PCS_DW10_LN01_B		0x6C428
> -#define _PORT_PCS_DW10_LN01_C		0x6C828
> -#define _PORT_PCS_DW10_GRP_A		0x162C28
> -#define _PORT_PCS_DW10_GRP_B		0x6CC28
> -#define _PORT_PCS_DW10_GRP_C		0x6CE28
> -#define BXT_PORT_PCS_DW10_LN01(port)	_MMIO_PORT3(port, _PORT_PCS_DW10_LN01_A, \
> -						     _PORT_PCS_DW10_LN01_B, \
> -						     _PORT_PCS_DW10_LN01_C)
> -#define BXT_PORT_PCS_DW10_GRP(port)	_MMIO_PORT3(port, _PORT_PCS_DW10_GRP_A,  \
> -						     _PORT_PCS_DW10_GRP_B,  \
> -						     _PORT_PCS_DW10_GRP_C)
> +#define _PORT_PCS_DW10_LN01_CH0		0x428
> +#define _PORT_PCS_DW10_LN01_CH1		0x828
> +#define _PORT_PCS_DW10_GRP_CH0		0xC28
> +#define _PORT_PCS_DW10_GRP_CH1		0xE28
>  #define   TX2_SWING_CALC_INIT		(1 << 31)
>  #define   TX1_SWING_CALC_INIT		(1 << 30)
> -
> -#define _PORT_PCS_DW12_LN01_A		0x162430
> -#define _PORT_PCS_DW12_LN01_B		0x6C430
> -#define _PORT_PCS_DW12_LN01_C		0x6C830
> -#define _PORT_PCS_DW12_LN23_A		0x162630
> -#define _PORT_PCS_DW12_LN23_B		0x6C630
> -#define _PORT_PCS_DW12_LN23_C		0x6CA30
> -#define _PORT_PCS_DW12_GRP_A		0x162c30
> -#define _PORT_PCS_DW12_GRP_B		0x6CC30
> -#define _PORT_PCS_DW12_GRP_C		0x6CE30
> +#define BXT_PORT_PCS_DW10_LN01(base, ch)	\
> +	_MMIO((base) + _PIPE(ch, _PORT_PCS_DW10_LN01_CH0,		\
> +			     _PORT_PCS_DW10_LN01_CH1))
> +#define BXT_PORT_PCS_DW10_GRP(base, ch)	\
> +	_MMIO((base) + _PIPE(ch, _PORT_PCS_DW10_GRP_CH0,		\
> +			     _PORT_PCS_DW10_GRP_CH1))
> +
> +#define _PORT_PCS_DW12_LN01_CH0		0x430
> +#define _PORT_PCS_DW12_LN01_CH1		0x830
> +#define _PORT_PCS_DW12_LN23_CH0		0x630
> +#define _PORT_PCS_DW12_LN23_CH1		0xA30
> +#define _PORT_PCS_DW12_GRP_CH0		0xC30
> +#define _PORT_PCS_DW12_GRP_CH1		0xE30
>  #define   LANESTAGGER_STRAP_OVRD	(1 << 6)
>  #define   LANE_STAGGER_MASK		0x1F
> -#define BXT_PORT_PCS_DW12_LN01(port)	_MMIO_PORT3(port, _PORT_PCS_DW12_LN01_A, \
> -						     _PORT_PCS_DW12_LN01_B, \
> -						     _PORT_PCS_DW12_LN01_C)
> -#define BXT_PORT_PCS_DW12_LN23(port)	_MMIO_PORT3(port, _PORT_PCS_DW12_LN23_A, \
> -						     _PORT_PCS_DW12_LN23_B, \
> -						     _PORT_PCS_DW12_LN23_C)
> -#define BXT_PORT_PCS_DW12_GRP(port)	_MMIO_PORT3(port, _PORT_PCS_DW12_GRP_A, \
> -						     _PORT_PCS_DW12_GRP_B, \
> -						     _PORT_PCS_DW12_GRP_C)
> +#define BXT_PORT_PCS_DW12_LN01(base, ch)	\
> +	_MMIO((base) + _PIPE(ch, _PORT_PCS_DW12_LN01_CH0, _PORT_PCS_DW12_LN01_CH1))
> +#define BXT_PORT_PCS_DW12_LN23(base, ch)	\
> +	_MMIO((base) + _PIPE(ch, _PORT_PCS_DW12_LN23_CH0, _PORT_PCS_DW12_LN23_CH1))
> +#define BXT_PORT_PCS_DW12_GRP(base, ch)	\
> +	_MMIO((base) + _PIPE(ch, _PORT_PCS_DW12_GRP_CH0, _PORT_PCS_DW12_GRP_CH1))
>  
>  /* BXT PHY TX registers */
>  #define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
>  					  ((lane) & 1) * 0x80)
>  
> -#define _PORT_TX_DW2_LN0_A		0x162508
> -#define _PORT_TX_DW2_LN0_B		0x6C508
> -#define _PORT_TX_DW2_LN0_C		0x6C908
> -#define _PORT_TX_DW2_GRP_A		0x162D08
> -#define _PORT_TX_DW2_GRP_B		0x6CD08
> -#define _PORT_TX_DW2_GRP_C		0x6CF08
> -#define BXT_PORT_TX_DW2_GRP(port)	_MMIO_PORT3(port, _PORT_TX_DW2_GRP_A,  \
> -						     _PORT_TX_DW2_GRP_B,  \
> -						     _PORT_TX_DW2_GRP_C)
> -#define BXT_PORT_TX_DW2_LN0(port)	_MMIO_PORT3(port, _PORT_TX_DW2_LN0_A,  \
> -						     _PORT_TX_DW2_LN0_B,  \
> -						     _PORT_TX_DW2_LN0_C)
> +#define _PORT_TX_DW2_LN0_CH0		0x508
> +#define _PORT_TX_DW2_LN0_CH1		0x908
> +#define _PORT_TX_DW2_GRP_CH0		0xD08
> +#define _PORT_TX_DW2_GRP_CH1		0xF08
>  #define   MARGIN_000_SHIFT		16
>  #define   MARGIN_000			(0xFF << MARGIN_000_SHIFT)
>  #define   UNIQ_TRANS_SCALE_SHIFT	8
>  #define   UNIQ_TRANS_SCALE		(0xFF << UNIQ_TRANS_SCALE_SHIFT)
> -
> -#define _PORT_TX_DW3_LN0_A		0x16250C
> -#define _PORT_TX_DW3_LN0_B		0x6C50C
> -#define _PORT_TX_DW3_LN0_C		0x6C90C
> -#define _PORT_TX_DW3_GRP_A		0x162D0C
> -#define _PORT_TX_DW3_GRP_B		0x6CD0C
> -#define _PORT_TX_DW3_GRP_C		0x6CF0C
> -#define BXT_PORT_TX_DW3_GRP(port)	_MMIO_PORT3(port, _PORT_TX_DW3_GRP_A,  \
> -						     _PORT_TX_DW3_GRP_B,  \
> -						     _PORT_TX_DW3_GRP_C)
> -#define BXT_PORT_TX_DW3_LN0(port)	_MMIO_PORT3(port, _PORT_TX_DW3_LN0_A,  \
> -						     _PORT_TX_DW3_LN0_B,  \
> -						     _PORT_TX_DW3_LN0_C)
> +#define BXT_PORT_TX_DW2_GRP(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_TX_DW2_GRP_CH0, _PORT_TX_DW2_GRP_CH1))
> +#define BXT_PORT_TX_DW2_LN0(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_TX_DW2_LN0_CH0, _PORT_TX_DW2_LN0_CH1))
> +
> +#define _PORT_TX_DW3_LN0_CH0		0x50C
> +#define _PORT_TX_DW3_LN0_CH1		0x90C
> +#define _PORT_TX_DW3_GRP_CH0		0xD0C
> +#define _PORT_TX_DW3_GRP_CH1		0xF0C
>  #define   SCALE_DCOMP_METHOD		(1 << 26)
>  #define   UNIQUE_TRANGE_EN_METHOD	(1 << 27)
> +#define BXT_PORT_TX_DW3_GRP(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_TX_DW3_GRP_CH0, _PORT_TX_DW3_GRP_CH1))
> +#define BXT_PORT_TX_DW3_LN0(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_TX_DW3_LN0_CH0, _PORT_TX_DW3_LN0_CH1))
> +
>  
> -#define _PORT_TX_DW4_LN0_A		0x162510
> -#define _PORT_TX_DW4_LN0_B		0x6C510
> -#define _PORT_TX_DW4_LN0_C		0x6C910
> -#define _PORT_TX_DW4_GRP_A		0x162D10
> -#define _PORT_TX_DW4_GRP_B		0x6CD10
> -#define _PORT_TX_DW4_GRP_C		0x6CF10
> -#define BXT_PORT_TX_DW4_LN0(port)	_MMIO_PORT3(port, _PORT_TX_DW4_LN0_A,  \
> -						     _PORT_TX_DW4_LN0_B,  \
> -						     _PORT_TX_DW4_LN0_C)
> -#define BXT_PORT_TX_DW4_GRP(port)	_MMIO_PORT3(port, _PORT_TX_DW4_GRP_A,  \
> -						     _PORT_TX_DW4_GRP_B,  \
> -						     _PORT_TX_DW4_GRP_C)
> +#define _PORT_TX_DW4_LN0_CH0		0x510
> +#define _PORT_TX_DW4_LN0_CH1		0x910
> +#define _PORT_TX_DW4_GRP_CH0		0xD10
> +#define _PORT_TX_DW4_GRP_CH1		0xF10
>  #define   DEEMPH_SHIFT			24
>  #define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)
> +#define BXT_PORT_TX_DW4_GRP(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_TX_DW4_GRP_CH0, _PORT_TX_DW4_GRP_CH1))
> +#define BXT_PORT_TX_DW4_LN0(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_TX_DW4_LN0_CH0, _PORT_TX_DW4_LN0_CH1))
>  
> -#define _PORT_TX_DW14_LN0_A		0x162538
> -#define _PORT_TX_DW14_LN0_B		0x6C538
> -#define _PORT_TX_DW14_LN0_C		0x6C938
> +#define _PORT_TX_DW14_LN0_CH0		0x538
> +#define _PORT_TX_DW14_LN0_CH1		0x938
>  #define   LATENCY_OPTIM_SHIFT		30
>  #define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
> -#define BXT_PORT_TX_DW14_LN(port, lane)	_MMIO(_PORT3((port), _PORT_TX_DW14_LN0_A,   \
> -							_PORT_TX_DW14_LN0_B,   \
> -							_PORT_TX_DW14_LN0_C) + \
> -					 _BXT_LANE_OFFSET(lane))
> +#define BXT_PORT_TX_DW14_LN(base, ch, lane)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_TX_DW14_LN0_CH0,	\
> +				   _PORT_TX_DW14_LN0_CH1) + 	\
> +	      _BXT_LANE_OFFSET(lane))
>  
>  /* UAIMI scratch pad register 1 */
>  #define UAIMI_SPR1			_MMIO(0x4F074)
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index e8a75fd..07ef154 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -124,6 +124,11 @@ struct bxt_ddi_phy_info {
>  	bool dual_channel;
>  
>  	/**
> +	 * @mmio_base: base addess for accessing this PHY through mmio.
> +	 */
> +	u32 mmio_base;
> +
> +	/**
>  	 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
>  	 * Otherwise the GRC value will be copied from the phy indicated by
>  	 * this field.
> @@ -143,6 +148,7 @@ struct bxt_ddi_phy_info {
>  
>  static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
>  	[DPIO_PHY0] = {
> +		.mmio_base = BXT_PHY0_BASE,
>  		.dual_channel = true,
>  		.rcomp_phy = DPIO_PHY1,
>  
> @@ -152,6 +158,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
>  		}
>  	},
>  	[DPIO_PHY1] = {
> +		.mmio_base = BXT_PHY1_BASE,
>  		.dual_channel = false,
>  		.rcomp_phy = -1,
>  
> @@ -167,26 +174,58 @@ static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
>  		BIT(phy_info->channel[DPIO_CH0].port);
>  }
>  
> +void bxt_port_to_phy_channel(enum port port,
> +			     u32 *mmio_base, enum dpio_channel *ch)
> +{
> +	const struct bxt_ddi_phy_info *phy_info;
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(bxt_ddi_phy_info); i++) {
> +		phy_info = &bxt_ddi_phy_info[i];
> +
> +		if (port == phy_info->channel[DPIO_CH0].port) {
> +			*mmio_base = phy_info->mmio_base;
> +			*ch = DPIO_CH0;
> +			return;
> +		}
> +
> +		if (phy_info->dual_channel &&
> +		    port == phy_info->channel[DPIO_CH1].port) {
> +			*mmio_base = phy_info->mmio_base;
> +			*ch = DPIO_CH1;
> +			return;
> +		}
> +	}
> +
> +	WARN(1, "PHY not found for PORT %c", port_name(port));
> +	*mmio_base = BXT_PHY0_BASE;
> +	*ch = DPIO_CH0;
> +}
> +
>  void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
>  				  enum port port, u32 margin, u32 scale,
>  				  u32 enable, u32 deemphasis)
>  {
>  	u32 val;
> +	u32 phy;
> +	enum dpio_channel ch;
> +
> +	bxt_port_to_phy_channel(port, &phy, &ch);
>  
>  	/*
>  	 * While we write to the group register to program all lanes at once we
>  	 * can read only lane registers and we pick lanes 0/1 for that.
>  	 */
> -	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
> +	val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
>  	val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
> -	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
> +	I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
>  
> -	val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
> +	val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch));
>  	val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
>  	val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT;
> -	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
> +	I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val);
>  
> -	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
> +	val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch));
>  	val &= ~SCALE_DCOMP_METHOD;
>  	if (enable)
>  		val |= SCALE_DCOMP_METHOD;
> @@ -194,16 +233,16 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
>  	if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
>  		DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
>  
> -	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
> +	I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val);
>  
> -	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
> +	val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch));
>  	val &= ~DE_EMPHASIS;
>  	val |= deemphasis << DEEMPH_SHIFT;
> -	I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
> +	I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val);
>  
> -	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
> +	val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
>  	val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
> -	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
> +	I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
>  }
>  
>  bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
> @@ -215,7 +254,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
>  	if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
>  		return false;
>  
> -	if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
> +	if ((I915_READ(BXT_PORT_CL1CM_DW0(phy_info->mmio_base)) &
>  	     (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
>  		DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
>  				 phy);
> @@ -224,7 +263,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
>  	}
>  
>  	if (phy_info->rcomp_phy == -1 &&
> -	    !(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE)) {
> +	    !(I915_READ(BXT_PORT_REF_DW3(phy_info->mmio_base)) & GRC_DONE)) {
>  		DRM_DEBUG_DRIVER("DDI PHY %d powered, but GRC isn't done\n",
>  				 phy);
>  
> @@ -256,7 +295,11 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
>  
>  static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
>  {
> -	u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
> +	const struct bxt_ddi_phy_info *phy_info;
> +	u32 val;
> +
> +	phy_info = &bxt_ddi_phy_info[phy];
> +	val = I915_READ(BXT_PORT_REF_DW6(phy_info->mmio_base));
>  
>  	return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
>  }
> @@ -264,8 +307,12 @@ static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
>  static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
>  				  enum dpio_phy phy)
>  {
> +	const struct bxt_ddi_phy_info *phy_info;
> +
> +	phy_info = &bxt_ddi_phy_info[phy];
> +
>  	if (intel_wait_for_register(dev_priv,
> -				    BXT_PORT_REF_DW3(phy),
> +				    BXT_PORT_REF_DW3(phy_info->mmio_base),
>  				    GRC_DONE, GRC_DONE,
>  				    10))
>  		DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
> @@ -305,35 +352,35 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
>  	 * HW team confirmed that the time to reach phypowergood status is
>  	 * anywhere between 50 us and 100us.
>  	 */
> -	if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
> +	if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy_info->mmio_base)) &
>  		(PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
>  		DRM_ERROR("timeout during PHY%d power on\n", phy);
>  	}
>  
>  	/* Program PLL Rcomp code offset */
> -	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
> +	val = I915_READ(BXT_PORT_CL1CM_DW9(phy_info->mmio_base));
>  	val &= ~IREF0RC_OFFSET_MASK;
>  	val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
> -	I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
> +	I915_WRITE(BXT_PORT_CL1CM_DW9(phy_info->mmio_base), val);
>  
> -	val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
> +	val = I915_READ(BXT_PORT_CL1CM_DW10(phy_info->mmio_base));
>  	val &= ~IREF1RC_OFFSET_MASK;
>  	val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
> -	I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
> +	I915_WRITE(BXT_PORT_CL1CM_DW10(phy_info->mmio_base), val);
>  
>  	/* Program power gating */
> -	val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
> +	val = I915_READ(BXT_PORT_CL1CM_DW28(phy_info->mmio_base));
>  	val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
>  		SUS_CLK_CONFIG;
> -	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
> +	I915_WRITE(BXT_PORT_CL1CM_DW28(phy_info->mmio_base), val);
>  
>  	if (phy_info->dual_channel) {
> -		val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
> +		val = I915_READ(BXT_PORT_CL2CM_DW6(phy_info->mmio_base));
>  		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
> -		I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
> +		I915_WRITE(BXT_PORT_CL2CM_DW6(phy_info->mmio_base), val);
>  	}
>  
> -	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
> +	val = I915_READ(BXT_PORT_CL1CM_DW30(phy_info->mmio_base));
>  	val &= ~OCL2_LDOFUSE_PWR_DIS;
>  	/*
>  	 * On PHY1 disable power on the second channel, since no port is
> @@ -347,7 +394,7 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
>  	 */
>  	if (!phy_info->dual_channel)
>  		val |= OCL2_LDOFUSE_PWR_DIS;
> -	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
> +	I915_WRITE(BXT_PORT_CL1CM_DW30(phy_info->mmio_base), val);
>  
>  	if (phy_info->rcomp_phy != -1) {
>  		uint32_t grc_code;
> @@ -361,11 +408,11 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
>  		grc_code = val << GRC_CODE_FAST_SHIFT |
>  			   val << GRC_CODE_SLOW_SHIFT |
>  			   val;
> -		I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code);
> +		I915_WRITE(BXT_PORT_REF_DW6(phy_info->mmio_base), grc_code);
>  
> -		val = I915_READ(BXT_PORT_REF_DW8(phy));
> +		val = I915_READ(BXT_PORT_REF_DW8(phy_info->mmio_base));
>  		val |= GRC_DIS | GRC_RDY_OVRD;
> -		I915_WRITE(BXT_PORT_REF_DW8(phy), val);
> +		I915_WRITE(BXT_PORT_REF_DW8(phy_info->mmio_base), val);
>  	}
>  
>  	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> @@ -461,20 +508,20 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
>  	ok = true;
>  
>  	/* PLL Rcomp code offset */
> -	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
> +	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy_info->mmio_base),
>  		    IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
>  		    "BXT_PORT_CL1CM_DW9(%d)", phy);
> -	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
> +	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy_info->mmio_base),
>  		    IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
>  		    "BXT_PORT_CL1CM_DW10(%d)", phy);
>  
>  	/* Power gating */
>  	mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
> -	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
> +	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy_info->mmio_base), mask, mask,
>  		    "BXT_PORT_CL1CM_DW28(%d)", phy);
>  
>  	if (phy_info->dual_channel)
> -		ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
> +		ok &= _CHK(BXT_PORT_CL2CM_DW6(phy_info->mmio_base),
>  			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
>  			   "BXT_PORT_CL2CM_DW6(%d)", phy);
>  
> @@ -491,11 +538,11 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
>  			   grc_code;
>  		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
>  		       GRC_CODE_NOM_MASK;
> -		ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
> -			    "BXT_PORT_REF_DW6(%d)", phy);
> +		ok &= _CHK(BXT_PORT_REF_DW6(phy_info->mmio_base), mask,
> +			   grc_code, "BXT_PORT_REF_DW6(%d)", phy);
>  
>  		mask = GRC_DIS | GRC_RDY_OVRD;
> -		ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
> +		ok &= _CHK(BXT_PORT_REF_DW8(phy_info->mmio_base), mask, mask,
>  			    "BXT_PORT_REF_DW8(%d)", phy);
>  	}
>  
> @@ -527,10 +574,14 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
>  	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
>  	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
>  	enum port port = dport->port;
> +	u32 phy;
> +	enum dpio_channel ch;
>  	int lane;
>  
> +	bxt_port_to_phy_channel(port, &phy, &ch);
> +
>  	for (lane = 0; lane < 4; lane++) {
> -		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
> +		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
>  
>  		/*
>  		 * Note that on CHV this flag is called UPAR, but has
> @@ -540,7 +591,7 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
>  		if (lane_lat_optim_mask & BIT(lane))
>  			val |= LATENCY_OPTIM;
>  
> -		I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
> +		I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val);
>  	}
>  }
>  
> @@ -550,12 +601,16 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
>  	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
>  	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
>  	enum port port = dport->port;
> +	u32 phy;
> +	enum dpio_channel ch;
>  	int lane;
>  	uint8_t mask;
>  
> +	bxt_port_to_phy_channel(port, &phy, &ch);
> +
>  	mask = 0;
>  	for (lane = 0; lane < 4; lane++) {
> -		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
> +		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
>  
>  		if (val & LATENCY_OPTIM)
>  			mask |= BIT(lane);
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 1c59ca5..a4a9f05 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1371,6 +1371,10 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
>  {
>  	uint32_t temp;
>  	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
> +	u32 phy;
> +	enum dpio_channel ch;
> +
> +	bxt_port_to_phy_channel(port, &phy, &ch);
>  
>  	/* Non-SSC reference */
>  	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> @@ -1378,72 +1382,72 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
>  	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
>  
>  	/* Disable 10 bit clock */
> -	temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
> +	temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
>  	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
> -	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
> +	I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
>  
>  	/* Write P1 & P2 */
> -	temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
> +	temp = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
>  	temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
>  	temp |= pll->config.hw_state.ebb0;
> -	I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
> +	I915_WRITE(BXT_PORT_PLL_EBB_0(phy, ch), temp);
>  
>  	/* Write M2 integer */
> -	temp = I915_READ(BXT_PORT_PLL(port, 0));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 0));
>  	temp &= ~PORT_PLL_M2_MASK;
>  	temp |= pll->config.hw_state.pll0;
> -	I915_WRITE(BXT_PORT_PLL(port, 0), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 0), temp);
>  
>  	/* Write N */
> -	temp = I915_READ(BXT_PORT_PLL(port, 1));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 1));
>  	temp &= ~PORT_PLL_N_MASK;
>  	temp |= pll->config.hw_state.pll1;
> -	I915_WRITE(BXT_PORT_PLL(port, 1), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 1), temp);
>  
>  	/* Write M2 fraction */
> -	temp = I915_READ(BXT_PORT_PLL(port, 2));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 2));
>  	temp &= ~PORT_PLL_M2_FRAC_MASK;
>  	temp |= pll->config.hw_state.pll2;
> -	I915_WRITE(BXT_PORT_PLL(port, 2), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 2), temp);
>  
>  	/* Write M2 fraction enable */
> -	temp = I915_READ(BXT_PORT_PLL(port, 3));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 3));
>  	temp &= ~PORT_PLL_M2_FRAC_ENABLE;
>  	temp |= pll->config.hw_state.pll3;
> -	I915_WRITE(BXT_PORT_PLL(port, 3), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 3), temp);
>  
>  	/* Write coeff */
> -	temp = I915_READ(BXT_PORT_PLL(port, 6));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 6));
>  	temp &= ~PORT_PLL_PROP_COEFF_MASK;
>  	temp &= ~PORT_PLL_INT_COEFF_MASK;
>  	temp &= ~PORT_PLL_GAIN_CTL_MASK;
>  	temp |= pll->config.hw_state.pll6;
> -	I915_WRITE(BXT_PORT_PLL(port, 6), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 6), temp);
>  
>  	/* Write calibration val */
> -	temp = I915_READ(BXT_PORT_PLL(port, 8));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 8));
>  	temp &= ~PORT_PLL_TARGET_CNT_MASK;
>  	temp |= pll->config.hw_state.pll8;
> -	I915_WRITE(BXT_PORT_PLL(port, 8), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 8), temp);
>  
> -	temp = I915_READ(BXT_PORT_PLL(port, 9));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 9));
>  	temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
>  	temp |= pll->config.hw_state.pll9;
> -	I915_WRITE(BXT_PORT_PLL(port, 9), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 9), temp);
>  
> -	temp = I915_READ(BXT_PORT_PLL(port, 10));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 10));
>  	temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
>  	temp &= ~PORT_PLL_DCO_AMP_MASK;
>  	temp |= pll->config.hw_state.pll10;
> -	I915_WRITE(BXT_PORT_PLL(port, 10), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 10), temp);
>  
>  	/* Recalibrate with new settings */
> -	temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
> +	temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
>  	temp |= PORT_PLL_RECALIBRATE;
> -	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
> +	I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
>  	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
>  	temp |= pll->config.hw_state.ebb4;
> -	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
> +	I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
>  
>  	/* Enable PLL */
>  	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> @@ -1459,11 +1463,11 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
>  	 * While we write to the group register to program all lanes at once we
>  	 * can read only lane registers and we pick lanes 0/1 for that.
>  	 */
> -	temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
> +	temp = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
>  	temp &= ~LANE_STAGGER_MASK;
>  	temp &= ~LANESTAGGER_STRAP_OVRD;
>  	temp |= pll->config.hw_state.pcsdw12;
> -	I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
> +	I915_WRITE(BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
>  }
>  
>  static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
> @@ -1485,6 +1489,10 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
>  	uint32_t val;
>  	bool ret;
> +	u32 phy;
> +	enum dpio_channel ch;
> +
> +	bxt_port_to_phy_channel(port, &phy, &ch);
>  
>  	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
>  		return false;
> @@ -1495,36 +1503,36 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  	if (!(val & PORT_PLL_ENABLE))
>  		goto out;
>  
> -	hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
> +	hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
>  	hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
>  
> -	hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
> +	hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
>  	hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
>  
> -	hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
> +	hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0));
>  	hw_state->pll0 &= PORT_PLL_M2_MASK;
>  
> -	hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
> +	hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1));
>  	hw_state->pll1 &= PORT_PLL_N_MASK;
>  
> -	hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
> +	hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2));
>  	hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
>  
> -	hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
> +	hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3));
>  	hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
>  
> -	hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
> +	hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6));
>  	hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
>  			  PORT_PLL_INT_COEFF_MASK |
>  			  PORT_PLL_GAIN_CTL_MASK;
>  
> -	hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
> +	hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8));
>  	hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
>  
> -	hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
> +	hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9));
>  	hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
>  
> -	hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
> +	hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10));
>  	hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
>  			   PORT_PLL_DCO_AMP_MASK;
>  
> @@ -1533,11 +1541,11 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  	 * can read only lane registers. We configure all lanes the same way, so
>  	 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
>  	 */
> -	hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
> -	if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
> +	hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
> +	if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
>  		DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
>  				 hw_state->pcsdw12,
> -				 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
> +				 I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)));
>  	hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
>  
>  	ret = true;
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✗ Fi.CI.BAT: warning for Broxton ddi phy refactoring

[Patchwork]

== Series Details ==

Series: Broxton ddi phy refactoring
URL   : https://patchwork.freedesktop.org/series/13320/
State : warning

== Summary ==

Series 13320v1 Broxton ddi phy refactoring
https://patchwork.freedesktop.org/api/1.0/series/13320/revisions/1/mbox/

Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                dmesg-warn -> PASS       (fi-byt-j1900)
        Subgroup suspend-read-crc-pipe-b:
                pass       -> DMESG-WARN (fi-byt-j1900)
Test kms_psr_sink_crc:
        Subgroup psr_basic:
                dmesg-warn -> PASS       (fi-skl-6700hq)

fi-bdw-5557u     total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050     total:244  pass:202  dwarn:0   dfail:0   fail:0   skip:42 
fi-bxt-t5700     total:244  pass:214  dwarn:0   dfail:0   fail:0   skip:30 
fi-byt-j1900     total:244  pass:211  dwarn:1   dfail:0   fail:1   skip:31 
fi-byt-n2820     total:244  pass:208  dwarn:0   dfail:0   fail:1   skip:35 
fi-hsw-4770      total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-hsw-4770r     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ilk-650       total:244  pass:182  dwarn:0   dfail:0   fail:2   skip:60 
fi-ivb-3520m     total:244  pass:219  dwarn:0   dfail:0   fail:0   skip:25 
fi-ivb-3770      total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 
fi-kbl-7200u     total:244  pass:220  dwarn:0   dfail:0   fail:0   skip:24 
fi-skl-6260u     total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6700k     total:244  pass:219  dwarn:1   dfail:0   fail:0   skip:24 
fi-skl-6770hq    total:244  pass:228  dwarn:1   dfail:0   fail:1   skip:14 
fi-snb-2520m     total:244  pass:208  dwarn:0   dfail:0   fail:0   skip:36 
fi-snb-2600      total:244  pass:207  dwarn:0   dfail:0   fail:0   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_2628/

0ff41ae4e5f0bbbb83e3abcc170c1dab648f28b3 drm-intel-nightly: 2016y-10m-05d-09h-47m-15s UTC integration manifest
dae03a4 drm/i915: Address broxton phy registers based on phy and channel number
474f0a2 drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_info
12bf891 drm/i915: Create a struct to hold information about the broxton phys
13a64e5 drm/i915: Move broxton vswing sequence to intel_dpio_phy.c
76d4a1d drm/i915: Move DPIO phy documentation section to intel_dpio_phy.c
88e0e98 drm/i915: Move broxton phy code to intel_dpio_phy.c
3cbc17f drm/i915: Pass lane count to bxt_ddi_phy_calc_lane_optmin_mask()
158e044 drm/i915: Explicitly map broxton DPIO power wells to phys
a7ca7d0 drm/i915: Rename struct i915_power_well field data to id

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