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From: Andrew Jones <drjones@redhat.com>
To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
	qemu-devel@nongnu.org, qemu-arm@nongnu.org
Cc: marc.zyngier@arm.com, andre.przywara@arm.com, pbonzini@redhat.com
Subject: [kvm-unit-tests PATCH v6 04/11] arm/arm64: add some delay routines
Date: Mon, 14 Nov 2016 22:08:32 +0100	[thread overview]
Message-ID: <1479157719-31021-5-git-send-email-drjones@redhat.com> (raw)
In-Reply-To: <1479157719-31021-1-git-send-email-drjones@redhat.com>

Allow a thread to wait some specified amount of time. Can
specify in cycles, usecs, and msecs.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
---
 lib/arm/asm/processor.h   | 19 +++++++++++++++++++
 lib/arm/processor.c       | 15 +++++++++++++++
 lib/arm64/asm/processor.h | 19 +++++++++++++++++++
 lib/arm64/processor.c     | 15 +++++++++++++++
 4 files changed, 68 insertions(+)

diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h
index ecf5bbe1824a..bc46d1f980ee 100644
--- a/lib/arm/asm/processor.h
+++ b/lib/arm/asm/processor.h
@@ -5,7 +5,9 @@
  *
  * This work is licensed under the terms of the GNU LGPL, version 2.
  */
+#include <libcflat.h>
 #include <asm/ptrace.h>
+#include <asm/barrier.h>
 
 enum vector {
 	EXCPTN_RST,
@@ -51,4 +53,21 @@ extern int mpidr_to_cpu(unsigned long mpidr);
 extern void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr);
 extern bool is_user(void);
 
+static inline u64 get_cntvct(void)
+{
+	u64 vct;
+	isb();
+	asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (vct));
+	return vct;
+}
+
+extern void delay(u64 cycles);
+extern void udelay(unsigned long usecs);
+
+static inline void mdelay(unsigned long msecs)
+{
+	while (msecs--)
+		udelay(1000);
+}
+
 #endif /* _ASMARM_PROCESSOR_H_ */
diff --git a/lib/arm/processor.c b/lib/arm/processor.c
index 54fdb87ef019..c2ee360df688 100644
--- a/lib/arm/processor.c
+++ b/lib/arm/processor.c
@@ -9,6 +9,7 @@
 #include <asm/ptrace.h>
 #include <asm/processor.h>
 #include <asm/thread_info.h>
+#include <asm/barrier.h>
 
 static const char *processor_modes[] = {
 	"USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" ,
@@ -141,3 +142,17 @@ bool is_user(void)
 {
 	return current_thread_info()->flags & TIF_USER_MODE;
 }
+
+void delay(u64 cycles)
+{
+	u64 start = get_cntvct();
+	while ((get_cntvct() - start) < cycles)
+		cpu_relax();
+}
+
+void udelay(unsigned long usec)
+{
+	unsigned int frq;
+	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq));
+	delay((u64)usec * frq / 1000000);
+}
diff --git a/lib/arm64/asm/processor.h b/lib/arm64/asm/processor.h
index 7e448dc81a6a..94f7ce35b65c 100644
--- a/lib/arm64/asm/processor.h
+++ b/lib/arm64/asm/processor.h
@@ -17,8 +17,10 @@
 #define SCTLR_EL1_M	(1 << 0)
 
 #ifndef __ASSEMBLY__
+#include <libcflat.h>
 #include <asm/ptrace.h>
 #include <asm/esr.h>
+#include <asm/barrier.h>
 
 enum vector {
 	EL1T_SYNC,
@@ -89,5 +91,22 @@ extern int mpidr_to_cpu(unsigned long mpidr);
 extern void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr);
 extern bool is_user(void);
 
+static inline u64 get_cntvct(void)
+{
+	u64 vct;
+	isb();
+	asm volatile("mrs %0, cntvct_el0" : "=r" (vct));
+	return vct;
+}
+
+extern void delay(u64 cycles);
+extern void udelay(unsigned long usecs);
+
+static inline void mdelay(unsigned long msecs)
+{
+	while (msecs--)
+		udelay(1000);
+}
+
 #endif /* !__ASSEMBLY__ */
 #endif /* _ASMARM64_PROCESSOR_H_ */
diff --git a/lib/arm64/processor.c b/lib/arm64/processor.c
index deeab4ec9c8a..50fa835c6f1e 100644
--- a/lib/arm64/processor.c
+++ b/lib/arm64/processor.c
@@ -9,6 +9,7 @@
 #include <asm/ptrace.h>
 #include <asm/processor.h>
 #include <asm/thread_info.h>
+#include <asm/barrier.h>
 
 static const char *vector_names[] = {
 	"el1t_sync",
@@ -253,3 +254,17 @@ bool is_user(void)
 {
 	return current_thread_info()->flags & TIF_USER_MODE;
 }
+
+void delay(u64 cycles)
+{
+	u64 start = get_cntvct();
+	while ((get_cntvct() - start) < cycles)
+		cpu_relax();
+}
+
+void udelay(unsigned long usec)
+{
+	unsigned int frq;
+	asm volatile("mrs %0, cntfrq_el0" : "=r" (frq));
+	delay((u64)usec * frq / 1000000);
+}
-- 
2.7.4

_______________________________________________
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kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <drjones@redhat.com>
To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
	qemu-devel@nongnu.org, qemu-arm@nongnu.org
Cc: pbonzini@redhat.com, andre.przywara@arm.com,
	peter.maydell@linaro.org, alex.bennee@linaro.org,
	marc.zyngier@arm.com, eric.auger@redhat.com,
	christoffer.dall@linaro.org
Subject: [Qemu-devel] [kvm-unit-tests PATCH v6 04/11] arm/arm64: add some delay routines
Date: Mon, 14 Nov 2016 22:08:32 +0100	[thread overview]
Message-ID: <1479157719-31021-5-git-send-email-drjones@redhat.com> (raw)
In-Reply-To: <1479157719-31021-1-git-send-email-drjones@redhat.com>

Allow a thread to wait some specified amount of time. Can
specify in cycles, usecs, and msecs.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
---
 lib/arm/asm/processor.h   | 19 +++++++++++++++++++
 lib/arm/processor.c       | 15 +++++++++++++++
 lib/arm64/asm/processor.h | 19 +++++++++++++++++++
 lib/arm64/processor.c     | 15 +++++++++++++++
 4 files changed, 68 insertions(+)

diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h
index ecf5bbe1824a..bc46d1f980ee 100644
--- a/lib/arm/asm/processor.h
+++ b/lib/arm/asm/processor.h
@@ -5,7 +5,9 @@
  *
  * This work is licensed under the terms of the GNU LGPL, version 2.
  */
+#include <libcflat.h>
 #include <asm/ptrace.h>
+#include <asm/barrier.h>
 
 enum vector {
 	EXCPTN_RST,
@@ -51,4 +53,21 @@ extern int mpidr_to_cpu(unsigned long mpidr);
 extern void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr);
 extern bool is_user(void);
 
+static inline u64 get_cntvct(void)
+{
+	u64 vct;
+	isb();
+	asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (vct));
+	return vct;
+}
+
+extern void delay(u64 cycles);
+extern void udelay(unsigned long usecs);
+
+static inline void mdelay(unsigned long msecs)
+{
+	while (msecs--)
+		udelay(1000);
+}
+
 #endif /* _ASMARM_PROCESSOR_H_ */
diff --git a/lib/arm/processor.c b/lib/arm/processor.c
index 54fdb87ef019..c2ee360df688 100644
--- a/lib/arm/processor.c
+++ b/lib/arm/processor.c
@@ -9,6 +9,7 @@
 #include <asm/ptrace.h>
 #include <asm/processor.h>
 #include <asm/thread_info.h>
+#include <asm/barrier.h>
 
 static const char *processor_modes[] = {
 	"USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" ,
@@ -141,3 +142,17 @@ bool is_user(void)
 {
 	return current_thread_info()->flags & TIF_USER_MODE;
 }
+
+void delay(u64 cycles)
+{
+	u64 start = get_cntvct();
+	while ((get_cntvct() - start) < cycles)
+		cpu_relax();
+}
+
+void udelay(unsigned long usec)
+{
+	unsigned int frq;
+	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq));
+	delay((u64)usec * frq / 1000000);
+}
diff --git a/lib/arm64/asm/processor.h b/lib/arm64/asm/processor.h
index 7e448dc81a6a..94f7ce35b65c 100644
--- a/lib/arm64/asm/processor.h
+++ b/lib/arm64/asm/processor.h
@@ -17,8 +17,10 @@
 #define SCTLR_EL1_M	(1 << 0)
 
 #ifndef __ASSEMBLY__
+#include <libcflat.h>
 #include <asm/ptrace.h>
 #include <asm/esr.h>
+#include <asm/barrier.h>
 
 enum vector {
 	EL1T_SYNC,
@@ -89,5 +91,22 @@ extern int mpidr_to_cpu(unsigned long mpidr);
 extern void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr);
 extern bool is_user(void);
 
+static inline u64 get_cntvct(void)
+{
+	u64 vct;
+	isb();
+	asm volatile("mrs %0, cntvct_el0" : "=r" (vct));
+	return vct;
+}
+
+extern void delay(u64 cycles);
+extern void udelay(unsigned long usecs);
+
+static inline void mdelay(unsigned long msecs)
+{
+	while (msecs--)
+		udelay(1000);
+}
+
 #endif /* !__ASSEMBLY__ */
 #endif /* _ASMARM64_PROCESSOR_H_ */
diff --git a/lib/arm64/processor.c b/lib/arm64/processor.c
index deeab4ec9c8a..50fa835c6f1e 100644
--- a/lib/arm64/processor.c
+++ b/lib/arm64/processor.c
@@ -9,6 +9,7 @@
 #include <asm/ptrace.h>
 #include <asm/processor.h>
 #include <asm/thread_info.h>
+#include <asm/barrier.h>
 
 static const char *vector_names[] = {
 	"el1t_sync",
@@ -253,3 +254,17 @@ bool is_user(void)
 {
 	return current_thread_info()->flags & TIF_USER_MODE;
 }
+
+void delay(u64 cycles)
+{
+	u64 start = get_cntvct();
+	while ((get_cntvct() - start) < cycles)
+		cpu_relax();
+}
+
+void udelay(unsigned long usec)
+{
+	unsigned int frq;
+	asm volatile("mrs %0, cntfrq_el0" : "=r" (frq));
+	delay((u64)usec * frq / 1000000);
+}
-- 
2.7.4

  parent reply	other threads:[~2016-11-14 21:08 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-14 21:08 [kvm-unit-tests PATCH v6 00/11] arm/arm64: add gic framework Andrew Jones
2016-11-14 21:08 ` [Qemu-devel] " Andrew Jones
2016-11-14 21:08 ` [kvm-unit-tests PATCH v6 01/11] lib: xstr: allow multiple args Andrew Jones
2016-11-14 21:08   ` [Qemu-devel] " Andrew Jones
2016-11-14 21:08 ` [kvm-unit-tests PATCH v6 02/11] arm64: fix get_"sysreg32" and make MPIDR 64bit Andrew Jones
2016-11-14 21:08   ` [Qemu-devel] " Andrew Jones
2016-11-14 21:08 ` [kvm-unit-tests PATCH v6 03/11] arm/arm64: smp: support more than 8 cpus Andrew Jones
2016-11-14 21:08   ` [Qemu-devel] " Andrew Jones
2016-11-23 10:38   ` Auger Eric
2016-11-23 10:38     ` [Qemu-devel] " Auger Eric
2016-11-14 21:08 ` Andrew Jones [this message]
2016-11-14 21:08   ` [Qemu-devel] [kvm-unit-tests PATCH v6 04/11] arm/arm64: add some delay routines Andrew Jones
2016-11-14 21:08 ` [kvm-unit-tests PATCH v6 05/11] arm/arm64: irq enable/disable Andrew Jones
2016-11-14 21:08   ` [Qemu-devel] " Andrew Jones
2016-11-14 21:08 ` [kvm-unit-tests PATCH v6 06/11] arm/arm64: add initial gicv2 support Andrew Jones
2016-11-14 21:08   ` [Qemu-devel] " Andrew Jones
2016-11-23 10:38   ` Auger Eric
2016-11-23 10:38     ` [Qemu-devel] " Auger Eric
2016-11-14 21:08 ` [kvm-unit-tests PATCH v6 07/11] arm/arm64: gicv2: add an IPI test Andrew Jones
2016-11-14 21:08   ` [Qemu-devel] " Andrew Jones
2016-11-14 21:08 ` [kvm-unit-tests PATCH v6 08/11] libcflat: add IS_ALIGNED() macro, and page sizes Andrew Jones
2016-11-14 21:08   ` [Qemu-devel] " Andrew Jones
2016-11-23 10:38   ` Auger Eric
2016-11-23 10:38     ` [Qemu-devel] " Auger Eric
2016-11-14 21:08 ` [kvm-unit-tests PATCH v6 09/11] arm/arm64: add initial gicv3 support Andrew Jones
2016-11-14 21:08   ` [Qemu-devel] " Andrew Jones
2016-11-23 10:38   ` Auger Eric
2016-11-23 10:38     ` [Qemu-devel] " Auger Eric
2016-11-14 21:08 ` [kvm-unit-tests PATCH v6 10/11] arm/arm64: gicv3: add an IPI test Andrew Jones
2016-11-14 21:08   ` [Qemu-devel] " Andrew Jones
2016-11-23 11:05   ` Auger Eric
2016-11-23 11:05     ` [Qemu-devel] " Auger Eric
2016-11-23 12:57     ` Andrew Jones
2016-11-23 12:57       ` Andrew Jones
2016-11-14 21:08 ` [kvm-unit-tests PATCH v6 11/11] arm/arm64: gic: don't just use zero Andrew Jones
2016-11-14 21:08   ` [Qemu-devel] " Andrew Jones
2016-11-23 11:28   ` Auger Eric
2016-11-23 11:28     ` [Qemu-devel] " Auger Eric
2016-11-23 13:01     ` Andrew Jones
2016-11-23 13:01       ` [Qemu-devel] " Andrew Jones
2016-11-23 13:33       ` Auger Eric
2016-11-23 13:33         ` [Qemu-devel] " Auger Eric
2016-11-23 13:46         ` Andrew Jones
2016-11-23 13:46           ` [Qemu-devel] " Andrew Jones
2016-11-22 18:45 ` [Qemu-devel] [kvm-unit-tests PATCH v6 00/11] arm/arm64: add gic framework Andrew Jones
2016-11-23  9:55   ` Andre Przywara
2016-11-23  9:55     ` Andre Przywara
2016-11-23 10:09   ` Alex Bennée
2016-11-23 10:09     ` Alex Bennée
2016-11-23 11:33     ` Auger Eric
2016-11-23 11:33       ` Auger Eric
2016-11-23 13:08       ` Andrew Jones

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