* [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support
@ 2016-12-27 10:04 Peng Fan
2016-12-27 10:04 ` [U-Boot] [PATCH V2 01/20] imx: mx7ulp: Add mx7ulp to Kconfig Peng Fan
` (20 more replies)
0 siblings, 21 replies; 48+ messages in thread
From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw)
To: u-boot
This patchset is to add i.MX7 ULP support default enabling OF_CONTROL.
Also there are some new IPs, such lpi2c/lpuart/rapid gpio2p and etc.
V2:
Restructure the lpuart driver and add i.MX7ULP support.
Reuse code in imx-common
Add HAB support
Add plugin support
Add wdog file license
Add maintainer file
Addressed some issues in board code.
Peng Fan (17):
imx: mx7ulp: Add mx7ulp to Kconfig
imx: mx7ulp: add registers header file
imx: mx7ulp: add iomux driver to support IOMUXC0 and IOMUXC1
imx: mx7ulp: Add clock framework and functions
imx: mx7ulp: Add soc level initialization codes and functions
imx: mx7ulp: handle all the lpuarts in get_lpuart_clk
gpio: Add Rapid GPIO2P driver for i.MX7ULP
mxc_ocotp: Update driver to support OCOTP controller on i.MX7ULP
pinctrl: Add i.MX7ULP pinctrl driver
i2c: lpi2c: add lpi2c driver for i.MX7ULP
serial: lpuart: restructure lpuart driver
serial: lpuart: add i.MX7ULP support
mx7ulp: Add HAB boot support
arm: dts: add i.MX7ULP dtsi file
mmc: fsl_esdhc: support i.MX7ULP
imx: imx7ulp: add EVK board support
imx: mx7ulp_evk: enable mmc/regulator support
Ye Li (3):
imx: mx7ulp: Implement the clock functions for i2c driver
mx7ulp: Add iomux pins header file
wdog: Add the watchdog driver for MX7ULP.
arch/arm/Kconfig | 7 +
arch/arm/Makefile | 2 +-
arch/arm/cpu/armv7/Makefile | 3 +-
arch/arm/cpu/armv7/mx7ulp/Kconfig | 17 +
arch/arm/cpu/armv7/mx7ulp/Makefile | 8 +
arch/arm/cpu/armv7/mx7ulp/clock.c | 364 +++++++
arch/arm/cpu/armv7/mx7ulp/iomux.c | 70 ++
arch/arm/cpu/armv7/mx7ulp/pcc.c | 286 +++++
arch/arm/cpu/armv7/mx7ulp/scg.c | 1086 +++++++++++++++++++
arch/arm/cpu/armv7/mx7ulp/soc.c | 282 +++++
arch/arm/cpu/armv7/vf610/generic.c | 5 +
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imx7ulp-evk.dts | 426 ++++++++
arch/arm/dts/imx7ulp-pinfunc.h | 882 +++++++++++++++
arch/arm/dts/imx7ulp-uboot.dtsi | 43 +
arch/arm/dts/imx7ulp.dtsi | 598 +++++++++++
arch/arm/imx-common/Makefile | 4 +
arch/arm/imx-common/hab.c | 3 +-
.../arm/include/asm/arch-fsl-layerscape/imx-regs.h | 42 -
arch/arm/include/asm/arch-imx/cpu.h | 2 +
arch/arm/include/asm/arch-ls102xa/imx-regs.h | 40 -
arch/arm/include/asm/arch-mx7ulp/clock.h | 43 +
arch/arm/include/asm/arch-mx7ulp/gpio.h | 22 +
arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 1130 ++++++++++++++++++++
arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h | 520 +++++++++
arch/arm/include/asm/arch-mx7ulp/iomux.h | 95 ++
arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h | 910 ++++++++++++++++
arch/arm/include/asm/arch-mx7ulp/pcc.h | 377 +++++++
arch/arm/include/asm/arch-mx7ulp/scg.h | 342 ++++++
arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 21 +
arch/arm/include/asm/arch-vf610/clock.h | 1 +
arch/arm/include/asm/arch-vf610/imx-regs.h | 28 -
arch/arm/include/asm/imx-common/sys_proto.h | 2 +
board/freescale/mx7ulp_evk/Kconfig | 12 +
board/freescale/mx7ulp_evk/MAINTAINERS | 7 +
board/freescale/mx7ulp_evk/Makefile | 10 +
board/freescale/mx7ulp_evk/imximage.cfg | 137 +++
board/freescale/mx7ulp_evk/mx7ulp_evk.c | 48 +
board/freescale/mx7ulp_evk/plugin.S | 224 ++++
configs/mx7ulp_evk_defconfig | 25 +
configs/mx7ulp_evk_plugin_defconfig | 26 +
drivers/gpio/Kconfig | 7 +
drivers/gpio/Makefile | 1 +
drivers/gpio/imx_rgpio2p.c | 224 ++++
drivers/i2c/Kconfig | 6 +
drivers/i2c/Makefile | 1 +
drivers/i2c/imx_lpi2c.c | 462 ++++++++
drivers/misc/mxc_ocotp.c | 52 +-
drivers/mmc/fsl_esdhc.c | 8 +
drivers/pinctrl/nxp/Kconfig | 14 +
drivers/pinctrl/nxp/Makefile | 1 +
drivers/pinctrl/nxp/pinctrl-imx.c | 10 +-
drivers/pinctrl/nxp/pinctrl-imx.h | 3 +
drivers/pinctrl/nxp/pinctrl-imx7ulp.c | 41 +
drivers/serial/serial_lpuart.c | 336 ++++--
drivers/watchdog/Kconfig | 8 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/ulp_wdog.c | 98 ++
include/configs/mx7ulp_evk.h | 203 ++++
include/dt-bindings/clock/imx7ulp-clock.h | 161 +++
include/fsl_lpuart.h | 72 ++
61 files changed, 9631 insertions(+), 230 deletions(-)
create mode 100644 arch/arm/cpu/armv7/mx7ulp/Kconfig
create mode 100644 arch/arm/cpu/armv7/mx7ulp/Makefile
create mode 100644 arch/arm/cpu/armv7/mx7ulp/clock.c
create mode 100644 arch/arm/cpu/armv7/mx7ulp/iomux.c
create mode 100644 arch/arm/cpu/armv7/mx7ulp/pcc.c
create mode 100644 arch/arm/cpu/armv7/mx7ulp/scg.c
create mode 100644 arch/arm/cpu/armv7/mx7ulp/soc.c
create mode 100644 arch/arm/dts/imx7ulp-evk.dts
create mode 100644 arch/arm/dts/imx7ulp-pinfunc.h
create mode 100644 arch/arm/dts/imx7ulp-uboot.dtsi
create mode 100644 arch/arm/dts/imx7ulp.dtsi
create mode 100644 arch/arm/include/asm/arch-mx7ulp/clock.h
create mode 100644 arch/arm/include/asm/arch-mx7ulp/gpio.h
create mode 100644 arch/arm/include/asm/arch-mx7ulp/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h
create mode 100644 arch/arm/include/asm/arch-mx7ulp/iomux.h
create mode 100644 arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h
create mode 100644 arch/arm/include/asm/arch-mx7ulp/pcc.h
create mode 100644 arch/arm/include/asm/arch-mx7ulp/scg.h
create mode 100644 arch/arm/include/asm/arch-mx7ulp/sys_proto.h
create mode 100644 board/freescale/mx7ulp_evk/Kconfig
create mode 100644 board/freescale/mx7ulp_evk/MAINTAINERS
create mode 100644 board/freescale/mx7ulp_evk/Makefile
create mode 100644 board/freescale/mx7ulp_evk/imximage.cfg
create mode 100644 board/freescale/mx7ulp_evk/mx7ulp_evk.c
create mode 100644 board/freescale/mx7ulp_evk/plugin.S
create mode 100644 configs/mx7ulp_evk_defconfig
create mode 100644 configs/mx7ulp_evk_plugin_defconfig
create mode 100644 drivers/gpio/imx_rgpio2p.c
create mode 100644 drivers/i2c/imx_lpi2c.c
create mode 100644 drivers/pinctrl/nxp/pinctrl-imx7ulp.c
create mode 100644 drivers/watchdog/ulp_wdog.c
create mode 100644 include/configs/mx7ulp_evk.h
create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h
create mode 100644 include/fsl_lpuart.h
--
2.6.2
^ permalink raw reply [flat|nested] 48+ messages in thread* [U-Boot] [PATCH V2 01/20] imx: mx7ulp: Add mx7ulp to Kconfig 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2017-02-12 8:39 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 02/20] imx: mx7ulp: add registers header file Peng Fan ` (19 subsequent siblings) 20 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot i.MX7ULP is a new series SoC which has different architecture from previous i.MX platforms. Create a new cpu folder for it, and add it to Kconfig. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: None arch/arm/Kconfig | 7 +++++++ arch/arm/cpu/armv7/Makefile | 3 ++- arch/arm/cpu/armv7/mx7ulp/Kconfig | 6 ++++++ 3 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/mx7ulp/Kconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d871a45..543027c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -461,6 +461,11 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC. +config ARCH_MX7ULP + bool "NXP MX7ULP" + select CPU_V7 + select ROM_UNIFIED_SECTIONS + config ARCH_MX7 bool "Freescale MX7" select CPU_V7 @@ -924,6 +929,8 @@ source "arch/arm/mach-mvebu/Kconfig" source "arch/arm/cpu/armv7/ls102xa/Kconfig" +source "arch/arm/cpu/armv7/mx7ulp/Kconfig" + source "arch/arm/cpu/armv7/mx7/Kconfig" source "arch/arm/cpu/armv7/mx6/Kconfig" diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 0e515a4..02e8778 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,7 +12,7 @@ obj-y += cache_v7.o cache_v7_asm.o obj-y += cpu.o cp15.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_LS102XA),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_ARCH_MX7ULP)$(CONFIG_LS102XA),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif @@ -37,6 +37,7 @@ obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/ obj-$(if $(filter mx5,$(SOC)),y) += mx5/ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ +obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ obj-$(CONFIG_RMOBILE) += rmobile/ obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ diff --git a/arch/arm/cpu/armv7/mx7ulp/Kconfig b/arch/arm/cpu/armv7/mx7ulp/Kconfig new file mode 100644 index 0000000..85efd6d --- /dev/null +++ b/arch/arm/cpu/armv7/mx7ulp/Kconfig @@ -0,0 +1,6 @@ +if ARCH_MX7ULP + +config SYS_SOC + default "mx7ulp" + +endif -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 01/20] imx: mx7ulp: Add mx7ulp to Kconfig 2016-12-27 10:04 ` [U-Boot] [PATCH V2 01/20] imx: mx7ulp: Add mx7ulp to Kconfig Peng Fan @ 2017-02-12 8:39 ` Stefano Babic 0 siblings, 0 replies; 48+ messages in thread From: Stefano Babic @ 2017-02-12 8:39 UTC (permalink / raw) To: u-boot On 27/12/2016 11:04, Peng Fan wrote: > i.MX7ULP is a new series SoC which has different architecture > from previous i.MX platforms. Create a new cpu folder for it, > and add it to Kconfig. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Signed-off-by: Ye Li <ye.li@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > None > > arch/arm/Kconfig | 7 +++++++ > arch/arm/cpu/armv7/Makefile | 3 ++- > arch/arm/cpu/armv7/mx7ulp/Kconfig | 6 ++++++ > 3 files changed, 15 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/cpu/armv7/mx7ulp/Kconfig > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index d871a45..543027c 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -461,6 +461,11 @@ config ARCH_MESON > targeted at media players and tablet computers. We currently > support the S905 (GXBaby) 64-bit SoC. > > +config ARCH_MX7ULP > + bool "NXP MX7ULP" > + select CPU_V7 > + select ROM_UNIFIED_SECTIONS > + > config ARCH_MX7 > bool "Freescale MX7" > select CPU_V7 > @@ -924,6 +929,8 @@ source "arch/arm/mach-mvebu/Kconfig" > > source "arch/arm/cpu/armv7/ls102xa/Kconfig" > > +source "arch/arm/cpu/armv7/mx7ulp/Kconfig" > + > source "arch/arm/cpu/armv7/mx7/Kconfig" > > source "arch/arm/cpu/armv7/mx6/Kconfig" > diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile > index 0e515a4..02e8778 100644 > --- a/arch/arm/cpu/armv7/Makefile > +++ b/arch/arm/cpu/armv7/Makefile > @@ -12,7 +12,7 @@ obj-y += cache_v7.o cache_v7_asm.o > obj-y += cpu.o cp15.o > obj-y += syslib.o > > -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_LS102XA),) > +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_ARCH_MX7ULP)$(CONFIG_LS102XA),) > ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) > obj-y += lowlevel_init.o > endif > @@ -37,6 +37,7 @@ obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/ > obj-$(if $(filter mx5,$(SOC)),y) += mx5/ > obj-$(CONFIG_MX6) += mx6/ > obj-$(CONFIG_MX7) += mx7/ > +obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ > obj-$(CONFIG_RMOBILE) += rmobile/ > obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ > obj-$(CONFIG_ARCH_SUNXI) += sunxi/ > diff --git a/arch/arm/cpu/armv7/mx7ulp/Kconfig b/arch/arm/cpu/armv7/mx7ulp/Kconfig > new file mode 100644 > index 0000000..85efd6d > --- /dev/null > +++ b/arch/arm/cpu/armv7/mx7ulp/Kconfig > @@ -0,0 +1,6 @@ > +if ARCH_MX7ULP > + > +config SYS_SOC > + default "mx7ulp" > + > +endif > Reviewed-by : Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 02/20] imx: mx7ulp: add registers header file 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan 2016-12-27 10:04 ` [U-Boot] [PATCH V2 01/20] imx: mx7ulp: Add mx7ulp to Kconfig Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2017-02-12 8:40 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 03/20] imx: mx7ulp: add iomux driver to support IOMUXC0 and IOMUXC1 Peng Fan ` (18 subsequent siblings) 20 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Add imx-regs.h for i.MX7ULP registers addresses definitions and some registers structures. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: None arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 1125 +++++++++++++++++++++++++++ 1 file changed, 1125 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx7ulp/imx-regs.h diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h new file mode 100644 index 0000000..30d0ba4 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -0,0 +1,1125 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MX7ULP_REGS_H_ +#define _MX7ULP_REGS_H_ + +#include <linux/sizes.h> + +#define CAAM_SEC_SRAM_BASE (0x26000000) +#define CAAM_SEC_SRAM_SIZE (SZ_32K) +#define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) + +#define OCRAM_0_BASE (0x2F000000) +#define OCRAM_0_SIZE (SZ_128K) +#define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1) + +#define OCRAM_1_BASE (0x2F020000) +#define OCRAM_1_SIZE (SZ_128K) +#define OCRAM_1_END (OCRAM_1_BASE + OCRAM_1_SIZE - 1) + +#define TCML_BASE (0x1FFD0000) +#define TCMU_BASE (0x20000000) + +#define AIPS3_BASE (0x40800000UL) +#define AIPS3_SLOT_SIZE (SZ_64K) +#define AIPS2_BASE (0x40000000UL) +#define AIPS2_SLOT_SIZE (SZ_64K) +#define AIPS1_BASE (0x41080000UL) +#define AIPS1_SLOT_SIZE (SZ_4K) +#define AIPS0_BASE (0x41000000UL) +#define AIPS0_SLOT_SIZE (SZ_4K) +#define IOMUXC0_AIPS0_SLOT (61) +#define WDG0_AIPS0_SLOT (37) +#define WDG1_AIPS2_SLOT (61) +#define WDG2_AIPS2_SLOT (67) +#define WDG0_PCC0_SLOT (37) +#define WDG1_PCC2_SLOT (61) +#define IOMUXC1_AIPS3_SLOT (44) +#define CMC0_AIPS1_SLOT (36) +#define CMC1_AIPS2_SLOT (65) +#define SCG0_AIPS0_SLOT (39) +#define PCC0_AIPS0_SLOT (38) +#define PCC1_AIPS1_SLOT (50) +#define PCC2_AIPS2_SLOT (63) +#define PCC3_AIPS3_SLOT (51) +#define SCG1_AIPS2_SLOT (62) +#define SIM0_AIPS1_SLOT (35) +#define SIM1_AIPS1_SLOT (48) +#define USBOTG0_AIPS2_SLOT (51) +#define USBOTG1_AIPS2_SLOT (52) +#define USBPHY_AIPS2_SLOT (53) +#define USDHC0_AIPS2_SLOT (55) +#define USDHC1_AIPS2_SLOT (56) +#define RGPIO2P0_AIPS0_SLOT (15) +#define RGPIO2P1_AIPS2_SLOT (15) +#define IOMUXC0_AIPS0_SLOT (61) +#define OCOTP_CTRL_AIPS1_SLOT (38) +#define OCOTP_CTRL_PCC1_SLOT (38) +#define SIM1_PCC1_SLOT (48) +#define SCG1_PCC2_SLOT (62) +#define MMDC0_AIPS3_SLOT (43) +#define IOMUXC_DDR_AIPS3_SLOT (45) +#define MMDC0_PCC3_SLOT (43) + +#define LPI2C0_AIPS0_SLOT (51) +#define LPI2C1_AIPS0_SLOT (52) +#define LPI2C2_AIPS0_SLOT (53) +#define LPI2C3_AIPS0_SLOT (54) +#define LPI2C4_AIPS2_SLOT (43) +#define LPI2C5_AIPS2_SLOT (44) +#define LPI2C6_AIPS3_SLOT (36) +#define LPI2C7_AIPS3_SLOT (37) + +#define USDHC0_PCC2_SLOT (55) +#define USDHC1_PCC2_SLOT (56) + +#define LPUART0_PCC0_SLOT (58) +#define LPUART1_PCC0_SLOT (59) +#define LPUART2_PCC1_SLOT (43) +#define LPUART3_PCC1_SLOT (44) +#define LPUART4_PCC2_SLOT (45) +#define LPUART5_PCC2_SLOT (46) +#define LPUART6_PCC3_SLOT (38) +#define LPUART7_PCC3_SLOT (39) +#define LPUART0_AIPS0_SLOT (58) +#define LPUART1_AIPS0_SLOT (59) +#define LPUART2_AIPS1_SLOT (43) +#define LPUART3_AIPS1_SLOT (44) +#define LPUART4_AIPS2_SLOT (45) +#define LPUART5_AIPS2_SLOT (46) +#define LPUART6_AIPS3_SLOT (38) +#define LPUART7_AIPS3_SLOT (39) + +#define CORE_B_ROM_SIZE (SZ_32K + SZ_64K) +#define CORE_B_ROM_BASE (0x00000000) + +#define IOMUXC_PCR_MUX_ALT0 (0<<8) +#define IOMUXC_PCR_MUX_ALT1 (1<<8) +#define IOMUXC_PCR_MUX_ALT2 (2<<8) +#define IOMUXC_PCR_MUX_ALT3 (3<<8) +#define IOMUXC_PCR_MUX_ALT4 (4<<8) +#define IOMUXC_PCR_MUX_ALT5 (5<<8) +#define IOMUXC_PCR_MUX_ALT6 (6<<8) +#define IOMUXC_PCR_MUX_ALT7 (7<<8) +#define IOMUXC_PCR_MUX_ALT8 (8<<8) +#define IOMUXC_PCR_MUX_ALT9 (9<<8) +#define IOMUXC_PCR_MUX_ALT10 (10<<8) +#define IOMUXC_PCR_MUX_ALT11 (11<<8) +#define IOMUXC_PCR_MUX_ALT12 (12<<8) +#define IOMUXC_PCR_MUX_ALT13 (13<<8) +#define IOMUXC_PCR_MUX_ALT14 (14<<8) +#define IOMUXC_PCR_MUX_ALT15 (15<<8) + +#define IOMUXC_PSMI_IMUX_ALT0 (0x0) +#define IOMUXC_PSMI_IMUX_ALT1 (0x1) +#define IOMUXC_PSMI_IMUX_ALT2 (0x2) +#define IOMUXC_PSMI_IMUX_ALT3 (0x3) +#define IOMUXC_PSMI_IMUX_ALT4 (0x4) +#define IOMUXC_PSMI_IMUX_ALT5 (0x5) +#define IOMUXC_PSMI_IMUX_ALT6 (0x6) +#define IOMUXC_PSMI_IMUX_ALT7 (0x7) + + +#define SIM_SOPT1_EN_SNVS_HARD_RST (1<<8) +#define SIM_SOPT1_PMIC_STBY_REQ (1<<2) +#define SIM_SOPT1_A7_SW_RESET (1<<0) + +#define IOMUXC_PCR_MUX_ALT_SHIFT (8) +#define IOMUXC_PCR_MUX_ALT_MASK (0xF00) +#define IOMUXC_PSMI_IMUX_ALT_SHIFT (0) + +#define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) +#define IOMUXC1_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC1_AIPS3_SLOT))) +#define WDG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * WDG0_AIPS0_SLOT))) +#define WDG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG1_AIPS2_SLOT))) +#define WDG2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG2_AIPS2_SLOT))) +#define SCG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * SCG0_AIPS0_SLOT))) +#define SCG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SCG1_AIPS2_SLOT))) +#define PCC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * PCC0_AIPS0_SLOT))) +#define PCC1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * PCC1_AIPS1_SLOT))) +#define PCC2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * PCC2_AIPS2_SLOT))) +#define PCC3_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * PCC3_AIPS3_SLOT))) +#define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) +#define PSMI0_RBASE ((IOMUXC0_RBASE + 0x100)) /* in iomuxc0 after pta and ptb */ +#define CMC0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * CMC0_AIPS1_SLOT))) +#define CMC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * CMC1_AIPS2_SLOT))) +#define OCOTP_BASE_ADDR ((AIPS1_BASE + (AIPS1_SLOT_SIZE * OCOTP_CTRL_AIPS1_SLOT))) +#define SIM0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM0_AIPS1_SLOT))) +#define SIM1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM1_AIPS1_SLOT))) +#define MMDC0_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * MMDC0_AIPS3_SLOT))) + +#define USBOTG0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG0_AIPS2_SLOT))) +#define USBOTG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG1_AIPS2_SLOT))) +#define USBPHY_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBPHY_AIPS2_SLOT))) +#define USB_PHY0_BASE_ADDR USBPHY_RBASE +#define USB_BASE_ADDR USBOTG0_RBASE + +#define LPI2C1_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C0_AIPS0_SLOT))) +#define LPI2C2_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C1_AIPS0_SLOT))) +#define LPI2C3_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C2_AIPS0_SLOT))) +#define LPI2C4_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C3_AIPS0_SLOT))) +#define LPI2C5_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C4_AIPS2_SLOT))) +#define LPI2C6_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C5_AIPS2_SLOT))) +#define LPI2C7_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C6_AIPS3_SLOT))) +#define LPI2C8_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C7_AIPS3_SLOT))) + +#define LPUART0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART0_AIPS0_SLOT))) +#define LPUART1_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART1_AIPS0_SLOT))) +#define LPUART2_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART2_AIPS1_SLOT))) +#define LPUART3_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART3_AIPS1_SLOT))) +#define LPUART4_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART4_AIPS2_SLOT))) +#define LPUART5_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART5_AIPS2_SLOT))) +#define LPUART6_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART6_AIPS3_SLOT))) +#define LPUART7_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART7_AIPS3_SLOT))) + +#define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT))) +#define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT))) + +#define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT))) +#define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT))) + +#define WDG0_PCC_REG (PCC0_RBASE + (4 * WDG0_PCC0_SLOT)) +#define WDG1_PCC_REG (PCC2_RBASE + (4 * WDG1_PCC2_SLOT)) +#define CMC0_SRS (CMC0_RBASE + 0x20) +#define CMC0_SSRS (CMC0_RBASE + 0x28) +#define CMC1_SRS (CMC1_RBASE + 0x20) +#define CMC1_SSRS (CMC1_RBASE + 0x28) + +#define IOMUXC0_PCR0 (IOMUXC0_RBASE + (4 * 0)) +#define IOMUXC0_PCR1 (IOMUXC0_RBASE + (4 * 1)) +#define IOMUXC0_PCR2 (IOMUXC0_RBASE + (4 * 2)) +#define IOMUXC0_PCR3 (IOMUXC0_RBASE + (4 * 3)) +#define IOMUXC0_PSMI62 (PSMI0_RBASE + (4 * 62)) +#define IOMUXC0_PSMI63 (PSMI0_RBASE + (4 * 63)) +#define IOMUXC0_PSMI64 (PSMI0_RBASE + (4 * 64)) + +#define SCG_CSR (SCG0_RBASE + 0x010) +#define SCG_RCCR (SCG0_RBASE + 0x014) +#define SCG_VCCR (SCG0_RBASE + 0x018) +#define SCG_HCCR (SCG0_RBASE + 0x01c) + +#define LPUART0_PCC_REG (PCC0_RBASE + (4 * LPUART0_PCC0_SLOT)) +#define LPUART1_PCC_REG (PCC0_RBASE + (4 * LPUART1_PCC0_SLOT)) +#define LPUART2_PCC_REG (PCC1_RBASE + (4 * LPUART2_PCC1_SLOT)) +#define LPUART3_PCC_REG (PCC1_RBASE + (4 * LPUART3_PCC1_SLOT)) +#define LPUART4_PCC_REG (PCC2_RBASE + (4 * LPUART4_PCC2_SLOT)) +#define LPUART5_PCC_REG (PCC2_RBASE + (4 * LPUART5_PCC2_SLOT)) +#define LPUART6_PCC_REG (PCC3_RBASE + (4 * LPUART6_PCC3_SLOT)) +#define LPUART7_PCC_REG (PCC3_RBASE + (4 * LPUART7_PCC3_SLOT)) + +#define USDHC0_PCC_REG (PCC2_RBASE + (4 * USDHC0_PCC2_SLOT)) +#define USDHC1_PCC_REG (PCC2_RBASE + (4 * USDHC1_PCC2_SLOT)) + +#define SIM1_PCC_REG (PCC1_RBASE + (4 * SIM1_PCC1_SLOT)) +#define SCG1_PCC_REG (PCC2_RBASE + (4 * SCG1_PCC2_SLOT)) + +#define OCOTP_CTRL_PCC_REG (PCC1_RBASE + (4 * OCOTP_CTRL_PCC1_SLOT)) + +#define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT))) +#define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT)) + +#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) +#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) +#define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) +#define IOMUXC_DPCR_DDR_DQS3 ((IOMUXC_DDR_RBASE + (4 * 35))) + + +#define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0))) +#define IOMUXC_DPCR_DDR_DQ1 ((IOMUXC_DDR_RBASE + (4 * 1))) +#define IOMUXC_DPCR_DDR_DQ2 ((IOMUXC_DDR_RBASE + (4 * 2))) +#define IOMUXC_DPCR_DDR_DQ3 ((IOMUXC_DDR_RBASE + (4 * 3))) +#define IOMUXC_DPCR_DDR_DQ4 ((IOMUXC_DDR_RBASE + (4 * 4))) +#define IOMUXC_DPCR_DDR_DQ5 ((IOMUXC_DDR_RBASE + (4 * 5))) +#define IOMUXC_DPCR_DDR_DQ6 ((IOMUXC_DDR_RBASE + (4 * 6))) +#define IOMUXC_DPCR_DDR_DQ7 ((IOMUXC_DDR_RBASE + (4 * 7))) +#define IOMUXC_DPCR_DDR_DQ8 ((IOMUXC_DDR_RBASE + (4 * 8))) +#define IOMUXC_DPCR_DDR_DQ9 ((IOMUXC_DDR_RBASE + (4 * 9))) +#define IOMUXC_DPCR_DDR_DQ10 ((IOMUXC_DDR_RBASE + (4 * 10))) +#define IOMUXC_DPCR_DDR_DQ11 ((IOMUXC_DDR_RBASE + (4 * 11))) +#define IOMUXC_DPCR_DDR_DQ12 ((IOMUXC_DDR_RBASE + (4 * 12))) +#define IOMUXC_DPCR_DDR_DQ13 ((IOMUXC_DDR_RBASE + (4 * 13))) +#define IOMUXC_DPCR_DDR_DQ14 ((IOMUXC_DDR_RBASE + (4 * 14))) +#define IOMUXC_DPCR_DDR_DQ15 ((IOMUXC_DDR_RBASE + (4 * 15))) +#define IOMUXC_DPCR_DDR_DQ16 ((IOMUXC_DDR_RBASE + (4 * 16))) +#define IOMUXC_DPCR_DDR_DQ17 ((IOMUXC_DDR_RBASE + (4 * 17))) +#define IOMUXC_DPCR_DDR_DQ18 ((IOMUXC_DDR_RBASE + (4 * 18))) +#define IOMUXC_DPCR_DDR_DQ19 ((IOMUXC_DDR_RBASE + (4 * 19))) +#define IOMUXC_DPCR_DDR_DQ20 ((IOMUXC_DDR_RBASE + (4 * 20))) +#define IOMUXC_DPCR_DDR_DQ21 ((IOMUXC_DDR_RBASE + (4 * 21))) +#define IOMUXC_DPCR_DDR_DQ22 ((IOMUXC_DDR_RBASE + (4 * 22))) +#define IOMUXC_DPCR_DDR_DQ23 ((IOMUXC_DDR_RBASE + (4 * 23))) +#define IOMUXC_DPCR_DDR_DQ24 ((IOMUXC_DDR_RBASE + (4 * 24))) +#define IOMUXC_DPCR_DDR_DQ25 ((IOMUXC_DDR_RBASE + (4 * 25))) +#define IOMUXC_DPCR_DDR_DQ26 ((IOMUXC_DDR_RBASE + (4 * 26))) +#define IOMUXC_DPCR_DDR_DQ27 ((IOMUXC_DDR_RBASE + (4 * 27))) +#define IOMUXC_DPCR_DDR_DQ28 ((IOMUXC_DDR_RBASE + (4 * 28))) +#define IOMUXC_DPCR_DDR_DQ29 ((IOMUXC_DDR_RBASE + (4 * 29))) +#define IOMUXC_DPCR_DDR_DQ30 ((IOMUXC_DDR_RBASE + (4 * 30))) +#define IOMUXC_DPCR_DDR_DQ31 ((IOMUXC_DDR_RBASE + (4 * 31))) + +/* Remap the rgpio2p registers addr to driver's addr */ +#define RGPIO2P_GPIO1_BASE_ADDR RGPIO2P0_RBASE +#define RGPIO2P_GPIO2_BASE_ADDR (RGPIO2P0_RBASE + 0x40) +#define RGPIO2P_GPIO3_BASE_ADDR (RGPIO2P1_RBASE) +#define RGPIO2P_GPIO4_BASE_ADDR (RGPIO2P1_RBASE + 0x40) +#define RGPIO2P_GPIO5_BASE_ADDR (RGPIO2P1_RBASE + 0x80) +#define RGPIO2P_GPIO6_BASE_ADDR (RGPIO2P1_RBASE + 0xc0) + +/* MMDC registers addresses */ +#define MMDC_MDCTL_OFFSET (0x000) +#define MMDC_MDPDC_OFFSET (0x004) +#define MMDC_MDOTC_OFFSET (0x008) +#define MMDC_MDCFG0_OFFSET (0x00C) +#define MMDC_MDCFG1_OFFSET (0x010) +#define MMDC_MDCFG2_OFFSET (0x014) +#define MMDC_MDMISC_OFFSET (0x018) +#define MMDC_MDSCR_OFFSET (0x01C) +#define MMDC_MDREF_OFFSET (0x020) +#define MMDC_MDRWD_OFFSET (0x02C) +#define MMDC_MDOR_OFFSET (0x030) +#define MMDC_MDMRR_OFFSET (0x034) +#define MMDC_MDCFG3LP_OFFSET (0x038) +#define MMDC_MDMR4_OFFSET (0x03C) +#define MMDC_MDASP_OFFSET (0x040) + +#define MMDC_MAARCR_OFFSET (0x400) +#define MMDC_MAPSR_OFFSET (0x404) +#define MMDC_MAEXIDR0_OFFSET (0x408) +#define MMDC_MAEXIDR1_OFFSET (0x40C) +#define MMDC_MADPCR0_OFFSET (0x410) +#define MMDC_MADPCR1_OFFSET (0x414) +#define MMDC_MADPSR0_OFFSET (0x418) +#define MMDC_MADPSR1_OFFSET (0x41C) +#define MMDC_MADPSR2_OFFSET (0x420) +#define MMDC_MADPSR3_OFFSET (0x424) +#define MMDC_MADPSR4_OFFSET (0x428) +#define MMDC_MADPSR5_OFFSET (0x42C) +#define MMDC_MASBS0_OFFSET (0x430) +#define MMDC_MASBS1_OFFSET (0x434) +#define MMDC_MAGENP_OFFSET (0x440) + +#define MMDC_MPZQHWCTRL_OFFSET (0x800) +#define MMDC_MPZQSWCTRL_OFFSET (0x804) +#define MMDC_MPWLGCR_OFFSET (0x808) +#define MMDC_MPWLDECTRL0_OFFSET (0x80C) +#define MMDC_MPWLDECTRL1_OFFSET (0x810) +#define MMDC_MPWLDLST_OFFSET (0x814) +#define MMDC_MPODTCTRL_OFFSET (0x818) +#define MMDC_MPREDQBY0DL_OFFSET (0x81C) +#define MMDC_MPREDQBY1DL_OFFSET (0x820) +#define MMDC_MPREDQBY2DL_OFFSET (0x824) +#define MMDC_MPREDQBY3DL_OFFSET (0x828) +#define MMDC_MPWRDQBY0DL_OFFSET (0x82C) +#define MMDC_MPWRDQBY1DL_OFFSET (0x830) +#define MMDC_MPWRDQBY2DL_OFFSET (0x834) +#define MMDC_MPWRDQBY3DL_OFFSET (0x838) +#define MMDC_MPDGCTRL0_OFFSET (0x83C) +#define MMDC_MPDGCTRL1_OFFSET (0x840) +#define MMDC_MPDGDLST_OFFSET (0x844) +#define MMDC_MPRDDLCTL_OFFSET (0x848) +#define MMDC_MPRDDLST_OFFSET (0x84C) +#define MMDC_MPWRDLCTL_OFFSET (0x850) +#define MMDC_MPWRDLST_OFFSET (0x854) +#define MMDC_MPSDCTRL_OFFSET (0x858) +#define MMDC_MPZQLP2CTL_OFFSET (0x85C) +#define MMDC_MPRDDLHWCTL_OFFSET (0x860) +#define MMDC_MPWRDLHWCTL_OFFSET (0x864) +#define MMDC_MPRDDLHWST0_OFFSET (0x868) +#define MMDC_MPRDDLHWST1_OFFSET (0x86C) +#define MMDC_MPWRDLHWST0_OFFSET (0x870) +#define MMDC_MPWRDLHWST1_OFFSET (0x874) +#define MMDC_MPWLHWERR_OFFSET (0x878) +#define MMDC_MPDGHWST0_OFFSET (0x87C) +#define MMDC_MPDGHWST1_OFFSET (0x880) +#define MMDC_MPDGHWST2_OFFSET (0x884) +#define MMDC_MPDGHWST3_OFFSET (0x888) +#define MMDC_MPPDCMPR1_OFFSET (0x88C) +#define MMDC_MPPDCMPR2_OFFSET (0x890) +#define MMDC_MPSWDAR_OFFSET (0x894) +#define MMDC_MPSWDRDR0_OFFSET (0x898) +#define MMDC_MPSWDRDR1_OFFSET (0x89C) +#define MMDC_MPSWDRDR2_OFFSET (0x8A0) +#define MMDC_MPSWDRDR3_OFFSET (0x8A4) +#define MMDC_MPSWDRDR4_OFFSET (0x8A8) +#define MMDC_MPSWDRDR5_OFFSET (0x8AC) +#define MMDC_MPSWDRDR6_OFFSET (0x8B0) +#define MMDC_MPSWDRDR7_OFFSET (0x8B4) +#define MMDC_MPMUR_OFFSET (0x8B8) +#define MMDC_MPWRCADL_OFFSET (0x8BC) +#define MMDC_MPDCCR_OFFSET (0x8C0) +#define MMDC_MPBC_OFFSET (0x8C4) +#define MMDC_MPSWDRAR_OFFSET (0x8C8) + +/* First MMDC invalid IPS address */ +#define MMDC_IPS_ILL_ADDR_START_OFFSET (0x8CC) +#define MMDC_REGS_BASE MMDC0_RBASE + +#define MMDC_MDCTL ((MMDC_REGS_BASE + MMDC_MDCTL_OFFSET)) +#define MMDC_MDPDC ((MMDC_REGS_BASE + MMDC_MDPDC_OFFSET)) +#define MMDC_MDOTC ((MMDC_REGS_BASE + MMDC_MDOTC_OFFSET)) +#define MMDC_MDCFG0 ((MMDC_REGS_BASE + MMDC_MDCFG0_OFFSET)) +#define MMDC_MDCFG1 ((MMDC_REGS_BASE + MMDC_MDCFG1_OFFSET)) +#define MMDC_MDCFG2 ((MMDC_REGS_BASE + MMDC_MDCFG2_OFFSET)) +#define MMDC_MDMISC ((MMDC_REGS_BASE + MMDC_MDMISC_OFFSET)) +#define MMDC_MDSCR ((MMDC_REGS_BASE + MMDC_MDSCR_OFFSET)) +#define MMDC_MDREF ((MMDC_REGS_BASE + MMDC_MDREF_OFFSET)) +#define MMDC_MDRWD ((MMDC_REGS_BASE + MMDC_MDRWD_OFFSET)) +#define MMDC_MDOR ((MMDC_REGS_BASE + MMDC_MDOR_OFFSET)) +#define MMDC_MDMRR ((MMDC_REGS_BASE + MMDC_MDMRR_OFFSET)) +#define MMDC_MDCFG3LP ((MMDC_REGS_BASE + MMDC_MDCFG3LP_OFFSET)) +#define MMDC_MDMR4 ((MMDC_REGS_BASE + MMDC_MDMR4_OFFSET)) +#define MMDC_MDASP ((MMDC_REGS_BASE + MMDC_MDASP_OFFSET)) + +#define MMDC_MAARCR ((MMDC_REGS_BASE + MMDC_MAARCR_OFFSET)) +#define MMDC_MAPSR ((MMDC_REGS_BASE + MMDC_MAPSR_OFFSET)) +#define MMDC_MAEXIDR0 ((MMDC_REGS_BASE + MMDC_MAEXIDR0_OFFSET)) +#define MMDC_MAEXIDR1 ((MMDC_REGS_BASE + MMDC_MAEXIDR1_OFFSET)) +#define MMDC_MADPCR0 ((MMDC_REGS_BASE + MMDC_MADPCR0_OFFSET)) +#define MMDC_MADPCR1 ((MMDC_REGS_BASE + MMDC_MADPCR1_OFFSET)) +#define MMDC_MADPSR0 ((MMDC_REGS_BASE + MMDC_MADPSR0_OFFSET)) +#define MMDC_MADPSR1 ((MMDC_REGS_BASE + MMDC_MADPSR1_OFFSET)) +#define MMDC_MADPSR2 ((MMDC_REGS_BASE + MMDC_MADPSR2_OFFSET)) +#define MMDC_MADPSR3 ((MMDC_REGS_BASE + MMDC_MADPSR3_OFFSET)) +#define MMDC_MADPSR4 ((MMDC_REGS_BASE + MMDC_MADPSR4_OFFSET)) +#define MMDC_MADPSR5 ((MMDC_REGS_BASE + MMDC_MADPSR5_OFFSET)) +#define MMDC_MASBS0 ((MMDC_REGS_BASE + MMDC_MASBS0_OFFSET)) +#define MMDC_MASBS1 ((MMDC_REGS_BASE + MMDC_MASBS1_OFFSET)) +#define MMDC_MAGENP ((MMDC_REGS_BASE + MMDC_MAGENP_OFFSET)) + +#define MMDC_MPZQHWCTRL ((MMDC_REGS_BASE + MMDC_MPZQHWCTRL_OFFSET)) +#define MMDC_MPZQSWCTRL ((MMDC_REGS_BASE + MMDC_MPZQSWCTRL_OFFSET)) +#define MMDC_MPWLGCR ((MMDC_REGS_BASE + MMDC_MPWLGCR_OFFSET)) +#define MMDC_MPWLDECTRL0 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL0_OFFSET)) +#define MMDC_MPWLDECTRL1 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL1_OFFSET)) +#define MMDC_MPWLDLST ((MMDC_REGS_BASE + MMDC_MPWLDLST_OFFSET)) +#define MMDC_MPODTCTRL ((MMDC_REGS_BASE + MMDC_MPODTCTRL_OFFSET)) +#define MMDC_MPREDQBY0DL ((MMDC_REGS_BASE + MMDC_MPREDQBY0DL_OFFSET)) +#define MMDC_MPREDQBY1DL ((MMDC_REGS_BASE + MMDC_MPREDQBY1DL_OFFSET)) +#define MMDC_MPREDQBY2DL ((MMDC_REGS_BASE + MMDC_MPREDQBY2DL_OFFSET)) +#define MMDC_MPREDQBY3DL ((MMDC_REGS_BASE + MMDC_MPREDQBY3DL_OFFSET)) +#define MMDC_MPWRDQBY0DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY0DL_OFFSET)) +#define MMDC_MPWRDQBY1DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY1DL_OFFSET)) +#define MMDC_MPWRDQBY2DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY2DL_OFFSET)) +#define MMDC_MPWRDQBY3DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY3DL_OFFSET)) +#define MMDC_MPDGCTRL0 ((MMDC_REGS_BASE + MMDC_MPDGCTRL0_OFFSET)) +#define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) +#define MMDC_MPDGDLST ((MMDC_REGS_BASE + MMDC_MPDGDLST_OFFSET)) +#define MMDC_MPRDDLCTL ((MMDC_REGS_BASE + MMDC_MPRDDLCTL_OFFSET)) +#define MMDC_MPRDDLST ((MMDC_REGS_BASE + MMDC_MPRDDLST_OFFSET)) +#define MMDC_MPWRDLCTL ((MMDC_REGS_BASE + MMDC_MPWRDLCTL_OFFSET)) +#define MMDC_MPWRDLST ((MMDC_REGS_BASE + MMDC_MPWRDLST_OFFSET)) +#define MMDC_MPSDCTRL ((MMDC_REGS_BASE + MMDC_MPSDCTRL_OFFSET)) +#define MMDC_MPZQLP2CTL ((MMDC_REGS_BASE + MMDC_MPZQLP2CTL_OFFSET)) +#define MMDC_MPRDDLHWCTL ((MMDC_REGS_BASE + MMDC_MPRDDLHWCTL_OFFSET)) +#define MMDC_MPWRDLHWCTL ((MMDC_REGS_BASE + MMDC_MPWRDLHWCTL_OFFSET)) +#define MMDC_MPRDDLHWST0 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST0_OFFSET)) +#define MMDC_MPRDDLHWST1 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST1_OFFSET)) +#define MMDC_MPWRDLHWST0 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST0_OFFSET)) +#define MMDC_MPWRDLHWST1 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST1_OFFSET)) +#define MMDC_MPWLHWERR ((MMDC_REGS_BASE + MMDC_MPWLHWERR_OFFSET)) +#define MMDC_MPDGHWST0 ((MMDC_REGS_BASE + MMDC_MPDGHWST0_OFFSET)) +#define MMDC_MPDGHWST1 ((MMDC_REGS_BASE + MMDC_MPDGHWST1_OFFSET)) +#define MMDC_MPDGHWST2 ((MMDC_REGS_BASE + MMDC_MPDGHWST2_OFFSET)) +#define MMDC_MPDGHWST3 ((MMDC_REGS_BASE + MMDC_MPDGHWST3_OFFSET)) +#define MMDC_MPPDCMPR1 ((MMDC_REGS_BASE + MMDC_MPPDCMPR1_OFFSET)) +#define MMDC_MPPDCMPR2 ((MMDC_REGS_BASE + MMDC_MPPDCMPR2_OFFSET)) +#define MMDC_MPSWDAR ((MMDC_REGS_BASE + MMDC_MPSWDAR_OFFSET)) +#define MMDC_MPSWDRDR0 ((MMDC_REGS_BASE + MMDC_MPSWDRDR0_OFFSET)) +#define MMDC_MPSWDRDR1 ((MMDC_REGS_BASE + MMDC_MPSWDRDR1_OFFSET)) +#define MMDC_MPSWDRDR2 ((MMDC_REGS_BASE + MMDC_MPSWDRDR2_OFFSET)) +#define MMDC_MPSWDRDR3 ((MMDC_REGS_BASE + MMDC_MPSWDRDR3_OFFSET)) +#define MMDC_MPSWDRDR4 ((MMDC_REGS_BASE + MMDC_MPSWDRDR4_OFFSET)) +#define MMDC_MPSWDRDR5 ((MMDC_REGS_BASE + MMDC_MPSWDRDR5_OFFSET)) +#define MMDC_MPSWDRDR6 ((MMDC_REGS_BASE + MMDC_MPSWDRDR6_OFFSET)) +#define MMDC_MPSWDRDR7 ((MMDC_REGS_BASE + MMDC_MPSWDRDR7_OFFSET)) +#define MMDC_MPMUR ((MMDC_REGS_BASE + MMDC_MPMUR_OFFSET)) +#define MMDC_MPWRCADL ((MMDC_REGS_BASE + MMDC_MPWRCADL_OFFSET)) +#define MMDC_MPDCCR ((MMDC_REGS_BASE + MMDC_MPDCCR_OFFSET)) +#define MMDC_MPBC ((MMDC_REGS_BASE + MMDC_MPBC_OFFSET)) +#define MMDC_MPSWDRAR ((MMDC_REGS_BASE + MMDC_MPSWDRAR_OFFSET)) + +/* MMDC registers bit defines */ +#define MMDC_MDCTL_SDE_0 (31) +#define MMDC_MDCTL_SDE_1 (30) +#define MMDC_MDCTL_ROW (24) +#define MMDC_MDCTL_COL (20) +#define MMDC_MDCTL_BL (19) +#define MMDC_MDCTL_DSIZ (16) + +/* MDMISC */ +#define MMDC_MDMISC_CS0_RDY (31) +#define MMDC_MDMISC_CS1_RDY (30) +#define MMDC_MDMISC_CK1_DEL (22) +#define MMDC_MDMISC_CK1_GATING (21) +#define MMDC_MDMISC_CALIB_PER_CS (20) +#define MMDC_MDMISC_ADDR_MIRROR (19) +#define MMDC_MDMISC_LHD (18) +#define MMDC_MDMISC_WALAT (16) +#define MMDC_MDMISC_BI (12) +#define MMDC_MDMISC_LPDDR2_S (11) +#define MMDC_MDMISC_MIF3_MODE (9) +#define MMDC_MDMISC_RALAT (6) +#define MMDC_MDMISC_DDR_4_BANK (5) +#define MMDC_MDMISC_DDR_TYPE (3) +#define MMDC_MDMISC_RST (1) + +/* MPWLGCR */ +#define MMDC_MPWLGCR_WL_HW_ERR (8) + +/* MDSCR */ +#define MMDC_MDSCR_CMD_ADDR_MSB (24) +#define MMDC_MDSCR_MR_OP (24) +#define MMDC_MDSCR_CMD_ADDR_LSB (16) +#define MMDC_MDSCR_MR_ADDR (16) +#define MMDC_MDSCR_CON_REQ (15) +#define MMDC_MDSCR_CON_ACK (14) +#define MMDC_MDSCR_MRR_READ_DATA_VALID (10) +#define MMDC_MDSCR_WL_EN (9) +#define MMDC_MDSCR_CMD (4) +#define MMDC_MDSCR_CMD_CS (3) +#define MMDC_MDSCR_CMD_BA (0) + +/* MPZQHWCTRL */ +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR (16) +#define MMDC_MPZQHWCTRL_ZQ_MODE (0) + +/* MPZQSWCTRL */ +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP (16) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL (13) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD (12) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL (7) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL (2) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES (1) +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR (0) + +/* MPDGCTRL0 */ +#define MMDC_MPDGCTRL0_RST_RD_FIFO (31) +#define MMDC_MPDGCTRL0_DG_CMP_CYC (30) +#define MMDC_MPDGCTRL0_DG_DIS (29) +#define MMDC_MPDGCTRL0_HW_DG_EN (28) +#define MMDC_MPDGCTRL0_HW_DG_ERR (12) + +/* MPRDDLHWCTL */ +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC (5) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN (4) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR (0) + +/* MPWRDLHWCTL */ +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC (5) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN (4) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR (0) + +/* MPSWDAR */ +#define MMDC_MPSWDAR_TEST_DUMMY_EN (6) +#define MMDC_MPSWDAR_SW_DUM_CMP3 (5) +#define MMDC_MPSWDAR_SW_DUM_CMP2 (4) +#define MMDC_MPSWDAR_SW_DUM_CMP1 (3) +#define MMDC_MPSWDAR_SW_DUM_CMP0 (2) +#define MMDC_MPSWDAR_SW_DUMMY_RD (1) +#define MMDC_MPSWDAR_SW_DUMMY_WR (0) + +/* MADPCR0 */ +#define MMDC_MADPCR0_SBS (9) +#define MMDC_MADPCR0_SBS_EN (8) + +/* MASBS1 */ +#define MMDC_MASBS1_SBS_VLD (0) +#define MMDC_MASBS1_SBS_TYPE (1) + +/* MDREF */ +#define MMDC_MDREF_REF_CNT (16) +#define MMDC_MDREF_REF_SEL (14) +#define MMDC_MDREF_REFR (11) +#define MMDC_MDREF_START_REF (0) + +/* MPWLGCR */ +#define MMDC_MPWLGCR_HW_WL_EN (0) + +/* MPBC */ +#define MMDC_MPBC_BIST_DM_LP_EN (0) +#define MMDC_MPBC_BIST_CA0_LP_EN (1) +#define MMDC_MPBC_BIST_DQ0_LP_EN (3) +#define MMDC_MPBC_BIST_DQ1_LP_EN (4) +#define MMDC_MPBC_BIST_DQ2_LP_EN (5) +#define MMDC_MPBC_BIST_DQ3_LP_EN (6) + +/* MPMUR */ +#define MMDC_MPMUR_FRC_MSR (11) + +/* MPODTCTRL */ +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN (3) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN (2) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN (1) +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN (0) + +/* MAPSR */ +#define MMDC_MAPSR_DVACK (25) +#define MMDC_MAPSR_LPACK (24) +#define MMDC_MAPSR_DVFS (21) +#define MMDC_MAPSR_LPMD (20) + +/* MAARCR */ +#define MMDC_MAARCR_ARCR_EXC_ERR_EN (28) + +/* MPZQLP2CTL */ +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS (24) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL (16) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT (0) + +/* MDCFG3LP */ +#define MMDC_MDCFG3LP_tRC_LP (16) +#define MMDC_MDCFG3LP_tRCD_LP (8) +#define MMDC_MDCFG3LP_tRPpb_LP (4) +#define MMDC_MDCFG3LP_tRPab_LP (0) + +/* MDOR */ +#define MMDC_MDOR_tXPR (16) +#define MMDC_MDOR_SDE_to_RST (8) +#define MMDC_MDOR_RST_to_CKE (0) + +/* MDCFG0 */ +#define MMDC_MDCFG0_tRFC (24) +#define MMDC_MDCFG0_tXS (16) +#define MMDC_MDCFG0_tXP (13) +#define MMDC_MDCFG0_tXPDLL (9) +#define MMDC_MDCFG0_tFAW (4) +#define MMDC_MDCFG0_tCL (0) + +/* MDCFG1 */ +#define MMDC_MDCFG1_tRCD (29) +#define MMDC_MDCFG1_tRP (26) +#define MMDC_MDCFG1_tRC (21) +#define MMDC_MDCFG1_tRAS (16) +#define MMDC_MDCFG1_tRPA (15) +#define MMDC_MDCFG1_tWR (9) +#define MMDC_MDCFG1_tMRD (5) +#define MMDC_MDCFG1_tCWL (0) + +/* MDCFG2 */ +#define MMDC_MDCFG2_tDLLK (16) +#define MMDC_MDCFG2_tRTP (6) +#define MMDC_MDCFG2_tWTR (3) +#define MMDC_MDCFG2_tRRD (0) + +/* MDRWD */ +#define MMDC_MDRWD_tDAI (16) +#define MMDC_MDRWD_RTW_SAME (12) +#define MMDC_MDRWD_WTR_DIFF (9) +#define MMDC_MDRWD_WTW_DIFF (6) +#define MMDC_MDRWD_RTW_DIFF (3) +#define MMDC_MDRWD_RTR_DIFF (0) + +/* MDPDC */ +#define MMDC_MDPDC_PRCT_1 (28) +#define MMDC_MDPDC_PRCT_0 (24) +#define MMDC_MDPDC_tCKE (16) +#define MMDC_MDPDC_PWDT_1 (12) +#define MMDC_MDPDC_PWDT_0 (8) +#define MMDC_MDPDC_SLOW_PD (7) +#define MMDC_MDPDC_BOTH_CS_PD (6) +#define MMDC_MDPDC_tCKSRX (3) +#define MMDC_MDPDC_tCKSRE (0) + +/* MDASP */ +#define MMDC_MDASP_CS0_END (0) + +/* MAEXIDR0 */ +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1 (16) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0 (0) + +/* MAEXIDR1 */ +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3 (16) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2 (0) + +/* MPWRDLCTL */ +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3 (24) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2 (16) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1 (8) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0 (0) + +/* MPRDDLCTL */ +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3 (24) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2 (16) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1 (8) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0 (0) + +/* MPWRDQBY0DL */ +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL (30) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL (28) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL (24) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL (20) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL (16) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL (12) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL (8) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL (4) +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL (0) + +/* MPWRDQBY1DL */ +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL (30) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL (28) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL (24) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL (20) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL (16) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL (12) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL (8) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL (4) +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL (0) + +/* MPWRDQBY2DL */ +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL (30) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL (28) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL (24) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL (20) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL (16) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL (12) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL (8) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL (4) +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL (0) + +/* MPWRDQBY3DL */ +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL (30) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL (28) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL (24) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL (20) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL (16) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL (12) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL (8) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL (4) +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL (0) + +/* Fields masks */ +#define MMDC_MDCTL_SDE_0_MASK ((0x1 << MMDC_MDCTL_SDE_0)) +#define MMDC_MDCTL_SDE_1_MASK ((0x1 << MMDC_MDCTL_SDE_1)) +#define MMDC_MDCTL_BL_MASK ((0x1 << MMDC_MDCTL_BL)) +#define MMDC_MDCTL_ROW_MASK ((0x7 << MMDC_MDCTL_ROW)) +#define MMDC_MDCTL_COL_MASK ((0x7 << MMDC_MDCTL_COL)) +#define MMDC_MDCTL_DSIZ_MASK ((0x3 << MMDC_MDCTL_DSIZ)) + +/* MDMISC */ +#define MMDC_MDMISC_CS0_RDY_MASK ((0x1 << MMDC_MDMISC_CS0_RDY)) +#define MMDC_MDMISC_CS1_RDY_MASK ((0x1 << MMDC_MDMISC_CS1_RDY)) +#define MMDC_MDMISC_CK1_DEL_MASK ((0x3 << MMDC_MDMISC_CK1_DEL)) +#define MMDC_MDMISC_CK1_GATING_MASK ((0x1 << MMDC_MDMISC_CK1_GATING)) +#define MMDC_MDMISC_CALIB_PER_CS_MASK ((0x1 << MMDC_MDMISC_CALIB_PER_CS)) +#define MMDC_MDMISC_ADDR_MIRROR_MASK ((0x1 << MMDC_MDMISC_ADDR_MIRROR)) +#define MMDC_MDMISC_LHD_MASK ((0x1 << MMDC_MDMISC_LHD)) +#define MMDC_MDMISC_WALAT_MASK ((0x3 << MMDC_MDMISC_WALAT)) +#define MMDC_MDMISC_BI_MASK ((0x1 << MMDC_MDMISC_BI)) +#define MMDC_MDMISC_LPDDR2_S_MASK ((0x1 << MMDC_MDMISC_LPDDR2_S)) +#define MMDC_MDMISC_MIF3_MODE_MASK ((0x3 << MMDC_MDMISC_MIF3_MODE)) +#define MMDC_MDMISC_RALAT_MASK ((0x7 << MMDC_MDMISC_RALAT)) +#define MMDC_MDMISC_DDR_4_BANK_MASK ((0x1 << MMDC_MDMISC_DDR_4_BANK)) +#define MMDC_MDMISC_DDR_TYPE_MASK ((0x3 << MMDC_MDMISC_DDR_TYPE)) +#define MMDC_MDMISC_RST_MASK ((0x1 << MMDC_MDMISC_RST)) + +/* MPWLGCR */ +#define MMDC_MPWLGCR_WL_HW_ERR_MASK ((0xf << MMDC_MPWLGCR_WL_HW_ERR)) + +/* MDSCR */ +#define MMDC_MDSCR_CMD_ADDR_MSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_MSB)) +#define MMDC_MDSCR_MR_OP_MASK ((0xff << MMDC_MDSCR_MR_OP)) +#define MMDC_MDSCR_CMD_ADDR_LSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_LSB)) +#define MMDC_MDSCR_MR_ADDR_MASK ((0xff << MMDC_MDSCR_MR_ADDR)) +#define MMDC_MDSCR_CON_REQ_MASK ((0x1 << MMDC_MDSCR_CON_REQ)) +#define MMDC_MDSCR_CON_ACK_MASK ((0x1 << MMDC_MDSCR_CON_ACK)) +#define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK ((0x1 << MMDC_MDSCR_MRR_READ_DATA_VALID)) +#define MMDC_MDSCR_WL_EN_MASK ((0x1 << MMDC_MDSCR_WL_EN)) +#define MMDC_MDSCR_CMD_MASK ((0x7 << MMDC_MDSCR_CMD)) +#define MMDC_MDSCR_CMD_CS_MASK ((0x1 << MMDC_MDSCR_CMD_CS)) +#define MMDC_MDSCR_CMD_BA_MASK ((0x7 << MMDC_MDSCR_CMD_BA)) + +/* MPZQHWCTRL */ +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK ((0x1 << MMDC_MPZQHWCTRL_ZQ_HW_FOR)) +#define MMDC_MPZQHWCTRL_ZQ_MODE_MASK ((0x3 << MMDC_MPZQHWCTRL_ZQ_MODE)) + +/* MPZQSWCTRL */ +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK ((0x3 << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP)) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK ((0x1 << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL)) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_PD)) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL)) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL)) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_RES)) +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_FOR)) + +/* MPDGCTRL0 */ +#define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK ((0x1 << MMDC_MPDGCTRL0_RST_RD_FIFO)) +#define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK ((0x1 << MMDC_MPDGCTRL0_DG_CMP_CYC)) +#define MMDC_MPDGCTRL0_DG_DIS_MASK ((0x1 << MMDC_MPDGCTRL0_DG_DIS)) +#define MMDC_MPDGCTRL0_HW_DG_EN_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_EN)) +#define MMDC_MPDGCTRL0_HW_DG_ERR_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_ERR)) + +/* MPRDDLHWCTL */ +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC)) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_EN)) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR_MASK ((0xf << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR)) + +/* MPWRDLHWCTL */ +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC)) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_EN)) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR_MASK ((0xf << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR)) + +/* MPSWDAR */ +#define MMDC_MPSWDAR_TEST_DUMMY_EN_MASK ((0x1 << MMDC_MPSWDAR_TEST_DUMMY_EN)) +#define MMDC_MPSWDAR_SW_DUM_CMP3_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP3)) +#define MMDC_MPSWDAR_SW_DUM_CMP2_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP2)) +#define MMDC_MPSWDAR_SW_DUM_CMP1_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP1)) +#define MMDC_MPSWDAR_SW_DUM_CMP0_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP0)) +#define MMDC_MPSWDAR_SW_DUMMY_RD_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_RD)) +#define MMDC_MPSWDAR_SW_DUMMY_WR_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_WR)) + +/* MADPCR0 */ +#define MMDC_MADPCR0_SBS_MASK ((0x1 << MMDC_MADPCR0_SBS)) +#define MMDC_MADPCR0_SBS_EN_MASK ((0x1 << MMDC_MADPCR0_SBS_EN)) + +/* MASBS1 */ +#define MMDC_MASBS1_SBS_VLD_MASK ((0x1 << MMDC_MASBS1_SBS_VLD)) +#define MMDC_MASBS1_SBS_TYPE_MASK ((0x1 << MMDC_MASBS1_SBS_TYPE)) + +/* MDREF */ +#define MMDC_MDREF_REF_CNT_MASK ((0xffff << MMDC_MDREF_REF_CNT)) +#define MMDC_MDREF_REF_SEL_MASK ((0x3 << MMDC_MDREF_REF_SEL)) +#define MMDC_MDREF_REFR_MASK ((0x7 << MMDC_MDREF_REFR)) +#define MMDC_MDREF_START_REF_MASK ((0x1 << MMDC_MDREF_START_REF)) + +/* MPWLGCR */ +#define MMDC_MPWLGCR_HW_WL_EN_MASK ((0x1 << MMDC_MPWLGCR_HW_WL_EN)) + +/* MPBC */ +#define MMDC_MPBC_BIST_DM_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DM_LP_EN)) +#define MMDC_MPBC_BIST_CA0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_CA0_LP_EN)) +#define MMDC_MPBC_BIST_DQ0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ0_LP_EN)) +#define MMDC_MPBC_BIST_DQ1_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ1_LP_EN)) +#define MMDC_MPBC_BIST_DQ2_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ2_LP_EN)) +#define MMDC_MPBC_BIST_DQ3_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ3_LP_EN)) +#define MMDC_MPBC_BIST_DQ_LP_EN_MASK ((0xf << MMDC_MPBC_BIST_DQ0_LP_EN)) + +/* MPMUR */ +#define MMDC_MPMUR_FRC_MSR_MASK ((0x1 << MMDC_MPMUR_FRC_MSR)) + +/* MPODTCTRL */ +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_ACT_EN)) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_PAS_EN)) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_ACT_EN)) +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_PAS_EN)) + +/* MAPSR */ +#define MMDC_MAPSR_DVACK_MASK ((0x1 << MMDC_MAPSR_DVACK)) +#define MMDC_MAPSR_LPACK_MASK ((0x1 << MMDC_MAPSR_LPACK)) +#define MMDC_MAPSR_DVFS_MASK ((0x1 << MMDC_MAPSR_DVFS)) +#define MMDC_MAPSR_LPMD_MASK ((0x1 << MMDC_MAPSR_LPMD)) + +/* MAARCR */ +#define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK ((0x1 << MMDC_MAARCR_ARCR_EXC_ERR_EN)) + +/* MPZQLP2CTL */ +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK ((0x7f << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS)) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK ((0xff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL)) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK ((0x1ff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT)) + +/* MDCFG3LP */ +#define MMDC_MDCFG3LP_tRC_LP_MASK ((0x3f << MMDC_MDCFG3LP_tRC_LP)) +#define MMDC_MDCFG3LP_tRCD_LP_MASK ((0xf << MMDC_MDCFG3LP_tRCD_LP)) +#define MMDC_MDCFG3LP_tRPpb_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPpb_LP)) +#define MMDC_MDCFG3LP_tRPab_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPab_LP)) + +/* MDOR */ +#define MMDC_MDOR_tXPR_MASK ((0xff << MMDC_MDOR_tXPR)) +#define MMDC_MDOR_SDE_to_RST_MASK ((0x3f << MMDC_MDOR_SDE_to_RST)) +#define MMDC_MDOR_RST_to_CKE_MASK ((0x3f << MMDC_MDOR_RST_to_CKE)) + +/* MDCFG0 */ +#define MMDC_MDCFG0_tRFC_MASK ((0xff << MMDC_MDCFG0_tRFC)) +#define MMDC_MDCFG0_tXS_MASK ((0xff << MMDC_MDCFG0_tXS)) +#define MMDC_MDCFG0_tXP_MASK ((0x7 << MMDC_MDCFG0_tXP)) +#define MMDC_MDCFG0_tXPDLL_MASK ((0xf << MMDC_MDCFG0_tXPDLL)) +#define MMDC_MDCFG0_tFAW_MASK ((0x1f << MMDC_MDCFG0_tFAW)) +#define MMDC_MDCFG0_tCL_MASK ((0xf << MMDC_MDCFG0_tCL)) + +/* MDCFG1 */ +#define MMDC_MDCFG1_tRCD_MASK ((0x7 << MMDC_MDCFG1_tRCD)) +#define MMDC_MDCFG1_tRP_MASK ((0x7 << MMDC_MDCFG1_tRP)) +#define MMDC_MDCFG1_tRC_MASK ((0x1f << MMDC_MDCFG1_tRC)) +#define MMDC_MDCFG1_tRAS_MASK ((0x1f << MMDC_MDCFG1_tRAS)) +#define MMDC_MDCFG1_tRPA_MASK ((0x1 << MMDC_MDCFG1_tRPA)) +#define MMDC_MDCFG1_tWR_MASK ((0x7 << MMDC_MDCFG1_tWR)) +#define MMDC_MDCFG1_tMRD_MASK ((0xf << MMDC_MDCFG1_tMRD)) +#define MMDC_MDCFG1_tCWL_MASK ((0x7 << MMDC_MDCFG1_tCWL)) + +/* MDCFG2 */ +#define MMDC_MDCFG2_tDLLK_MASK ((0x1ff << MMDC_MDCFG2_tDLLK)) +#define MMDC_MDCFG2_tRTP_MASK ((0x7 << MMDC_MDCFG2_tRTP)) +#define MMDC_MDCFG2_tWTR_MASK ((0x7 << MMDC_MDCFG2_tWTR)) +#define MMDC_MDCFG2_tRRD_MASK ((0x7 << MMDC_MDCFG2_tRRD)) + +/* MDRWD */ +#define MMDC_MDRWD_tDAI_MASK ((0x1fff << MMDC_MDRWD_tDAI)) +#define MMDC_MDRWD_RTW_SAME_MASK ((0x7 << MMDC_MDRWD_RTW_SAME)) +#define MMDC_MDRWD_WTR_DIFF_MASK ((0x7 << MMDC_MDRWD_WTR_DIFF)) +#define MMDC_MDRWD_WTW_DIFF_MASK ((0x7 << MMDC_MDRWD_WTW_DIFF)) +#define MMDC_MDRWD_RTW_DIFF_MASK ((0x7 << MMDC_MDRWD_RTW_DIFF)) +#define MMDC_MDRWD_RTR_DIFF_MASK ((0x7 << MMDC_MDRWD_RTR_DIFF)) + +/* MDPDC */ +#define MMDC_MDPDC_PRCT_1_MASK ((0x7 << MMDC_MDPDC_PRCT_1)) +#define MMDC_MDPDC_PRCT_0_MASK ((0x7 << MMDC_MDPDC_PRCT_0)) +#define MMDC_MDPDC_tCKE_MASK ((0x7 << MMDC_MDPDC_tCKE)) +#define MMDC_MDPDC_PWDT_1_MASK ((0xf << MMDC_MDPDC_PWDT_1)) +#define MMDC_MDPDC_PWDT_0_MASK ((0xf << MMDC_MDPDC_PWDT_0)) +#define MMDC_MDPDC_SLOW_PD_MASK ((0x1 << MMDC_MDPDC_SLOW_PD)) +#define MMDC_MDPDC_BOTH_CS_PD_MASK ((0x1 << MMDC_MDPDC_BOTH_CS_PD)) +#define MMDC_MDPDC_tCKSRX_MASK ((0x7 << MMDC_MDPDC_tCKSRX)) +#define MMDC_MDPDC_tCKSRE_MASK ((0x7 << MMDC_MDPDC_tCKSRE)) + +/* MDASP */ +#define MMDC_MDASP_CS0_END_MASK ((0x7f << MMDC_MDASP_CS0_END)) + +/* MAEXIDR0 */ +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR1)) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR0)) + +/* MAEXIDR1 */ +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR3)) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR2)) + +/* MPWRDLCTL */ +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3)) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2)) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1)) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0)) + +/* MPRDDLCTL */ +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3)) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2)) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1)) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0)) + +/* MPWRDQBY0DL */ +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DM0_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ7_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ6_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ5_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ4_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ3_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ2_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ1_DEL)) +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ0_DEL)) + +/* MPWRDQBY1DL */ +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DM1_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ15_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ14_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ13_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ12_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ11_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ10_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ9_DEL)) +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ8_DEL)) + +/* MPWRDQBY2DL */ +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DM2_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ23_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ22_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ21_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ20_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ19_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ18_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ17_DEL)) +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ16_DEL)) + +/* MPWRDQBY3DL */ +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DM3_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ31_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ30_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ29_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ28_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ27_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ26_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL)) +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL)) + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) + +#include <asm/types.h> + +struct fuse_word { + u32 fuse; + u32 rsvd[3]; +}; + +struct ocotp_regs { + u32 ctrl; + u32 ctrl_set; + u32 ctrl_clr; + u32 ctrl_tog; + u32 pdn; + u32 rsvd0[3]; + u32 data; + u32 rsvd1[3]; + u32 read_ctrl; + u32 rsvd2[3]; + u32 read_fuse_data; + u32 rsvd3[3]; + u32 sw_sticky; + u32 rsvd4[3]; + u32 scs; + u32 scs_set; + u32 scs_clr; + u32 scs_tog; + u32 out_status; + u32 out_status_set; + u32 out_status_clr; + u32 out_status_tog; + u32 startword; + u32 rsvd5[3]; + u32 version; + u32 rsvd6[19]; + struct fuse_word mem_repair[8]; + u32 rsvd7[0xa8]; + + /* fuse banks */ + struct fuse_bank { + u32 fuse_regs[0x20]; + } bank[0]; +}; + +struct fuse_bank1_regs { + u32 lock0; + u32 rsvd0[3]; + u32 lock1; + u32 rsvd1[3]; + u32 lock2; + u32 rsvd2[3]; + u32 cfg0; + u32 rsvd3[3]; + u32 cfg1; + u32 rsvd4[3]; + u32 cfg2; + u32 rsvd5[3]; + u32 cfg3; + u32 rsvd6[3]; + u32 cfg4; + u32 rsvd7[3]; +}; + +struct fuse_bank2_regs { + struct fuse_word boot[8]; +}; + +struct fuse_bank3_regs { + u32 mem0; + u32 rsvd0[3]; + u32 mem1; + u32 rsvd1[3]; + u32 mem2; + u32 rsvd2[3]; + u32 mem3; + u32 rsvd3[3]; + u32 ana0; + u32 rsvd4[3]; + u32 ana1; + u32 rsvd5[3]; + u32 ana2; + u32 rsvd6[3]; + u32 ana3; + u32 rsvd7[3]; +}; + +struct fuse_bank7_regs { + u32 sjc_resp0; + u32 rsvd0[3]; + u32 sjc_resp1; + u32 rsvd1[3]; + u32 gp0; + u32 rsvd2[3]; + u32 gp1; + u32 rsvd3[3]; + u32 gp2; + u32 rsvd4[3]; + u32 gp3; + u32 rsvd5[3]; + u32 gp4; + u32 rsvd6[3]; + u32 gp5; + u32 rsvd7[3]; +}; + +struct usbphy_regs { + u32 usbphy_pwd; /* 0x000 */ + u32 usbphy_pwd_set; /* 0x004 */ + u32 usbphy_pwd_clr; /* 0x008 */ + u32 usbphy_pwd_tog; /* 0x00c */ + u32 usbphy_tx; /* 0x010 */ + u32 usbphy_tx_set; /* 0x014 */ + u32 usbphy_tx_clr; /* 0x018 */ + u32 usbphy_tx_tog; /* 0x01c */ + u32 usbphy_rx; /* 0x020 */ + u32 usbphy_rx_set; /* 0x024 */ + u32 usbphy_rx_clr; /* 0x028 */ + u32 usbphy_rx_tog; /* 0x02c */ + u32 usbphy_ctrl; /* 0x030 */ + u32 usbphy_ctrl_set; /* 0x034 */ + u32 usbphy_ctrl_clr; /* 0x038 */ + u32 usbphy_ctrl_tog; /* 0x03c */ + u32 usbphy_status; /* 0x040 */ + u32 reserved0[3]; + u32 usbphy_debug0; /* 0x050 */ + u32 usbphy_debug0_set; /* 0x054 */ + u32 usbphy_debug0_clr; /* 0x058 */ + u32 usbphy_debug0_tog; /* 0x05c */ + u32 reserved1[4]; + u32 usbphy_debug1; /* 0x070 */ + u32 usbphy_debug1_set; /* 0x074 */ + u32 usbphy_debug1_clr; /* 0x078 */ + u32 usbphy_debug1_tog; /* 0x07c */ + u32 usbphy_version; /* 0x080 */ + u32 reserved2[7]; + u32 usb1_pll_480_ctrl; /* 0x0a0 */ + u32 usb1_pll_480_ctrl_set; /* 0x0a4 */ + u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */ + u32 usb1_pll_480_ctrl_tog; /* 0x0ac */ + u32 reserved3[4]; + u32 usb1_vbus_detect; /* 0xc0 */ + u32 usb1_vbus_detect_set; /* 0xc4 */ + u32 usb1_vbus_detect_clr; /* 0xc8 */ + u32 usb1_vbus_detect_tog; /* 0xcc */ + u32 usb1_vbus_det_stat; /* 0xd0 */ + u32 reserved4[3]; + u32 usb1_chrg_detect; /* 0xe0 */ + u32 usb1_chrg_detect_set; /* 0xe4 */ + u32 usb1_chrg_detect_clr; /* 0xe8 */ + u32 usb1_chrg_detect_tog; /* 0xec */ + u32 usb1_chrg_det_stat; /* 0xf0 */ + u32 reserved5[3]; + u32 usbphy_anactrl; /* 0x100 */ + u32 usbphy_anactrl_set; /* 0x104 */ + u32 usbphy_anactrl_clr; /* 0x108 */ + u32 usbphy_anactrl_tog; /* 0x10c */ + u32 usb1_loopback; /* 0x110 */ + u32 usb1_loopback_set; /* 0x114 */ + u32 usb1_loopback_clr; /* 0x118 */ + u32 usb1_loopback_tog; /* 0x11c */ + u32 usb1_loopback_hsfscnt; /* 0x120 */ + u32 usb1_loopback_hsfscnt_set; /* 0x124 */ + u32 usb1_loopback_hsfscnt_clr; /* 0x128 */ + u32 usb1_loopback_hsfscnt_tog; /* 0x12c */ + u32 usphy_trim_override_en; /* 0x130 */ + u32 usphy_trim_override_en_set; /* 0x134 */ + u32 usphy_trim_override_en_clr; /* 0x138 */ + u32 usphy_trim_override_en_tog; /* 0x13c */ + u32 usb1_pfda_ctrl1; /* 0x140 */ + u32 usb1_pfda_ctrl1_set; /* 0x144 */ + u32 usb1_pfda_ctrl1_clr; /* 0x148 */ + u32 usb1_pfda_ctrl1_tog; /* 0x14c */ +}; + + +#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) +#define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140) + +#endif + +#endif /* _MX7ULP_REGS_H_*/ -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 02/20] imx: mx7ulp: add registers header file 2016-12-27 10:04 ` [U-Boot] [PATCH V2 02/20] imx: mx7ulp: add registers header file Peng Fan @ 2017-02-12 8:40 ` Stefano Babic 0 siblings, 0 replies; 48+ messages in thread From: Stefano Babic @ 2017-02-12 8:40 UTC (permalink / raw) To: u-boot On 27/12/2016 11:04, Peng Fan wrote: > Add imx-regs.h for i.MX7ULP registers addresses definitions and some > registers structures. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Signed-off-by: Ye Li <ye.li@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > None > > arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 1125 +++++++++++++++++++++++++++ > 1 file changed, 1125 insertions(+) > create mode 100644 arch/arm/include/asm/arch-mx7ulp/imx-regs.h > > diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h > new file mode 100644 > index 0000000..30d0ba4 > --- /dev/null > +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h > @@ -0,0 +1,1125 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef _MX7ULP_REGS_H_ > +#define _MX7ULP_REGS_H_ > + > +#include <linux/sizes.h> > + > +#define CAAM_SEC_SRAM_BASE (0x26000000) > +#define CAAM_SEC_SRAM_SIZE (SZ_32K) > +#define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) > + > +#define OCRAM_0_BASE (0x2F000000) > +#define OCRAM_0_SIZE (SZ_128K) > +#define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1) > + > +#define OCRAM_1_BASE (0x2F020000) > +#define OCRAM_1_SIZE (SZ_128K) > +#define OCRAM_1_END (OCRAM_1_BASE + OCRAM_1_SIZE - 1) > + > +#define TCML_BASE (0x1FFD0000) > +#define TCMU_BASE (0x20000000) > + > +#define AIPS3_BASE (0x40800000UL) > +#define AIPS3_SLOT_SIZE (SZ_64K) > +#define AIPS2_BASE (0x40000000UL) > +#define AIPS2_SLOT_SIZE (SZ_64K) > +#define AIPS1_BASE (0x41080000UL) > +#define AIPS1_SLOT_SIZE (SZ_4K) > +#define AIPS0_BASE (0x41000000UL) > +#define AIPS0_SLOT_SIZE (SZ_4K) > +#define IOMUXC0_AIPS0_SLOT (61) > +#define WDG0_AIPS0_SLOT (37) > +#define WDG1_AIPS2_SLOT (61) > +#define WDG2_AIPS2_SLOT (67) > +#define WDG0_PCC0_SLOT (37) > +#define WDG1_PCC2_SLOT (61) > +#define IOMUXC1_AIPS3_SLOT (44) > +#define CMC0_AIPS1_SLOT (36) > +#define CMC1_AIPS2_SLOT (65) > +#define SCG0_AIPS0_SLOT (39) > +#define PCC0_AIPS0_SLOT (38) > +#define PCC1_AIPS1_SLOT (50) > +#define PCC2_AIPS2_SLOT (63) > +#define PCC3_AIPS3_SLOT (51) > +#define SCG1_AIPS2_SLOT (62) > +#define SIM0_AIPS1_SLOT (35) > +#define SIM1_AIPS1_SLOT (48) > +#define USBOTG0_AIPS2_SLOT (51) > +#define USBOTG1_AIPS2_SLOT (52) > +#define USBPHY_AIPS2_SLOT (53) > +#define USDHC0_AIPS2_SLOT (55) > +#define USDHC1_AIPS2_SLOT (56) > +#define RGPIO2P0_AIPS0_SLOT (15) > +#define RGPIO2P1_AIPS2_SLOT (15) > +#define IOMUXC0_AIPS0_SLOT (61) > +#define OCOTP_CTRL_AIPS1_SLOT (38) > +#define OCOTP_CTRL_PCC1_SLOT (38) > +#define SIM1_PCC1_SLOT (48) > +#define SCG1_PCC2_SLOT (62) > +#define MMDC0_AIPS3_SLOT (43) > +#define IOMUXC_DDR_AIPS3_SLOT (45) > +#define MMDC0_PCC3_SLOT (43) > + > +#define LPI2C0_AIPS0_SLOT (51) > +#define LPI2C1_AIPS0_SLOT (52) > +#define LPI2C2_AIPS0_SLOT (53) > +#define LPI2C3_AIPS0_SLOT (54) > +#define LPI2C4_AIPS2_SLOT (43) > +#define LPI2C5_AIPS2_SLOT (44) > +#define LPI2C6_AIPS3_SLOT (36) > +#define LPI2C7_AIPS3_SLOT (37) > + > +#define USDHC0_PCC2_SLOT (55) > +#define USDHC1_PCC2_SLOT (56) > + > +#define LPUART0_PCC0_SLOT (58) > +#define LPUART1_PCC0_SLOT (59) > +#define LPUART2_PCC1_SLOT (43) > +#define LPUART3_PCC1_SLOT (44) > +#define LPUART4_PCC2_SLOT (45) > +#define LPUART5_PCC2_SLOT (46) > +#define LPUART6_PCC3_SLOT (38) > +#define LPUART7_PCC3_SLOT (39) > +#define LPUART0_AIPS0_SLOT (58) > +#define LPUART1_AIPS0_SLOT (59) > +#define LPUART2_AIPS1_SLOT (43) > +#define LPUART3_AIPS1_SLOT (44) > +#define LPUART4_AIPS2_SLOT (45) > +#define LPUART5_AIPS2_SLOT (46) > +#define LPUART6_AIPS3_SLOT (38) > +#define LPUART7_AIPS3_SLOT (39) > + > +#define CORE_B_ROM_SIZE (SZ_32K + SZ_64K) > +#define CORE_B_ROM_BASE (0x00000000) > + > +#define IOMUXC_PCR_MUX_ALT0 (0<<8) > +#define IOMUXC_PCR_MUX_ALT1 (1<<8) > +#define IOMUXC_PCR_MUX_ALT2 (2<<8) > +#define IOMUXC_PCR_MUX_ALT3 (3<<8) > +#define IOMUXC_PCR_MUX_ALT4 (4<<8) > +#define IOMUXC_PCR_MUX_ALT5 (5<<8) > +#define IOMUXC_PCR_MUX_ALT6 (6<<8) > +#define IOMUXC_PCR_MUX_ALT7 (7<<8) > +#define IOMUXC_PCR_MUX_ALT8 (8<<8) > +#define IOMUXC_PCR_MUX_ALT9 (9<<8) > +#define IOMUXC_PCR_MUX_ALT10 (10<<8) > +#define IOMUXC_PCR_MUX_ALT11 (11<<8) > +#define IOMUXC_PCR_MUX_ALT12 (12<<8) > +#define IOMUXC_PCR_MUX_ALT13 (13<<8) > +#define IOMUXC_PCR_MUX_ALT14 (14<<8) > +#define IOMUXC_PCR_MUX_ALT15 (15<<8) > + > +#define IOMUXC_PSMI_IMUX_ALT0 (0x0) > +#define IOMUXC_PSMI_IMUX_ALT1 (0x1) > +#define IOMUXC_PSMI_IMUX_ALT2 (0x2) > +#define IOMUXC_PSMI_IMUX_ALT3 (0x3) > +#define IOMUXC_PSMI_IMUX_ALT4 (0x4) > +#define IOMUXC_PSMI_IMUX_ALT5 (0x5) > +#define IOMUXC_PSMI_IMUX_ALT6 (0x6) > +#define IOMUXC_PSMI_IMUX_ALT7 (0x7) > + > + > +#define SIM_SOPT1_EN_SNVS_HARD_RST (1<<8) > +#define SIM_SOPT1_PMIC_STBY_REQ (1<<2) > +#define SIM_SOPT1_A7_SW_RESET (1<<0) > + > +#define IOMUXC_PCR_MUX_ALT_SHIFT (8) > +#define IOMUXC_PCR_MUX_ALT_MASK (0xF00) > +#define IOMUXC_PSMI_IMUX_ALT_SHIFT (0) > + > +#define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) > +#define IOMUXC1_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC1_AIPS3_SLOT))) > +#define WDG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * WDG0_AIPS0_SLOT))) > +#define WDG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG1_AIPS2_SLOT))) > +#define WDG2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG2_AIPS2_SLOT))) > +#define SCG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * SCG0_AIPS0_SLOT))) > +#define SCG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SCG1_AIPS2_SLOT))) > +#define PCC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * PCC0_AIPS0_SLOT))) > +#define PCC1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * PCC1_AIPS1_SLOT))) > +#define PCC2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * PCC2_AIPS2_SLOT))) > +#define PCC3_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * PCC3_AIPS3_SLOT))) > +#define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT))) > +#define PSMI0_RBASE ((IOMUXC0_RBASE + 0x100)) /* in iomuxc0 after pta and ptb */ > +#define CMC0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * CMC0_AIPS1_SLOT))) > +#define CMC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * CMC1_AIPS2_SLOT))) > +#define OCOTP_BASE_ADDR ((AIPS1_BASE + (AIPS1_SLOT_SIZE * OCOTP_CTRL_AIPS1_SLOT))) > +#define SIM0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM0_AIPS1_SLOT))) > +#define SIM1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM1_AIPS1_SLOT))) > +#define MMDC0_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * MMDC0_AIPS3_SLOT))) > + > +#define USBOTG0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG0_AIPS2_SLOT))) > +#define USBOTG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG1_AIPS2_SLOT))) > +#define USBPHY_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBPHY_AIPS2_SLOT))) > +#define USB_PHY0_BASE_ADDR USBPHY_RBASE > +#define USB_BASE_ADDR USBOTG0_RBASE > + > +#define LPI2C1_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C0_AIPS0_SLOT))) > +#define LPI2C2_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C1_AIPS0_SLOT))) > +#define LPI2C3_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C2_AIPS0_SLOT))) > +#define LPI2C4_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C3_AIPS0_SLOT))) > +#define LPI2C5_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C4_AIPS2_SLOT))) > +#define LPI2C6_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C5_AIPS2_SLOT))) > +#define LPI2C7_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C6_AIPS3_SLOT))) > +#define LPI2C8_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C7_AIPS3_SLOT))) > + > +#define LPUART0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART0_AIPS0_SLOT))) > +#define LPUART1_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART1_AIPS0_SLOT))) > +#define LPUART2_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART2_AIPS1_SLOT))) > +#define LPUART3_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART3_AIPS1_SLOT))) > +#define LPUART4_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART4_AIPS2_SLOT))) > +#define LPUART5_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART5_AIPS2_SLOT))) > +#define LPUART6_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART6_AIPS3_SLOT))) > +#define LPUART7_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART7_AIPS3_SLOT))) > + > +#define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT))) > +#define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT))) > + > +#define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT))) > +#define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT))) > + > +#define WDG0_PCC_REG (PCC0_RBASE + (4 * WDG0_PCC0_SLOT)) > +#define WDG1_PCC_REG (PCC2_RBASE + (4 * WDG1_PCC2_SLOT)) > +#define CMC0_SRS (CMC0_RBASE + 0x20) > +#define CMC0_SSRS (CMC0_RBASE + 0x28) > +#define CMC1_SRS (CMC1_RBASE + 0x20) > +#define CMC1_SSRS (CMC1_RBASE + 0x28) > + > +#define IOMUXC0_PCR0 (IOMUXC0_RBASE + (4 * 0)) > +#define IOMUXC0_PCR1 (IOMUXC0_RBASE + (4 * 1)) > +#define IOMUXC0_PCR2 (IOMUXC0_RBASE + (4 * 2)) > +#define IOMUXC0_PCR3 (IOMUXC0_RBASE + (4 * 3)) > +#define IOMUXC0_PSMI62 (PSMI0_RBASE + (4 * 62)) > +#define IOMUXC0_PSMI63 (PSMI0_RBASE + (4 * 63)) > +#define IOMUXC0_PSMI64 (PSMI0_RBASE + (4 * 64)) > + > +#define SCG_CSR (SCG0_RBASE + 0x010) > +#define SCG_RCCR (SCG0_RBASE + 0x014) > +#define SCG_VCCR (SCG0_RBASE + 0x018) > +#define SCG_HCCR (SCG0_RBASE + 0x01c) > + > +#define LPUART0_PCC_REG (PCC0_RBASE + (4 * LPUART0_PCC0_SLOT)) > +#define LPUART1_PCC_REG (PCC0_RBASE + (4 * LPUART1_PCC0_SLOT)) > +#define LPUART2_PCC_REG (PCC1_RBASE + (4 * LPUART2_PCC1_SLOT)) > +#define LPUART3_PCC_REG (PCC1_RBASE + (4 * LPUART3_PCC1_SLOT)) > +#define LPUART4_PCC_REG (PCC2_RBASE + (4 * LPUART4_PCC2_SLOT)) > +#define LPUART5_PCC_REG (PCC2_RBASE + (4 * LPUART5_PCC2_SLOT)) > +#define LPUART6_PCC_REG (PCC3_RBASE + (4 * LPUART6_PCC3_SLOT)) > +#define LPUART7_PCC_REG (PCC3_RBASE + (4 * LPUART7_PCC3_SLOT)) > + > +#define USDHC0_PCC_REG (PCC2_RBASE + (4 * USDHC0_PCC2_SLOT)) > +#define USDHC1_PCC_REG (PCC2_RBASE + (4 * USDHC1_PCC2_SLOT)) > + > +#define SIM1_PCC_REG (PCC1_RBASE + (4 * SIM1_PCC1_SLOT)) > +#define SCG1_PCC_REG (PCC2_RBASE + (4 * SCG1_PCC2_SLOT)) > + > +#define OCOTP_CTRL_PCC_REG (PCC1_RBASE + (4 * OCOTP_CTRL_PCC1_SLOT)) > + > +#define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT))) > +#define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT)) > + > +#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) > +#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) > +#define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) > +#define IOMUXC_DPCR_DDR_DQS3 ((IOMUXC_DDR_RBASE + (4 * 35))) > + > + > +#define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0))) > +#define IOMUXC_DPCR_DDR_DQ1 ((IOMUXC_DDR_RBASE + (4 * 1))) > +#define IOMUXC_DPCR_DDR_DQ2 ((IOMUXC_DDR_RBASE + (4 * 2))) > +#define IOMUXC_DPCR_DDR_DQ3 ((IOMUXC_DDR_RBASE + (4 * 3))) > +#define IOMUXC_DPCR_DDR_DQ4 ((IOMUXC_DDR_RBASE + (4 * 4))) > +#define IOMUXC_DPCR_DDR_DQ5 ((IOMUXC_DDR_RBASE + (4 * 5))) > +#define IOMUXC_DPCR_DDR_DQ6 ((IOMUXC_DDR_RBASE + (4 * 6))) > +#define IOMUXC_DPCR_DDR_DQ7 ((IOMUXC_DDR_RBASE + (4 * 7))) > +#define IOMUXC_DPCR_DDR_DQ8 ((IOMUXC_DDR_RBASE + (4 * 8))) > +#define IOMUXC_DPCR_DDR_DQ9 ((IOMUXC_DDR_RBASE + (4 * 9))) > +#define IOMUXC_DPCR_DDR_DQ10 ((IOMUXC_DDR_RBASE + (4 * 10))) > +#define IOMUXC_DPCR_DDR_DQ11 ((IOMUXC_DDR_RBASE + (4 * 11))) > +#define IOMUXC_DPCR_DDR_DQ12 ((IOMUXC_DDR_RBASE + (4 * 12))) > +#define IOMUXC_DPCR_DDR_DQ13 ((IOMUXC_DDR_RBASE + (4 * 13))) > +#define IOMUXC_DPCR_DDR_DQ14 ((IOMUXC_DDR_RBASE + (4 * 14))) > +#define IOMUXC_DPCR_DDR_DQ15 ((IOMUXC_DDR_RBASE + (4 * 15))) > +#define IOMUXC_DPCR_DDR_DQ16 ((IOMUXC_DDR_RBASE + (4 * 16))) > +#define IOMUXC_DPCR_DDR_DQ17 ((IOMUXC_DDR_RBASE + (4 * 17))) > +#define IOMUXC_DPCR_DDR_DQ18 ((IOMUXC_DDR_RBASE + (4 * 18))) > +#define IOMUXC_DPCR_DDR_DQ19 ((IOMUXC_DDR_RBASE + (4 * 19))) > +#define IOMUXC_DPCR_DDR_DQ20 ((IOMUXC_DDR_RBASE + (4 * 20))) > +#define IOMUXC_DPCR_DDR_DQ21 ((IOMUXC_DDR_RBASE + (4 * 21))) > +#define IOMUXC_DPCR_DDR_DQ22 ((IOMUXC_DDR_RBASE + (4 * 22))) > +#define IOMUXC_DPCR_DDR_DQ23 ((IOMUXC_DDR_RBASE + (4 * 23))) > +#define IOMUXC_DPCR_DDR_DQ24 ((IOMUXC_DDR_RBASE + (4 * 24))) > +#define IOMUXC_DPCR_DDR_DQ25 ((IOMUXC_DDR_RBASE + (4 * 25))) > +#define IOMUXC_DPCR_DDR_DQ26 ((IOMUXC_DDR_RBASE + (4 * 26))) > +#define IOMUXC_DPCR_DDR_DQ27 ((IOMUXC_DDR_RBASE + (4 * 27))) > +#define IOMUXC_DPCR_DDR_DQ28 ((IOMUXC_DDR_RBASE + (4 * 28))) > +#define IOMUXC_DPCR_DDR_DQ29 ((IOMUXC_DDR_RBASE + (4 * 29))) > +#define IOMUXC_DPCR_DDR_DQ30 ((IOMUXC_DDR_RBASE + (4 * 30))) > +#define IOMUXC_DPCR_DDR_DQ31 ((IOMUXC_DDR_RBASE + (4 * 31))) > + > +/* Remap the rgpio2p registers addr to driver's addr */ > +#define RGPIO2P_GPIO1_BASE_ADDR RGPIO2P0_RBASE > +#define RGPIO2P_GPIO2_BASE_ADDR (RGPIO2P0_RBASE + 0x40) > +#define RGPIO2P_GPIO3_BASE_ADDR (RGPIO2P1_RBASE) > +#define RGPIO2P_GPIO4_BASE_ADDR (RGPIO2P1_RBASE + 0x40) > +#define RGPIO2P_GPIO5_BASE_ADDR (RGPIO2P1_RBASE + 0x80) > +#define RGPIO2P_GPIO6_BASE_ADDR (RGPIO2P1_RBASE + 0xc0) > + > +/* MMDC registers addresses */ > +#define MMDC_MDCTL_OFFSET (0x000) > +#define MMDC_MDPDC_OFFSET (0x004) > +#define MMDC_MDOTC_OFFSET (0x008) > +#define MMDC_MDCFG0_OFFSET (0x00C) > +#define MMDC_MDCFG1_OFFSET (0x010) > +#define MMDC_MDCFG2_OFFSET (0x014) > +#define MMDC_MDMISC_OFFSET (0x018) > +#define MMDC_MDSCR_OFFSET (0x01C) > +#define MMDC_MDREF_OFFSET (0x020) > +#define MMDC_MDRWD_OFFSET (0x02C) > +#define MMDC_MDOR_OFFSET (0x030) > +#define MMDC_MDMRR_OFFSET (0x034) > +#define MMDC_MDCFG3LP_OFFSET (0x038) > +#define MMDC_MDMR4_OFFSET (0x03C) > +#define MMDC_MDASP_OFFSET (0x040) > + > +#define MMDC_MAARCR_OFFSET (0x400) > +#define MMDC_MAPSR_OFFSET (0x404) > +#define MMDC_MAEXIDR0_OFFSET (0x408) > +#define MMDC_MAEXIDR1_OFFSET (0x40C) > +#define MMDC_MADPCR0_OFFSET (0x410) > +#define MMDC_MADPCR1_OFFSET (0x414) > +#define MMDC_MADPSR0_OFFSET (0x418) > +#define MMDC_MADPSR1_OFFSET (0x41C) > +#define MMDC_MADPSR2_OFFSET (0x420) > +#define MMDC_MADPSR3_OFFSET (0x424) > +#define MMDC_MADPSR4_OFFSET (0x428) > +#define MMDC_MADPSR5_OFFSET (0x42C) > +#define MMDC_MASBS0_OFFSET (0x430) > +#define MMDC_MASBS1_OFFSET (0x434) > +#define MMDC_MAGENP_OFFSET (0x440) > + > +#define MMDC_MPZQHWCTRL_OFFSET (0x800) > +#define MMDC_MPZQSWCTRL_OFFSET (0x804) > +#define MMDC_MPWLGCR_OFFSET (0x808) > +#define MMDC_MPWLDECTRL0_OFFSET (0x80C) > +#define MMDC_MPWLDECTRL1_OFFSET (0x810) > +#define MMDC_MPWLDLST_OFFSET (0x814) > +#define MMDC_MPODTCTRL_OFFSET (0x818) > +#define MMDC_MPREDQBY0DL_OFFSET (0x81C) > +#define MMDC_MPREDQBY1DL_OFFSET (0x820) > +#define MMDC_MPREDQBY2DL_OFFSET (0x824) > +#define MMDC_MPREDQBY3DL_OFFSET (0x828) > +#define MMDC_MPWRDQBY0DL_OFFSET (0x82C) > +#define MMDC_MPWRDQBY1DL_OFFSET (0x830) > +#define MMDC_MPWRDQBY2DL_OFFSET (0x834) > +#define MMDC_MPWRDQBY3DL_OFFSET (0x838) > +#define MMDC_MPDGCTRL0_OFFSET (0x83C) > +#define MMDC_MPDGCTRL1_OFFSET (0x840) > +#define MMDC_MPDGDLST_OFFSET (0x844) > +#define MMDC_MPRDDLCTL_OFFSET (0x848) > +#define MMDC_MPRDDLST_OFFSET (0x84C) > +#define MMDC_MPWRDLCTL_OFFSET (0x850) > +#define MMDC_MPWRDLST_OFFSET (0x854) > +#define MMDC_MPSDCTRL_OFFSET (0x858) > +#define MMDC_MPZQLP2CTL_OFFSET (0x85C) > +#define MMDC_MPRDDLHWCTL_OFFSET (0x860) > +#define MMDC_MPWRDLHWCTL_OFFSET (0x864) > +#define MMDC_MPRDDLHWST0_OFFSET (0x868) > +#define MMDC_MPRDDLHWST1_OFFSET (0x86C) > +#define MMDC_MPWRDLHWST0_OFFSET (0x870) > +#define MMDC_MPWRDLHWST1_OFFSET (0x874) > +#define MMDC_MPWLHWERR_OFFSET (0x878) > +#define MMDC_MPDGHWST0_OFFSET (0x87C) > +#define MMDC_MPDGHWST1_OFFSET (0x880) > +#define MMDC_MPDGHWST2_OFFSET (0x884) > +#define MMDC_MPDGHWST3_OFFSET (0x888) > +#define MMDC_MPPDCMPR1_OFFSET (0x88C) > +#define MMDC_MPPDCMPR2_OFFSET (0x890) > +#define MMDC_MPSWDAR_OFFSET (0x894) > +#define MMDC_MPSWDRDR0_OFFSET (0x898) > +#define MMDC_MPSWDRDR1_OFFSET (0x89C) > +#define MMDC_MPSWDRDR2_OFFSET (0x8A0) > +#define MMDC_MPSWDRDR3_OFFSET (0x8A4) > +#define MMDC_MPSWDRDR4_OFFSET (0x8A8) > +#define MMDC_MPSWDRDR5_OFFSET (0x8AC) > +#define MMDC_MPSWDRDR6_OFFSET (0x8B0) > +#define MMDC_MPSWDRDR7_OFFSET (0x8B4) > +#define MMDC_MPMUR_OFFSET (0x8B8) > +#define MMDC_MPWRCADL_OFFSET (0x8BC) > +#define MMDC_MPDCCR_OFFSET (0x8C0) > +#define MMDC_MPBC_OFFSET (0x8C4) > +#define MMDC_MPSWDRAR_OFFSET (0x8C8) > + > +/* First MMDC invalid IPS address */ > +#define MMDC_IPS_ILL_ADDR_START_OFFSET (0x8CC) > +#define MMDC_REGS_BASE MMDC0_RBASE > + > +#define MMDC_MDCTL ((MMDC_REGS_BASE + MMDC_MDCTL_OFFSET)) > +#define MMDC_MDPDC ((MMDC_REGS_BASE + MMDC_MDPDC_OFFSET)) > +#define MMDC_MDOTC ((MMDC_REGS_BASE + MMDC_MDOTC_OFFSET)) > +#define MMDC_MDCFG0 ((MMDC_REGS_BASE + MMDC_MDCFG0_OFFSET)) > +#define MMDC_MDCFG1 ((MMDC_REGS_BASE + MMDC_MDCFG1_OFFSET)) > +#define MMDC_MDCFG2 ((MMDC_REGS_BASE + MMDC_MDCFG2_OFFSET)) > +#define MMDC_MDMISC ((MMDC_REGS_BASE + MMDC_MDMISC_OFFSET)) > +#define MMDC_MDSCR ((MMDC_REGS_BASE + MMDC_MDSCR_OFFSET)) > +#define MMDC_MDREF ((MMDC_REGS_BASE + MMDC_MDREF_OFFSET)) > +#define MMDC_MDRWD ((MMDC_REGS_BASE + MMDC_MDRWD_OFFSET)) > +#define MMDC_MDOR ((MMDC_REGS_BASE + MMDC_MDOR_OFFSET)) > +#define MMDC_MDMRR ((MMDC_REGS_BASE + MMDC_MDMRR_OFFSET)) > +#define MMDC_MDCFG3LP ((MMDC_REGS_BASE + MMDC_MDCFG3LP_OFFSET)) > +#define MMDC_MDMR4 ((MMDC_REGS_BASE + MMDC_MDMR4_OFFSET)) > +#define MMDC_MDASP ((MMDC_REGS_BASE + MMDC_MDASP_OFFSET)) > + > +#define MMDC_MAARCR ((MMDC_REGS_BASE + MMDC_MAARCR_OFFSET)) > +#define MMDC_MAPSR ((MMDC_REGS_BASE + MMDC_MAPSR_OFFSET)) > +#define MMDC_MAEXIDR0 ((MMDC_REGS_BASE + MMDC_MAEXIDR0_OFFSET)) > +#define MMDC_MAEXIDR1 ((MMDC_REGS_BASE + MMDC_MAEXIDR1_OFFSET)) > +#define MMDC_MADPCR0 ((MMDC_REGS_BASE + MMDC_MADPCR0_OFFSET)) > +#define MMDC_MADPCR1 ((MMDC_REGS_BASE + MMDC_MADPCR1_OFFSET)) > +#define MMDC_MADPSR0 ((MMDC_REGS_BASE + MMDC_MADPSR0_OFFSET)) > +#define MMDC_MADPSR1 ((MMDC_REGS_BASE + MMDC_MADPSR1_OFFSET)) > +#define MMDC_MADPSR2 ((MMDC_REGS_BASE + MMDC_MADPSR2_OFFSET)) > +#define MMDC_MADPSR3 ((MMDC_REGS_BASE + MMDC_MADPSR3_OFFSET)) > +#define MMDC_MADPSR4 ((MMDC_REGS_BASE + MMDC_MADPSR4_OFFSET)) > +#define MMDC_MADPSR5 ((MMDC_REGS_BASE + MMDC_MADPSR5_OFFSET)) > +#define MMDC_MASBS0 ((MMDC_REGS_BASE + MMDC_MASBS0_OFFSET)) > +#define MMDC_MASBS1 ((MMDC_REGS_BASE + MMDC_MASBS1_OFFSET)) > +#define MMDC_MAGENP ((MMDC_REGS_BASE + MMDC_MAGENP_OFFSET)) > + > +#define MMDC_MPZQHWCTRL ((MMDC_REGS_BASE + MMDC_MPZQHWCTRL_OFFSET)) > +#define MMDC_MPZQSWCTRL ((MMDC_REGS_BASE + MMDC_MPZQSWCTRL_OFFSET)) > +#define MMDC_MPWLGCR ((MMDC_REGS_BASE + MMDC_MPWLGCR_OFFSET)) > +#define MMDC_MPWLDECTRL0 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL0_OFFSET)) > +#define MMDC_MPWLDECTRL1 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL1_OFFSET)) > +#define MMDC_MPWLDLST ((MMDC_REGS_BASE + MMDC_MPWLDLST_OFFSET)) > +#define MMDC_MPODTCTRL ((MMDC_REGS_BASE + MMDC_MPODTCTRL_OFFSET)) > +#define MMDC_MPREDQBY0DL ((MMDC_REGS_BASE + MMDC_MPREDQBY0DL_OFFSET)) > +#define MMDC_MPREDQBY1DL ((MMDC_REGS_BASE + MMDC_MPREDQBY1DL_OFFSET)) > +#define MMDC_MPREDQBY2DL ((MMDC_REGS_BASE + MMDC_MPREDQBY2DL_OFFSET)) > +#define MMDC_MPREDQBY3DL ((MMDC_REGS_BASE + MMDC_MPREDQBY3DL_OFFSET)) > +#define MMDC_MPWRDQBY0DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY0DL_OFFSET)) > +#define MMDC_MPWRDQBY1DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY1DL_OFFSET)) > +#define MMDC_MPWRDQBY2DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY2DL_OFFSET)) > +#define MMDC_MPWRDQBY3DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY3DL_OFFSET)) > +#define MMDC_MPDGCTRL0 ((MMDC_REGS_BASE + MMDC_MPDGCTRL0_OFFSET)) > +#define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) > +#define MMDC_MPDGDLST ((MMDC_REGS_BASE + MMDC_MPDGDLST_OFFSET)) > +#define MMDC_MPRDDLCTL ((MMDC_REGS_BASE + MMDC_MPRDDLCTL_OFFSET)) > +#define MMDC_MPRDDLST ((MMDC_REGS_BASE + MMDC_MPRDDLST_OFFSET)) > +#define MMDC_MPWRDLCTL ((MMDC_REGS_BASE + MMDC_MPWRDLCTL_OFFSET)) > +#define MMDC_MPWRDLST ((MMDC_REGS_BASE + MMDC_MPWRDLST_OFFSET)) > +#define MMDC_MPSDCTRL ((MMDC_REGS_BASE + MMDC_MPSDCTRL_OFFSET)) > +#define MMDC_MPZQLP2CTL ((MMDC_REGS_BASE + MMDC_MPZQLP2CTL_OFFSET)) > +#define MMDC_MPRDDLHWCTL ((MMDC_REGS_BASE + MMDC_MPRDDLHWCTL_OFFSET)) > +#define MMDC_MPWRDLHWCTL ((MMDC_REGS_BASE + MMDC_MPWRDLHWCTL_OFFSET)) > +#define MMDC_MPRDDLHWST0 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST0_OFFSET)) > +#define MMDC_MPRDDLHWST1 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST1_OFFSET)) > +#define MMDC_MPWRDLHWST0 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST0_OFFSET)) > +#define MMDC_MPWRDLHWST1 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST1_OFFSET)) > +#define MMDC_MPWLHWERR ((MMDC_REGS_BASE + MMDC_MPWLHWERR_OFFSET)) > +#define MMDC_MPDGHWST0 ((MMDC_REGS_BASE + MMDC_MPDGHWST0_OFFSET)) > +#define MMDC_MPDGHWST1 ((MMDC_REGS_BASE + MMDC_MPDGHWST1_OFFSET)) > +#define MMDC_MPDGHWST2 ((MMDC_REGS_BASE + MMDC_MPDGHWST2_OFFSET)) > +#define MMDC_MPDGHWST3 ((MMDC_REGS_BASE + MMDC_MPDGHWST3_OFFSET)) > +#define MMDC_MPPDCMPR1 ((MMDC_REGS_BASE + MMDC_MPPDCMPR1_OFFSET)) > +#define MMDC_MPPDCMPR2 ((MMDC_REGS_BASE + MMDC_MPPDCMPR2_OFFSET)) > +#define MMDC_MPSWDAR ((MMDC_REGS_BASE + MMDC_MPSWDAR_OFFSET)) > +#define MMDC_MPSWDRDR0 ((MMDC_REGS_BASE + MMDC_MPSWDRDR0_OFFSET)) > +#define MMDC_MPSWDRDR1 ((MMDC_REGS_BASE + MMDC_MPSWDRDR1_OFFSET)) > +#define MMDC_MPSWDRDR2 ((MMDC_REGS_BASE + MMDC_MPSWDRDR2_OFFSET)) > +#define MMDC_MPSWDRDR3 ((MMDC_REGS_BASE + MMDC_MPSWDRDR3_OFFSET)) > +#define MMDC_MPSWDRDR4 ((MMDC_REGS_BASE + MMDC_MPSWDRDR4_OFFSET)) > +#define MMDC_MPSWDRDR5 ((MMDC_REGS_BASE + MMDC_MPSWDRDR5_OFFSET)) > +#define MMDC_MPSWDRDR6 ((MMDC_REGS_BASE + MMDC_MPSWDRDR6_OFFSET)) > +#define MMDC_MPSWDRDR7 ((MMDC_REGS_BASE + MMDC_MPSWDRDR7_OFFSET)) > +#define MMDC_MPMUR ((MMDC_REGS_BASE + MMDC_MPMUR_OFFSET)) > +#define MMDC_MPWRCADL ((MMDC_REGS_BASE + MMDC_MPWRCADL_OFFSET)) > +#define MMDC_MPDCCR ((MMDC_REGS_BASE + MMDC_MPDCCR_OFFSET)) > +#define MMDC_MPBC ((MMDC_REGS_BASE + MMDC_MPBC_OFFSET)) > +#define MMDC_MPSWDRAR ((MMDC_REGS_BASE + MMDC_MPSWDRAR_OFFSET)) > + > +/* MMDC registers bit defines */ > +#define MMDC_MDCTL_SDE_0 (31) > +#define MMDC_MDCTL_SDE_1 (30) > +#define MMDC_MDCTL_ROW (24) > +#define MMDC_MDCTL_COL (20) > +#define MMDC_MDCTL_BL (19) > +#define MMDC_MDCTL_DSIZ (16) > + > +/* MDMISC */ > +#define MMDC_MDMISC_CS0_RDY (31) > +#define MMDC_MDMISC_CS1_RDY (30) > +#define MMDC_MDMISC_CK1_DEL (22) > +#define MMDC_MDMISC_CK1_GATING (21) > +#define MMDC_MDMISC_CALIB_PER_CS (20) > +#define MMDC_MDMISC_ADDR_MIRROR (19) > +#define MMDC_MDMISC_LHD (18) > +#define MMDC_MDMISC_WALAT (16) > +#define MMDC_MDMISC_BI (12) > +#define MMDC_MDMISC_LPDDR2_S (11) > +#define MMDC_MDMISC_MIF3_MODE (9) > +#define MMDC_MDMISC_RALAT (6) > +#define MMDC_MDMISC_DDR_4_BANK (5) > +#define MMDC_MDMISC_DDR_TYPE (3) > +#define MMDC_MDMISC_RST (1) > + > +/* MPWLGCR */ > +#define MMDC_MPWLGCR_WL_HW_ERR (8) > + > +/* MDSCR */ > +#define MMDC_MDSCR_CMD_ADDR_MSB (24) > +#define MMDC_MDSCR_MR_OP (24) > +#define MMDC_MDSCR_CMD_ADDR_LSB (16) > +#define MMDC_MDSCR_MR_ADDR (16) > +#define MMDC_MDSCR_CON_REQ (15) > +#define MMDC_MDSCR_CON_ACK (14) > +#define MMDC_MDSCR_MRR_READ_DATA_VALID (10) > +#define MMDC_MDSCR_WL_EN (9) > +#define MMDC_MDSCR_CMD (4) > +#define MMDC_MDSCR_CMD_CS (3) > +#define MMDC_MDSCR_CMD_BA (0) > + > +/* MPZQHWCTRL */ > +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR (16) > +#define MMDC_MPZQHWCTRL_ZQ_MODE (0) > + > +/* MPZQSWCTRL */ > +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP (16) > +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL (13) > +#define MMDC_MPZQSWCTRL_ZQ_SW_PD (12) > +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL (7) > +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL (2) > +#define MMDC_MPZQSWCTRL_ZQ_SW_RES (1) > +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR (0) > + > +/* MPDGCTRL0 */ > +#define MMDC_MPDGCTRL0_RST_RD_FIFO (31) > +#define MMDC_MPDGCTRL0_DG_CMP_CYC (30) > +#define MMDC_MPDGCTRL0_DG_DIS (29) > +#define MMDC_MPDGCTRL0_HW_DG_EN (28) > +#define MMDC_MPDGCTRL0_HW_DG_ERR (12) > + > +/* MPRDDLHWCTL */ > +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC (5) > +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN (4) > +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR (0) > + > +/* MPWRDLHWCTL */ > +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC (5) > +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN (4) > +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR (0) > + > +/* MPSWDAR */ > +#define MMDC_MPSWDAR_TEST_DUMMY_EN (6) > +#define MMDC_MPSWDAR_SW_DUM_CMP3 (5) > +#define MMDC_MPSWDAR_SW_DUM_CMP2 (4) > +#define MMDC_MPSWDAR_SW_DUM_CMP1 (3) > +#define MMDC_MPSWDAR_SW_DUM_CMP0 (2) > +#define MMDC_MPSWDAR_SW_DUMMY_RD (1) > +#define MMDC_MPSWDAR_SW_DUMMY_WR (0) > + > +/* MADPCR0 */ > +#define MMDC_MADPCR0_SBS (9) > +#define MMDC_MADPCR0_SBS_EN (8) > + > +/* MASBS1 */ > +#define MMDC_MASBS1_SBS_VLD (0) > +#define MMDC_MASBS1_SBS_TYPE (1) > + > +/* MDREF */ > +#define MMDC_MDREF_REF_CNT (16) > +#define MMDC_MDREF_REF_SEL (14) > +#define MMDC_MDREF_REFR (11) > +#define MMDC_MDREF_START_REF (0) > + > +/* MPWLGCR */ > +#define MMDC_MPWLGCR_HW_WL_EN (0) > + > +/* MPBC */ > +#define MMDC_MPBC_BIST_DM_LP_EN (0) > +#define MMDC_MPBC_BIST_CA0_LP_EN (1) > +#define MMDC_MPBC_BIST_DQ0_LP_EN (3) > +#define MMDC_MPBC_BIST_DQ1_LP_EN (4) > +#define MMDC_MPBC_BIST_DQ2_LP_EN (5) > +#define MMDC_MPBC_BIST_DQ3_LP_EN (6) > + > +/* MPMUR */ > +#define MMDC_MPMUR_FRC_MSR (11) > + > +/* MPODTCTRL */ > +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN (3) > +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN (2) > +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN (1) > +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN (0) > + > +/* MAPSR */ > +#define MMDC_MAPSR_DVACK (25) > +#define MMDC_MAPSR_LPACK (24) > +#define MMDC_MAPSR_DVFS (21) > +#define MMDC_MAPSR_LPMD (20) > + > +/* MAARCR */ > +#define MMDC_MAARCR_ARCR_EXC_ERR_EN (28) > + > +/* MPZQLP2CTL */ > +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS (24) > +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL (16) > +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT (0) > + > +/* MDCFG3LP */ > +#define MMDC_MDCFG3LP_tRC_LP (16) > +#define MMDC_MDCFG3LP_tRCD_LP (8) > +#define MMDC_MDCFG3LP_tRPpb_LP (4) > +#define MMDC_MDCFG3LP_tRPab_LP (0) > + > +/* MDOR */ > +#define MMDC_MDOR_tXPR (16) > +#define MMDC_MDOR_SDE_to_RST (8) > +#define MMDC_MDOR_RST_to_CKE (0) > + > +/* MDCFG0 */ > +#define MMDC_MDCFG0_tRFC (24) > +#define MMDC_MDCFG0_tXS (16) > +#define MMDC_MDCFG0_tXP (13) > +#define MMDC_MDCFG0_tXPDLL (9) > +#define MMDC_MDCFG0_tFAW (4) > +#define MMDC_MDCFG0_tCL (0) > + > +/* MDCFG1 */ > +#define MMDC_MDCFG1_tRCD (29) > +#define MMDC_MDCFG1_tRP (26) > +#define MMDC_MDCFG1_tRC (21) > +#define MMDC_MDCFG1_tRAS (16) > +#define MMDC_MDCFG1_tRPA (15) > +#define MMDC_MDCFG1_tWR (9) > +#define MMDC_MDCFG1_tMRD (5) > +#define MMDC_MDCFG1_tCWL (0) > + > +/* MDCFG2 */ > +#define MMDC_MDCFG2_tDLLK (16) > +#define MMDC_MDCFG2_tRTP (6) > +#define MMDC_MDCFG2_tWTR (3) > +#define MMDC_MDCFG2_tRRD (0) > + > +/* MDRWD */ > +#define MMDC_MDRWD_tDAI (16) > +#define MMDC_MDRWD_RTW_SAME (12) > +#define MMDC_MDRWD_WTR_DIFF (9) > +#define MMDC_MDRWD_WTW_DIFF (6) > +#define MMDC_MDRWD_RTW_DIFF (3) > +#define MMDC_MDRWD_RTR_DIFF (0) > + > +/* MDPDC */ > +#define MMDC_MDPDC_PRCT_1 (28) > +#define MMDC_MDPDC_PRCT_0 (24) > +#define MMDC_MDPDC_tCKE (16) > +#define MMDC_MDPDC_PWDT_1 (12) > +#define MMDC_MDPDC_PWDT_0 (8) > +#define MMDC_MDPDC_SLOW_PD (7) > +#define MMDC_MDPDC_BOTH_CS_PD (6) > +#define MMDC_MDPDC_tCKSRX (3) > +#define MMDC_MDPDC_tCKSRE (0) > + > +/* MDASP */ > +#define MMDC_MDASP_CS0_END (0) > + > +/* MAEXIDR0 */ > +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1 (16) > +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0 (0) > + > +/* MAEXIDR1 */ > +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3 (16) > +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2 (0) > + > +/* MPWRDLCTL */ > +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3 (24) > +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2 (16) > +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1 (8) > +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0 (0) > + > +/* MPRDDLCTL */ > +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3 (24) > +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2 (16) > +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1 (8) > +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0 (0) > + > +/* MPWRDQBY0DL */ > +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL (30) > +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL (28) > +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL (24) > +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL (20) > +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL (16) > +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL (12) > +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL (8) > +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL (4) > +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL (0) > + > +/* MPWRDQBY1DL */ > +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL (30) > +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL (28) > +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL (24) > +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL (20) > +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL (16) > +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL (12) > +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL (8) > +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL (4) > +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL (0) > + > +/* MPWRDQBY2DL */ > +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL (30) > +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL (28) > +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL (24) > +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL (20) > +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL (16) > +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL (12) > +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL (8) > +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL (4) > +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL (0) > + > +/* MPWRDQBY3DL */ > +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL (30) > +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL (28) > +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL (24) > +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL (20) > +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL (16) > +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL (12) > +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL (8) > +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL (4) > +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL (0) > + > +/* Fields masks */ > +#define MMDC_MDCTL_SDE_0_MASK ((0x1 << MMDC_MDCTL_SDE_0)) > +#define MMDC_MDCTL_SDE_1_MASK ((0x1 << MMDC_MDCTL_SDE_1)) > +#define MMDC_MDCTL_BL_MASK ((0x1 << MMDC_MDCTL_BL)) > +#define MMDC_MDCTL_ROW_MASK ((0x7 << MMDC_MDCTL_ROW)) > +#define MMDC_MDCTL_COL_MASK ((0x7 << MMDC_MDCTL_COL)) > +#define MMDC_MDCTL_DSIZ_MASK ((0x3 << MMDC_MDCTL_DSIZ)) > + > +/* MDMISC */ > +#define MMDC_MDMISC_CS0_RDY_MASK ((0x1 << MMDC_MDMISC_CS0_RDY)) > +#define MMDC_MDMISC_CS1_RDY_MASK ((0x1 << MMDC_MDMISC_CS1_RDY)) > +#define MMDC_MDMISC_CK1_DEL_MASK ((0x3 << MMDC_MDMISC_CK1_DEL)) > +#define MMDC_MDMISC_CK1_GATING_MASK ((0x1 << MMDC_MDMISC_CK1_GATING)) > +#define MMDC_MDMISC_CALIB_PER_CS_MASK ((0x1 << MMDC_MDMISC_CALIB_PER_CS)) > +#define MMDC_MDMISC_ADDR_MIRROR_MASK ((0x1 << MMDC_MDMISC_ADDR_MIRROR)) > +#define MMDC_MDMISC_LHD_MASK ((0x1 << MMDC_MDMISC_LHD)) > +#define MMDC_MDMISC_WALAT_MASK ((0x3 << MMDC_MDMISC_WALAT)) > +#define MMDC_MDMISC_BI_MASK ((0x1 << MMDC_MDMISC_BI)) > +#define MMDC_MDMISC_LPDDR2_S_MASK ((0x1 << MMDC_MDMISC_LPDDR2_S)) > +#define MMDC_MDMISC_MIF3_MODE_MASK ((0x3 << MMDC_MDMISC_MIF3_MODE)) > +#define MMDC_MDMISC_RALAT_MASK ((0x7 << MMDC_MDMISC_RALAT)) > +#define MMDC_MDMISC_DDR_4_BANK_MASK ((0x1 << MMDC_MDMISC_DDR_4_BANK)) > +#define MMDC_MDMISC_DDR_TYPE_MASK ((0x3 << MMDC_MDMISC_DDR_TYPE)) > +#define MMDC_MDMISC_RST_MASK ((0x1 << MMDC_MDMISC_RST)) > + > +/* MPWLGCR */ > +#define MMDC_MPWLGCR_WL_HW_ERR_MASK ((0xf << MMDC_MPWLGCR_WL_HW_ERR)) > + > +/* MDSCR */ > +#define MMDC_MDSCR_CMD_ADDR_MSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_MSB)) > +#define MMDC_MDSCR_MR_OP_MASK ((0xff << MMDC_MDSCR_MR_OP)) > +#define MMDC_MDSCR_CMD_ADDR_LSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_LSB)) > +#define MMDC_MDSCR_MR_ADDR_MASK ((0xff << MMDC_MDSCR_MR_ADDR)) > +#define MMDC_MDSCR_CON_REQ_MASK ((0x1 << MMDC_MDSCR_CON_REQ)) > +#define MMDC_MDSCR_CON_ACK_MASK ((0x1 << MMDC_MDSCR_CON_ACK)) > +#define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK ((0x1 << MMDC_MDSCR_MRR_READ_DATA_VALID)) > +#define MMDC_MDSCR_WL_EN_MASK ((0x1 << MMDC_MDSCR_WL_EN)) > +#define MMDC_MDSCR_CMD_MASK ((0x7 << MMDC_MDSCR_CMD)) > +#define MMDC_MDSCR_CMD_CS_MASK ((0x1 << MMDC_MDSCR_CMD_CS)) > +#define MMDC_MDSCR_CMD_BA_MASK ((0x7 << MMDC_MDSCR_CMD_BA)) > + > +/* MPZQHWCTRL */ > +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK ((0x1 << MMDC_MPZQHWCTRL_ZQ_HW_FOR)) > +#define MMDC_MPZQHWCTRL_ZQ_MODE_MASK ((0x3 << MMDC_MPZQHWCTRL_ZQ_MODE)) > + > +/* MPZQSWCTRL */ > +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK ((0x3 << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP)) > +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK ((0x1 << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL)) > +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_PD)) > +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL)) > +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL)) > +#define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_RES)) > +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_FOR)) > + > +/* MPDGCTRL0 */ > +#define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK ((0x1 << MMDC_MPDGCTRL0_RST_RD_FIFO)) > +#define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK ((0x1 << MMDC_MPDGCTRL0_DG_CMP_CYC)) > +#define MMDC_MPDGCTRL0_DG_DIS_MASK ((0x1 << MMDC_MPDGCTRL0_DG_DIS)) > +#define MMDC_MPDGCTRL0_HW_DG_EN_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_EN)) > +#define MMDC_MPDGCTRL0_HW_DG_ERR_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_ERR)) > + > +/* MPRDDLHWCTL */ > +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC)) > +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_EN)) > +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR_MASK ((0xf << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR)) > + > +/* MPWRDLHWCTL */ > +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC)) > +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_EN)) > +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR_MASK ((0xf << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR)) > + > +/* MPSWDAR */ > +#define MMDC_MPSWDAR_TEST_DUMMY_EN_MASK ((0x1 << MMDC_MPSWDAR_TEST_DUMMY_EN)) > +#define MMDC_MPSWDAR_SW_DUM_CMP3_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP3)) > +#define MMDC_MPSWDAR_SW_DUM_CMP2_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP2)) > +#define MMDC_MPSWDAR_SW_DUM_CMP1_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP1)) > +#define MMDC_MPSWDAR_SW_DUM_CMP0_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP0)) > +#define MMDC_MPSWDAR_SW_DUMMY_RD_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_RD)) > +#define MMDC_MPSWDAR_SW_DUMMY_WR_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_WR)) > + > +/* MADPCR0 */ > +#define MMDC_MADPCR0_SBS_MASK ((0x1 << MMDC_MADPCR0_SBS)) > +#define MMDC_MADPCR0_SBS_EN_MASK ((0x1 << MMDC_MADPCR0_SBS_EN)) > + > +/* MASBS1 */ > +#define MMDC_MASBS1_SBS_VLD_MASK ((0x1 << MMDC_MASBS1_SBS_VLD)) > +#define MMDC_MASBS1_SBS_TYPE_MASK ((0x1 << MMDC_MASBS1_SBS_TYPE)) > + > +/* MDREF */ > +#define MMDC_MDREF_REF_CNT_MASK ((0xffff << MMDC_MDREF_REF_CNT)) > +#define MMDC_MDREF_REF_SEL_MASK ((0x3 << MMDC_MDREF_REF_SEL)) > +#define MMDC_MDREF_REFR_MASK ((0x7 << MMDC_MDREF_REFR)) > +#define MMDC_MDREF_START_REF_MASK ((0x1 << MMDC_MDREF_START_REF)) > + > +/* MPWLGCR */ > +#define MMDC_MPWLGCR_HW_WL_EN_MASK ((0x1 << MMDC_MPWLGCR_HW_WL_EN)) > + > +/* MPBC */ > +#define MMDC_MPBC_BIST_DM_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DM_LP_EN)) > +#define MMDC_MPBC_BIST_CA0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_CA0_LP_EN)) > +#define MMDC_MPBC_BIST_DQ0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ0_LP_EN)) > +#define MMDC_MPBC_BIST_DQ1_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ1_LP_EN)) > +#define MMDC_MPBC_BIST_DQ2_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ2_LP_EN)) > +#define MMDC_MPBC_BIST_DQ3_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ3_LP_EN)) > +#define MMDC_MPBC_BIST_DQ_LP_EN_MASK ((0xf << MMDC_MPBC_BIST_DQ0_LP_EN)) > + > +/* MPMUR */ > +#define MMDC_MPMUR_FRC_MSR_MASK ((0x1 << MMDC_MPMUR_FRC_MSR)) > + > +/* MPODTCTRL */ > +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_ACT_EN)) > +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_PAS_EN)) > +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_ACT_EN)) > +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_PAS_EN)) > + > +/* MAPSR */ > +#define MMDC_MAPSR_DVACK_MASK ((0x1 << MMDC_MAPSR_DVACK)) > +#define MMDC_MAPSR_LPACK_MASK ((0x1 << MMDC_MAPSR_LPACK)) > +#define MMDC_MAPSR_DVFS_MASK ((0x1 << MMDC_MAPSR_DVFS)) > +#define MMDC_MAPSR_LPMD_MASK ((0x1 << MMDC_MAPSR_LPMD)) > + > +/* MAARCR */ > +#define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK ((0x1 << MMDC_MAARCR_ARCR_EXC_ERR_EN)) > + > +/* MPZQLP2CTL */ > +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK ((0x7f << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS)) > +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK ((0xff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL)) > +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK ((0x1ff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT)) > + > +/* MDCFG3LP */ > +#define MMDC_MDCFG3LP_tRC_LP_MASK ((0x3f << MMDC_MDCFG3LP_tRC_LP)) > +#define MMDC_MDCFG3LP_tRCD_LP_MASK ((0xf << MMDC_MDCFG3LP_tRCD_LP)) > +#define MMDC_MDCFG3LP_tRPpb_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPpb_LP)) > +#define MMDC_MDCFG3LP_tRPab_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPab_LP)) > + > +/* MDOR */ > +#define MMDC_MDOR_tXPR_MASK ((0xff << MMDC_MDOR_tXPR)) > +#define MMDC_MDOR_SDE_to_RST_MASK ((0x3f << MMDC_MDOR_SDE_to_RST)) > +#define MMDC_MDOR_RST_to_CKE_MASK ((0x3f << MMDC_MDOR_RST_to_CKE)) > + > +/* MDCFG0 */ > +#define MMDC_MDCFG0_tRFC_MASK ((0xff << MMDC_MDCFG0_tRFC)) > +#define MMDC_MDCFG0_tXS_MASK ((0xff << MMDC_MDCFG0_tXS)) > +#define MMDC_MDCFG0_tXP_MASK ((0x7 << MMDC_MDCFG0_tXP)) > +#define MMDC_MDCFG0_tXPDLL_MASK ((0xf << MMDC_MDCFG0_tXPDLL)) > +#define MMDC_MDCFG0_tFAW_MASK ((0x1f << MMDC_MDCFG0_tFAW)) > +#define MMDC_MDCFG0_tCL_MASK ((0xf << MMDC_MDCFG0_tCL)) > + > +/* MDCFG1 */ > +#define MMDC_MDCFG1_tRCD_MASK ((0x7 << MMDC_MDCFG1_tRCD)) > +#define MMDC_MDCFG1_tRP_MASK ((0x7 << MMDC_MDCFG1_tRP)) > +#define MMDC_MDCFG1_tRC_MASK ((0x1f << MMDC_MDCFG1_tRC)) > +#define MMDC_MDCFG1_tRAS_MASK ((0x1f << MMDC_MDCFG1_tRAS)) > +#define MMDC_MDCFG1_tRPA_MASK ((0x1 << MMDC_MDCFG1_tRPA)) > +#define MMDC_MDCFG1_tWR_MASK ((0x7 << MMDC_MDCFG1_tWR)) > +#define MMDC_MDCFG1_tMRD_MASK ((0xf << MMDC_MDCFG1_tMRD)) > +#define MMDC_MDCFG1_tCWL_MASK ((0x7 << MMDC_MDCFG1_tCWL)) > + > +/* MDCFG2 */ > +#define MMDC_MDCFG2_tDLLK_MASK ((0x1ff << MMDC_MDCFG2_tDLLK)) > +#define MMDC_MDCFG2_tRTP_MASK ((0x7 << MMDC_MDCFG2_tRTP)) > +#define MMDC_MDCFG2_tWTR_MASK ((0x7 << MMDC_MDCFG2_tWTR)) > +#define MMDC_MDCFG2_tRRD_MASK ((0x7 << MMDC_MDCFG2_tRRD)) > + > +/* MDRWD */ > +#define MMDC_MDRWD_tDAI_MASK ((0x1fff << MMDC_MDRWD_tDAI)) > +#define MMDC_MDRWD_RTW_SAME_MASK ((0x7 << MMDC_MDRWD_RTW_SAME)) > +#define MMDC_MDRWD_WTR_DIFF_MASK ((0x7 << MMDC_MDRWD_WTR_DIFF)) > +#define MMDC_MDRWD_WTW_DIFF_MASK ((0x7 << MMDC_MDRWD_WTW_DIFF)) > +#define MMDC_MDRWD_RTW_DIFF_MASK ((0x7 << MMDC_MDRWD_RTW_DIFF)) > +#define MMDC_MDRWD_RTR_DIFF_MASK ((0x7 << MMDC_MDRWD_RTR_DIFF)) > + > +/* MDPDC */ > +#define MMDC_MDPDC_PRCT_1_MASK ((0x7 << MMDC_MDPDC_PRCT_1)) > +#define MMDC_MDPDC_PRCT_0_MASK ((0x7 << MMDC_MDPDC_PRCT_0)) > +#define MMDC_MDPDC_tCKE_MASK ((0x7 << MMDC_MDPDC_tCKE)) > +#define MMDC_MDPDC_PWDT_1_MASK ((0xf << MMDC_MDPDC_PWDT_1)) > +#define MMDC_MDPDC_PWDT_0_MASK ((0xf << MMDC_MDPDC_PWDT_0)) > +#define MMDC_MDPDC_SLOW_PD_MASK ((0x1 << MMDC_MDPDC_SLOW_PD)) > +#define MMDC_MDPDC_BOTH_CS_PD_MASK ((0x1 << MMDC_MDPDC_BOTH_CS_PD)) > +#define MMDC_MDPDC_tCKSRX_MASK ((0x7 << MMDC_MDPDC_tCKSRX)) > +#define MMDC_MDPDC_tCKSRE_MASK ((0x7 << MMDC_MDPDC_tCKSRE)) > + > +/* MDASP */ > +#define MMDC_MDASP_CS0_END_MASK ((0x7f << MMDC_MDASP_CS0_END)) > + > +/* MAEXIDR0 */ > +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR1)) > +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR0)) > + > +/* MAEXIDR1 */ > +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR3)) > +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR2)) > + > +/* MPWRDLCTL */ > +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3)) > +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2)) > +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1)) > +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0)) > + > +/* MPRDDLCTL */ > +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3)) > +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2)) > +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1)) > +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0)) > + > +/* MPWRDQBY0DL */ > +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DM0_DEL)) > +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ7_DEL)) > +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ6_DEL)) > +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ5_DEL)) > +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ4_DEL)) > +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ3_DEL)) > +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ2_DEL)) > +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ1_DEL)) > +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ0_DEL)) > + > +/* MPWRDQBY1DL */ > +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DM1_DEL)) > +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ15_DEL)) > +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ14_DEL)) > +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ13_DEL)) > +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ12_DEL)) > +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ11_DEL)) > +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ10_DEL)) > +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ9_DEL)) > +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ8_DEL)) > + > +/* MPWRDQBY2DL */ > +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DM2_DEL)) > +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ23_DEL)) > +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ22_DEL)) > +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ21_DEL)) > +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ20_DEL)) > +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ19_DEL)) > +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ18_DEL)) > +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ17_DEL)) > +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ16_DEL)) > + > +/* MPWRDQBY3DL */ > +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DM3_DEL)) > +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ31_DEL)) > +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ30_DEL)) > +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ29_DEL)) > +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ28_DEL)) > +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ27_DEL)) > +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ26_DEL)) > +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL)) > +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL)) > + > +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) > + > +#include <asm/types.h> > + > +struct fuse_word { > + u32 fuse; > + u32 rsvd[3]; > +}; > + > +struct ocotp_regs { > + u32 ctrl; > + u32 ctrl_set; > + u32 ctrl_clr; > + u32 ctrl_tog; > + u32 pdn; > + u32 rsvd0[3]; > + u32 data; > + u32 rsvd1[3]; > + u32 read_ctrl; > + u32 rsvd2[3]; > + u32 read_fuse_data; > + u32 rsvd3[3]; > + u32 sw_sticky; > + u32 rsvd4[3]; > + u32 scs; > + u32 scs_set; > + u32 scs_clr; > + u32 scs_tog; > + u32 out_status; > + u32 out_status_set; > + u32 out_status_clr; > + u32 out_status_tog; > + u32 startword; > + u32 rsvd5[3]; > + u32 version; > + u32 rsvd6[19]; > + struct fuse_word mem_repair[8]; > + u32 rsvd7[0xa8]; > + > + /* fuse banks */ > + struct fuse_bank { > + u32 fuse_regs[0x20]; > + } bank[0]; > +}; > + > +struct fuse_bank1_regs { > + u32 lock0; > + u32 rsvd0[3]; > + u32 lock1; > + u32 rsvd1[3]; > + u32 lock2; > + u32 rsvd2[3]; > + u32 cfg0; > + u32 rsvd3[3]; > + u32 cfg1; > + u32 rsvd4[3]; > + u32 cfg2; > + u32 rsvd5[3]; > + u32 cfg3; > + u32 rsvd6[3]; > + u32 cfg4; > + u32 rsvd7[3]; > +}; > + > +struct fuse_bank2_regs { > + struct fuse_word boot[8]; > +}; > + > +struct fuse_bank3_regs { > + u32 mem0; > + u32 rsvd0[3]; > + u32 mem1; > + u32 rsvd1[3]; > + u32 mem2; > + u32 rsvd2[3]; > + u32 mem3; > + u32 rsvd3[3]; > + u32 ana0; > + u32 rsvd4[3]; > + u32 ana1; > + u32 rsvd5[3]; > + u32 ana2; > + u32 rsvd6[3]; > + u32 ana3; > + u32 rsvd7[3]; > +}; > + > +struct fuse_bank7_regs { > + u32 sjc_resp0; > + u32 rsvd0[3]; > + u32 sjc_resp1; > + u32 rsvd1[3]; > + u32 gp0; > + u32 rsvd2[3]; > + u32 gp1; > + u32 rsvd3[3]; > + u32 gp2; > + u32 rsvd4[3]; > + u32 gp3; > + u32 rsvd5[3]; > + u32 gp4; > + u32 rsvd6[3]; > + u32 gp5; > + u32 rsvd7[3]; > +}; > + > +struct usbphy_regs { > + u32 usbphy_pwd; /* 0x000 */ > + u32 usbphy_pwd_set; /* 0x004 */ > + u32 usbphy_pwd_clr; /* 0x008 */ > + u32 usbphy_pwd_tog; /* 0x00c */ > + u32 usbphy_tx; /* 0x010 */ > + u32 usbphy_tx_set; /* 0x014 */ > + u32 usbphy_tx_clr; /* 0x018 */ > + u32 usbphy_tx_tog; /* 0x01c */ > + u32 usbphy_rx; /* 0x020 */ > + u32 usbphy_rx_set; /* 0x024 */ > + u32 usbphy_rx_clr; /* 0x028 */ > + u32 usbphy_rx_tog; /* 0x02c */ > + u32 usbphy_ctrl; /* 0x030 */ > + u32 usbphy_ctrl_set; /* 0x034 */ > + u32 usbphy_ctrl_clr; /* 0x038 */ > + u32 usbphy_ctrl_tog; /* 0x03c */ > + u32 usbphy_status; /* 0x040 */ > + u32 reserved0[3]; > + u32 usbphy_debug0; /* 0x050 */ > + u32 usbphy_debug0_set; /* 0x054 */ > + u32 usbphy_debug0_clr; /* 0x058 */ > + u32 usbphy_debug0_tog; /* 0x05c */ > + u32 reserved1[4]; > + u32 usbphy_debug1; /* 0x070 */ > + u32 usbphy_debug1_set; /* 0x074 */ > + u32 usbphy_debug1_clr; /* 0x078 */ > + u32 usbphy_debug1_tog; /* 0x07c */ > + u32 usbphy_version; /* 0x080 */ > + u32 reserved2[7]; > + u32 usb1_pll_480_ctrl; /* 0x0a0 */ > + u32 usb1_pll_480_ctrl_set; /* 0x0a4 */ > + u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */ > + u32 usb1_pll_480_ctrl_tog; /* 0x0ac */ > + u32 reserved3[4]; > + u32 usb1_vbus_detect; /* 0xc0 */ > + u32 usb1_vbus_detect_set; /* 0xc4 */ > + u32 usb1_vbus_detect_clr; /* 0xc8 */ > + u32 usb1_vbus_detect_tog; /* 0xcc */ > + u32 usb1_vbus_det_stat; /* 0xd0 */ > + u32 reserved4[3]; > + u32 usb1_chrg_detect; /* 0xe0 */ > + u32 usb1_chrg_detect_set; /* 0xe4 */ > + u32 usb1_chrg_detect_clr; /* 0xe8 */ > + u32 usb1_chrg_detect_tog; /* 0xec */ > + u32 usb1_chrg_det_stat; /* 0xf0 */ > + u32 reserved5[3]; > + u32 usbphy_anactrl; /* 0x100 */ > + u32 usbphy_anactrl_set; /* 0x104 */ > + u32 usbphy_anactrl_clr; /* 0x108 */ > + u32 usbphy_anactrl_tog; /* 0x10c */ > + u32 usb1_loopback; /* 0x110 */ > + u32 usb1_loopback_set; /* 0x114 */ > + u32 usb1_loopback_clr; /* 0x118 */ > + u32 usb1_loopback_tog; /* 0x11c */ > + u32 usb1_loopback_hsfscnt; /* 0x120 */ > + u32 usb1_loopback_hsfscnt_set; /* 0x124 */ > + u32 usb1_loopback_hsfscnt_clr; /* 0x128 */ > + u32 usb1_loopback_hsfscnt_tog; /* 0x12c */ > + u32 usphy_trim_override_en; /* 0x130 */ > + u32 usphy_trim_override_en_set; /* 0x134 */ > + u32 usphy_trim_override_en_clr; /* 0x138 */ > + u32 usphy_trim_override_en_tog; /* 0x13c */ > + u32 usb1_pfda_ctrl1; /* 0x140 */ > + u32 usb1_pfda_ctrl1_set; /* 0x144 */ > + u32 usb1_pfda_ctrl1_clr; /* 0x148 */ > + u32 usb1_pfda_ctrl1_tog; /* 0x14c */ > +}; > + > + > +#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) > +#define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140) > + > +#endif > + > +#endif /* _MX7ULP_REGS_H_*/ > Reviewed-by : Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 03/20] imx: mx7ulp: add iomux driver to support IOMUXC0 and IOMUXC1 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan 2016-12-27 10:04 ` [U-Boot] [PATCH V2 01/20] imx: mx7ulp: Add mx7ulp to Kconfig Peng Fan 2016-12-27 10:04 ` [U-Boot] [PATCH V2 02/20] imx: mx7ulp: add registers header file Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2017-02-12 8:45 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 04/20] imx: mx7ulp: Add clock framework and functions Peng Fan ` (17 subsequent siblings) 20 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Add a new driver under ULP directory to support its IOMUXC controllers. The ULP has two IOMUXC, the IOMUXC0 is used for M4 domain, while IOMUXC1 is for A7. We set IOMUXC1 as the default IOMUX in this driver. Any pins in IOMUXC0 needs to configure with IOMUX_CONFIG_MPORTS in its mux_mode field. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: none arch/arm/cpu/armv7/mx7ulp/Makefile | 8 +++ arch/arm/cpu/armv7/mx7ulp/iomux.c | 70 +++++++++++++++++++++++ arch/arm/include/asm/arch-mx7ulp/iomux.h | 95 ++++++++++++++++++++++++++++++++ 3 files changed, 173 insertions(+) create mode 100644 arch/arm/cpu/armv7/mx7ulp/Makefile create mode 100644 arch/arm/cpu/armv7/mx7ulp/iomux.c create mode 100644 arch/arm/include/asm/arch-mx7ulp/iomux.h diff --git a/arch/arm/cpu/armv7/mx7ulp/Makefile b/arch/arm/cpu/armv7/mx7ulp/Makefile new file mode 100644 index 0000000..be038e7 --- /dev/null +++ b/arch/arm/cpu/armv7/mx7ulp/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +# + +obj-y := iomux.o diff --git a/arch/arm/cpu/armv7/mx7ulp/iomux.c b/arch/arm/cpu/armv7/mx7ulp/iomux.c new file mode 100644 index 0000000..1eba24e --- /dev/null +++ b/arch/arm/cpu/armv7/mx7ulp/iomux.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> + +static void *base = (void *)IOMUXC_BASE_ADDR; + +/* + * iomuxc0 base address. In imx7ulp-pins.h, + * the offsets of pins in iomuxc0 are from 0xD000, + * so we set the base address to (0x4103D000 - 0xD000 = 0x41030000) + */ +static void *base_mports = (void *)(AIPS0_BASE + 0x30000); + +/* + * configures a single pad in the iomuxer + */ +void mx7ulp_iomux_setup_pad(iomux_cfg_t pad) +{ + u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; + u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; + u32 sel_input_ofs = + (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; + u32 sel_input = + (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; + u32 pad_ctrl_ofs = mux_ctrl_ofs; + u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; + + debug("[PAD CFG] = 0x%16llX \r\n\tmux_ctl = 0x%X(0x%X) sel_input = 0x%X(0x%X) pad_ctrl = 0x%X(0x%X)\r\n", + pad, mux_ctrl_ofs, mux_mode, sel_input_ofs, sel_input, + pad_ctrl_ofs, pad_ctrl); + + if (mux_mode & IOMUX_CONFIG_MPORTS) { + mux_mode &= ~IOMUX_CONFIG_MPORTS; + base = base_mports; + } else { + base = (void *)IOMUXC_BASE_ADDR; + } + + __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & + IOMUXC_PCR_MUX_ALT_MASK), base + mux_ctrl_ofs); + + if (sel_input_ofs) + __raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT), + base + sel_input_ofs); + + if (!(pad_ctrl & NO_PAD_CTRL)) + __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & + IOMUXC_PCR_MUX_ALT_MASK) | + (pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)), + base + pad_ctrl_ofs); +} + +/* configures a list of pads within declared with IOMUX_PADS macro */ +void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, + unsigned count) +{ + iomux_cfg_t const *p = pad_list; + int i; + + for (i = 0; i < count; i++) { + mx7ulp_iomux_setup_pad(*p); + p++; + } +} diff --git a/arch/arm/include/asm/arch-mx7ulp/iomux.h b/arch/arm/include/asm/arch-mx7ulp/iomux.h new file mode 100644 index 0000000..a2307db --- /dev/null +++ b/arch/arm/include/asm/arch-mx7ulp/iomux.h @@ -0,0 +1,95 @@ +/* + * Based on Linux i.MX iomux-v3.h file: + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * <armlinux@phytec.de> + * + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MACH_IOMUX_H__ +#define __MACH_IOMUX_H__ + +/* + * build IOMUX_PAD structure + * + * This iomux scheme is based around pads, which are the physical balls + * on the processor. + * + * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls + * things like driving strength and pullup/pulldown. + * - Each pad can have but not necessarily does have an output routing register + * (IOMUXC_SW_MUX_CTL_PAD_x). + * - Each pad can have but not necessarily does have an input routing register + * (IOMUXC_x_SELECT_INPUT) + * + * The three register sets do not have a fixed offset to each other, + * hence we order this table by pad control registers (which all pads + * have) and put the optional i/o routing registers into additional + * fields. + * + * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode> + * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> + * + * IOMUX/PAD Bit field definitions + * + * MUX_CTRL_OFS: 0..15 (16) + * SEL_INPUT_OFS: 16..31 (16) + * MUX_MODE: 32..37 (6) + * SEL_INP: 38..41 (4) + * PAD_CTRL + NO_PAD_CTRL: 42..60 (19) + * reserved: 61-63 (3) +*/ + +typedef u64 iomux_cfg_t; + +#define MUX_CTRL_OFS_SHIFT 0 +#define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT) +#define MUX_SEL_INPUT_OFS_SHIFT 16 +#define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0xffff << \ + MUX_SEL_INPUT_OFS_SHIFT) + +#define MUX_MODE_SHIFT 32 +#define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT) +#define MUX_SEL_INPUT_SHIFT 38 +#define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) +#define MUX_PAD_CTRL_SHIFT 42 +#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT) + +#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) + +#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ + sel_input, pad_ctrl) \ + (((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ + ((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ + ((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ + ((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \ + ((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) + +#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ + MUX_PAD_CTRL(pad)) + + +#define IOMUX_CONFIG_MPORTS 0x20 +#define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \ + MUX_MODE_SHIFT) + +/* Bit definition below needs to be fixed acccording to ulp rm */ + +#define NO_PAD_CTRL (1 << 18) +#define PAD_CTL_OBE_ENABLE (1 << 17) +#define PAD_CTL_IBE_ENABLE (1 << 16) +#define PAD_CTL_DSE (1 << 6) +#define PAD_CTL_ODE (1 << 5) +#define PAD_CTL_SRE_FAST (0 << 2) +#define PAD_CTL_SRE_SLOW (1 << 2) +#define PAD_CTL_PUE (1 << 1) +#define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE) +#define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE) + + +void mx7ulp_iomux_setup_pad(iomux_cfg_t pad); +void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, + unsigned count); +#endif /* __MACH_IOMUX_H__*/ -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 03/20] imx: mx7ulp: add iomux driver to support IOMUXC0 and IOMUXC1 2016-12-27 10:04 ` [U-Boot] [PATCH V2 03/20] imx: mx7ulp: add iomux driver to support IOMUXC0 and IOMUXC1 Peng Fan @ 2017-02-12 8:45 ` Stefano Babic 0 siblings, 0 replies; 48+ messages in thread From: Stefano Babic @ 2017-02-12 8:45 UTC (permalink / raw) To: u-boot Hi Peng, On 27/12/2016 11:04, Peng Fan wrote: > Add a new driver under ULP directory to support its IOMUXC > controllers. The ULP has two IOMUXC, the IOMUXC0 is used > for M4 domain, while IOMUXC1 is for A7. We set IOMUXC1 as > the default IOMUX in this driver. Any pins in IOMUXC0 needs > to configure with IOMUX_CONFIG_MPORTS in its mux_mode field. > > Signed-off-by: Ye Li <ye.li@nxp.com> > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > none > > arch/arm/cpu/armv7/mx7ulp/Makefile | 8 +++ > arch/arm/cpu/armv7/mx7ulp/iomux.c | 70 +++++++++++++++++++++++ > arch/arm/include/asm/arch-mx7ulp/iomux.h | 95 ++++++++++++++++++++++++++++++++ > 3 files changed, 173 insertions(+) > create mode 100644 arch/arm/cpu/armv7/mx7ulp/Makefile > create mode 100644 arch/arm/cpu/armv7/mx7ulp/iomux.c > create mode 100644 arch/arm/include/asm/arch-mx7ulp/iomux.h > > diff --git a/arch/arm/cpu/armv7/mx7ulp/Makefile b/arch/arm/cpu/armv7/mx7ulp/Makefile > new file mode 100644 > index 0000000..be038e7 > --- /dev/null > +++ b/arch/arm/cpu/armv7/mx7ulp/Makefile > @@ -0,0 +1,8 @@ > +# > +# (C) Copyright 2016 Freescale Semiconductor, Inc. > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > +# > + > +obj-y := iomux.o > diff --git a/arch/arm/cpu/armv7/mx7ulp/iomux.c b/arch/arm/cpu/armv7/mx7ulp/iomux.c > new file mode 100644 > index 0000000..1eba24e > --- /dev/null > +++ b/arch/arm/cpu/armv7/mx7ulp/iomux.c > @@ -0,0 +1,70 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > +#include <common.h> > +#include <asm/io.h> > +#include <asm/arch/imx-regs.h> > +#include <asm/arch/iomux.h> > + > +static void *base = (void *)IOMUXC_BASE_ADDR; > + > +/* > + * iomuxc0 base address. In imx7ulp-pins.h, > + * the offsets of pins in iomuxc0 are from 0xD000, > + * so we set the base address to (0x4103D000 - 0xD000 = 0x41030000) > + */ > +static void *base_mports = (void *)(AIPS0_BASE + 0x30000); > + > +/* > + * configures a single pad in the iomuxer > + */ > +void mx7ulp_iomux_setup_pad(iomux_cfg_t pad) > +{ > + u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; > + u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; > + u32 sel_input_ofs = > + (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; > + u32 sel_input = > + (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; > + u32 pad_ctrl_ofs = mux_ctrl_ofs; > + u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; > + > + debug("[PAD CFG] = 0x%16llX \r\n\tmux_ctl = 0x%X(0x%X) sel_input = 0x%X(0x%X) pad_ctrl = 0x%X(0x%X)\r\n", > + pad, mux_ctrl_ofs, mux_mode, sel_input_ofs, sel_input, > + pad_ctrl_ofs, pad_ctrl); > + > + if (mux_mode & IOMUX_CONFIG_MPORTS) { > + mux_mode &= ~IOMUX_CONFIG_MPORTS; > + base = base_mports; > + } else { > + base = (void *)IOMUXC_BASE_ADDR; > + } > + > + __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & > + IOMUXC_PCR_MUX_ALT_MASK), base + mux_ctrl_ofs); > + > + if (sel_input_ofs) > + __raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT), > + base + sel_input_ofs); > + > + if (!(pad_ctrl & NO_PAD_CTRL)) > + __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & > + IOMUXC_PCR_MUX_ALT_MASK) | > + (pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)), > + base + pad_ctrl_ofs); > +} > + > +/* configures a list of pads within declared with IOMUX_PADS macro */ > +void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, > + unsigned count) > +{ > + iomux_cfg_t const *p = pad_list; > + int i; > + > + for (i = 0; i < count; i++) { > + mx7ulp_iomux_setup_pad(*p); > + p++; > + } > +} > diff --git a/arch/arm/include/asm/arch-mx7ulp/iomux.h b/arch/arm/include/asm/arch-mx7ulp/iomux.h > new file mode 100644 > index 0000000..a2307db > --- /dev/null > +++ b/arch/arm/include/asm/arch-mx7ulp/iomux.h > @@ -0,0 +1,95 @@ > +/* > + * Based on Linux i.MX iomux-v3.h file: > + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, > + * <armlinux@phytec.de> > + * > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __MACH_IOMUX_H__ > +#define __MACH_IOMUX_H__ > + > +/* > + * build IOMUX_PAD structure > + * > + * This iomux scheme is based around pads, which are the physical balls > + * on the processor. > + * > + * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls > + * things like driving strength and pullup/pulldown. > + * - Each pad can have but not necessarily does have an output routing register > + * (IOMUXC_SW_MUX_CTL_PAD_x). > + * - Each pad can have but not necessarily does have an input routing register > + * (IOMUXC_x_SELECT_INPUT) > + * > + * The three register sets do not have a fixed offset to each other, > + * hence we order this table by pad control registers (which all pads > + * have) and put the optional i/o routing registers into additional > + * fields. > + * > + * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode> > + * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> > + * > + * IOMUX/PAD Bit field definitions > + * > + * MUX_CTRL_OFS: 0..15 (16) > + * SEL_INPUT_OFS: 16..31 (16) > + * MUX_MODE: 32..37 (6) > + * SEL_INP: 38..41 (4) > + * PAD_CTRL + NO_PAD_CTRL: 42..60 (19) > + * reserved: 61-63 (3) > +*/ > + > +typedef u64 iomux_cfg_t; > + > +#define MUX_CTRL_OFS_SHIFT 0 > +#define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT) > +#define MUX_SEL_INPUT_OFS_SHIFT 16 > +#define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0xffff << \ > + MUX_SEL_INPUT_OFS_SHIFT) > + > +#define MUX_MODE_SHIFT 32 > +#define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT) > +#define MUX_SEL_INPUT_SHIFT 38 > +#define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) > +#define MUX_PAD_CTRL_SHIFT 42 > +#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT) > + > +#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) > + > +#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ > + sel_input, pad_ctrl) \ > + (((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ > + ((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ > + ((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ > + ((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \ > + ((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) > + > +#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ > + MUX_PAD_CTRL(pad)) > + > + > +#define IOMUX_CONFIG_MPORTS 0x20 > +#define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \ > + MUX_MODE_SHIFT) > + > +/* Bit definition below needs to be fixed acccording to ulp rm */ > + > +#define NO_PAD_CTRL (1 << 18) > +#define PAD_CTL_OBE_ENABLE (1 << 17) > +#define PAD_CTL_IBE_ENABLE (1 << 16) > +#define PAD_CTL_DSE (1 << 6) > +#define PAD_CTL_ODE (1 << 5) > +#define PAD_CTL_SRE_FAST (0 << 2) > +#define PAD_CTL_SRE_SLOW (1 << 2) > +#define PAD_CTL_PUE (1 << 1) > +#define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE) > +#define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE) > + > + > +void mx7ulp_iomux_setup_pad(iomux_cfg_t pad); > +void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, > + unsigned count); > +#endif /* __MACH_IOMUX_H__*/ > Thought about if this code can go to iomux_v3.c in imx-common, but functions here are simple and merging together makes the code more difficult to read. So I have not a better idea for it. IMHO it is ok to put it in a separate directory as you did. Reviewed-by : Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 04/20] imx: mx7ulp: Add clock framework and functions 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (2 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 03/20] imx: mx7ulp: add iomux driver to support IOMUXC0 and IOMUXC1 Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2017-02-12 9:12 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 05/20] imx: mx7ulp: Add soc level initialization codes " Peng Fan ` (16 subsequent siblings) 20 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set clock source, divider, clock rate and parent source. Users need to include pcc.h to use the APIs to for peripherals clock. Each peripheral clock is defined in enum pcc_clk type. SCG relevants APIs are defined in scg.h which supports clock rate get, PLL/PFD enablement and settings, and all SCG clock initialization. User need use enum scg_clk to access each clock source. In clock.c, we initialize necessary clocks at u-boot s_init and implement the clock functions used by driver modules to operate clocks dynamically. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: None arch/arm/cpu/armv7/mx7ulp/Makefile | 2 +- arch/arm/cpu/armv7/mx7ulp/clock.c | 286 ++++++++ arch/arm/cpu/armv7/mx7ulp/pcc.c | 286 ++++++++ arch/arm/cpu/armv7/mx7ulp/scg.c | 1086 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx7ulp/clock.h | 38 ++ arch/arm/include/asm/arch-mx7ulp/pcc.h | 377 +++++++++++ arch/arm/include/asm/arch-mx7ulp/scg.h | 342 ++++++++++ 7 files changed, 2416 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/mx7ulp/clock.c create mode 100644 arch/arm/cpu/armv7/mx7ulp/pcc.c create mode 100644 arch/arm/cpu/armv7/mx7ulp/scg.c create mode 100644 arch/arm/include/asm/arch-mx7ulp/clock.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/pcc.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/scg.h diff --git a/arch/arm/cpu/armv7/mx7ulp/Makefile b/arch/arm/cpu/armv7/mx7ulp/Makefile index be038e7..6f37e8c 100644 --- a/arch/arm/cpu/armv7/mx7ulp/Makefile +++ b/arch/arm/cpu/armv7/mx7ulp/Makefile @@ -5,4 +5,4 @@ # # -obj-y := iomux.o +obj-y := clock.o iomux.o pcc.o scg.o diff --git a/arch/arm/cpu/armv7/mx7ulp/clock.c b/arch/arm/cpu/armv7/mx7ulp/clock.c new file mode 100644 index 0000000..534f632 --- /dev/null +++ b/arch/arm/cpu/armv7/mx7ulp/clock.c @@ -0,0 +1,286 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <div64.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +int get_clocks(void) +{ +#ifdef CONFIG_FSL_ESDHC +#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE + gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE + gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); +#endif +#endif + return 0; +} + +static u32 get_fast_plat_clk(void) +{ + return scg_clk_get_rate(SCG_NIC0_CLK); +} + +static u32 get_slow_plat_clk(void) +{ + return scg_clk_get_rate(SCG_NIC1_CLK); +} + +static u32 get_ipg_clk(void) +{ + return scg_clk_get_rate(SCG_NIC1_BUS_CLK); +} + +u32 get_lpuart_clk(void) +{ + return pcc_clock_get_rate(PER_CLK_LPUART4); +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return scg_clk_get_rate(SCG_CORE_CLK); + case MXC_AXI_CLK: + return get_fast_plat_clk(); + case MXC_AHB_CLK: + return get_slow_plat_clk(); + case MXC_IPG_CLK: + return get_ipg_clk(); + case MXC_I2C_CLK: + return pcc_clock_get_rate(PER_CLK_LPI2C4); + case MXC_UART_CLK: + return pcc_clock_get_rate(PER_CLK_LPUART4); + case MXC_ESDHC_CLK: + return pcc_clock_get_rate(PER_CLK_USDHC0); + case MXC_ESDHC2_CLK: + return pcc_clock_get_rate(PER_CLK_USDHC1); + case MXC_DDR_CLK: + return scg_clk_get_rate(SCG_DDR_CLK); + default: + printf("Unsupported mxc_clock %d\n", clk); + break; + } + + return 0; +} + +void init_clk_usdhc(u32 index) +{ + switch (index) { + case 0: + /*Disable the clock before configure it */ + pcc_clock_enable(PER_CLK_USDHC0, false); + + /* 158MHz / 1 = 158MHz */ + pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK); + pcc_clock_div_config(PER_CLK_USDHC0, false, 1); + pcc_clock_enable(PER_CLK_USDHC0, true); + break; + case 1: + /*Disable the clock before configure it */ + pcc_clock_enable(PER_CLK_USDHC1, false); + + /* 158MHz / 1 = 158MHz */ + pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK); + pcc_clock_div_config(PER_CLK_USDHC1, false, 1); + pcc_clock_enable(PER_CLK_USDHC1, true); + break; + default: + printf("Invalid index for USDHC %d\n", index); + break; + } +} + +#ifdef CONFIG_MXC_OCOTP + +#define OCOTP_CTRL_PCC1_SLOT (38) +#define OCOTP_CTRL_HIGH4K_PCC1_SLOT (39) + +void enable_ocotp_clk(unsigned char enable) +{ + u32 val; + + /* + * Seems the OCOTP CLOCKs have been enabled at default, + * check its inuse flag + */ + + val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT); + if (!(val & PCC_INUSE_MASK)) + writel(PCC_CGC_MASK, (PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT)); + + val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT); + if (!(val & PCC_INUSE_MASK)) + writel(PCC_CGC_MASK, + (PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT)); +} +#endif + +void enable_usboh3_clk(unsigned char enable) +{ + if (enable) { + pcc_clock_enable(PER_CLK_USB0, false); + pcc_clock_sel(PER_CLK_USB0, SCG_NIC1_BUS_CLK); + pcc_clock_enable(PER_CLK_USB0, true); + +#ifdef CONFIG_USB_MAX_CONTROLLER_COUNT + if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) { + pcc_clock_enable(PER_CLK_USB1, false); + pcc_clock_sel(PER_CLK_USB1, SCG_NIC1_BUS_CLK); + pcc_clock_enable(PER_CLK_USB1, true); + } +#endif + + pcc_clock_enable(PER_CLK_USB_PHY, true); + pcc_clock_enable(PER_CLK_USB_PL301, true); + } else { + pcc_clock_enable(PER_CLK_USB0, false); + pcc_clock_enable(PER_CLK_USB1, false); + pcc_clock_enable(PER_CLK_USB_PHY, false); + pcc_clock_enable(PER_CLK_USB_PL301, false); + } +} + +static void lpuart_set_clk(uint32_t index, enum scg_clk clk) +{ + const enum pcc_clk lpuart_pcc_clks[] = { + PER_CLK_LPUART4, + PER_CLK_LPUART5, + PER_CLK_LPUART6, + PER_CLK_LPUART7, + }; + + if (index < 4 || index > 7) + return; + +#ifndef CONFIG_CLK_DEBUG + pcc_clock_enable(lpuart_pcc_clks[index - 4], false); +#endif + pcc_clock_sel(lpuart_pcc_clks[index - 4], clk); + pcc_clock_enable(lpuart_pcc_clks[index - 4], true); +} + +static void init_clk_lpuart(void) +{ + u32 index = 0, i; + + const u32 lpuart_array[] = { + LPUART0_RBASE, + LPUART1_RBASE, + LPUART2_RBASE, + LPUART3_RBASE, + LPUART4_RBASE, + LPUART5_RBASE, + LPUART6_RBASE, + LPUART7_RBASE, + }; + + for (i = 0; i < 8; i++) { + if (lpuart_array[i] == LPUART_BASE) { + index = i; + break; + } + } + + lpuart_set_clk(index, SCG_SOSC_DIV2_CLK); +} + +static void init_clk_rgpio2p(void) +{ + /*Enable RGPIO2P1 clock */ + pcc_clock_enable(PER_CLK_RGPIO2P1, true); + + /* + * Hard code to enable RGPIO2P0 clock since it is not + * in clock frame for A7 domain + */ + writel(PCC_CGC_MASK, (PCC0_RBASE + 0x3C)); +} + +/* Configure PLL/PFD freq */ +void clock_init(void) +{ + /* ROM has enabled clocks: + * A4 side: SIRC 16Mhz (DIV1-3 off), FIRC 48Mhz (DIV1-2 on), + * Non-LP-boot: SOSC, SPLL PFD0 (scs selected) + * A7 side: SPLL PFD0 (scs selected, 413Mhz), + * APLL PFD0 (352Mhz), DDRCLK, all NIC clocks + * A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz, + * IP BUS (NIC1_BUS) = 58.6Mhz + * + * In u-boot: + * 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs. + * 2. Enable USB PLL + * 3. Init the clocks of peripherals used in u-boot bu + * without set rate interface.The clocks for these + * peripherals are enabled in this intialization. + * 4.Other peripherals with set clock rate interface + * does not be set in this function. + */ + + scg_a7_firc_init(); + + scg_a7_soscdiv_init(); + + /* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */ + scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35); + scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 20); + scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12); + + init_clk_lpuart(); + + init_clk_rgpio2p(); + + enable_usboh3_clk(1); +} + +/* + * Dump some core clockes. + */ +int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u32 addr = 0; + u32 freq; + freq = decode_pll(PLL_A7_SPLL); + printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000); + + freq = decode_pll(PLL_A7_APLL); + printf("PLL_A7_APLL %8d MHz\n", freq / 1000000); + + freq = decode_pll(PLL_USB); + printf("PLL_USB %8d MHz\n", freq / 1000000); + + printf("\n"); + + printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000); + printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); + printf("UART %8d kHz\n", pcc_clock_get_rate(PER_CLK_LPUART4) / 1000); + printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); + printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); + printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); + printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); + printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); + printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000); + + addr = (u32) clock_init; + printf("[%s] addr = 0x%08X\r\n", __func__, addr); + scg_a7_info(); + + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks, + "display clocks", + "" +); diff --git a/arch/arm/cpu/armv7/mx7ulp/pcc.c b/arch/arm/cpu/armv7/mx7ulp/pcc.c new file mode 100644 index 0000000..edd84e5 --- /dev/null +++ b/arch/arm/cpu/armv7/mx7ulp/pcc.c @@ -0,0 +1,286 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <div64.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/pcc.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define PCC_CLKSRC_TYPES 2 +#define PCC_CLKSRC_NUM 7 + +static enum scg_clk pcc_clksrc[PCC_CLKSRC_TYPES][PCC_CLKSRC_NUM] = { + { SCG_NIC1_BUS_CLK, + SCG_NIC1_CLK, + SCG_DDR_CLK, + SCG_APLL_PFD2_CLK, + SCG_APLL_PFD1_CLK, + SCG_APLL_PFD0_CLK, + USB_PLL_OUT, + }, + { SCG_SOSC_DIV2_CLK, /* SOSC BUS clock */ + MIPI_PLL_OUT, + SCG_FIRC_DIV2_CLK, /* FIRC BUS clock */ + SCG_ROSC_CLK, + SCG_NIC1_BUS_CLK, + SCG_NIC1_CLK, + SCG_APLL_PFD3_CLK, + }, +}; + +static struct pcc_entry pcc_arrays[] = { + {PCC2_RBASE, DMA1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, + {PCC2_RBASE, RGPIO1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, + {PCC2_RBASE, FLEXBUS0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, + {PCC2_RBASE, SEMA42_1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, + {PCC2_RBASE, DMA1_CH_MUX0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, + {PCC2_RBASE, SNVS_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, + {PCC2_RBASE, CAAM_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, + {PCC2_RBASE, LPTPM4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC2_RBASE, LPTPM5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC2_RBASE, LPIT1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC2_RBASE, LPSPI2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC2_RBASE, LPSPI3_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC2_RBASE, LPI2C4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC2_RBASE, LPI2C5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC2_RBASE, LPUART4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC2_RBASE, LPUART5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC2_RBASE, FLEXIO1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC2_RBASE, USBOTG0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV}, + {PCC2_RBASE, USBOTG1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV}, + {PCC2_RBASE, USBPHY_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, + {PCC2_RBASE, USB_PL301_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, + {PCC2_RBASE, USDHC0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV}, + {PCC2_RBASE, USDHC1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV}, + {PCC2_RBASE, WDG1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV}, + {PCC2_RBASE, WDG2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV}, + + {PCC3_RBASE, LPTPM6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC3_RBASE, LPTPM7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC3_RBASE, LPI2C6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC3_RBASE, LPI2C7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC3_RBASE, LPUART6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC3_RBASE, LPUART7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, + {PCC3_RBASE, VIU0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, + {PCC3_RBASE, DSI0_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV}, + {PCC3_RBASE, LCDIF0_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV}, + {PCC3_RBASE, MMDC0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, + {PCC3_RBASE, PORTC_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, + {PCC3_RBASE, PORTD_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, + {PCC3_RBASE, PORTE_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, + {PCC3_RBASE, PORTF_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, + {PCC3_RBASE, GPU3D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV}, + {PCC3_RBASE, GPU2D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV}, +}; + +int pcc_clock_enable(enum pcc_clk clk, bool enable) +{ + u32 reg, val; + + if (clk >= ARRAY_SIZE(pcc_arrays)) + return -EINVAL; + + reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; + + val = readl(reg); + + clk_debug("pcc_clock_enable: clk %d, reg 0x%x, val 0x%x, enable %d\n", + clk, reg, val, enable); + + if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK)) + return -EPERM; + + if (enable) + val |= PCC_CGC_MASK; + else + val &= ~PCC_CGC_MASK; + + writel(val, reg); + + clk_debug("pcc_clock_enable: val 0x%x\n", val); + + return 0; +} + +/* The clock source select needs clock is disabled */ +int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src) +{ + u32 reg, val, i, clksrc_type; + + if (clk >= ARRAY_SIZE(pcc_arrays)) + return -EINVAL; + + clksrc_type = pcc_arrays[clk].clksrc; + if (clksrc_type >= CLKSRC_NO_PCS) { + printf("No PCS field for the PCC %d, clksrc type %d\n", + clk, clksrc_type); + return -EPERM; + } + + for (i = 0; i < PCC_CLKSRC_NUM; i++) { + if (pcc_clksrc[clksrc_type][i] == src) { + /* Find the clock src, then set it to PCS */ + break; + } + } + + if (i == PCC_CLKSRC_NUM) { + printf("Not find the parent scg_clk in PCS of PCC %d, invalid scg_clk %d\n", clk, src); + return -EINVAL; + } + + reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; + + val = readl(reg); + + clk_debug("pcc_clock_sel: clk %d, reg 0x%x, val 0x%x, clksrc_type %d\n", + clk, reg, val, clksrc_type); + + if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) || + (val & PCC_CGC_MASK)) { + printf("Not permit to select clock source val = 0x%x\n", val); + return -EPERM; + } + + val &= ~PCC_PCS_MASK; + val |= ((i + 1) << PCC_PCS_OFFSET); + + writel(val, reg); + + clk_debug("pcc_clock_sel: val 0x%x\n", val); + + return 0; +} + +int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div) +{ + u32 reg, val; + + if (clk >= ARRAY_SIZE(pcc_arrays) || div > 8 || + (div == 1 && frac != 0)) + return -EINVAL; + + if (pcc_arrays[clk].div >= PCC_NO_DIV) { + printf("No DIV/FRAC field for the PCC %d\n", clk); + return -EPERM; + } + + reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; + + val = readl(reg); + + if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) || + (val & PCC_CGC_MASK)) { + printf("Not permit to set div/frac val = 0x%x\n", val); + return -EPERM; + } + + if (frac) + val |= PCC_FRAC_MASK; + else + val &= ~PCC_FRAC_MASK; + + val &= ~PCC_PCD_MASK; + val |= (div - 1) & PCC_PCD_MASK; + + writel(val, reg); + + return 0; +} + +bool pcc_clock_is_enable(enum pcc_clk clk) +{ + u32 reg, val; + + if (clk >= ARRAY_SIZE(pcc_arrays)) + return -EINVAL; + + reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; + val = readl(reg); + + if ((val & PCC_INUSE_MASK) || (val & PCC_CGC_MASK)) + return true; + + return false; +} + +int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src) +{ + u32 reg, val, clksrc_type; + + if (clk >= ARRAY_SIZE(pcc_arrays)) + return -EINVAL; + + clksrc_type = pcc_arrays[clk].clksrc; + if (clksrc_type >= CLKSRC_NO_PCS) { + printf("No PCS field for the PCC %d, clksrc type %d\n", + clk, clksrc_type); + return -EPERM; + } + + reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; + + val = readl(reg); + + clk_debug("pcc_clock_get_clksrc: clk %d, reg 0x%x, val 0x%x, type %d\n", + clk, reg, val, clksrc_type); + + if (!(val & PCC_PR_MASK)) { + printf("This pcc slot is not present = 0x%x\n", val); + return -EPERM; + } + + val &= PCC_PCS_MASK; + val = (val >> PCC_PCS_OFFSET); + + if (!val) { + printf("Clock source is off\n"); + return -EIO; + } + + *src = pcc_clksrc[clksrc_type][val - 1]; + + clk_debug("pcc_clock_get_clksrc: parent scg clk %d\n", *src); + + return 0; +} + +u32 pcc_clock_get_rate(enum pcc_clk clk) +{ + u32 reg, val, rate, frac, div; + enum scg_clk parent; + int ret; + + ret = pcc_clock_get_clksrc(clk, &parent); + if (ret) + return 0; + + rate = scg_clk_get_rate(parent); + + clk_debug("pcc_clock_get_rate: parent rate %u\n", rate); + + if (pcc_arrays[clk].div == PCC_HAS_DIV) { + reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; + val = readl(reg); + + frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET; + div = (val & PCC_PCD_MASK) >> PCC_PCD_OFFSET; + + /* + * Theoretically don't have overflow in the calc, + * the rate won't exceed 2G + */ + rate = rate * (frac + 1) / (div + 1); + } + + clk_debug("pcc_clock_get_rate: rate %u\n", rate); + return rate; +} diff --git a/arch/arm/cpu/armv7/mx7ulp/scg.c b/arch/arm/cpu/armv7/mx7ulp/scg.c new file mode 100644 index 0000000..7bbde58 --- /dev/null +++ b/arch/arm/cpu/armv7/mx7ulp/scg.c @@ -0,0 +1,1086 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <div64.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/pcc.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +scg_p scg1_regs = (scg_p)SCG1_RBASE; + +static u32 scg_src_get_rate(enum scg_clk clksrc) +{ + u32 reg; + + switch (clksrc) { + case SCG_SOSC_CLK: + reg = readl(&scg1_regs->sosccsr); + if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK)) + return 0; + + return 24000000; + case SCG_FIRC_CLK: + reg = readl(&scg1_regs->firccsr); + if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK)) + return 0; + + return 48000000; + case SCG_SIRC_CLK: + reg = readl(&scg1_regs->sirccsr); + if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK)) + return 0; + + return 16000000; + case SCG_ROSC_CLK: + reg = readl(&scg1_regs->rtccsr); + if (!(reg & SCG_ROSC_CSR_ROSCVLD_MASK)) + return 0; + + return 32768; + default: + break; + } + + return 0; +} + +static u32 scg_sircdiv_get_rate(enum scg_clk clk) +{ + u32 reg, val, rate; + u32 shift, mask; + + switch (clk) { + case SCG_SIRC_DIV1_CLK: + mask = SCG_SIRCDIV_DIV1_MASK; + shift = SCG_SIRCDIV_DIV1_SHIFT; + break; + case SCG_SIRC_DIV2_CLK: + mask = SCG_SIRCDIV_DIV2_MASK; + shift = SCG_SIRCDIV_DIV2_SHIFT; + break; + case SCG_SIRC_DIV3_CLK: + mask = SCG_SIRCDIV_DIV3_MASK; + shift = SCG_SIRCDIV_DIV3_SHIFT; + break; + default: + return 0; + } + + reg = readl(&scg1_regs->sirccsr); + if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK)) + return 0; + + reg = readl(&scg1_regs->sircdiv); + val = (reg & mask) >> shift; + + if (!val) /*clock disabled*/ + return 0; + + rate = scg_src_get_rate(SCG_SIRC_CLK); + rate = rate / (1 << (val - 1)); + + return rate; +} + +static u32 scg_fircdiv_get_rate(enum scg_clk clk) +{ + u32 reg, val, rate; + u32 shift, mask; + + switch (clk) { + case SCG_FIRC_DIV1_CLK: + mask = SCG_FIRCDIV_DIV1_MASK; + shift = SCG_FIRCDIV_DIV1_SHIFT; + break; + case SCG_FIRC_DIV2_CLK: + mask = SCG_FIRCDIV_DIV2_MASK; + shift = SCG_FIRCDIV_DIV2_SHIFT; + break; + case SCG_FIRC_DIV3_CLK: + mask = SCG_FIRCDIV_DIV3_MASK; + shift = SCG_FIRCDIV_DIV3_SHIFT; + break; + default: + return 0; + } + + reg = readl(&scg1_regs->firccsr); + if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK)) + return 0; + + reg = readl(&scg1_regs->fircdiv); + val = (reg & mask) >> shift; + + if (!val) /*clock disabled*/ + return 0; + + rate = scg_src_get_rate(SCG_FIRC_CLK); + rate = rate / (1 << (val - 1)); + + return rate; +} + +static u32 scg_soscdiv_get_rate(enum scg_clk clk) +{ + u32 reg, val, rate; + u32 shift, mask; + + switch (clk) { + case SCG_SOSC_DIV1_CLK: + mask = SCG_SOSCDIV_DIV1_MASK; + shift = SCG_SOSCDIV_DIV1_SHIFT; + break; + case SCG_SOSC_DIV2_CLK: + mask = SCG_SOSCDIV_DIV2_MASK; + shift = SCG_SOSCDIV_DIV2_SHIFT; + break; + case SCG_SOSC_DIV3_CLK: + mask = SCG_SOSCDIV_DIV3_MASK; + shift = SCG_SOSCDIV_DIV3_SHIFT; + break; + default: + return 0; + } + + reg = readl(&scg1_regs->sosccsr); + if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK)) + return 0; + + reg = readl(&scg1_regs->soscdiv); + val = (reg & mask) >> shift; + + if (!val) /*clock disabled*/ + return 0; + + rate = scg_src_get_rate(SCG_SOSC_CLK); + rate = rate / (1 << (val - 1)); + + return rate; +} + +static u32 scg_apll_pfd_get_rate(enum scg_clk clk) +{ + u32 reg, val, rate; + u32 shift, mask, gate, valid; + + switch (clk) { + case SCG_APLL_PFD0_CLK: + gate = SCG_PLL_PFD0_GATE_MASK; + valid = SCG_PLL_PFD0_VALID_MASK; + mask = SCG_PLL_PFD0_FRAC_MASK; + shift = SCG_PLL_PFD0_FRAC_SHIFT; + break; + case SCG_APLL_PFD1_CLK: + gate = SCG_PLL_PFD1_GATE_MASK; + valid = SCG_PLL_PFD1_VALID_MASK; + mask = SCG_PLL_PFD1_FRAC_MASK; + shift = SCG_PLL_PFD1_FRAC_SHIFT; + break; + case SCG_APLL_PFD2_CLK: + gate = SCG_PLL_PFD2_GATE_MASK; + valid = SCG_PLL_PFD2_VALID_MASK; + mask = SCG_PLL_PFD2_FRAC_MASK; + shift = SCG_PLL_PFD2_FRAC_SHIFT; + break; + case SCG_APLL_PFD3_CLK: + gate = SCG_PLL_PFD3_GATE_MASK; + valid = SCG_PLL_PFD3_VALID_MASK; + mask = SCG_PLL_PFD3_FRAC_MASK; + shift = SCG_PLL_PFD3_FRAC_SHIFT; + break; + default: + return 0; + } + + reg = readl(&scg1_regs->apllpfd); + if (reg & gate || !(reg & valid)) + return 0; + + clk_debug("scg_apll_pfd_get_rate reg 0x%x\n", reg); + + val = (reg & mask) >> shift; + rate = decode_pll(PLL_A7_APLL); + + rate = rate / val * 18; + + clk_debug("scg_apll_pfd_get_rate rate %u\n", rate); + + return rate; +} + +static u32 scg_spll_pfd_get_rate(enum scg_clk clk) +{ + u32 reg, val, rate; + u32 shift, mask, gate, valid; + + switch (clk) { + case SCG_SPLL_PFD0_CLK: + gate = SCG_PLL_PFD0_GATE_MASK; + valid = SCG_PLL_PFD0_VALID_MASK; + mask = SCG_PLL_PFD0_FRAC_MASK; + shift = SCG_PLL_PFD0_FRAC_SHIFT; + break; + case SCG_SPLL_PFD1_CLK: + gate = SCG_PLL_PFD1_GATE_MASK; + valid = SCG_PLL_PFD1_VALID_MASK; + mask = SCG_PLL_PFD1_FRAC_MASK; + shift = SCG_PLL_PFD1_FRAC_SHIFT; + break; + case SCG_SPLL_PFD2_CLK: + gate = SCG_PLL_PFD2_GATE_MASK; + valid = SCG_PLL_PFD2_VALID_MASK; + mask = SCG_PLL_PFD2_FRAC_MASK; + shift = SCG_PLL_PFD2_FRAC_SHIFT; + break; + case SCG_SPLL_PFD3_CLK: + gate = SCG_PLL_PFD3_GATE_MASK; + valid = SCG_PLL_PFD3_VALID_MASK; + mask = SCG_PLL_PFD3_FRAC_MASK; + shift = SCG_PLL_PFD3_FRAC_SHIFT; + break; + default: + return 0; + } + + reg = readl(&scg1_regs->spllpfd); + if (reg & gate || !(reg & valid)) + return 0; + + clk_debug("scg_spll_pfd_get_rate reg 0x%x\n", reg); + + val = (reg & mask) >> shift; + rate = decode_pll(PLL_A7_SPLL); + + rate = rate / val * 18; + + clk_debug("scg_spll_pfd_get_rate rate %u\n", rate); + + return rate; +} + +static u32 scg_apll_get_rate(void) +{ + u32 reg, val, rate; + + reg = readl(&scg1_regs->apllcfg); + val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT; + + if (!val) { + /* APLL clock after two dividers */ + rate = decode_pll(PLL_A7_APLL); + + val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >> + SCG_PLL_CFG_POSTDIV1_SHIFT; + rate = rate / (val + 1); + + val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >> + SCG_PLL_CFG_POSTDIV2_SHIFT; + rate = rate / (val + 1); + } else { + /* APLL PFD clock */ + val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >> + SCG_PLL_CFG_PFDSEL_SHIFT; + rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val); + } + + return rate; +} + +static u32 scg_spll_get_rate(void) +{ + u32 reg, val, rate; + + reg = readl(&scg1_regs->spllcfg); + val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT; + + clk_debug("scg_spll_get_rate reg 0x%x\n", reg); + + if (!val) { + /* APLL clock after two dividers */ + rate = decode_pll(PLL_A7_SPLL); + + val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >> + SCG_PLL_CFG_POSTDIV1_SHIFT; + rate = rate / (val + 1); + + val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >> + SCG_PLL_CFG_POSTDIV2_SHIFT; + rate = rate / (val + 1); + + clk_debug("scg_spll_get_rate SPLL %u\n", rate); + + } else { + /* APLL PFD clock */ + val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >> + SCG_PLL_CFG_PFDSEL_SHIFT; + rate = scg_spll_pfd_get_rate(SCG_SPLL_PFD0_CLK + val); + + clk_debug("scg_spll_get_rate PFD %u\n", rate); + } + + return rate; +} + +static u32 scg_ddr_get_rate(void) +{ + u32 reg, val, rate, div; + + reg = readl(&scg1_regs->ddrccr); + val = (reg & SCG_DDRCCR_DDRCS_MASK) >> SCG_DDRCCR_DDRCS_SHIFT; + div = (reg & SCG_DDRCCR_DDRDIV_MASK) >> SCG_DDRCCR_DDRDIV_SHIFT; + + if (!div) + return 0; + + if (!val) { + reg = readl(&scg1_regs->apllcfg); + val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >> + SCG_PLL_CFG_PFDSEL_SHIFT; + rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val); + } else { + rate = decode_pll(PLL_USB); + } + + rate = rate / (1 << (div - 1)); + return rate; +} + +static u32 scg_nic_get_rate(enum scg_clk clk) +{ + u32 reg, val, rate; + u32 shift, mask; + + reg = readl(&scg1_regs->niccsr); + val = (reg & SCG_NICCSR_NICCS_MASK) >> SCG_NICCSR_NICCS_SHIFT; + + clk_debug("scg_nic_get_rate niccsr 0x%x\n", reg); + + if (!val) + rate = scg_src_get_rate(SCG_FIRC_CLK); + else + rate = scg_ddr_get_rate(); + + clk_debug("scg_nic_get_rate parent rate %u\n", rate); + + val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT; + + rate = rate / (val + 1); + + clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate); + + switch (clk) { + case SCG_NIC0_CLK: + return rate; + case SCG_GPU_CLK: + mask = SCG_NICCSR_GPUDIV_MASK; + shift = SCG_NICCSR_GPUDIV_SHIFT; + break; + case SCG_NIC1_EXT_CLK: + case SCG_NIC1_BUS_CLK: + case SCG_NIC1_CLK: + mask = SCG_NICCSR_NIC1DIV_MASK; + shift = SCG_NICCSR_NIC1DIV_SHIFT; + break; + default: + return 0; + } + + val = (reg & mask) >> shift; + rate = rate / (val + 1); + + clk_debug("scg_nic_get_rate NIC1 rate %u\n", rate); + + switch (clk) { + case SCG_GPU_CLK: + case SCG_NIC1_CLK: + return rate; + case SCG_NIC1_EXT_CLK: + mask = SCG_NICCSR_NIC1EXTDIV_MASK; + shift = SCG_NICCSR_NIC1EXTDIV_SHIFT; + break; + case SCG_NIC1_BUS_CLK: + mask = SCG_NICCSR_NIC1BUSDIV_MASK; + shift = SCG_NICCSR_NIC1BUSDIV_SHIFT; + break; + default: + return 0; + } + + val = (reg & mask) >> shift; + rate = rate / (val + 1); + + clk_debug("scg_nic_get_rate NIC1 bus rate %u\n", rate); + return rate; +} + + +static enum scg_clk scg_scs_array[4] = { + SCG_SOSC_CLK, SCG_SIRC_CLK, SCG_FIRC_CLK, SCG_ROSC_CLK, +}; + +static u32 scg_sys_get_rate(enum scg_clk clk) +{ + u32 reg, val, rate; + + if (clk != SCG_CORE_CLK && clk != SCG_BUS_CLK) + return 0; + + reg = readl(&scg1_regs->csr); + val = (reg & SCG_CCR_SCS_MASK) >> SCG_CCR_SCS_SHIFT; + + clk_debug("scg_sys_get_rate reg 0x%x\n", reg); + + switch (val) { + case SCG_SCS_SYS_OSC: + case SCG_SCS_SLOW_IRC: + case SCG_SCS_FAST_IRC: + case SCG_SCS_RTC_OSC: + rate = scg_src_get_rate(scg_scs_array[val]); + break; + case 5: + rate = scg_apll_get_rate(); + break; + case 6: + rate = scg_spll_get_rate(); + break; + default: + return 0; + } + + clk_debug("scg_sys_get_rate parent rate %u\n", rate); + + val = (reg & SCG_CCR_DIVCORE_MASK) >> SCG_CCR_DIVCORE_SHIFT; + + rate = rate / (val + 1); + + if (clk == SCG_BUS_CLK) { + val = (reg & SCG_CCR_DIVBUS_MASK) >> SCG_CCR_DIVBUS_SHIFT; + rate = rate / (val + 1); + } + + return rate; +} + +u32 decode_pll(enum pll_clocks pll) +{ + u32 reg, pre_div, infreq, mult; + u32 num, denom; + + /* + * Alought there are four choices for the bypass src, + * we choose OSC_24M which is the default set in ROM. + */ + switch (pll) { + case PLL_A7_SPLL: + reg = readl(&scg1_regs->spllcsr); + + if (!(reg & SCG_SPLL_CSR_SPLLVLD_MASK)) + return 0; + + reg = readl(&scg1_regs->spllcfg); + + pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >> + SCG_PLL_CFG_PREDIV_SHIFT; + pre_div += 1; + + mult = (reg & SCG1_SPLL_CFG_MULT_MASK) >> + SCG_PLL_CFG_MULT_SHIFT; + + infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >> + SCG_PLL_CFG_CLKSRC_SHIFT; + if (!infreq) + infreq = scg_src_get_rate(SCG_SOSC_CLK); + else + infreq = scg_src_get_rate(SCG_FIRC_CLK); + + num = readl(&scg1_regs->spllnum); + denom = readl(&scg1_regs->splldenom); + + return (infreq / pre_div) * (mult + num / denom); + + case PLL_A7_APLL: + reg = readl(&scg1_regs->apllcsr); + + if (!(reg & SCG_APLL_CSR_APLLVLD_MASK)) + return 0; + + reg = readl(&scg1_regs->apllcfg); + + pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >> + SCG_PLL_CFG_PREDIV_SHIFT; + pre_div += 1; + + mult = (reg & SCG_APLL_CFG_MULT_MASK) >> + SCG_PLL_CFG_MULT_SHIFT; + + infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >> + SCG_PLL_CFG_CLKSRC_SHIFT; + if (!infreq) + infreq = scg_src_get_rate(SCG_SOSC_CLK); + else + infreq = scg_src_get_rate(SCG_FIRC_CLK); + + num = readl(&scg1_regs->apllnum); + denom = readl(&scg1_regs->aplldenom); + + return (infreq / pre_div) * (mult + num / denom); + + case PLL_USB: + reg = readl(&scg1_regs->upllcsr); + + if (!(reg & SCG_UPLL_CSR_UPLLVLD_MASK)) + return 0; + + return 480000000u; + + case PLL_MIPI: + return 480000000u; + default: + printf("Unsupported pll clocks %d\n", pll); + break; + } + + return 0; +} + +u32 scg_clk_get_rate(enum scg_clk clk) +{ + switch (clk) { + case SCG_SIRC_DIV1_CLK: + case SCG_SIRC_DIV2_CLK: + case SCG_SIRC_DIV3_CLK: + return scg_sircdiv_get_rate(clk); + + case SCG_FIRC_DIV1_CLK: + case SCG_FIRC_DIV2_CLK: + case SCG_FIRC_DIV3_CLK: + return scg_fircdiv_get_rate(clk); + + case SCG_SOSC_DIV1_CLK: + case SCG_SOSC_DIV2_CLK: + case SCG_SOSC_DIV3_CLK: + return scg_soscdiv_get_rate(clk); + + case SCG_CORE_CLK: + case SCG_BUS_CLK: + return scg_sys_get_rate(clk); + + case SCG_SPLL_PFD0_CLK: + case SCG_SPLL_PFD1_CLK: + case SCG_SPLL_PFD2_CLK: + case SCG_SPLL_PFD3_CLK: + return scg_spll_pfd_get_rate(clk); + + case SCG_APLL_PFD0_CLK: + case SCG_APLL_PFD1_CLK: + case SCG_APLL_PFD2_CLK: + case SCG_APLL_PFD3_CLK: + return scg_apll_pfd_get_rate(clk); + + case SCG_DDR_CLK: + return scg_ddr_get_rate(); + + case SCG_NIC0_CLK: + case SCG_GPU_CLK: + case SCG_NIC1_CLK: + case SCG_NIC1_BUS_CLK: + case SCG_NIC1_EXT_CLK: + return scg_nic_get_rate(clk); + + case USB_PLL_OUT: + return decode_pll(PLL_USB); + + case MIPI_PLL_OUT: + return decode_pll(PLL_MIPI); + + case SCG_SOSC_CLK: + case SCG_FIRC_CLK: + case SCG_SIRC_CLK: + case SCG_ROSC_CLK: + return scg_src_get_rate(clk); + default: + return 0; + } +} + +int scg_enable_pll_pfd(enum scg_clk clk, u32 frac) +{ + u32 reg; + u32 shift, mask, gate, valid; + u32 addr; + + if (frac < 12 || frac > 35) + return -EINVAL; + + switch (clk) { + case SCG_SPLL_PFD0_CLK: + case SCG_APLL_PFD0_CLK: + gate = SCG_PLL_PFD0_GATE_MASK; + valid = SCG_PLL_PFD0_VALID_MASK; + mask = SCG_PLL_PFD0_FRAC_MASK; + shift = SCG_PLL_PFD0_FRAC_SHIFT; + + if (clk == SCG_SPLL_PFD0_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + case SCG_SPLL_PFD1_CLK: + case SCG_APLL_PFD1_CLK: + gate = SCG_PLL_PFD1_GATE_MASK; + valid = SCG_PLL_PFD1_VALID_MASK; + mask = SCG_PLL_PFD1_FRAC_MASK; + shift = SCG_PLL_PFD1_FRAC_SHIFT; + + if (clk == SCG_SPLL_PFD1_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + case SCG_SPLL_PFD2_CLK: + case SCG_APLL_PFD2_CLK: + gate = SCG_PLL_PFD2_GATE_MASK; + valid = SCG_PLL_PFD2_VALID_MASK; + mask = SCG_PLL_PFD2_FRAC_MASK; + shift = SCG_PLL_PFD2_FRAC_SHIFT; + + if (clk == SCG_SPLL_PFD2_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + case SCG_SPLL_PFD3_CLK: + case SCG_APLL_PFD3_CLK: + gate = SCG_PLL_PFD3_GATE_MASK; + valid = SCG_PLL_PFD3_VALID_MASK; + mask = SCG_PLL_PFD3_FRAC_MASK; + shift = SCG_PLL_PFD3_FRAC_SHIFT; + + if (clk == SCG_SPLL_PFD3_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + default: + return -EINVAL; + } + + /* Gate the PFD */ + reg = readl(addr); + reg |= gate; + writel(reg, addr); + + /* Write Frac divider */ + reg &= ~mask; + reg |= (frac << shift) & mask; + writel(reg, addr); + + /* + * Un-gate the PFD + * (Need un-gate before checking valid, not align with RM) + */ + reg &= ~gate; + writel(reg, addr); + + /* Wait for PFD clock being valid */ + do { + reg = readl(addr); + } while (!(reg & valid)); + + return 0; +} + +#define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2) +int scg_enable_usb_pll(bool usb_control) +{ + u32 sosc_rate; + s32 timeout = 1000000; + u32 reg; + + struct usbphy_regs *usbphy = + (struct usbphy_regs *)USBPHY_RBASE; + + sosc_rate = scg_src_get_rate(SCG_SOSC_CLK); + if (!sosc_rate) + return -EPERM; + + reg = readl(SIM0_RBASE + 0x3C); + if (usb_control) + reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK; + else + reg |= SIM_MISC_CTRL0_USB_PLL_EN_MASK; + writel(reg, SIM0_RBASE + 0x3C); + + if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) { + writel(0x1c00000, &usbphy->usb1_pll_480_ctrl_clr); + + switch (sosc_rate) { + case 24000000: + writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set); + break; + + case 30000000: + writel(0x800000, &usbphy->usb1_pll_480_ctrl_set); + break; + + case 19200000: + writel(0x1400000, &usbphy->usb1_pll_480_ctrl_set); + break; + + default: + writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set); + break; + } + + /* Enable the regulator first */ + writel(PLL_USB_REG_ENABLE_MASK, + &usbphy->usb1_pll_480_ctrl_set); + + /* Wait at least 15us */ + udelay(15); + + /* Enable the power */ + writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set); + + /* Wait lock */ + while (timeout--) { + if (readl(&usbphy->usb1_pll_480_ctrl) & + PLL_USB_LOCK_MASK) + break; + } + + if (timeout <= 0) { + /* If timeout, we power down the pll */ + writel(PLL_USB_PWR_MASK, + &usbphy->usb1_pll_480_ctrl_clr); + return -ETIME; + } + } + + /* Clear the bypass */ + writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr); + + /* Enable the PLL clock out to USB */ + writel((PLL_USB_EN_USB_CLKS_MASK | PLL_USB_ENABLE_MASK), + &usbphy->usb1_pll_480_ctrl_set); + + if (!usb_control) { + while (timeout--) { + if (readl(&scg1_regs->upllcsr) & + SCG_UPLL_CSR_UPLLVLD_MASK) + break; + } + + if (timeout <= 0) { + reg = readl(SIM0_RBASE + 0x3C); + reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK; + writel(reg, SIM0_RBASE + 0x3C); + return -ETIME; + } + } + + return 0; +} + + +/* A7 domain system clock source is SPLL */ +#define SCG1_RCCR_SCS_NUM ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT) + +/* A7 Core clck = SPLL PFD0 / 1 = 500MHz / 1 = 500MHz */ +#define SCG1_RCCR_DIVCORE_NUM ((0x0) << SCG_CCR_DIVCORE_SHIFT) +#define SCG1_RCCR_CFG_MASK (SCG_CCR_SCS_MASK | SCG_CCR_DIVBUS_MASK) + +/* A7 Plat clck = A7 Core Clock / 2 = 250MHz / 1 = 250MHz */ +#define SCG1_RCCR_DIVBUS_NUM ((0x1) << SCG_CCR_DIVBUS_SHIFT) +#define SCG1_RCCR_CFG_NUM (SCG1_RCCR_SCS_NUM | SCG1_RCCR_DIVBUS_NUM) + +void scg_a7_rccr_init(void) +{ + u32 rccr_reg_val = 0; + + rccr_reg_val = readl(&scg1_regs->rccr); + + rccr_reg_val &= (~SCG1_RCCR_CFG_MASK); + rccr_reg_val |= (SCG1_RCCR_CFG_NUM); + + writel(rccr_reg_val, &scg1_regs->rccr); +} + +/* POSTDIV2 = 1 */ +#define SCG1_SPLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT) +/* POSTDIV1 = 1 */ +#define SCG1_SPLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT) + +/* MULT = 22 */ +#define SCG1_SPLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT) + +/* PFD0 output clock selected */ +#define SCG1_SPLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT) +/* PREDIV = 1 */ +#define SCG1_SPLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT) +/* SPLL output clocks (including PFD outputs) selected */ +#define SCG1_SPLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT) +/* SPLL PFD output clock selected */ +#define SCG1_SPLL_CFG_PLLSEL_NUM ((0x1) << SCG_PLL_CFG_PLLSEL_SHIFT) +/* Clock source is System OSC */ +#define SCG1_SPLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT) +#define SCG1_SPLL_CFG_NUM_24M_OSC (SCG1_SPLL_CFG_POSTDIV2_NUM | \ + SCG1_SPLL_CFG_POSTDIV1_NUM | \ + (22 << SCG_PLL_CFG_MULT_SHIFT) | \ + SCG1_SPLL_CFG_PFDSEL_NUM | \ + SCG1_SPLL_CFG_PREDIV_NUM | \ + SCG1_SPLL_CFG_BYPASS_NUM | \ + SCG1_SPLL_CFG_PLLSEL_NUM | \ + SCG1_SPLL_CFG_CLKSRC_NUM) +/*413Mhz = A7 SPLL(528MHz) * 18/23 */ +#define SCG1_SPLL_PFD0_FRAC_NUM ((23) << SCG_PLL_PFD0_FRAC_SHIFT) + +void scg_a7_spll_init(void) +{ + u32 val = 0; + + /* Disable A7 System PLL */ + val = readl(&scg1_regs->spllcsr); + val &= ~SCG_SPLL_CSR_SPLLEN_MASK; + writel(val, &scg1_regs->spllcsr); + + /* + * Per block guide, + * "When changing PFD values, it is recommneded PFDx clock + * gets gated first by writing a value of 1 to PFDx_CLKGATE register, + * then program the new PFD value, then poll the PFDx_VALID + * flag to set before writing a value of 0 to PFDx_CLKGATE + * to ungate the PFDx clock and allow PFDx clock to run" + */ + + /* Gate off A7 SPLL PFD0 ~ PDF4 */ + val = readl(&scg1_regs->spllpfd); + val |= (SCG_PLL_PFD3_GATE_MASK | + SCG_PLL_PFD2_GATE_MASK | + SCG_PLL_PFD1_GATE_MASK | + SCG_PLL_PFD0_GATE_MASK); + writel(val, &scg1_regs->spllpfd); + + /* ================ A7 SPLL Configuration Start ============== */ + + /* Configure A7 System PLL */ + writel(SCG1_SPLL_CFG_NUM_24M_OSC, &scg1_regs->spllcfg); + + /* Enable A7 System PLL */ + val = readl(&scg1_regs->spllcsr); + val |= SCG_SPLL_CSR_SPLLEN_MASK; + writel(val, &scg1_regs->spllcsr); + + /* Wait for A7 SPLL clock ready */ + while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK)) + ; + + /* Configure A7 SPLL PFD0 */ + val = readl(&scg1_regs->spllpfd); + val &= ~SCG_PLL_PFD0_FRAC_MASK; + val |= SCG1_SPLL_PFD0_FRAC_NUM; + writel(val, &scg1_regs->spllpfd); + + /* Un-gate A7 SPLL PFD0 */ + val = readl(&scg1_regs->spllpfd); + val &= ~SCG_PLL_PFD0_GATE_MASK; + writel(val, &scg1_regs->spllpfd); + + /* Wait for A7 SPLL PFD0 clock being valid */ + while (!(readl(&scg1_regs->spllpfd) & SCG_PLL_PFD0_VALID_MASK)) + ; + + /* ================ A7 SPLL Configuration End ============== */ +} + +/* DDR clock source is APLL PFD0 (396MHz) */ +#define SCG1_DDRCCR_DDRCS_NUM ((0x0) << SCG_DDRCCR_DDRCS_SHIFT) +/* DDR clock = APLL PFD0 / 1 = 396MHz / 1 = 396MHz */ +#define SCG1_DDRCCR_DDRDIV_NUM ((0x1) << SCG_DDRCCR_DDRDIV_SHIFT) +/* DDR clock = APLL PFD0 / 2 = 396MHz / 2 = 198MHz */ +#define SCG1_DDRCCR_DDRDIV_LF_NUM ((0x2) << SCG_DDRCCR_DDRDIV_SHIFT) +#define SCG1_DDRCCR_CFG_NUM (SCG1_DDRCCR_DDRCS_NUM | \ + SCG1_DDRCCR_DDRDIV_NUM) +#define SCG1_DDRCCR_CFG_LF_NUM (SCG1_DDRCCR_DDRCS_NUM | \ + SCG1_DDRCCR_DDRDIV_LF_NUM) +void scg_a7_ddrclk_init(void) +{ + writel(SCG1_DDRCCR_CFG_NUM, &scg1_regs->ddrccr); +} + +/* SCG1(A7) APLLCFG configurations */ +/* divide by 1 <<28 */ +#define SCG1_APLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT) +/* divide by 1 <<24 */ +#define SCG1_APLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT) +/* MULT is 22 <<16 */ +#define SCG1_APLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT) +/* PFD0 output clock selected <<14 */ +#define SCG1_APLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT) +/* PREDIV = 1 <<8 */ +#define SCG1_APLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT) +/* APLL output clocks (including PFD outputs) selected <<2 */ +#define SCG1_APLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT) +/* APLL PFD output clock selected <<1 */ +#define SCG1_APLL_CFG_PLLSEL_NUM ((0x0) << SCG_PLL_CFG_PLLSEL_SHIFT) +/* Clock source is System OSC <<0 */ +#define SCG1_APLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT) + +/* + * A7 APLL = 24MHz / 1 * 22 / 1 / 1 = 528MHz, + * system PLL is sourced from APLL, + * APLL clock source is system OSC (24MHz) + */ +#define SCG1_APLL_CFG_NUM_24M_OSC (SCG1_APLL_CFG_POSTDIV2_NUM | \ + SCG1_APLL_CFG_POSTDIV1_NUM | \ + (22 << SCG_PLL_CFG_MULT_SHIFT) | \ + SCG1_APLL_CFG_PFDSEL_NUM | \ + SCG1_APLL_CFG_PREDIV_NUM | \ + SCG1_APLL_CFG_BYPASS_NUM | \ + SCG1_APLL_CFG_PLLSEL_NUM | \ + SCG1_APLL_CFG_CLKSRC_NUM) + +/* PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz */ +#define SCG1_APLL_PFD0_FRAC_NUM (27) + + +void scg_a7_apll_init(void) +{ + u32 val = 0; + + /* Disable A7 Auxiliary PLL */ + val = readl(&scg1_regs->apllcsr); + val &= ~SCG_APLL_CSR_APLLEN_MASK; + writel(val, &scg1_regs->apllcsr); + + /* Gate off A7 APLL PFD0 ~ PDF4 */ + val = readl(&scg1_regs->apllpfd); + val |= 0x80808080; + writel(val, &scg1_regs->apllpfd); + + /* ================ A7 APLL Configuration Start ============== */ + /* Configure A7 Auxiliary PLL */ + writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg); + + /* Enable A7 Auxiliary PLL */ + val = readl(&scg1_regs->apllcsr); + val |= SCG_APLL_CSR_APLLEN_MASK; + writel(val, &scg1_regs->apllcsr); + + /* Wait for A7 APLL clock ready */ + while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK)) + ; + + /* Configure A7 APLL PFD0 */ + val = readl(&scg1_regs->apllpfd); + val &= ~SCG_PLL_PFD0_FRAC_MASK; + val |= SCG1_APLL_PFD0_FRAC_NUM; + writel(val, &scg1_regs->apllpfd); + + /* Un-gate A7 APLL PFD0 */ + val = readl(&scg1_regs->apllpfd); + val &= ~SCG_PLL_PFD0_GATE_MASK; + writel(val, &scg1_regs->apllpfd); + + /* Wait for A7 APLL PFD0 clock being valid */ + while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK)) + ; +} + +/* SCG1(A7) FIRC DIV configurations */ +/* Disable FIRC DIV3 */ +#define SCG1_FIRCDIV_DIV3_NUM ((0x0) << SCG_FIRCDIV_DIV3_SHIFT) +/* FIRC DIV2 = 48MHz / 1 = 48MHz */ +#define SCG1_FIRCDIV_DIV2_NUM ((0x1) << SCG_FIRCDIV_DIV2_SHIFT) +/* Disable FIRC DIV1 */ +#define SCG1_FIRCDIV_DIV1_NUM ((0x0) << SCG_FIRCDIV_DIV1_SHIFT) + +void scg_a7_firc_init(void) +{ + /* Wait for FIRC clock ready */ + while (!(readl(&scg1_regs->firccsr) & SCG_FIRC_CSR_FIRCVLD_MASK)) + ; + + /* Configure A7 FIRC DIV1 ~ DIV3 */ + writel((SCG1_FIRCDIV_DIV3_NUM | + SCG1_FIRCDIV_DIV2_NUM | + SCG1_FIRCDIV_DIV1_NUM), &scg1_regs->fircdiv); +} + +/* SCG1(A7) NICCCR configurations */ +/* NIC clock source is DDR clock (396/198MHz) */ +#define SCG1_NICCCR_NICCS_NUM ((0x1) << SCG_NICCCR_NICCS_SHIFT) + +/* NIC0 clock = DDR Clock / 2 = 396MHz / 2 = 198MHz */ +#define SCG1_NICCCR_NIC0_DIV_NUM ((0x1) << SCG_NICCCR_NIC0_DIV_SHIFT) +/* NIC0 clock = DDR Clock / 1 = 198MHz / 1 = 198MHz */ +#define SCG1_NICCCR_NIC0_DIV_LF_NUM ((0x0) << SCG_NICCCR_NIC0_DIV_SHIFT) +/* NIC1 clock = NIC0 Clock / 1 = 198MHz / 2 = 198MHz */ +#define SCG1_NICCCR_NIC1_DIV_NUM ((0x0) << SCG_NICCCR_NIC1_DIV_SHIFT) +/* NIC1 bus clock = NIC1 Clock / 3 = 198MHz / 3 = 66MHz */ +#define SCG1_NICCCR_NIC1_DIVBUS_NUM ((0x2) << SCG_NICCCR_NIC1_DIVBUS_SHIFT) +#define SCG1_NICCCR_CFG_NUM (SCG1_NICCCR_NICCS_NUM | \ + SCG1_NICCCR_NIC0_DIV_NUM | \ + SCG1_NICCCR_NIC1_DIV_NUM | \ + SCG1_NICCCR_NIC1_DIVBUS_NUM) + +void scg_a7_nicclk_init(void) +{ + writel(SCG1_NICCCR_CFG_NUM, &scg1_regs->nicccr); +} + +/* SCG1(A7) FIRC DIV configurations */ +/* Enable FIRC DIV3 */ +#define SCG1_SOSCDIV_DIV3_NUM ((0x1) << SCG_SOSCDIV_DIV3_SHIFT) +/* FIRC DIV2 = 48MHz / 1 = 48MHz */ +#define SCG1_SOSCDIV_DIV2_NUM ((0x1) << SCG_SOSCDIV_DIV2_SHIFT) +/* Enable FIRC DIV1 */ +#define SCG1_SOSCDIV_DIV1_NUM ((0x1) << SCG_SOSCDIV_DIV1_SHIFT) + +void scg_a7_soscdiv_init(void) +{ + /* Wait for FIRC clock ready */ + while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK)) + ; + + /* Configure A7 FIRC DIV1 ~ DIV3 */ + writel((SCG1_SOSCDIV_DIV3_NUM | SCG1_SOSCDIV_DIV2_NUM | + SCG1_SOSCDIV_DIV1_NUM), &scg1_regs->soscdiv); +} + +void scg_a7_sys_clk_sel(enum scg_sys_src clk) +{ + u32 rccr_reg_val = 0; + + clk_debug("%s: system clock selected as %s\n", "[SCG]", + clk == SCG_SCS_SYS_OSC ? "SYS_OSC" : + clk == SCG_SCS_SLOW_IRC ? "SLOW_IRC" : + clk == SCG_SCS_FAST_IRC ? "FAST_IRC" : + clk == SCG_SCS_RTC_OSC ? "RTC_OSC" : + clk == SCG_SCS_AUX_PLL ? "AUX_PLL" : + clk == SCG_SCS_SYS_PLL ? "SYS_PLL" : + clk == SCG_SCS_USBPHY_PLL ? "USBPHY_PLL" : + "Invalid source" + ); + + rccr_reg_val = readl(&scg1_regs->rccr); + rccr_reg_val &= ~SCG_CCR_SCS_MASK; + rccr_reg_val |= (clk << SCG_CCR_SCS_SHIFT); + writel(rccr_reg_val, &scg1_regs->rccr); +} + +void scg_a7_info(void) +{ + printf("SCG Version: 0x%x\n", readl(&scg1_regs->verid)); + printf("SCG Parameter: 0x%x\n", readl(&scg1_regs->param)); + printf("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr)); + printf("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr)); +} diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h new file mode 100644 index 0000000..f21052e --- /dev/null +++ b/arch/arm/include/asm/arch-mx7ulp/clock.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_CLOCK_H +#define _ASM_ARCH_CLOCK_H + +#include <common.h> +#include <asm/arch/pcc.h> +#include <asm/arch/scg.h> + +/* Mainly for compatible to imx common code. */ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_AXI_CLK, + MXC_DDR_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_I2C_CLK, +}; + +u32 mxc_get_clock(enum mxc_clock clk); +u32 get_lpuart_clk(void); +#ifdef CONFIG_MXC_OCOTP +void enable_ocotp_clk(unsigned char enable); +#endif +#ifdef CONFIG_USB_EHCI +void enable_usboh3_clk(unsigned char enable); +#endif +void init_clk_usdhc(u32 index); +void clock_init(void); +#endif diff --git a/arch/arm/include/asm/arch-mx7ulp/pcc.h b/arch/arm/include/asm/arch-mx7ulp/pcc.h new file mode 100644 index 0000000..051dcb5 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7ulp/pcc.h @@ -0,0 +1,377 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_PCC_H +#define _ASM_ARCH_PCC_H + +#include <common.h> +#include <asm/arch/scg.h> + +/* PCC2 */ + +/* On-Platform (32 entries) */ +#define RSVD0_PCC2_SLOT (0) +#define RSVD1_PCC2_SLOT (1) +#define CA7_GIC_PCC2_SLOT (2) +#define RSVD3_PCC2_SLOT (3) +#define RSVD4_PCC2_SLOT (4) +#define RSVD5_PCC2_SLOT (5) +#define RSVD6_PCC2_SLOT (6) +#define RSVD7_PCC2_SLOT (7) +#define DMA1_PCC2_SLOT (8) +#define RSVD9_PCC2_SLOT (9) +#define RSVD10_PCC2_SLOT (10) +#define RSVD11_PCC2_SLOT (11) +#define RSVD12_PCC2_SLOT (12) +#define RSVD13_PCC2_SLOT (13) +#define RSVD14_PCC2_SLOT (14) +#define RGPIO1_PCC2_SLOT (15) +#define FLEXBUS0_PCC2_SLOT (16) +#define RSVD17_PCC2_SLOT (17) +#define RSVD18_PCC2_SLOT (18) +#define RSVD19_PCC2_SLOT (19) +#define RSVD20_PCC2_SLOT (20) +#define RSVD21_PCC2_SLOT (21) +#define RSVD22_PCC2_SLOT (22) +#define RSVD23_PCC2_SLOT (23) +#define RSVD24_PCC2_SLOT (24) +#define RSVD25_PCC2_SLOT (25) +#define RSVD26_PCC2_SLOT (26) +#define SEMA42_1_PCC2_SLOT (27) +#define RSVD28_PCC2_SLOT (28) +#define RSVD29_PCC2_SLOT (29) +#define RSVD30_PCC2_SLOT (30) +#define RSVD31_PCC2_SLOT (31) + +/* Off-Platform (96 entries) */ + +#define RSVD32_PCC2_SLOT (32) +#define DMA1_CH_MUX0_PCC2_SLOT (33) +#define MU_B_PCC2_SLOT (34) +#define SNVS_PCC2_SLOT (35) +#define CAAM_PCC2_SLOT (36) +#define LPTPM4_PCC2_SLOT (37) +#define LPTPM5_PCC2_SLOT (38) +#define LPIT1_PCC2_SLOT (39) +#define RSVD40_PCC2_SLOT (40) +#define LPSPI2_PCC2_SLOT (41) +#define LPSPI3_PCC2_SLOT (42) +#define LPI2C4_PCC2_SLOT (43) +#define LPI2C5_PCC2_SLOT (44) +#define LPUART4_PCC2_SLOT (45) +#define LPUART5_PCC2_SLOT (46) +#define RSVD47_PCC2_SLOT (47) +#define RSVD48_PCC2_SLOT (48) +#define FLEXIO1_PCC2_SLOT (49) +#define RSVD50_PCC2_SLOT (50) +#define USBOTG0_PCC2_SLOT (51) +#define USBOTG1_PCC2_SLOT (52) +#define USBPHY_PCC2_SLOT (53) +#define USB_PL301_PCC2_SLOT (54) +#define USDHC0_PCC2_SLOT (55) +#define USDHC1_PCC2_SLOT (56) +#define RSVD57_PCC2_SLOT (57) +#define TRGMUX1_PCC2_SLOT (58) +#define RSVD59_PCC2_SLOT (59) +#define RSVD60_PCC2_SLOT (60) +#define WDG1_PCC2_SLOT (61) +#define SCG1_PCC2_SLOT (62) +#define PCC2_PCC2_SLOT (63) +#define PMC1_PCC2_SLOT (64) +#define SMC1_PCC2_SLOT (65) +#define RCM1_PCC2_SLOT (66) +#define WDG2_PCC2_SLOT (67) +#define RSVD68_PCC2_SLOT (68) +#define TEST_SPACE1_PCC2_SLOT (69) +#define TEST_SPACE2_PCC2_SLOT (70) +#define TEST_SPACE3_PCC2_SLOT (71) +#define RSVD72_PCC2_SLOT (72) +#define RSVD73_PCC2_SLOT (73) +#define RSVD74_PCC2_SLOT (74) +#define RSVD75_PCC2_SLOT (75) +#define RSVD76_PCC2_SLOT (76) +#define RSVD77_PCC2_SLOT (77) +#define RSVD78_PCC2_SLOT (78) +#define RSVD79_PCC2_SLOT (79) +#define RSVD80_PCC2_SLOT (80) +#define RSVD81_PCC2_SLOT (81) +#define RSVD82_PCC2_SLOT (82) +#define RSVD83_PCC2_SLOT (83) +#define RSVD84_PCC2_SLOT (84) +#define RSVD85_PCC2_SLOT (85) +#define RSVD86_PCC2_SLOT (86) +#define RSVD87_PCC2_SLOT (87) +#define RSVD88_PCC2_SLOT (88) +#define RSVD89_PCC2_SLOT (89) +#define RSVD90_PCC2_SLOT (90) +#define RSVD91_PCC2_SLOT (91) +#define RSVD92_PCC2_SLOT (92) +#define RSVD93_PCC2_SLOT (93) +#define RSVD94_PCC2_SLOT (94) +#define RSVD95_PCC2_SLOT (95) +#define RSVD96_PCC2_SLOT (96) +#define RSVD97_PCC2_SLOT (97) +#define RSVD98_PCC2_SLOT (98) +#define RSVD99_PCC2_SLOT (99) +#define RSVD100_PCC2_SLOT (100) +#define RSVD101_PCC2_SLOT (101) +#define RSVD102_PCC2_SLOT (102) +#define RSVD103_PCC2_SLOT (103) +#define RSVD104_PCC2_SLOT (104) +#define RSVD105_PCC2_SLOT (105) +#define RSVD106_PCC2_SLOT (106) +#define RSVD107_PCC2_SLOT (107) +#define RSVD108_PCC2_SLOT (108) +#define RSVD109_PCC2_SLOT (109) +#define RSVD110_PCC2_SLOT (110) +#define RSVD111_PCC2_SLOT (111) +#define RSVD112_PCC2_SLOT (112) +#define RSVD113_PCC2_SLOT (113) +#define RSVD114_PCC2_SLOT (114) +#define RSVD115_PCC2_SLOT (115) +#define RSVD116_PCC2_SLOT (116) +#define RSVD117_PCC2_SLOT (117) +#define RSVD118_PCC2_SLOT (118) +#define RSVD119_PCC2_SLOT (119) +#define RSVD120_PCC2_SLOT (120) +#define RSVD121_PCC2_SLOT (121) +#define RSVD122_PCC2_SLOT (122) +#define RSVD123_PCC2_SLOT (123) +#define RSVD124_PCC2_SLOT (124) +#define RSVD125_PCC2_SLOT (125) +#define RSVD126_PCC2_SLOT (126) +#define RSVD127_PCC2_SLOT (127) + +/*------------------------------------------------------------------------- + * PCC3 + *------------------------------------------------------------------------- + */ + +/* On-Platform (32 entries) */ + +#define RSVD0_PCC3_SLOT (0) +#define RSVD1_PCC3_SLOT (1) +#define RSVD2_PCC3_SLOT (2) +#define RSVD3_PCC3_SLOT (3) +#define RSVD4_PCC3_SLOT (4) +#define RSVD5_PCC3_SLOT (5) +#define RSVD6_PCC3_SLOT (6) +#define RSVD7_PCC3_SLOT (7) +#define RSVD8_PCC3_SLOT (8) +#define RSVD9_PCC3_SLOT (9) +#define RSVD10_PCC3_SLOT (10) +#define RSVD11_PCC3_SLOT (11) +#define RSVD12_PCC3_SLOT (12) +#define RSVD13_PCC3_SLOT (13) +#define RSVD14_PCC3_SLOT (14) +#define RSVD15_PCC3_SLOT (15) +#define ROMCP1_PCC3_SLOT (16) +#define RSVD17_PCC3_SLOT (17) +#define RSVD18_PCC3_SLOT (18) +#define RSVD19_PCC3_SLOT (19) +#define RSVD20_PCC3_SLOT (20) +#define RSVD21_PCC3_SLOT (21) +#define RSVD22_PCC3_SLOT (22) +#define RSVD23_PCC3_SLOT (23) +#define RSVD24_PCC3_SLOT (24) +#define RSVD25_PCC3_SLOT (25) +#define RSVD26_PCC3_SLOT (26) +#define RSVD27_PCC3_SLOT (27) +#define RSVD28_PCC3_SLOT (28) +#define RSVD29_PCC3_SLOT (29) +#define RSVD30_PCC3_SLOT (30) +#define RSVD31_PCC3_SLOT (31) + +/* Off-Platform (96 entries) */ + +#define RSVD32_PCC3_SLOT (32) +#define LPTPM6_PCC3_SLOT (33) +#define LPTPM7_PCC3_SLOT (34) +#define RSVD35_PCC3_SLOT (35) +#define LPI2C6_PCC3_SLOT (36) +#define LPI2C7_PCC3_SLOT (37) +#define LPUART6_PCC3_SLOT (38) +#define LPUART7_PCC3_SLOT (39) +#define VIU0_PCC3_SLOT (40) +#define DSI0_PCC3_SLOT (41) +#define LCDIF0_PCC3_SLOT (42) +#define MMDC0_PCC3_SLOT (43) +#define IOMUXC1_PCC3_SLOT (44) +#define IOMUXC_DDR_PCC3_SLOT (45) +#define PORTC_PCC3_SLOT (46) +#define PORTD_PCC3_SLOT (47) +#define PORTE_PCC3_SLOT (48) +#define PORTF_PCC3_SLOT (49) +#define RSVD50_PCC3_SLOT (50) +#define PCC3_PCC3_SLOT (51) +#define RSVD52_PCC3_SLOT (52) +#define WKPU_PCC3_SLOT (53) +#define RSVD54_PCC3_SLOT (54) +#define RSVD55_PCC3_SLOT (55) +#define RSVD56_PCC3_SLOT (56) +#define RSVD57_PCC3_SLOT (57) +#define RSVD58_PCC3_SLOT (58) +#define RSVD59_PCC3_SLOT (59) +#define RSVD60_PCC3_SLOT (60) +#define RSVD61_PCC3_SLOT (61) +#define RSVD62_PCC3_SLOT (62) +#define RSVD63_PCC3_SLOT (63) +#define RSVD64_PCC3_SLOT (64) +#define RSVD65_PCC3_SLOT (65) +#define RSVD66_PCC3_SLOT (66) +#define RSVD67_PCC3_SLOT (67) +#define RSVD68_PCC3_SLOT (68) +#define RSVD69_PCC3_SLOT (69) +#define RSVD70_PCC3_SLOT (70) +#define RSVD71_PCC3_SLOT (71) +#define RSVD72_PCC3_SLOT (72) +#define RSVD73_PCC3_SLOT (73) +#define RSVD74_PCC3_SLOT (74) +#define RSVD75_PCC3_SLOT (75) +#define RSVD76_PCC3_SLOT (76) +#define RSVD77_PCC3_SLOT (77) +#define RSVD78_PCC3_SLOT (78) +#define RSVD79_PCC3_SLOT (79) +#define RSVD80_PCC3_SLOT (80) +#define GPU3D_PCC3_SLOT (81) +#define GPU2D_PCC3_SLOT (82) +#define RSVD83_PCC3_SLOT (83) +#define RSVD84_PCC3_SLOT (84) +#define RSVD85_PCC3_SLOT (85) +#define RSVD86_PCC3_SLOT (86) +#define RSVD87_PCC3_SLOT (87) +#define RSVD88_PCC3_SLOT (88) +#define RSVD89_PCC3_SLOT (89) +#define RSVD90_PCC3_SLOT (90) +#define RSVD91_PCC3_SLOT (91) +#define RSVD92_PCC3_SLOT (92) +#define RSVD93_PCC3_SLOT (93) +#define RSVD94_PCC3_SLOT (94) +#define RSVD95_PCC3_SLOT (95) +#define RSVD96_PCC3_SLOT (96) +#define RSVD97_PCC3_SLOT (97) +#define RSVD98_PCC3_SLOT (98) +#define RSVD99_PCC3_SLOT (99) +#define RSVD100_PCC3_SLOT (100) +#define RSVD101_PCC3_SLOT (101) +#define RSVD102_PCC3_SLOT (102) +#define RSVD103_PCC3_SLOT (103) +#define RSVD104_PCC3_SLOT (104) +#define RSVD105_PCC3_SLOT (105) +#define RSVD106_PCC3_SLOT (106) +#define RSVD107_PCC3_SLOT (107) +#define RSVD108_PCC3_SLOT (108) +#define RSVD109_PCC3_SLOT (109) +#define RSVD110_PCC3_SLOT (110) +#define RSVD111_PCC3_SLOT (111) +#define RSVD112_PCC3_SLOT (112) +#define RSVD113_PCC3_SLOT (113) +#define RSVD114_PCC3_SLOT (114) +#define RSVD115_PCC3_SLOT (115) +#define RSVD116_PCC3_SLOT (116) +#define RSVD117_PCC3_SLOT (117) +#define RSVD118_PCC3_SLOT (118) +#define RSVD119_PCC3_SLOT (119) +#define RSVD120_PCC3_SLOT (120) +#define RSVD121_PCC3_SLOT (121) +#define RSVD122_PCC3_SLOT (122) +#define RSVD123_PCC3_SLOT (123) +#define RSVD124_PCC3_SLOT (124) +#define RSVD125_PCC3_SLOT (125) +#define RSVD126_PCC3_SLOT (126) +#define RSVD127_PCC3_SLOT (127) + + +/* PCC registers */ +#define PCC_PR_OFFSET 31 +#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET) +#define PCC_CGC_OFFSET 30 +#define PCC_CGC_MASK (0x1 << PCC_CGC_OFFSET) +#define PCC_INUSE_OFFSET 29 +#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET) +#define PCC_PCS_OFFSET 24 +#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET) +#define PCC_FRAC_OFFSET 4 +#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET) +#define PCC_PCD_OFFSET 0 +#define PCC_PCD_MASK (0xf << PCC_PCD_OFFSET) + + +enum pcc_clksrc_type { + CLKSRC_PER_PLAT = 0, + CLKSRC_PER_BUS = 1, + CLKSRC_NO_PCS = 2, +}; + +enum pcc_div_type { + PCC_HAS_DIV, + PCC_NO_DIV, +}; + +/* All peripheral clocks on A7 PCCs */ +enum pcc_clk { + /*PCC2 clocks*/ + PER_CLK_DMA1 = 0, + PER_CLK_RGPIO2P1, + PER_CLK_FLEXBUS, + PER_CLK_SEMA42_1, + PER_CLK_DMA_MUX1, + PER_CLK_SNVS, + PER_CLK_CAAM, + PER_CLK_LPTPM4, + PER_CLK_LPTPM5, + PER_CLK_LPIT1, + PER_CLK_LPSPI2, + PER_CLK_LPSPI3, + PER_CLK_LPI2C4, + PER_CLK_LPI2C5, + PER_CLK_LPUART4, + PER_CLK_LPUART5, + PER_CLK_FLEXIO1, + PER_CLK_USB0, + PER_CLK_USB1, + PER_CLK_USB_PHY, + PER_CLK_USB_PL301, + PER_CLK_USDHC0, + PER_CLK_USDHC1, + PER_CLK_WDG1, + PER_CLK_WDG2, + + /*PCC3 clocks*/ + PER_CLK_LPTPM6, + PER_CLK_LPTPM7, + PER_CLK_LPI2C6, + PER_CLK_LPI2C7, + PER_CLK_LPUART6, + PER_CLK_LPUART7, + PER_CLK_VIU, + PER_CLK_DSI, + PER_CLK_LCDIF, + PER_CLK_MMDC, + PER_CLK_PCTLC, + PER_CLK_PCTLD, + PER_CLK_PCTLE, + PER_CLK_PCTLF, + PER_CLK_GPU3D, + PER_CLK_GPU2D, +}; + + +/* This structure keeps info for each pcc slot */ +struct pcc_entry { + u32 pcc_base; + u32 pcc_slot; + enum pcc_clksrc_type clksrc; + enum pcc_div_type div; +}; + +int pcc_clock_enable(enum pcc_clk clk, bool enable); +int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src); +int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div); +bool pcc_clock_is_enable(enum pcc_clk clk); +int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src); +u32 pcc_clock_get_rate(enum pcc_clk clk); +#endif diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h new file mode 100644 index 0000000..06a6e9f --- /dev/null +++ b/arch/arm/include/asm/arch-mx7ulp/scg.h @@ -0,0 +1,342 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_SCG_H +#define _ASM_ARCH_SCG_H + +#include <common.h> + +#ifdef CONFIG_CLK_DEBUG +#define clk_debug(fmt, args...) printf(fmt, ##args) +#else +#define clk_debug(fmt, args...) +#endif + +#define SCG_CCR_SCS_SHIFT (24) +#define SCG_CCR_SCS_MASK ((0xFUL) << SCG_CCR_SCS_SHIFT) +#define SCG_CCR_DIVCORE_SHIFT (16) +#define SCG_CCR_DIVCORE_MASK ((0xFUL) << SCG_CCR_DIVCORE_SHIFT) +#define SCG_CCR_DIVPLAT_SHIFT (12) +#define SCG_CCR_DIVPLAT_MASK ((0xFUL) << SCG_CCR_DIVPLAT_SHIFT) +#define SCG_CCR_DIVEXT_SHIFT (8) +#define SCG_CCR_DIVEXT_MASK ((0xFUL) << SCG_CCR_DIVEXT_SHIFT) +#define SCG_CCR_DIVBUS_SHIFT (4) +#define SCG_CCR_DIVBUS_MASK ((0xFUL) << SCG_CCR_DIVBUS_SHIFT) +#define SCG_CCR_DIVSLOW_SHIFT (0) +#define SCG_CCR_DIVSLOW_MASK ((0xFUL) << SCG_CCR_DIVSLOW_SHIFT) + +/* SCG DDR Clock Control Register */ +#define SCG_DDRCCR_DDRCS_SHIFT (24) +#define SCG_DDRCCR_DDRCS_MASK ((0x1UL) << SCG_DDRCCR_DDRCS_SHIFT) + +#define SCG_DDRCCR_DDRDIV_SHIFT (0) +#define SCG_DDRCCR_DDRDIV_MASK ((0x7UL) << SCG_DDRCCR_DDRDIV_SHIFT) + +/* SCG NIC Clock Control Register */ +#define SCG_NICCCR_NICCS_SHIFT (28) +#define SCG_NICCCR_NICCS_MASK ((0x1UL) << SCG_NICCCR_NICCS_SHIFT) + +#define SCG_NICCCR_NIC0_DIV_SHIFT (24) +#define SCG_NICCCR_NIC0_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC0_DIV_SHIFT) + +#define SCG_NICCCR_GPU_DIV_SHIFT (20) +#define SCG_NICCCR_GPU_DIV_MASK ((0xFUL) << SCG_NICCCR_GPU_DIV_SHIFT) + +#define SCG_NICCCR_NIC1_DIV_SHIFT (16) +#define SCG_NICCCR_NIC1_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIV_SHIFT) + +#define SCG_NICCCR_NIC1_DIVEXT_SHIFT (8) +#define SCG_NICCCR_NIC1_DIVEXT_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVEXT_SHIFT) + +#define SCG_NICCCR_NIC1_DIVBUS_SHIFT (4) +#define SCG_NICCCR_NIC1_DIVBUS_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVBUS_SHIFT) + +/* SCG NIC clock status register */ +#define SCG_NICCSR_NICCS_SHIFT (28) +#define SCG_NICCSR_NICCS_MASK ((0x1UL) << SCG_NICCSR_NICCS_SHIFT) + +#define SCG_NICCSR_NIC0DIV_SHIFT (24) +#define SCG_NICCSR_NIC0DIV_MASK ((0xFUL) << SCG_NICCSR_NIC0DIV_SHIFT) +#define SCG_NICCSR_GPUDIV_SHIFT (20) +#define SCG_NICCSR_GPUDIV_MASK ((0xFUL) << SCG_NICCSR_GPUDIV_SHIFT) +#define SCG_NICCSR_NIC1DIV_SHIFT (16) +#define SCG_NICCSR_NIC1DIV_MASK ((0xFUL) << SCG_NICCSR_NIC1DIV_SHIFT) +#define SCG_NICCSR_NIC1EXTDIV_SHIFT (8) +#define SCG_NICCSR_NIC1EXTDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1EXTDIV_SHIFT) +#define SCG_NICCSR_NIC1BUSDIV_SHIFT (4) +#define SCG_NICCSR_NIC1BUSDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1BUSDIV_SHIFT) + +/* SCG Slow IRC Control Status Register */ +#define SCG_SIRC_CSR_SIRCVLD_SHIFT (24) +#define SCG_SIRC_CSR_SIRCVLD_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCVLD_SHIFT) + +#define SCG_SIRC_CSR_SIRCEN_SHIFT (0) +#define SCG_SIRC_CSR_SIRCEN_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCEN_SHIFT) + +/* SCG Slow IRC Configuration Register */ +#define SCG_SIRCCFG_RANGE_SHIFT (0) +#define SCG_SIRCCFG_RANGE_MASK ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT) +#define SCG_SIRCCFG_RANGE_4M ((0x0UL) << SCG_SIRCCFG_RANGE_SHIFT) +#define SCG_SIRCCFG_RANGE_16M ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT) + +/* SCG Slow IRC Divide Register */ +#define SCG_SIRCDIV_DIV3_SHIFT (16) +#define SCG_SIRCDIV_DIV3_MASK ((0x7UL) << SCG_SIRCDIV_DIV3_SHIFT) + +#define SCG_SIRCDIV_DIV2_SHIFT (8) +#define SCG_SIRCDIV_DIV2_MASK ((0x7UL) << SCG_SIRCDIV_DIV2_SHIFT) + +#define SCG_SIRCDIV_DIV1_SHIFT (0) +#define SCG_SIRCDIV_DIV1_MASK ((0x7UL) << SCG_SIRCDIV_DIV1_SHIFT) +/* + * FIRC/SIRC DIV1 ==> xIRC_PLAT_CLK + * FIRC/SIRC DIV2 ==> xIRC_BUS_CLK + * FIRC/SIRC DIV3 ==> xIRC_SLOW_CLK + */ + +/* SCG Fast IRC Control Status Register */ +#define SCG_FIRC_CSR_FIRCVLD_SHIFT (24) +#define SCG_FIRC_CSR_FIRCVLD_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCVLD_SHIFT) + +#define SCG_FIRC_CSR_FIRCEN_SHIFT (0) +#define SCG_FIRC_CSR_FIRCEN_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCEN_SHIFT) + +/* SCG Fast IRC Divide Register */ +#define SCG_FIRCDIV_DIV3_SHIFT (16) +#define SCG_FIRCDIV_DIV3_MASK ((0x7UL) << SCG_FIRCDIV_DIV3_SHIFT) + +#define SCG_FIRCDIV_DIV2_SHIFT (8) +#define SCG_FIRCDIV_DIV2_MASK ((0x7UL) << SCG_FIRCDIV_DIV2_SHIFT) + +#define SCG_FIRCDIV_DIV1_SHIFT (0) +#define SCG_FIRCDIV_DIV1_MASK ((0x7UL) << SCG_FIRCDIV_DIV1_SHIFT) + +#define SCG_FIRCCFG_RANGE_SHIFT (0) +#define SCG_FIRCCFG_RANGE_MASK ((0x3UL) << SCG_FIRCCFG_RANGE_SHIFT) + +#define SCG_FIRCCFG_RANGE_SHIFT (0) +#define SCG_FIRCCFG_RANGE_48M ((0x0UL) << SCG_FIRCCFG_RANGE_SHIFT) + +/* SCG System OSC Control Status Register */ +#define SCG_SOSC_CSR_SOSCVLD_SHIFT (24) +#define SCG_SOSC_CSR_SOSCVLD_MASK ((0x1UL) << SCG_SOSC_CSR_SOSCVLD_SHIFT) + +/* SCG Fast IRC Divide Register */ +#define SCG_SOSCDIV_DIV3_SHIFT (16) +#define SCG_SOSCDIV_DIV3_MASK ((0x7UL) << SCG_SOSCDIV_DIV3_SHIFT) + +#define SCG_SOSCDIV_DIV2_SHIFT (8) +#define SCG_SOSCDIV_DIV2_MASK ((0x7UL) << SCG_SOSCDIV_DIV2_SHIFT) + +#define SCG_SOSCDIV_DIV1_SHIFT (0) +#define SCG_SOSCDIV_DIV1_MASK ((0x7UL) << SCG_SOSCDIV_DIV1_SHIFT) + +/* SCG RTC OSC Control Status Register */ +#define SCG_ROSC_CSR_ROSCVLD_SHIFT (24) +#define SCG_ROSC_CSR_ROSCVLD_MASK ((0x1UL) << SCG_ROSC_CSR_ROSCVLD_SHIFT) + +#define SCG_SPLL_CSR_SPLLVLD_SHIFT (24) +#define SCG_SPLL_CSR_SPLLVLD_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLVLD_SHIFT) +#define SCG_SPLL_CSR_SPLLEN_SHIFT (0) +#define SCG_SPLL_CSR_SPLLEN_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLEN_SHIFT) +#define SCG_APLL_CSR_APLLEN_SHIFT (0) +#define SCG_APLL_CSR_APLLEN_MASK (0x1UL) +#define SCG_APLL_CSR_APLLVLD_MASK (0x01000000) + +#define SCG_UPLL_CSR_UPLLVLD_MASK (0x01000000) + + +#define SCG_PLL_PFD3_GATE_MASK (0x80000000) +#define SCG_PLL_PFD2_GATE_MASK (0x00800000) +#define SCG_PLL_PFD1_GATE_MASK (0x00008000) +#define SCG_PLL_PFD0_GATE_MASK (0x00000080) +#define SCG_PLL_PFD3_VALID_MASK (0x40000000) +#define SCG_PLL_PFD2_VALID_MASK (0x00400000) +#define SCG_PLL_PFD1_VALID_MASK (0x00004000) +#define SCG_PLL_PFD0_VALID_MASK (0x00000040) + +#define SCG_PLL_PFD0_FRAC_SHIFT (0) +#define SCG_PLL_PFD0_FRAC_MASK ((0x3F) << SCG_PLL_PFD0_FRAC_SHIFT) +#define SCG_PLL_PFD1_FRAC_SHIFT (8) +#define SCG_PLL_PFD1_FRAC_MASK ((0x3F) << SCG_PLL_PFD1_FRAC_SHIFT) +#define SCG_PLL_PFD2_FRAC_SHIFT (16) +#define SCG_PLL_PFD2_FRAC_MASK ((0x3F) << SCG_PLL_PFD2_FRAC_SHIFT) +#define SCG_PLL_PFD3_FRAC_SHIFT (24) +#define SCG_PLL_PFD3_FRAC_MASK ((0x3F) << SCG_PLL_PFD3_FRAC_SHIFT) + +#define SCG_PLL_CFG_POSTDIV2_SHIFT (28) +#define SCG_PLL_CFG_POSTDIV2_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV2_SHIFT) +#define SCG_PLL_CFG_POSTDIV1_SHIFT (24) +#define SCG_PLL_CFG_POSTDIV1_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV1_SHIFT) +#define SCG_PLL_CFG_MULT_SHIFT (16) +#define SCG1_SPLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT) +#define SCG_APLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT) +#define SCG_PLL_CFG_PFDSEL_SHIFT (14) +#define SCG_PLL_CFG_PFDSEL_MASK ((0x3UL) << SCG_PLL_CFG_PFDSEL_SHIFT) +#define SCG_PLL_CFG_PREDIV_SHIFT (8) +#define SCG_PLL_CFG_PREDIV_MASK ((0x7UL) << SCG_PLL_CFG_PREDIV_SHIFT) +#define SCG_PLL_CFG_BYPASS_SHIFT (2) +/* 0: SPLL, 1: bypass */ +#define SCG_PLL_CFG_BYPASS_MASK ((0x1UL) << SCG_PLL_CFG_BYPASS_SHIFT) +#define SCG_PLL_CFG_PLLSEL_SHIFT (1) +/* 0: pll, 1: pfd */ +#define SCG_PLL_CFG_PLLSEL_MASK ((0x1UL) << SCG_PLL_CFG_PLLSEL_SHIFT) +#define SCG_PLL_CFG_CLKSRC_SHIFT (0) +/* 0: Sys-OSC, 1: FIRC */ +#define SCG_PLL_CFG_CLKSRC_MASK ((0x1UL) << SCG_PLL_CFG_CLKSRC_SHIFT) +#define SCG0_SPLL_CFG_MULT_SHIFT (17) +/* 0: Multiplier = 20, 1: Multiplier = 22 */ +#define SCG0_SPLL_CFG_MULT_MASK ((0x1UL) << SCG0_SPLL_CFG_MULT_SHIFT) + +#define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6) +#define PLL_USB_PWR_MASK (0x01 << 12) +#define PLL_USB_ENABLE_MASK (0x01 << 13) +#define PLL_USB_BYPASS_MASK (0x01 << 16) +#define PLL_USB_REG_ENABLE_MASK (0x01 << 21) +#define PLL_USB_DIV_SEL_MASK (0x07 << 22) +#define PLL_USB_LOCK_MASK (0x01 << 31) + +enum scg_clk { + SCG_SOSC_CLK, + SCG_FIRC_CLK, + SCG_SIRC_CLK, + SCG_ROSC_CLK, + SCG_SIRC_DIV1_CLK, + SCG_SIRC_DIV2_CLK, + SCG_SIRC_DIV3_CLK, + SCG_FIRC_DIV1_CLK, + SCG_FIRC_DIV2_CLK, + SCG_FIRC_DIV3_CLK, + SCG_SOSC_DIV1_CLK, + SCG_SOSC_DIV2_CLK, + SCG_SOSC_DIV3_CLK, + SCG_CORE_CLK, + SCG_BUS_CLK, + SCG_SPLL_PFD0_CLK, + SCG_SPLL_PFD1_CLK, + SCG_SPLL_PFD2_CLK, + SCG_SPLL_PFD3_CLK, + SCG_DDR_CLK, + SCG_NIC0_CLK, + SCG_GPU_CLK, + SCG_NIC1_CLK, + SCG_NIC1_BUS_CLK, + SCG_NIC1_EXT_CLK, + SCG_APLL_PFD0_CLK, + SCG_APLL_PFD1_CLK, + SCG_APLL_PFD2_CLK, + SCG_APLL_PFD3_CLK, + USB_PLL_OUT, + MIPI_PLL_OUT +}; + +enum scg_sys_src { + SCG_SCS_SYS_OSC = 1, + SCG_SCS_SLOW_IRC, + SCG_SCS_FAST_IRC, + SCG_SCS_RTC_OSC, + SCG_SCS_AUX_PLL, + SCG_SCS_SYS_PLL, + SCG_SCS_USBPHY_PLL, +}; + +/* PLL supported by i.mx7ulp */ +enum pll_clocks { + PLL_M4_SPLL, /* M4 SPLL */ + PLL_M4_APLL, /* M4 APLL*/ + PLL_A7_SPLL, /* A7 SPLL */ + PLL_A7_APLL, /* A7 APLL */ + PLL_USB, /* USB PLL*/ + PLL_MIPI, /* MIPI PLL */ +}; + +typedef struct scg_regs { + u32 verid; /* VERSION_ID */ + u32 param; /* PARAMETER */ + u32 rsvd11[2]; + + u32 csr; /* Clock Status Register */ + u32 rccr; /* Run Clock Control Register */ + u32 vccr; /* VLPR Clock Control Register */ + u32 hccr; /* HSRUN Clock Control Register */ + u32 clkoutcnfg; /* SCG CLKOUT Configuration Register */ + u32 rsvd12[3]; + u32 ddrccr; /* SCG DDR Clock Control Register */ + u32 rsvd13[3]; + u32 nicccr; /* NIC Clock Control Register */ + u32 niccsr; /* NIC Clock Status Register */ + u32 rsvd10[46]; + + u32 sosccsr; /* System OSC Control Status Register, offset 0x100 */ + u32 soscdiv; /* System OSC Divide Register */ + u32 sosccfg; /* System Oscillator Configuration Register */ + u32 sosctest; /* System Oscillator Test Register */ + u32 rsvd20[60]; + + u32 sirccsr; /* Slow IRC Control Status Register, offset 0x200 */ + u32 sircdiv; /* Slow IRC Divide Register */ + u32 sirccfg; /* Slow IRC Configuration Register */ + u32 sirctrim; /* Slow IRC Trim Register */ + u32 loptrim; /* Low Power Oscillator Trim Register */ + u32 sirctest; /* Slow IRC Test Register */ + u32 rsvd30[58]; + + u32 firccsr; /* Fast IRC Control Status Register, offset 0x300 */ + u32 fircdiv; + u32 firccfg; + u32 firctcfg; /* Fast IRC Trim Configuration Register */ + u32 firctriml; /* Fast IRC Trim Low Register */ + u32 firctrimh; + u32 fircstat; /* Fast IRC Status Register */ + u32 firctest; /* Fast IRC Test Register */ + u32 rsvd40[56]; + + u32 rtccsr; /* RTC OSC Control Status Register, offset 0x400 */ + u32 rsvd50[63]; + + u32 apllcsr; /* Auxiliary PLL Control Status Register, offset 0x500 */ + u32 aplldiv; /* Auxiliary PLL Divider Register */ + u32 apllcfg; /* Auxiliary PLL Configuration Register */ + u32 apllpfd; /* Auxiliary PLL PFD Register */ + u32 apllnum; /* Auxiliary PLL Numerator Register */ + u32 aplldenom; /* Auxiliary PLL Denominator Register */ + u32 apllss; /* Auxiliary PLL Spread Spectrum Register */ + u32 rsvd60[55]; + u32 apllock_cnfg; /* Auxiliary PLL LOCK Configuration Register */ + u32 rsvd61[1]; + + u32 spllcsr; /* System PLL Control Status Register, offset 0x600 */ + u32 splldiv; /* System PLL Divide Register */ + u32 spllcfg; /* System PLL Configuration Register */ + u32 spllpfd; /* System PLL Test Register */ + u32 spllnum; /* System PLL Numerator Register */ + u32 splldenom; /* System PLL Denominator Register */ + u32 spllss; /* System PLL Spread Spectrum Register */ + u32 rsvd70[55]; + u32 spllock_cnfg; /* System PLL LOCK Configuration Register */ + u32 rsvd71[1]; + + u32 upllcsr; /* USB PLL Control Status Register, offset 0x700 */ + u32 uplldiv; /* USB PLL Divide Register */ + u32 upllcfg; /* USB PLL Configuration Register */ +} scg_t, *scg_p; + +u32 scg_clk_get_rate(enum scg_clk clk); +int scg_enable_pll_pfd(enum scg_clk clk, u32 frac); +int scg_enable_usb_pll(bool usb_control); +u32 decode_pll(enum pll_clocks pll); + +void scg_a7_rccr_init(void); +void scg_a7_spll_init(void); +void scg_a7_ddrclk_init(void); +void scg_a7_apll_init(void); +void scg_a7_firc_init(void); +void scg_a7_nicclk_init(void); +void scg_a7_sys_clk_sel(enum scg_sys_src clk); +void scg_a7_info(void); +void scg_a7_soscdiv_init(void); + +#endif -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 04/20] imx: mx7ulp: Add clock framework and functions 2016-12-27 10:04 ` [U-Boot] [PATCH V2 04/20] imx: mx7ulp: Add clock framework and functions Peng Fan @ 2017-02-12 9:12 ` Stefano Babic 0 siblings, 0 replies; 48+ messages in thread From: Stefano Babic @ 2017-02-12 9:12 UTC (permalink / raw) To: u-boot Hi Peng, On 27/12/2016 11:04, Peng Fan wrote: > Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set > clock source, divider, clock rate and parent source. > Users need to include pcc.h to use the APIs to for peripherals clock. Each > peripheral clock is defined in enum pcc_clk type. > > SCG relevants APIs are defined in scg.h which supports clock rate get, PLL/PFD > enablement and settings, and all SCG clock initialization. User need use enum > scg_clk to access each clock source. > > In clock.c, we initialize necessary clocks at u-boot s_init and implement the > clock functions used by driver modules to operate clocks dynamically. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Signed-off-by: Ye Li <ye.li@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > None > > arch/arm/cpu/armv7/mx7ulp/Makefile | 2 +- > arch/arm/cpu/armv7/mx7ulp/clock.c | 286 ++++++++ > arch/arm/cpu/armv7/mx7ulp/pcc.c | 286 ++++++++ > arch/arm/cpu/armv7/mx7ulp/scg.c | 1086 ++++++++++++++++++++++++++++++ > arch/arm/include/asm/arch-mx7ulp/clock.h | 38 ++ > arch/arm/include/asm/arch-mx7ulp/pcc.h | 377 +++++++++++ > arch/arm/include/asm/arch-mx7ulp/scg.h | 342 ++++++++++ > 7 files changed, 2416 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/cpu/armv7/mx7ulp/clock.c > create mode 100644 arch/arm/cpu/armv7/mx7ulp/pcc.c > create mode 100644 arch/arm/cpu/armv7/mx7ulp/scg.c > create mode 100644 arch/arm/include/asm/arch-mx7ulp/clock.h > create mode 100644 arch/arm/include/asm/arch-mx7ulp/pcc.h > create mode 100644 arch/arm/include/asm/arch-mx7ulp/scg.h > > diff --git a/arch/arm/cpu/armv7/mx7ulp/Makefile b/arch/arm/cpu/armv7/mx7ulp/Makefile > index be038e7..6f37e8c 100644 > --- a/arch/arm/cpu/armv7/mx7ulp/Makefile > +++ b/arch/arm/cpu/armv7/mx7ulp/Makefile > @@ -5,4 +5,4 @@ > # > # > > -obj-y := iomux.o > +obj-y := clock.o iomux.o pcc.o scg.o > diff --git a/arch/arm/cpu/armv7/mx7ulp/clock.c b/arch/arm/cpu/armv7/mx7ulp/clock.c > new file mode 100644 > index 0000000..534f632 > --- /dev/null > +++ b/arch/arm/cpu/armv7/mx7ulp/clock.c > @@ -0,0 +1,286 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <div64.h> > +#include <asm/io.h> > +#include <errno.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/sys_proto.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +int get_clocks(void) > +{ > +#ifdef CONFIG_FSL_ESDHC > +#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE > + gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); > +#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE > + gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); > +#endif > +#endif > + return 0; > +} > + > +static u32 get_fast_plat_clk(void) > +{ > + return scg_clk_get_rate(SCG_NIC0_CLK); > +} > + > +static u32 get_slow_plat_clk(void) > +{ > + return scg_clk_get_rate(SCG_NIC1_CLK); > +} > + > +static u32 get_ipg_clk(void) > +{ > + return scg_clk_get_rate(SCG_NIC1_BUS_CLK); > +} > + > +u32 get_lpuart_clk(void) > +{ > + return pcc_clock_get_rate(PER_CLK_LPUART4); > +} > + > +unsigned int mxc_get_clock(enum mxc_clock clk) > +{ > + switch (clk) { > + case MXC_ARM_CLK: > + return scg_clk_get_rate(SCG_CORE_CLK); > + case MXC_AXI_CLK: > + return get_fast_plat_clk(); > + case MXC_AHB_CLK: > + return get_slow_plat_clk(); > + case MXC_IPG_CLK: > + return get_ipg_clk(); > + case MXC_I2C_CLK: > + return pcc_clock_get_rate(PER_CLK_LPI2C4); > + case MXC_UART_CLK: > + return pcc_clock_get_rate(PER_CLK_LPUART4); > + case MXC_ESDHC_CLK: > + return pcc_clock_get_rate(PER_CLK_USDHC0); > + case MXC_ESDHC2_CLK: > + return pcc_clock_get_rate(PER_CLK_USDHC1); > + case MXC_DDR_CLK: > + return scg_clk_get_rate(SCG_DDR_CLK); > + default: > + printf("Unsupported mxc_clock %d\n", clk); > + break; > + } > + > + return 0; > +} > + > +void init_clk_usdhc(u32 index) > +{ > + switch (index) { > + case 0: > + /*Disable the clock before configure it */ > + pcc_clock_enable(PER_CLK_USDHC0, false); > + > + /* 158MHz / 1 = 158MHz */ > + pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK); > + pcc_clock_div_config(PER_CLK_USDHC0, false, 1); > + pcc_clock_enable(PER_CLK_USDHC0, true); > + break; > + case 1: > + /*Disable the clock before configure it */ > + pcc_clock_enable(PER_CLK_USDHC1, false); > + > + /* 158MHz / 1 = 158MHz */ > + pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK); > + pcc_clock_div_config(PER_CLK_USDHC1, false, 1); > + pcc_clock_enable(PER_CLK_USDHC1, true); > + break; > + default: > + printf("Invalid index for USDHC %d\n", index); > + break; > + } > +} > + > +#ifdef CONFIG_MXC_OCOTP > + > +#define OCOTP_CTRL_PCC1_SLOT (38) > +#define OCOTP_CTRL_HIGH4K_PCC1_SLOT (39) > + > +void enable_ocotp_clk(unsigned char enable) > +{ > + u32 val; > + > + /* > + * Seems the OCOTP CLOCKs have been enabled at default, > + * check its inuse flag > + */ > + > + val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT); > + if (!(val & PCC_INUSE_MASK)) > + writel(PCC_CGC_MASK, (PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT)); > + > + val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT); > + if (!(val & PCC_INUSE_MASK)) > + writel(PCC_CGC_MASK, > + (PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT)); > +} > +#endif > + > +void enable_usboh3_clk(unsigned char enable) > +{ > + if (enable) { > + pcc_clock_enable(PER_CLK_USB0, false); > + pcc_clock_sel(PER_CLK_USB0, SCG_NIC1_BUS_CLK); > + pcc_clock_enable(PER_CLK_USB0, true); > + > +#ifdef CONFIG_USB_MAX_CONTROLLER_COUNT > + if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) { > + pcc_clock_enable(PER_CLK_USB1, false); > + pcc_clock_sel(PER_CLK_USB1, SCG_NIC1_BUS_CLK); > + pcc_clock_enable(PER_CLK_USB1, true); > + } > +#endif > + > + pcc_clock_enable(PER_CLK_USB_PHY, true); > + pcc_clock_enable(PER_CLK_USB_PL301, true); > + } else { > + pcc_clock_enable(PER_CLK_USB0, false); > + pcc_clock_enable(PER_CLK_USB1, false); > + pcc_clock_enable(PER_CLK_USB_PHY, false); > + pcc_clock_enable(PER_CLK_USB_PL301, false); > + } > +} > + > +static void lpuart_set_clk(uint32_t index, enum scg_clk clk) > +{ > + const enum pcc_clk lpuart_pcc_clks[] = { > + PER_CLK_LPUART4, > + PER_CLK_LPUART5, > + PER_CLK_LPUART6, > + PER_CLK_LPUART7, > + }; > + > + if (index < 4 || index > 7) > + return; > + > +#ifndef CONFIG_CLK_DEBUG > + pcc_clock_enable(lpuart_pcc_clks[index - 4], false); > +#endif > + pcc_clock_sel(lpuart_pcc_clks[index - 4], clk); > + pcc_clock_enable(lpuart_pcc_clks[index - 4], true); > +} > + > +static void init_clk_lpuart(void) > +{ > + u32 index = 0, i; > + > + const u32 lpuart_array[] = { > + LPUART0_RBASE, > + LPUART1_RBASE, > + LPUART2_RBASE, > + LPUART3_RBASE, > + LPUART4_RBASE, > + LPUART5_RBASE, > + LPUART6_RBASE, > + LPUART7_RBASE, > + }; > + > + for (i = 0; i < 8; i++) { > + if (lpuart_array[i] == LPUART_BASE) { > + index = i; > + break; > + } > + } > + > + lpuart_set_clk(index, SCG_SOSC_DIV2_CLK); > +} > + Maybe you can squash Patch 6/20 here into this one. > +static void init_clk_rgpio2p(void) > +{ > + /*Enable RGPIO2P1 clock */ > + pcc_clock_enable(PER_CLK_RGPIO2P1, true); > + > + /* > + * Hard code to enable RGPIO2P0 clock since it is not > + * in clock frame for A7 domain > + */ > + writel(PCC_CGC_MASK, (PCC0_RBASE + 0x3C)); > +} Please note that, because documentation for 7ulp is not available, I rely on you about this code. I am more checking if these patches has side-effects on the rest of i.MX code, but for the details and implementation for this new SOC I cannot do a lot. This because this function is quite obscure to me, but surely can be explained by reading the User Manual. > + > +/* Configure PLL/PFD freq */ > +void clock_init(void) > +{ > + /* ROM has enabled clocks: Nitpick: codestyle for multi-line comments > + * A4 side: SIRC 16Mhz (DIV1-3 off), FIRC 48Mhz (DIV1-2 on), > + * Non-LP-boot: SOSC, SPLL PFD0 (scs selected) > + * A7 side: SPLL PFD0 (scs selected, 413Mhz), > + * APLL PFD0 (352Mhz), DDRCLK, all NIC clocks > + * A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz, > + * IP BUS (NIC1_BUS) = 58.6Mhz > + * > + * In u-boot: > + * 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs. > + * 2. Enable USB PLL > + * 3. Init the clocks of peripherals used in u-boot bu > + * without set rate interface.The clocks for these > + * peripherals are enabled in this intialization. > + * 4.Other peripherals with set clock rate interface > + * does not be set in this function. > + */ > + > + scg_a7_firc_init(); > + > + scg_a7_soscdiv_init(); > + > + /* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */ > + scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35); > + scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 20); > + scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12); > + > + init_clk_lpuart(); > + > + init_clk_rgpio2p(); > + > + enable_usboh3_clk(1); > +} > + > +/* > + * Dump some core clockes. > + */ > +int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) > +{ > + u32 addr = 0; > + u32 freq; > + freq = decode_pll(PLL_A7_SPLL); > + printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000); > + > + freq = decode_pll(PLL_A7_APLL); > + printf("PLL_A7_APLL %8d MHz\n", freq / 1000000); > + > + freq = decode_pll(PLL_USB); > + printf("PLL_USB %8d MHz\n", freq / 1000000); > + > + printf("\n"); > + > + printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000); > + printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); > + printf("UART %8d kHz\n", pcc_clock_get_rate(PER_CLK_LPUART4) / 1000); > + printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); > + printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); > + printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); > + printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); > + printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); > + printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000); > + > + addr = (u32) clock_init; > + printf("[%s] addr = 0x%08X\r\n", __func__, addr); > + scg_a7_info(); > + > + return 0; > +} > + > +U_BOOT_CMD( > + clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks, > + "display clocks", > + "" > +); > diff --git a/arch/arm/cpu/armv7/mx7ulp/pcc.c b/arch/arm/cpu/armv7/mx7ulp/pcc.c > new file mode 100644 > index 0000000..edd84e5 > --- /dev/null > +++ b/arch/arm/cpu/armv7/mx7ulp/pcc.c > @@ -0,0 +1,286 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <div64.h> > +#include <asm/io.h> > +#include <errno.h> > +#include <asm/arch/imx-regs.h> > +#include <asm/arch/pcc.h> > +#include <asm/arch/sys_proto.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +#define PCC_CLKSRC_TYPES 2 > +#define PCC_CLKSRC_NUM 7 > + > +static enum scg_clk pcc_clksrc[PCC_CLKSRC_TYPES][PCC_CLKSRC_NUM] = { > + { SCG_NIC1_BUS_CLK, > + SCG_NIC1_CLK, > + SCG_DDR_CLK, > + SCG_APLL_PFD2_CLK, > + SCG_APLL_PFD1_CLK, > + SCG_APLL_PFD0_CLK, > + USB_PLL_OUT, > + }, > + { SCG_SOSC_DIV2_CLK, /* SOSC BUS clock */ > + MIPI_PLL_OUT, > + SCG_FIRC_DIV2_CLK, /* FIRC BUS clock */ > + SCG_ROSC_CLK, > + SCG_NIC1_BUS_CLK, > + SCG_NIC1_CLK, > + SCG_APLL_PFD3_CLK, > + }, > +}; > + > +static struct pcc_entry pcc_arrays[] = { > + {PCC2_RBASE, DMA1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, > + {PCC2_RBASE, RGPIO1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, > + {PCC2_RBASE, FLEXBUS0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, > + {PCC2_RBASE, SEMA42_1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, > + {PCC2_RBASE, DMA1_CH_MUX0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, > + {PCC2_RBASE, SNVS_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, > + {PCC2_RBASE, CAAM_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, > + {PCC2_RBASE, LPTPM4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC2_RBASE, LPTPM5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC2_RBASE, LPIT1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC2_RBASE, LPSPI2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC2_RBASE, LPSPI3_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC2_RBASE, LPI2C4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC2_RBASE, LPI2C5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC2_RBASE, LPUART4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC2_RBASE, LPUART5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC2_RBASE, FLEXIO1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC2_RBASE, USBOTG0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV}, > + {PCC2_RBASE, USBOTG1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV}, > + {PCC2_RBASE, USBPHY_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, > + {PCC2_RBASE, USB_PL301_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, > + {PCC2_RBASE, USDHC0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV}, > + {PCC2_RBASE, USDHC1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV}, > + {PCC2_RBASE, WDG1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV}, > + {PCC2_RBASE, WDG2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV}, > + > + {PCC3_RBASE, LPTPM6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC3_RBASE, LPTPM7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC3_RBASE, LPI2C6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC3_RBASE, LPI2C7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC3_RBASE, LPUART6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC3_RBASE, LPUART7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV}, > + {PCC3_RBASE, VIU0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, > + {PCC3_RBASE, DSI0_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV}, > + {PCC3_RBASE, LCDIF0_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV}, > + {PCC3_RBASE, MMDC0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, > + {PCC3_RBASE, PORTC_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, > + {PCC3_RBASE, PORTD_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, > + {PCC3_RBASE, PORTE_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, > + {PCC3_RBASE, PORTF_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV}, > + {PCC3_RBASE, GPU3D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV}, > + {PCC3_RBASE, GPU2D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV}, > +}; > + > +int pcc_clock_enable(enum pcc_clk clk, bool enable) > +{ > + u32 reg, val; > + > + if (clk >= ARRAY_SIZE(pcc_arrays)) > + return -EINVAL; > + > + reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; > + > + val = readl(reg); > + > + clk_debug("pcc_clock_enable: clk %d, reg 0x%x, val 0x%x, enable %d\n", > + clk, reg, val, enable); > + > + if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK)) > + return -EPERM; > + > + if (enable) > + val |= PCC_CGC_MASK; > + else > + val &= ~PCC_CGC_MASK; > + > + writel(val, reg); > + > + clk_debug("pcc_clock_enable: val 0x%x\n", val); > + > + return 0; > +} > + > +/* The clock source select needs clock is disabled */ > +int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src) > +{ > + u32 reg, val, i, clksrc_type; > + > + if (clk >= ARRAY_SIZE(pcc_arrays)) > + return -EINVAL; > + > + clksrc_type = pcc_arrays[clk].clksrc; > + if (clksrc_type >= CLKSRC_NO_PCS) { > + printf("No PCS field for the PCC %d, clksrc type %d\n", > + clk, clksrc_type); > + return -EPERM; > + } > + > + for (i = 0; i < PCC_CLKSRC_NUM; i++) { > + if (pcc_clksrc[clksrc_type][i] == src) { > + /* Find the clock src, then set it to PCS */ > + break; > + } > + } > + > + if (i == PCC_CLKSRC_NUM) { > + printf("Not find the parent scg_clk in PCS of PCC %d, invalid scg_clk %d\n", clk, src); > + return -EINVAL; > + } > + > + reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; > + > + val = readl(reg); > + > + clk_debug("pcc_clock_sel: clk %d, reg 0x%x, val 0x%x, clksrc_type %d\n", > + clk, reg, val, clksrc_type); > + > + if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) || > + (val & PCC_CGC_MASK)) { > + printf("Not permit to select clock source val = 0x%x\n", val); > + return -EPERM; > + } > + > + val &= ~PCC_PCS_MASK; > + val |= ((i + 1) << PCC_PCS_OFFSET); > + > + writel(val, reg); > + > + clk_debug("pcc_clock_sel: val 0x%x\n", val); > + > + return 0; > +} > + > +int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div) > +{ > + u32 reg, val; > + > + if (clk >= ARRAY_SIZE(pcc_arrays) || div > 8 || > + (div == 1 && frac != 0)) > + return -EINVAL; > + > + if (pcc_arrays[clk].div >= PCC_NO_DIV) { > + printf("No DIV/FRAC field for the PCC %d\n", clk); > + return -EPERM; > + } > + > + reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; > + > + val = readl(reg); > + > + if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) || > + (val & PCC_CGC_MASK)) { > + printf("Not permit to set div/frac val = 0x%x\n", val); > + return -EPERM; > + } > + > + if (frac) > + val |= PCC_FRAC_MASK; > + else > + val &= ~PCC_FRAC_MASK; > + > + val &= ~PCC_PCD_MASK; > + val |= (div - 1) & PCC_PCD_MASK; > + > + writel(val, reg); > + > + return 0; > +} > + > +bool pcc_clock_is_enable(enum pcc_clk clk) > +{ > + u32 reg, val; > + > + if (clk >= ARRAY_SIZE(pcc_arrays)) > + return -EINVAL; > + > + reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; > + val = readl(reg); > + > + if ((val & PCC_INUSE_MASK) || (val & PCC_CGC_MASK)) > + return true; > + > + return false; > +} > + > +int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src) > +{ > + u32 reg, val, clksrc_type; > + > + if (clk >= ARRAY_SIZE(pcc_arrays)) > + return -EINVAL; > + > + clksrc_type = pcc_arrays[clk].clksrc; > + if (clksrc_type >= CLKSRC_NO_PCS) { > + printf("No PCS field for the PCC %d, clksrc type %d\n", > + clk, clksrc_type); > + return -EPERM; > + } > + > + reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; > + > + val = readl(reg); > + > + clk_debug("pcc_clock_get_clksrc: clk %d, reg 0x%x, val 0x%x, type %d\n", > + clk, reg, val, clksrc_type); > + > + if (!(val & PCC_PR_MASK)) { > + printf("This pcc slot is not present = 0x%x\n", val); > + return -EPERM; > + } > + > + val &= PCC_PCS_MASK; > + val = (val >> PCC_PCS_OFFSET); > + > + if (!val) { > + printf("Clock source is off\n"); > + return -EIO; > + } > + > + *src = pcc_clksrc[clksrc_type][val - 1]; > + > + clk_debug("pcc_clock_get_clksrc: parent scg clk %d\n", *src); > + > + return 0; > +} > + > +u32 pcc_clock_get_rate(enum pcc_clk clk) > +{ > + u32 reg, val, rate, frac, div; > + enum scg_clk parent; > + int ret; > + > + ret = pcc_clock_get_clksrc(clk, &parent); > + if (ret) > + return 0; > + > + rate = scg_clk_get_rate(parent); > + > + clk_debug("pcc_clock_get_rate: parent rate %u\n", rate); > + > + if (pcc_arrays[clk].div == PCC_HAS_DIV) { > + reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4; > + val = readl(reg); > + > + frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET; > + div = (val & PCC_PCD_MASK) >> PCC_PCD_OFFSET; > + > + /* > + * Theoretically don't have overflow in the calc, > + * the rate won't exceed 2G > + */ > + rate = rate * (frac + 1) / (div + 1); > + } > + > + clk_debug("pcc_clock_get_rate: rate %u\n", rate); > + return rate; > +} > diff --git a/arch/arm/cpu/armv7/mx7ulp/scg.c b/arch/arm/cpu/armv7/mx7ulp/scg.c > new file mode 100644 > index 0000000..7bbde58 > --- /dev/null > +++ b/arch/arm/cpu/armv7/mx7ulp/scg.c > @@ -0,0 +1,1086 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <div64.h> > +#include <asm/io.h> > +#include <errno.h> > +#include <asm/arch/imx-regs.h> > +#include <asm/arch/pcc.h> > +#include <asm/arch/sys_proto.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +scg_p scg1_regs = (scg_p)SCG1_RBASE; > + > +static u32 scg_src_get_rate(enum scg_clk clksrc) > +{ > + u32 reg; > + > + switch (clksrc) { > + case SCG_SOSC_CLK: > + reg = readl(&scg1_regs->sosccsr); > + if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK)) > + return 0; > + > + return 24000000; > + case SCG_FIRC_CLK: > + reg = readl(&scg1_regs->firccsr); > + if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK)) > + return 0; > + > + return 48000000; > + case SCG_SIRC_CLK: > + reg = readl(&scg1_regs->sirccsr); > + if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK)) > + return 0; > + > + return 16000000; > + case SCG_ROSC_CLK: > + reg = readl(&scg1_regs->rtccsr); > + if (!(reg & SCG_ROSC_CSR_ROSCVLD_MASK)) > + return 0; > + > + return 32768; > + default: > + break; > + } > + > + return 0; > +} > + > +static u32 scg_sircdiv_get_rate(enum scg_clk clk) > +{ > + u32 reg, val, rate; > + u32 shift, mask; > + > + switch (clk) { > + case SCG_SIRC_DIV1_CLK: > + mask = SCG_SIRCDIV_DIV1_MASK; > + shift = SCG_SIRCDIV_DIV1_SHIFT; > + break; > + case SCG_SIRC_DIV2_CLK: > + mask = SCG_SIRCDIV_DIV2_MASK; > + shift = SCG_SIRCDIV_DIV2_SHIFT; > + break; > + case SCG_SIRC_DIV3_CLK: > + mask = SCG_SIRCDIV_DIV3_MASK; > + shift = SCG_SIRCDIV_DIV3_SHIFT; > + break; > + default: > + return 0; > + } > + > + reg = readl(&scg1_regs->sirccsr); > + if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK)) > + return 0; > + > + reg = readl(&scg1_regs->sircdiv); > + val = (reg & mask) >> shift; > + > + if (!val) /*clock disabled*/ > + return 0; > + > + rate = scg_src_get_rate(SCG_SIRC_CLK); > + rate = rate / (1 << (val - 1)); > + > + return rate; > +} > + > +static u32 scg_fircdiv_get_rate(enum scg_clk clk) > +{ > + u32 reg, val, rate; > + u32 shift, mask; > + > + switch (clk) { > + case SCG_FIRC_DIV1_CLK: > + mask = SCG_FIRCDIV_DIV1_MASK; > + shift = SCG_FIRCDIV_DIV1_SHIFT; > + break; > + case SCG_FIRC_DIV2_CLK: > + mask = SCG_FIRCDIV_DIV2_MASK; > + shift = SCG_FIRCDIV_DIV2_SHIFT; > + break; > + case SCG_FIRC_DIV3_CLK: > + mask = SCG_FIRCDIV_DIV3_MASK; > + shift = SCG_FIRCDIV_DIV3_SHIFT; > + break; > + default: > + return 0; > + } > + > + reg = readl(&scg1_regs->firccsr); > + if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK)) > + return 0; > + > + reg = readl(&scg1_regs->fircdiv); > + val = (reg & mask) >> shift; > + > + if (!val) /*clock disabled*/ > + return 0; > + > + rate = scg_src_get_rate(SCG_FIRC_CLK); > + rate = rate / (1 << (val - 1)); > + > + return rate; > +} > + > +static u32 scg_soscdiv_get_rate(enum scg_clk clk) > +{ > + u32 reg, val, rate; > + u32 shift, mask; > + > + switch (clk) { > + case SCG_SOSC_DIV1_CLK: > + mask = SCG_SOSCDIV_DIV1_MASK; > + shift = SCG_SOSCDIV_DIV1_SHIFT; > + break; > + case SCG_SOSC_DIV2_CLK: > + mask = SCG_SOSCDIV_DIV2_MASK; > + shift = SCG_SOSCDIV_DIV2_SHIFT; > + break; > + case SCG_SOSC_DIV3_CLK: > + mask = SCG_SOSCDIV_DIV3_MASK; > + shift = SCG_SOSCDIV_DIV3_SHIFT; > + break; > + default: > + return 0; > + } > + > + reg = readl(&scg1_regs->sosccsr); > + if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK)) > + return 0; > + > + reg = readl(&scg1_regs->soscdiv); > + val = (reg & mask) >> shift; > + > + if (!val) /*clock disabled*/ > + return 0; > + > + rate = scg_src_get_rate(SCG_SOSC_CLK); > + rate = rate / (1 << (val - 1)); > + > + return rate; > +} > + > +static u32 scg_apll_pfd_get_rate(enum scg_clk clk) > +{ > + u32 reg, val, rate; > + u32 shift, mask, gate, valid; > + > + switch (clk) { > + case SCG_APLL_PFD0_CLK: > + gate = SCG_PLL_PFD0_GATE_MASK; > + valid = SCG_PLL_PFD0_VALID_MASK; > + mask = SCG_PLL_PFD0_FRAC_MASK; > + shift = SCG_PLL_PFD0_FRAC_SHIFT; > + break; > + case SCG_APLL_PFD1_CLK: > + gate = SCG_PLL_PFD1_GATE_MASK; > + valid = SCG_PLL_PFD1_VALID_MASK; > + mask = SCG_PLL_PFD1_FRAC_MASK; > + shift = SCG_PLL_PFD1_FRAC_SHIFT; > + break; > + case SCG_APLL_PFD2_CLK: > + gate = SCG_PLL_PFD2_GATE_MASK; > + valid = SCG_PLL_PFD2_VALID_MASK; > + mask = SCG_PLL_PFD2_FRAC_MASK; > + shift = SCG_PLL_PFD2_FRAC_SHIFT; > + break; > + case SCG_APLL_PFD3_CLK: > + gate = SCG_PLL_PFD3_GATE_MASK; > + valid = SCG_PLL_PFD3_VALID_MASK; > + mask = SCG_PLL_PFD3_FRAC_MASK; > + shift = SCG_PLL_PFD3_FRAC_SHIFT; > + break; > + default: > + return 0; > + } > + > + reg = readl(&scg1_regs->apllpfd); > + if (reg & gate || !(reg & valid)) > + return 0; > + > + clk_debug("scg_apll_pfd_get_rate reg 0x%x\n", reg); > + > + val = (reg & mask) >> shift; > + rate = decode_pll(PLL_A7_APLL); > + > + rate = rate / val * 18; > + > + clk_debug("scg_apll_pfd_get_rate rate %u\n", rate); > + > + return rate; > +} > + > +static u32 scg_spll_pfd_get_rate(enum scg_clk clk) > +{ > + u32 reg, val, rate; > + u32 shift, mask, gate, valid; > + > + switch (clk) { > + case SCG_SPLL_PFD0_CLK: > + gate = SCG_PLL_PFD0_GATE_MASK; > + valid = SCG_PLL_PFD0_VALID_MASK; > + mask = SCG_PLL_PFD0_FRAC_MASK; > + shift = SCG_PLL_PFD0_FRAC_SHIFT; > + break; > + case SCG_SPLL_PFD1_CLK: > + gate = SCG_PLL_PFD1_GATE_MASK; > + valid = SCG_PLL_PFD1_VALID_MASK; > + mask = SCG_PLL_PFD1_FRAC_MASK; > + shift = SCG_PLL_PFD1_FRAC_SHIFT; > + break; > + case SCG_SPLL_PFD2_CLK: > + gate = SCG_PLL_PFD2_GATE_MASK; > + valid = SCG_PLL_PFD2_VALID_MASK; > + mask = SCG_PLL_PFD2_FRAC_MASK; > + shift = SCG_PLL_PFD2_FRAC_SHIFT; > + break; > + case SCG_SPLL_PFD3_CLK: > + gate = SCG_PLL_PFD3_GATE_MASK; > + valid = SCG_PLL_PFD3_VALID_MASK; > + mask = SCG_PLL_PFD3_FRAC_MASK; > + shift = SCG_PLL_PFD3_FRAC_SHIFT; > + break; > + default: > + return 0; > + } > + > + reg = readl(&scg1_regs->spllpfd); > + if (reg & gate || !(reg & valid)) > + return 0; > + > + clk_debug("scg_spll_pfd_get_rate reg 0x%x\n", reg); > + > + val = (reg & mask) >> shift; > + rate = decode_pll(PLL_A7_SPLL); > + > + rate = rate / val * 18; > + > + clk_debug("scg_spll_pfd_get_rate rate %u\n", rate); > + > + return rate; > +} > + > +static u32 scg_apll_get_rate(void) > +{ > + u32 reg, val, rate; > + > + reg = readl(&scg1_regs->apllcfg); > + val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT; > + > + if (!val) { > + /* APLL clock after two dividers */ > + rate = decode_pll(PLL_A7_APLL); > + > + val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >> > + SCG_PLL_CFG_POSTDIV1_SHIFT; > + rate = rate / (val + 1); > + > + val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >> > + SCG_PLL_CFG_POSTDIV2_SHIFT; > + rate = rate / (val + 1); > + } else { > + /* APLL PFD clock */ > + val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >> > + SCG_PLL_CFG_PFDSEL_SHIFT; > + rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val); > + } > + > + return rate; > +} > + > +static u32 scg_spll_get_rate(void) > +{ > + u32 reg, val, rate; > + > + reg = readl(&scg1_regs->spllcfg); > + val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT; > + > + clk_debug("scg_spll_get_rate reg 0x%x\n", reg); > + > + if (!val) { > + /* APLL clock after two dividers */ > + rate = decode_pll(PLL_A7_SPLL); > + > + val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >> > + SCG_PLL_CFG_POSTDIV1_SHIFT; > + rate = rate / (val + 1); > + > + val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >> > + SCG_PLL_CFG_POSTDIV2_SHIFT; > + rate = rate / (val + 1); > + > + clk_debug("scg_spll_get_rate SPLL %u\n", rate); > + > + } else { > + /* APLL PFD clock */ > + val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >> > + SCG_PLL_CFG_PFDSEL_SHIFT; > + rate = scg_spll_pfd_get_rate(SCG_SPLL_PFD0_CLK + val); > + > + clk_debug("scg_spll_get_rate PFD %u\n", rate); > + } > + > + return rate; > +} > + > +static u32 scg_ddr_get_rate(void) > +{ > + u32 reg, val, rate, div; > + > + reg = readl(&scg1_regs->ddrccr); > + val = (reg & SCG_DDRCCR_DDRCS_MASK) >> SCG_DDRCCR_DDRCS_SHIFT; > + div = (reg & SCG_DDRCCR_DDRDIV_MASK) >> SCG_DDRCCR_DDRDIV_SHIFT; > + > + if (!div) > + return 0; > + > + if (!val) { > + reg = readl(&scg1_regs->apllcfg); > + val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >> > + SCG_PLL_CFG_PFDSEL_SHIFT; > + rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val); > + } else { > + rate = decode_pll(PLL_USB); > + } > + > + rate = rate / (1 << (div - 1)); > + return rate; > +} > + > +static u32 scg_nic_get_rate(enum scg_clk clk) > +{ > + u32 reg, val, rate; > + u32 shift, mask; > + > + reg = readl(&scg1_regs->niccsr); > + val = (reg & SCG_NICCSR_NICCS_MASK) >> SCG_NICCSR_NICCS_SHIFT; > + > + clk_debug("scg_nic_get_rate niccsr 0x%x\n", reg); > + > + if (!val) > + rate = scg_src_get_rate(SCG_FIRC_CLK); > + else > + rate = scg_ddr_get_rate(); > + > + clk_debug("scg_nic_get_rate parent rate %u\n", rate); > + > + val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT; > + > + rate = rate / (val + 1); > + > + clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate); > + > + switch (clk) { > + case SCG_NIC0_CLK: > + return rate; > + case SCG_GPU_CLK: > + mask = SCG_NICCSR_GPUDIV_MASK; > + shift = SCG_NICCSR_GPUDIV_SHIFT; > + break; > + case SCG_NIC1_EXT_CLK: > + case SCG_NIC1_BUS_CLK: > + case SCG_NIC1_CLK: > + mask = SCG_NICCSR_NIC1DIV_MASK; > + shift = SCG_NICCSR_NIC1DIV_SHIFT; > + break; > + default: > + return 0; > + } > + > + val = (reg & mask) >> shift; > + rate = rate / (val + 1); > + > + clk_debug("scg_nic_get_rate NIC1 rate %u\n", rate); > + > + switch (clk) { > + case SCG_GPU_CLK: > + case SCG_NIC1_CLK: > + return rate; > + case SCG_NIC1_EXT_CLK: > + mask = SCG_NICCSR_NIC1EXTDIV_MASK; > + shift = SCG_NICCSR_NIC1EXTDIV_SHIFT; > + break; > + case SCG_NIC1_BUS_CLK: > + mask = SCG_NICCSR_NIC1BUSDIV_MASK; > + shift = SCG_NICCSR_NIC1BUSDIV_SHIFT; > + break; > + default: > + return 0; > + } > + > + val = (reg & mask) >> shift; > + rate = rate / (val + 1); > + > + clk_debug("scg_nic_get_rate NIC1 bus rate %u\n", rate); > + return rate; > +} > + > + > +static enum scg_clk scg_scs_array[4] = { > + SCG_SOSC_CLK, SCG_SIRC_CLK, SCG_FIRC_CLK, SCG_ROSC_CLK, > +}; > + > +static u32 scg_sys_get_rate(enum scg_clk clk) > +{ > + u32 reg, val, rate; > + > + if (clk != SCG_CORE_CLK && clk != SCG_BUS_CLK) > + return 0; > + > + reg = readl(&scg1_regs->csr); > + val = (reg & SCG_CCR_SCS_MASK) >> SCG_CCR_SCS_SHIFT; > + > + clk_debug("scg_sys_get_rate reg 0x%x\n", reg); > + > + switch (val) { > + case SCG_SCS_SYS_OSC: > + case SCG_SCS_SLOW_IRC: > + case SCG_SCS_FAST_IRC: > + case SCG_SCS_RTC_OSC: > + rate = scg_src_get_rate(scg_scs_array[val]); > + break; > + case 5: > + rate = scg_apll_get_rate(); > + break; > + case 6: > + rate = scg_spll_get_rate(); > + break; > + default: > + return 0; > + } > + > + clk_debug("scg_sys_get_rate parent rate %u\n", rate); > + > + val = (reg & SCG_CCR_DIVCORE_MASK) >> SCG_CCR_DIVCORE_SHIFT; > + > + rate = rate / (val + 1); > + > + if (clk == SCG_BUS_CLK) { > + val = (reg & SCG_CCR_DIVBUS_MASK) >> SCG_CCR_DIVBUS_SHIFT; > + rate = rate / (val + 1); > + } > + > + return rate; > +} > + > +u32 decode_pll(enum pll_clocks pll) > +{ > + u32 reg, pre_div, infreq, mult; > + u32 num, denom; > + > + /* > + * Alought there are four choices for the bypass src, > + * we choose OSC_24M which is the default set in ROM. > + */ > + switch (pll) { > + case PLL_A7_SPLL: > + reg = readl(&scg1_regs->spllcsr); > + > + if (!(reg & SCG_SPLL_CSR_SPLLVLD_MASK)) > + return 0; > + > + reg = readl(&scg1_regs->spllcfg); > + > + pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >> > + SCG_PLL_CFG_PREDIV_SHIFT; > + pre_div += 1; > + > + mult = (reg & SCG1_SPLL_CFG_MULT_MASK) >> > + SCG_PLL_CFG_MULT_SHIFT; > + > + infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >> > + SCG_PLL_CFG_CLKSRC_SHIFT; > + if (!infreq) > + infreq = scg_src_get_rate(SCG_SOSC_CLK); > + else > + infreq = scg_src_get_rate(SCG_FIRC_CLK); > + > + num = readl(&scg1_regs->spllnum); > + denom = readl(&scg1_regs->splldenom); > + > + return (infreq / pre_div) * (mult + num / denom); > + > + case PLL_A7_APLL: > + reg = readl(&scg1_regs->apllcsr); > + > + if (!(reg & SCG_APLL_CSR_APLLVLD_MASK)) > + return 0; > + > + reg = readl(&scg1_regs->apllcfg); > + > + pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >> > + SCG_PLL_CFG_PREDIV_SHIFT; > + pre_div += 1; > + > + mult = (reg & SCG_APLL_CFG_MULT_MASK) >> > + SCG_PLL_CFG_MULT_SHIFT; > + > + infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >> > + SCG_PLL_CFG_CLKSRC_SHIFT; > + if (!infreq) > + infreq = scg_src_get_rate(SCG_SOSC_CLK); > + else > + infreq = scg_src_get_rate(SCG_FIRC_CLK); > + > + num = readl(&scg1_regs->apllnum); > + denom = readl(&scg1_regs->aplldenom); > + > + return (infreq / pre_div) * (mult + num / denom); > + > + case PLL_USB: > + reg = readl(&scg1_regs->upllcsr); > + > + if (!(reg & SCG_UPLL_CSR_UPLLVLD_MASK)) > + return 0; > + > + return 480000000u; > + > + case PLL_MIPI: > + return 480000000u; > + default: > + printf("Unsupported pll clocks %d\n", pll); > + break; > + } > + > + return 0; > +} > + > +u32 scg_clk_get_rate(enum scg_clk clk) > +{ > + switch (clk) { > + case SCG_SIRC_DIV1_CLK: > + case SCG_SIRC_DIV2_CLK: > + case SCG_SIRC_DIV3_CLK: > + return scg_sircdiv_get_rate(clk); > + > + case SCG_FIRC_DIV1_CLK: > + case SCG_FIRC_DIV2_CLK: > + case SCG_FIRC_DIV3_CLK: > + return scg_fircdiv_get_rate(clk); > + > + case SCG_SOSC_DIV1_CLK: > + case SCG_SOSC_DIV2_CLK: > + case SCG_SOSC_DIV3_CLK: > + return scg_soscdiv_get_rate(clk); > + > + case SCG_CORE_CLK: > + case SCG_BUS_CLK: > + return scg_sys_get_rate(clk); > + > + case SCG_SPLL_PFD0_CLK: > + case SCG_SPLL_PFD1_CLK: > + case SCG_SPLL_PFD2_CLK: > + case SCG_SPLL_PFD3_CLK: > + return scg_spll_pfd_get_rate(clk); > + > + case SCG_APLL_PFD0_CLK: > + case SCG_APLL_PFD1_CLK: > + case SCG_APLL_PFD2_CLK: > + case SCG_APLL_PFD3_CLK: > + return scg_apll_pfd_get_rate(clk); > + > + case SCG_DDR_CLK: > + return scg_ddr_get_rate(); > + > + case SCG_NIC0_CLK: > + case SCG_GPU_CLK: > + case SCG_NIC1_CLK: > + case SCG_NIC1_BUS_CLK: > + case SCG_NIC1_EXT_CLK: > + return scg_nic_get_rate(clk); > + > + case USB_PLL_OUT: > + return decode_pll(PLL_USB); > + > + case MIPI_PLL_OUT: > + return decode_pll(PLL_MIPI); > + > + case SCG_SOSC_CLK: > + case SCG_FIRC_CLK: > + case SCG_SIRC_CLK: > + case SCG_ROSC_CLK: > + return scg_src_get_rate(clk); > + default: > + return 0; > + } > +} > + > +int scg_enable_pll_pfd(enum scg_clk clk, u32 frac) > +{ > + u32 reg; > + u32 shift, mask, gate, valid; > + u32 addr; > + > + if (frac < 12 || frac > 35) > + return -EINVAL; > + > + switch (clk) { > + case SCG_SPLL_PFD0_CLK: > + case SCG_APLL_PFD0_CLK: > + gate = SCG_PLL_PFD0_GATE_MASK; > + valid = SCG_PLL_PFD0_VALID_MASK; > + mask = SCG_PLL_PFD0_FRAC_MASK; > + shift = SCG_PLL_PFD0_FRAC_SHIFT; > + > + if (clk == SCG_SPLL_PFD0_CLK) > + addr = (u32)(&scg1_regs->spllpfd); > + else > + addr = (u32)(&scg1_regs->apllpfd); > + break; > + case SCG_SPLL_PFD1_CLK: > + case SCG_APLL_PFD1_CLK: > + gate = SCG_PLL_PFD1_GATE_MASK; > + valid = SCG_PLL_PFD1_VALID_MASK; > + mask = SCG_PLL_PFD1_FRAC_MASK; > + shift = SCG_PLL_PFD1_FRAC_SHIFT; > + > + if (clk == SCG_SPLL_PFD1_CLK) > + addr = (u32)(&scg1_regs->spllpfd); > + else > + addr = (u32)(&scg1_regs->apllpfd); > + break; > + case SCG_SPLL_PFD2_CLK: > + case SCG_APLL_PFD2_CLK: > + gate = SCG_PLL_PFD2_GATE_MASK; > + valid = SCG_PLL_PFD2_VALID_MASK; > + mask = SCG_PLL_PFD2_FRAC_MASK; > + shift = SCG_PLL_PFD2_FRAC_SHIFT; > + > + if (clk == SCG_SPLL_PFD2_CLK) > + addr = (u32)(&scg1_regs->spllpfd); > + else > + addr = (u32)(&scg1_regs->apllpfd); > + break; > + case SCG_SPLL_PFD3_CLK: > + case SCG_APLL_PFD3_CLK: > + gate = SCG_PLL_PFD3_GATE_MASK; > + valid = SCG_PLL_PFD3_VALID_MASK; > + mask = SCG_PLL_PFD3_FRAC_MASK; > + shift = SCG_PLL_PFD3_FRAC_SHIFT; > + > + if (clk == SCG_SPLL_PFD3_CLK) > + addr = (u32)(&scg1_regs->spllpfd); > + else > + addr = (u32)(&scg1_regs->apllpfd); > + break; > + default: > + return -EINVAL; > + } > + > + /* Gate the PFD */ > + reg = readl(addr); > + reg |= gate; > + writel(reg, addr); > + > + /* Write Frac divider */ > + reg &= ~mask; > + reg |= (frac << shift) & mask; > + writel(reg, addr); > + > + /* > + * Un-gate the PFD > + * (Need un-gate before checking valid, not align with RM) > + */ > + reg &= ~gate; > + writel(reg, addr); > + > + /* Wait for PFD clock being valid */ > + do { > + reg = readl(addr); > + } while (!(reg & valid)); > + > + return 0; > +} > + > +#define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2) > +int scg_enable_usb_pll(bool usb_control) > +{ > + u32 sosc_rate; > + s32 timeout = 1000000; > + u32 reg; > + > + struct usbphy_regs *usbphy = > + (struct usbphy_regs *)USBPHY_RBASE; > + > + sosc_rate = scg_src_get_rate(SCG_SOSC_CLK); > + if (!sosc_rate) > + return -EPERM; > + > + reg = readl(SIM0_RBASE + 0x3C); > + if (usb_control) > + reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK; > + else > + reg |= SIM_MISC_CTRL0_USB_PLL_EN_MASK; > + writel(reg, SIM0_RBASE + 0x3C); > + > + if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) { > + writel(0x1c00000, &usbphy->usb1_pll_480_ctrl_clr); > + > + switch (sosc_rate) { > + case 24000000: > + writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set); > + break; > + > + case 30000000: > + writel(0x800000, &usbphy->usb1_pll_480_ctrl_set); > + break; > + > + case 19200000: > + writel(0x1400000, &usbphy->usb1_pll_480_ctrl_set); > + break; > + > + default: > + writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set); > + break; > + } > + > + /* Enable the regulator first */ > + writel(PLL_USB_REG_ENABLE_MASK, > + &usbphy->usb1_pll_480_ctrl_set); > + > + /* Wait at least 15us */ > + udelay(15); > + > + /* Enable the power */ > + writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set); > + > + /* Wait lock */ > + while (timeout--) { > + if (readl(&usbphy->usb1_pll_480_ctrl) & > + PLL_USB_LOCK_MASK) > + break; > + } > + > + if (timeout <= 0) { > + /* If timeout, we power down the pll */ > + writel(PLL_USB_PWR_MASK, > + &usbphy->usb1_pll_480_ctrl_clr); > + return -ETIME; > + } > + } > + > + /* Clear the bypass */ > + writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr); > + > + /* Enable the PLL clock out to USB */ > + writel((PLL_USB_EN_USB_CLKS_MASK | PLL_USB_ENABLE_MASK), > + &usbphy->usb1_pll_480_ctrl_set); > + > + if (!usb_control) { > + while (timeout--) { > + if (readl(&scg1_regs->upllcsr) & > + SCG_UPLL_CSR_UPLLVLD_MASK) > + break; > + } > + > + if (timeout <= 0) { > + reg = readl(SIM0_RBASE + 0x3C); > + reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK; > + writel(reg, SIM0_RBASE + 0x3C); > + return -ETIME; > + } > + } > + > + return 0; > +} > + > + > +/* A7 domain system clock source is SPLL */ > +#define SCG1_RCCR_SCS_NUM ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT) > + > +/* A7 Core clck = SPLL PFD0 / 1 = 500MHz / 1 = 500MHz */ > +#define SCG1_RCCR_DIVCORE_NUM ((0x0) << SCG_CCR_DIVCORE_SHIFT) > +#define SCG1_RCCR_CFG_MASK (SCG_CCR_SCS_MASK | SCG_CCR_DIVBUS_MASK) > + > +/* A7 Plat clck = A7 Core Clock / 2 = 250MHz / 1 = 250MHz */ > +#define SCG1_RCCR_DIVBUS_NUM ((0x1) << SCG_CCR_DIVBUS_SHIFT) > +#define SCG1_RCCR_CFG_NUM (SCG1_RCCR_SCS_NUM | SCG1_RCCR_DIVBUS_NUM) > + > +void scg_a7_rccr_init(void) > +{ > + u32 rccr_reg_val = 0; > + > + rccr_reg_val = readl(&scg1_regs->rccr); > + > + rccr_reg_val &= (~SCG1_RCCR_CFG_MASK); > + rccr_reg_val |= (SCG1_RCCR_CFG_NUM); > + > + writel(rccr_reg_val, &scg1_regs->rccr); > +} > + > +/* POSTDIV2 = 1 */ > +#define SCG1_SPLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT) > +/* POSTDIV1 = 1 */ > +#define SCG1_SPLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT) > + > +/* MULT = 22 */ > +#define SCG1_SPLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT) > + > +/* PFD0 output clock selected */ > +#define SCG1_SPLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT) > +/* PREDIV = 1 */ > +#define SCG1_SPLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT) > +/* SPLL output clocks (including PFD outputs) selected */ > +#define SCG1_SPLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT) > +/* SPLL PFD output clock selected */ > +#define SCG1_SPLL_CFG_PLLSEL_NUM ((0x1) << SCG_PLL_CFG_PLLSEL_SHIFT) > +/* Clock source is System OSC */ > +#define SCG1_SPLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT) > +#define SCG1_SPLL_CFG_NUM_24M_OSC (SCG1_SPLL_CFG_POSTDIV2_NUM | \ > + SCG1_SPLL_CFG_POSTDIV1_NUM | \ > + (22 << SCG_PLL_CFG_MULT_SHIFT) | \ > + SCG1_SPLL_CFG_PFDSEL_NUM | \ > + SCG1_SPLL_CFG_PREDIV_NUM | \ > + SCG1_SPLL_CFG_BYPASS_NUM | \ > + SCG1_SPLL_CFG_PLLSEL_NUM | \ > + SCG1_SPLL_CFG_CLKSRC_NUM) > +/*413Mhz = A7 SPLL(528MHz) * 18/23 */ > +#define SCG1_SPLL_PFD0_FRAC_NUM ((23) << SCG_PLL_PFD0_FRAC_SHIFT) > + > +void scg_a7_spll_init(void) > +{ > + u32 val = 0; > + > + /* Disable A7 System PLL */ > + val = readl(&scg1_regs->spllcsr); > + val &= ~SCG_SPLL_CSR_SPLLEN_MASK; > + writel(val, &scg1_regs->spllcsr); > + > + /* > + * Per block guide, > + * "When changing PFD values, it is recommneded PFDx clock > + * gets gated first by writing a value of 1 to PFDx_CLKGATE register, > + * then program the new PFD value, then poll the PFDx_VALID > + * flag to set before writing a value of 0 to PFDx_CLKGATE > + * to ungate the PFDx clock and allow PFDx clock to run" > + */ > + > + /* Gate off A7 SPLL PFD0 ~ PDF4 */ > + val = readl(&scg1_regs->spllpfd); > + val |= (SCG_PLL_PFD3_GATE_MASK | > + SCG_PLL_PFD2_GATE_MASK | > + SCG_PLL_PFD1_GATE_MASK | > + SCG_PLL_PFD0_GATE_MASK); > + writel(val, &scg1_regs->spllpfd); > + > + /* ================ A7 SPLL Configuration Start ============== */ > + > + /* Configure A7 System PLL */ > + writel(SCG1_SPLL_CFG_NUM_24M_OSC, &scg1_regs->spllcfg); > + > + /* Enable A7 System PLL */ > + val = readl(&scg1_regs->spllcsr); > + val |= SCG_SPLL_CSR_SPLLEN_MASK; > + writel(val, &scg1_regs->spllcsr); > + > + /* Wait for A7 SPLL clock ready */ > + while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK)) > + ; > + > + /* Configure A7 SPLL PFD0 */ > + val = readl(&scg1_regs->spllpfd); > + val &= ~SCG_PLL_PFD0_FRAC_MASK; > + val |= SCG1_SPLL_PFD0_FRAC_NUM; > + writel(val, &scg1_regs->spllpfd); > + > + /* Un-gate A7 SPLL PFD0 */ > + val = readl(&scg1_regs->spllpfd); > + val &= ~SCG_PLL_PFD0_GATE_MASK; > + writel(val, &scg1_regs->spllpfd); > + > + /* Wait for A7 SPLL PFD0 clock being valid */ > + while (!(readl(&scg1_regs->spllpfd) & SCG_PLL_PFD0_VALID_MASK)) > + ; > + > + /* ================ A7 SPLL Configuration End ============== */ > +} > + > +/* DDR clock source is APLL PFD0 (396MHz) */ > +#define SCG1_DDRCCR_DDRCS_NUM ((0x0) << SCG_DDRCCR_DDRCS_SHIFT) > +/* DDR clock = APLL PFD0 / 1 = 396MHz / 1 = 396MHz */ > +#define SCG1_DDRCCR_DDRDIV_NUM ((0x1) << SCG_DDRCCR_DDRDIV_SHIFT) > +/* DDR clock = APLL PFD0 / 2 = 396MHz / 2 = 198MHz */ > +#define SCG1_DDRCCR_DDRDIV_LF_NUM ((0x2) << SCG_DDRCCR_DDRDIV_SHIFT) > +#define SCG1_DDRCCR_CFG_NUM (SCG1_DDRCCR_DDRCS_NUM | \ > + SCG1_DDRCCR_DDRDIV_NUM) > +#define SCG1_DDRCCR_CFG_LF_NUM (SCG1_DDRCCR_DDRCS_NUM | \ > + SCG1_DDRCCR_DDRDIV_LF_NUM) > +void scg_a7_ddrclk_init(void) > +{ > + writel(SCG1_DDRCCR_CFG_NUM, &scg1_regs->ddrccr); > +} > + > +/* SCG1(A7) APLLCFG configurations */ > +/* divide by 1 <<28 */ > +#define SCG1_APLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT) > +/* divide by 1 <<24 */ > +#define SCG1_APLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT) > +/* MULT is 22 <<16 */ > +#define SCG1_APLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT) > +/* PFD0 output clock selected <<14 */ > +#define SCG1_APLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT) > +/* PREDIV = 1 <<8 */ > +#define SCG1_APLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT) > +/* APLL output clocks (including PFD outputs) selected <<2 */ > +#define SCG1_APLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT) > +/* APLL PFD output clock selected <<1 */ > +#define SCG1_APLL_CFG_PLLSEL_NUM ((0x0) << SCG_PLL_CFG_PLLSEL_SHIFT) > +/* Clock source is System OSC <<0 */ > +#define SCG1_APLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT) > + > +/* > + * A7 APLL = 24MHz / 1 * 22 / 1 / 1 = 528MHz, > + * system PLL is sourced from APLL, > + * APLL clock source is system OSC (24MHz) > + */ > +#define SCG1_APLL_CFG_NUM_24M_OSC (SCG1_APLL_CFG_POSTDIV2_NUM | \ > + SCG1_APLL_CFG_POSTDIV1_NUM | \ > + (22 << SCG_PLL_CFG_MULT_SHIFT) | \ > + SCG1_APLL_CFG_PFDSEL_NUM | \ > + SCG1_APLL_CFG_PREDIV_NUM | \ > + SCG1_APLL_CFG_BYPASS_NUM | \ > + SCG1_APLL_CFG_PLLSEL_NUM | \ > + SCG1_APLL_CFG_CLKSRC_NUM) > + > +/* PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz */ > +#define SCG1_APLL_PFD0_FRAC_NUM (27) > + > + > +void scg_a7_apll_init(void) > +{ > + u32 val = 0; > + > + /* Disable A7 Auxiliary PLL */ > + val = readl(&scg1_regs->apllcsr); > + val &= ~SCG_APLL_CSR_APLLEN_MASK; > + writel(val, &scg1_regs->apllcsr); > + > + /* Gate off A7 APLL PFD0 ~ PDF4 */ > + val = readl(&scg1_regs->apllpfd); > + val |= 0x80808080; > + writel(val, &scg1_regs->apllpfd); > + > + /* ================ A7 APLL Configuration Start ============== */ > + /* Configure A7 Auxiliary PLL */ > + writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg); > + > + /* Enable A7 Auxiliary PLL */ > + val = readl(&scg1_regs->apllcsr); > + val |= SCG_APLL_CSR_APLLEN_MASK; > + writel(val, &scg1_regs->apllcsr); > + > + /* Wait for A7 APLL clock ready */ > + while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK)) > + ; > + > + /* Configure A7 APLL PFD0 */ > + val = readl(&scg1_regs->apllpfd); > + val &= ~SCG_PLL_PFD0_FRAC_MASK; > + val |= SCG1_APLL_PFD0_FRAC_NUM; > + writel(val, &scg1_regs->apllpfd); > + > + /* Un-gate A7 APLL PFD0 */ > + val = readl(&scg1_regs->apllpfd); > + val &= ~SCG_PLL_PFD0_GATE_MASK; > + writel(val, &scg1_regs->apllpfd); > + > + /* Wait for A7 APLL PFD0 clock being valid */ > + while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK)) > + ; > +} > + > +/* SCG1(A7) FIRC DIV configurations */ > +/* Disable FIRC DIV3 */ > +#define SCG1_FIRCDIV_DIV3_NUM ((0x0) << SCG_FIRCDIV_DIV3_SHIFT) > +/* FIRC DIV2 = 48MHz / 1 = 48MHz */ > +#define SCG1_FIRCDIV_DIV2_NUM ((0x1) << SCG_FIRCDIV_DIV2_SHIFT) > +/* Disable FIRC DIV1 */ > +#define SCG1_FIRCDIV_DIV1_NUM ((0x0) << SCG_FIRCDIV_DIV1_SHIFT) > + > +void scg_a7_firc_init(void) > +{ > + /* Wait for FIRC clock ready */ > + while (!(readl(&scg1_regs->firccsr) & SCG_FIRC_CSR_FIRCVLD_MASK)) > + ; > + > + /* Configure A7 FIRC DIV1 ~ DIV3 */ > + writel((SCG1_FIRCDIV_DIV3_NUM | > + SCG1_FIRCDIV_DIV2_NUM | > + SCG1_FIRCDIV_DIV1_NUM), &scg1_regs->fircdiv); > +} > + > +/* SCG1(A7) NICCCR configurations */ > +/* NIC clock source is DDR clock (396/198MHz) */ > +#define SCG1_NICCCR_NICCS_NUM ((0x1) << SCG_NICCCR_NICCS_SHIFT) > + > +/* NIC0 clock = DDR Clock / 2 = 396MHz / 2 = 198MHz */ > +#define SCG1_NICCCR_NIC0_DIV_NUM ((0x1) << SCG_NICCCR_NIC0_DIV_SHIFT) > +/* NIC0 clock = DDR Clock / 1 = 198MHz / 1 = 198MHz */ > +#define SCG1_NICCCR_NIC0_DIV_LF_NUM ((0x0) << SCG_NICCCR_NIC0_DIV_SHIFT) > +/* NIC1 clock = NIC0 Clock / 1 = 198MHz / 2 = 198MHz */ > +#define SCG1_NICCCR_NIC1_DIV_NUM ((0x0) << SCG_NICCCR_NIC1_DIV_SHIFT) > +/* NIC1 bus clock = NIC1 Clock / 3 = 198MHz / 3 = 66MHz */ > +#define SCG1_NICCCR_NIC1_DIVBUS_NUM ((0x2) << SCG_NICCCR_NIC1_DIVBUS_SHIFT) > +#define SCG1_NICCCR_CFG_NUM (SCG1_NICCCR_NICCS_NUM | \ > + SCG1_NICCCR_NIC0_DIV_NUM | \ > + SCG1_NICCCR_NIC1_DIV_NUM | \ > + SCG1_NICCCR_NIC1_DIVBUS_NUM) > + > +void scg_a7_nicclk_init(void) > +{ > + writel(SCG1_NICCCR_CFG_NUM, &scg1_regs->nicccr); > +} > + > +/* SCG1(A7) FIRC DIV configurations */ > +/* Enable FIRC DIV3 */ > +#define SCG1_SOSCDIV_DIV3_NUM ((0x1) << SCG_SOSCDIV_DIV3_SHIFT) > +/* FIRC DIV2 = 48MHz / 1 = 48MHz */ > +#define SCG1_SOSCDIV_DIV2_NUM ((0x1) << SCG_SOSCDIV_DIV2_SHIFT) > +/* Enable FIRC DIV1 */ > +#define SCG1_SOSCDIV_DIV1_NUM ((0x1) << SCG_SOSCDIV_DIV1_SHIFT) > + > +void scg_a7_soscdiv_init(void) > +{ > + /* Wait for FIRC clock ready */ > + while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK)) > + ; > + > + /* Configure A7 FIRC DIV1 ~ DIV3 */ > + writel((SCG1_SOSCDIV_DIV3_NUM | SCG1_SOSCDIV_DIV2_NUM | > + SCG1_SOSCDIV_DIV1_NUM), &scg1_regs->soscdiv); > +} > + > +void scg_a7_sys_clk_sel(enum scg_sys_src clk) > +{ > + u32 rccr_reg_val = 0; > + > + clk_debug("%s: system clock selected as %s\n", "[SCG]", > + clk == SCG_SCS_SYS_OSC ? "SYS_OSC" : > + clk == SCG_SCS_SLOW_IRC ? "SLOW_IRC" : > + clk == SCG_SCS_FAST_IRC ? "FAST_IRC" : > + clk == SCG_SCS_RTC_OSC ? "RTC_OSC" : > + clk == SCG_SCS_AUX_PLL ? "AUX_PLL" : > + clk == SCG_SCS_SYS_PLL ? "SYS_PLL" : > + clk == SCG_SCS_USBPHY_PLL ? "USBPHY_PLL" : > + "Invalid source" > + ); > + > + rccr_reg_val = readl(&scg1_regs->rccr); > + rccr_reg_val &= ~SCG_CCR_SCS_MASK; > + rccr_reg_val |= (clk << SCG_CCR_SCS_SHIFT); > + writel(rccr_reg_val, &scg1_regs->rccr); > +} > + > +void scg_a7_info(void) > +{ > + printf("SCG Version: 0x%x\n", readl(&scg1_regs->verid)); > + printf("SCG Parameter: 0x%x\n", readl(&scg1_regs->param)); > + printf("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr)); > + printf("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr)); > +} Is it just for debug ? > diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h > new file mode 100644 > index 0000000..f21052e > --- /dev/null > +++ b/arch/arm/include/asm/arch-mx7ulp/clock.h > @@ -0,0 +1,38 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef _ASM_ARCH_CLOCK_H > +#define _ASM_ARCH_CLOCK_H > + > +#include <common.h> > +#include <asm/arch/pcc.h> > +#include <asm/arch/scg.h> > + > +/* Mainly for compatible to imx common code. */ > +enum mxc_clock { > + MXC_ARM_CLK = 0, > + MXC_AHB_CLK, > + MXC_IPG_CLK, > + MXC_UART_CLK, > + MXC_CSPI_CLK, > + MXC_AXI_CLK, > + MXC_DDR_CLK, > + MXC_ESDHC_CLK, > + MXC_ESDHC2_CLK, > + MXC_I2C_CLK, > +}; > + > +u32 mxc_get_clock(enum mxc_clock clk); > +u32 get_lpuart_clk(void); > +#ifdef CONFIG_MXC_OCOTP > +void enable_ocotp_clk(unsigned char enable); > +#endif > +#ifdef CONFIG_USB_EHCI > +void enable_usboh3_clk(unsigned char enable); > +#endif > +void init_clk_usdhc(u32 index); > +void clock_init(void); > +#endif > diff --git a/arch/arm/include/asm/arch-mx7ulp/pcc.h b/arch/arm/include/asm/arch-mx7ulp/pcc.h > new file mode 100644 > index 0000000..051dcb5 > --- /dev/null > +++ b/arch/arm/include/asm/arch-mx7ulp/pcc.h > @@ -0,0 +1,377 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef _ASM_ARCH_PCC_H > +#define _ASM_ARCH_PCC_H > + > +#include <common.h> > +#include <asm/arch/scg.h> > + > +/* PCC2 */ > + > +/* On-Platform (32 entries) */ > +#define RSVD0_PCC2_SLOT (0) > +#define RSVD1_PCC2_SLOT (1) > +#define CA7_GIC_PCC2_SLOT (2) > +#define RSVD3_PCC2_SLOT (3) > +#define RSVD4_PCC2_SLOT (4) > +#define RSVD5_PCC2_SLOT (5) > +#define RSVD6_PCC2_SLOT (6) > +#define RSVD7_PCC2_SLOT (7) > +#define DMA1_PCC2_SLOT (8) > +#define RSVD9_PCC2_SLOT (9) > +#define RSVD10_PCC2_SLOT (10) > +#define RSVD11_PCC2_SLOT (11) > +#define RSVD12_PCC2_SLOT (12) > +#define RSVD13_PCC2_SLOT (13) > +#define RSVD14_PCC2_SLOT (14) > +#define RGPIO1_PCC2_SLOT (15) > +#define FLEXBUS0_PCC2_SLOT (16) > +#define RSVD17_PCC2_SLOT (17) > +#define RSVD18_PCC2_SLOT (18) > +#define RSVD19_PCC2_SLOT (19) > +#define RSVD20_PCC2_SLOT (20) > +#define RSVD21_PCC2_SLOT (21) > +#define RSVD22_PCC2_SLOT (22) > +#define RSVD23_PCC2_SLOT (23) > +#define RSVD24_PCC2_SLOT (24) > +#define RSVD25_PCC2_SLOT (25) > +#define RSVD26_PCC2_SLOT (26) > +#define SEMA42_1_PCC2_SLOT (27) > +#define RSVD28_PCC2_SLOT (28) > +#define RSVD29_PCC2_SLOT (29) > +#define RSVD30_PCC2_SLOT (30) > +#define RSVD31_PCC2_SLOT (31) Are not better described with enum ? > + > +/* Off-Platform (96 entries) */ > + > +#define RSVD32_PCC2_SLOT (32) > +#define DMA1_CH_MUX0_PCC2_SLOT (33) > +#define MU_B_PCC2_SLOT (34) > +#define SNVS_PCC2_SLOT (35) > +#define CAAM_PCC2_SLOT (36) > +#define LPTPM4_PCC2_SLOT (37) > +#define LPTPM5_PCC2_SLOT (38) > +#define LPIT1_PCC2_SLOT (39) > +#define RSVD40_PCC2_SLOT (40) > +#define LPSPI2_PCC2_SLOT (41) > +#define LPSPI3_PCC2_SLOT (42) > +#define LPI2C4_PCC2_SLOT (43) > +#define LPI2C5_PCC2_SLOT (44) > +#define LPUART4_PCC2_SLOT (45) > +#define LPUART5_PCC2_SLOT (46) > +#define RSVD47_PCC2_SLOT (47) > +#define RSVD48_PCC2_SLOT (48) > +#define FLEXIO1_PCC2_SLOT (49) > +#define RSVD50_PCC2_SLOT (50) > +#define USBOTG0_PCC2_SLOT (51) > +#define USBOTG1_PCC2_SLOT (52) > +#define USBPHY_PCC2_SLOT (53) > +#define USB_PL301_PCC2_SLOT (54) > +#define USDHC0_PCC2_SLOT (55) > +#define USDHC1_PCC2_SLOT (56) > +#define RSVD57_PCC2_SLOT (57) > +#define TRGMUX1_PCC2_SLOT (58) > +#define RSVD59_PCC2_SLOT (59) > +#define RSVD60_PCC2_SLOT (60) > +#define WDG1_PCC2_SLOT (61) > +#define SCG1_PCC2_SLOT (62) > +#define PCC2_PCC2_SLOT (63) > +#define PMC1_PCC2_SLOT (64) > +#define SMC1_PCC2_SLOT (65) > +#define RCM1_PCC2_SLOT (66) > +#define WDG2_PCC2_SLOT (67) > +#define RSVD68_PCC2_SLOT (68) > +#define TEST_SPACE1_PCC2_SLOT (69) > +#define TEST_SPACE2_PCC2_SLOT (70) > +#define TEST_SPACE3_PCC2_SLOT (71) > +#define RSVD72_PCC2_SLOT (72) > +#define RSVD73_PCC2_SLOT (73) > +#define RSVD74_PCC2_SLOT (74) > +#define RSVD75_PCC2_SLOT (75) > +#define RSVD76_PCC2_SLOT (76) > +#define RSVD77_PCC2_SLOT (77) > +#define RSVD78_PCC2_SLOT (78) > +#define RSVD79_PCC2_SLOT (79) > +#define RSVD80_PCC2_SLOT (80) > +#define RSVD81_PCC2_SLOT (81) > +#define RSVD82_PCC2_SLOT (82) > +#define RSVD83_PCC2_SLOT (83) > +#define RSVD84_PCC2_SLOT (84) > +#define RSVD85_PCC2_SLOT (85) > +#define RSVD86_PCC2_SLOT (86) > +#define RSVD87_PCC2_SLOT (87) > +#define RSVD88_PCC2_SLOT (88) > +#define RSVD89_PCC2_SLOT (89) > +#define RSVD90_PCC2_SLOT (90) > +#define RSVD91_PCC2_SLOT (91) > +#define RSVD92_PCC2_SLOT (92) > +#define RSVD93_PCC2_SLOT (93) > +#define RSVD94_PCC2_SLOT (94) > +#define RSVD95_PCC2_SLOT (95) > +#define RSVD96_PCC2_SLOT (96) > +#define RSVD97_PCC2_SLOT (97) > +#define RSVD98_PCC2_SLOT (98) > +#define RSVD99_PCC2_SLOT (99) > +#define RSVD100_PCC2_SLOT (100) > +#define RSVD101_PCC2_SLOT (101) > +#define RSVD102_PCC2_SLOT (102) > +#define RSVD103_PCC2_SLOT (103) > +#define RSVD104_PCC2_SLOT (104) > +#define RSVD105_PCC2_SLOT (105) > +#define RSVD106_PCC2_SLOT (106) > +#define RSVD107_PCC2_SLOT (107) > +#define RSVD108_PCC2_SLOT (108) > +#define RSVD109_PCC2_SLOT (109) > +#define RSVD110_PCC2_SLOT (110) > +#define RSVD111_PCC2_SLOT (111) > +#define RSVD112_PCC2_SLOT (112) > +#define RSVD113_PCC2_SLOT (113) > +#define RSVD114_PCC2_SLOT (114) > +#define RSVD115_PCC2_SLOT (115) > +#define RSVD116_PCC2_SLOT (116) > +#define RSVD117_PCC2_SLOT (117) > +#define RSVD118_PCC2_SLOT (118) > +#define RSVD119_PCC2_SLOT (119) > +#define RSVD120_PCC2_SLOT (120) > +#define RSVD121_PCC2_SLOT (121) > +#define RSVD122_PCC2_SLOT (122) > +#define RSVD123_PCC2_SLOT (123) > +#define RSVD124_PCC2_SLOT (124) > +#define RSVD125_PCC2_SLOT (125) > +#define RSVD126_PCC2_SLOT (126) > +#define RSVD127_PCC2_SLOT (127) ditto > + > +/*------------------------------------------------------------------------- > + * PCC3 > + *------------------------------------------------------------------------- > + */ > + > +/* On-Platform (32 entries) */ > + > +#define RSVD0_PCC3_SLOT (0) > +#define RSVD1_PCC3_SLOT (1) > +#define RSVD2_PCC3_SLOT (2) > +#define RSVD3_PCC3_SLOT (3) > +#define RSVD4_PCC3_SLOT (4) > +#define RSVD5_PCC3_SLOT (5) > +#define RSVD6_PCC3_SLOT (6) > +#define RSVD7_PCC3_SLOT (7) > +#define RSVD8_PCC3_SLOT (8) > +#define RSVD9_PCC3_SLOT (9) > +#define RSVD10_PCC3_SLOT (10) > +#define RSVD11_PCC3_SLOT (11) > +#define RSVD12_PCC3_SLOT (12) > +#define RSVD13_PCC3_SLOT (13) > +#define RSVD14_PCC3_SLOT (14) > +#define RSVD15_PCC3_SLOT (15) > +#define ROMCP1_PCC3_SLOT (16) > +#define RSVD17_PCC3_SLOT (17) > +#define RSVD18_PCC3_SLOT (18) > +#define RSVD19_PCC3_SLOT (19) > +#define RSVD20_PCC3_SLOT (20) > +#define RSVD21_PCC3_SLOT (21) > +#define RSVD22_PCC3_SLOT (22) > +#define RSVD23_PCC3_SLOT (23) > +#define RSVD24_PCC3_SLOT (24) > +#define RSVD25_PCC3_SLOT (25) > +#define RSVD26_PCC3_SLOT (26) > +#define RSVD27_PCC3_SLOT (27) > +#define RSVD28_PCC3_SLOT (28) > +#define RSVD29_PCC3_SLOT (29) > +#define RSVD30_PCC3_SLOT (30) > +#define RSVD31_PCC3_SLOT (31) > + > +/* Off-Platform (96 entries) */ > + > +#define RSVD32_PCC3_SLOT (32) > +#define LPTPM6_PCC3_SLOT (33) > +#define LPTPM7_PCC3_SLOT (34) > +#define RSVD35_PCC3_SLOT (35) > +#define LPI2C6_PCC3_SLOT (36) > +#define LPI2C7_PCC3_SLOT (37) > +#define LPUART6_PCC3_SLOT (38) > +#define LPUART7_PCC3_SLOT (39) > +#define VIU0_PCC3_SLOT (40) > +#define DSI0_PCC3_SLOT (41) > +#define LCDIF0_PCC3_SLOT (42) > +#define MMDC0_PCC3_SLOT (43) > +#define IOMUXC1_PCC3_SLOT (44) > +#define IOMUXC_DDR_PCC3_SLOT (45) > +#define PORTC_PCC3_SLOT (46) > +#define PORTD_PCC3_SLOT (47) > +#define PORTE_PCC3_SLOT (48) > +#define PORTF_PCC3_SLOT (49) > +#define RSVD50_PCC3_SLOT (50) > +#define PCC3_PCC3_SLOT (51) > +#define RSVD52_PCC3_SLOT (52) > +#define WKPU_PCC3_SLOT (53) > +#define RSVD54_PCC3_SLOT (54) > +#define RSVD55_PCC3_SLOT (55) > +#define RSVD56_PCC3_SLOT (56) > +#define RSVD57_PCC3_SLOT (57) > +#define RSVD58_PCC3_SLOT (58) > +#define RSVD59_PCC3_SLOT (59) > +#define RSVD60_PCC3_SLOT (60) > +#define RSVD61_PCC3_SLOT (61) > +#define RSVD62_PCC3_SLOT (62) > +#define RSVD63_PCC3_SLOT (63) > +#define RSVD64_PCC3_SLOT (64) > +#define RSVD65_PCC3_SLOT (65) > +#define RSVD66_PCC3_SLOT (66) > +#define RSVD67_PCC3_SLOT (67) > +#define RSVD68_PCC3_SLOT (68) > +#define RSVD69_PCC3_SLOT (69) > +#define RSVD70_PCC3_SLOT (70) > +#define RSVD71_PCC3_SLOT (71) > +#define RSVD72_PCC3_SLOT (72) > +#define RSVD73_PCC3_SLOT (73) > +#define RSVD74_PCC3_SLOT (74) > +#define RSVD75_PCC3_SLOT (75) > +#define RSVD76_PCC3_SLOT (76) > +#define RSVD77_PCC3_SLOT (77) > +#define RSVD78_PCC3_SLOT (78) > +#define RSVD79_PCC3_SLOT (79) > +#define RSVD80_PCC3_SLOT (80) > +#define GPU3D_PCC3_SLOT (81) > +#define GPU2D_PCC3_SLOT (82) > +#define RSVD83_PCC3_SLOT (83) > +#define RSVD84_PCC3_SLOT (84) > +#define RSVD85_PCC3_SLOT (85) > +#define RSVD86_PCC3_SLOT (86) > +#define RSVD87_PCC3_SLOT (87) > +#define RSVD88_PCC3_SLOT (88) > +#define RSVD89_PCC3_SLOT (89) > +#define RSVD90_PCC3_SLOT (90) > +#define RSVD91_PCC3_SLOT (91) > +#define RSVD92_PCC3_SLOT (92) > +#define RSVD93_PCC3_SLOT (93) > +#define RSVD94_PCC3_SLOT (94) > +#define RSVD95_PCC3_SLOT (95) > +#define RSVD96_PCC3_SLOT (96) > +#define RSVD97_PCC3_SLOT (97) > +#define RSVD98_PCC3_SLOT (98) > +#define RSVD99_PCC3_SLOT (99) > +#define RSVD100_PCC3_SLOT (100) > +#define RSVD101_PCC3_SLOT (101) > +#define RSVD102_PCC3_SLOT (102) > +#define RSVD103_PCC3_SLOT (103) > +#define RSVD104_PCC3_SLOT (104) > +#define RSVD105_PCC3_SLOT (105) > +#define RSVD106_PCC3_SLOT (106) > +#define RSVD107_PCC3_SLOT (107) > +#define RSVD108_PCC3_SLOT (108) > +#define RSVD109_PCC3_SLOT (109) > +#define RSVD110_PCC3_SLOT (110) > +#define RSVD111_PCC3_SLOT (111) > +#define RSVD112_PCC3_SLOT (112) > +#define RSVD113_PCC3_SLOT (113) > +#define RSVD114_PCC3_SLOT (114) > +#define RSVD115_PCC3_SLOT (115) > +#define RSVD116_PCC3_SLOT (116) > +#define RSVD117_PCC3_SLOT (117) > +#define RSVD118_PCC3_SLOT (118) > +#define RSVD119_PCC3_SLOT (119) > +#define RSVD120_PCC3_SLOT (120) > +#define RSVD121_PCC3_SLOT (121) > +#define RSVD122_PCC3_SLOT (122) > +#define RSVD123_PCC3_SLOT (123) > +#define RSVD124_PCC3_SLOT (124) > +#define RSVD125_PCC3_SLOT (125) > +#define RSVD126_PCC3_SLOT (126) > +#define RSVD127_PCC3_SLOT (127) > + > + > +/* PCC registers */ > +#define PCC_PR_OFFSET 31 > +#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET) > +#define PCC_CGC_OFFSET 30 > +#define PCC_CGC_MASK (0x1 << PCC_CGC_OFFSET) > +#define PCC_INUSE_OFFSET 29 > +#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET) > +#define PCC_PCS_OFFSET 24 > +#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET) > +#define PCC_FRAC_OFFSET 4 > +#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET) > +#define PCC_PCD_OFFSET 0 > +#define PCC_PCD_MASK (0xf << PCC_PCD_OFFSET) > + > + > +enum pcc_clksrc_type { > + CLKSRC_PER_PLAT = 0, > + CLKSRC_PER_BUS = 1, > + CLKSRC_NO_PCS = 2, > +}; > + > +enum pcc_div_type { > + PCC_HAS_DIV, > + PCC_NO_DIV, > +}; > + > +/* All peripheral clocks on A7 PCCs */ > +enum pcc_clk { > + /*PCC2 clocks*/ > + PER_CLK_DMA1 = 0, > + PER_CLK_RGPIO2P1, > + PER_CLK_FLEXBUS, > + PER_CLK_SEMA42_1, > + PER_CLK_DMA_MUX1, > + PER_CLK_SNVS, > + PER_CLK_CAAM, > + PER_CLK_LPTPM4, > + PER_CLK_LPTPM5, > + PER_CLK_LPIT1, > + PER_CLK_LPSPI2, > + PER_CLK_LPSPI3, > + PER_CLK_LPI2C4, > + PER_CLK_LPI2C5, > + PER_CLK_LPUART4, > + PER_CLK_LPUART5, > + PER_CLK_FLEXIO1, > + PER_CLK_USB0, > + PER_CLK_USB1, > + PER_CLK_USB_PHY, > + PER_CLK_USB_PL301, > + PER_CLK_USDHC0, > + PER_CLK_USDHC1, > + PER_CLK_WDG1, > + PER_CLK_WDG2, > + > + /*PCC3 clocks*/ > + PER_CLK_LPTPM6, > + PER_CLK_LPTPM7, > + PER_CLK_LPI2C6, > + PER_CLK_LPI2C7, > + PER_CLK_LPUART6, > + PER_CLK_LPUART7, > + PER_CLK_VIU, > + PER_CLK_DSI, > + PER_CLK_LCDIF, > + PER_CLK_MMDC, > + PER_CLK_PCTLC, > + PER_CLK_PCTLD, > + PER_CLK_PCTLE, > + PER_CLK_PCTLF, > + PER_CLK_GPU3D, > + PER_CLK_GPU2D, > +}; > + > + > +/* This structure keeps info for each pcc slot */ > +struct pcc_entry { > + u32 pcc_base; > + u32 pcc_slot; > + enum pcc_clksrc_type clksrc; > + enum pcc_div_type div; > +}; > + > +int pcc_clock_enable(enum pcc_clk clk, bool enable); > +int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src); > +int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div); > +bool pcc_clock_is_enable(enum pcc_clk clk); > +int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src); > +u32 pcc_clock_get_rate(enum pcc_clk clk); > +#endif > diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h > new file mode 100644 > index 0000000..06a6e9f > --- /dev/null > +++ b/arch/arm/include/asm/arch-mx7ulp/scg.h > @@ -0,0 +1,342 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef _ASM_ARCH_SCG_H > +#define _ASM_ARCH_SCG_H > + > +#include <common.h> > + > +#ifdef CONFIG_CLK_DEBUG > +#define clk_debug(fmt, args...) printf(fmt, ##args) > +#else > +#define clk_debug(fmt, args...) > +#endif > + > +#define SCG_CCR_SCS_SHIFT (24) > +#define SCG_CCR_SCS_MASK ((0xFUL) << SCG_CCR_SCS_SHIFT) > +#define SCG_CCR_DIVCORE_SHIFT (16) > +#define SCG_CCR_DIVCORE_MASK ((0xFUL) << SCG_CCR_DIVCORE_SHIFT) > +#define SCG_CCR_DIVPLAT_SHIFT (12) > +#define SCG_CCR_DIVPLAT_MASK ((0xFUL) << SCG_CCR_DIVPLAT_SHIFT) > +#define SCG_CCR_DIVEXT_SHIFT (8) > +#define SCG_CCR_DIVEXT_MASK ((0xFUL) << SCG_CCR_DIVEXT_SHIFT) > +#define SCG_CCR_DIVBUS_SHIFT (4) > +#define SCG_CCR_DIVBUS_MASK ((0xFUL) << SCG_CCR_DIVBUS_SHIFT) > +#define SCG_CCR_DIVSLOW_SHIFT (0) > +#define SCG_CCR_DIVSLOW_MASK ((0xFUL) << SCG_CCR_DIVSLOW_SHIFT) > + > +/* SCG DDR Clock Control Register */ > +#define SCG_DDRCCR_DDRCS_SHIFT (24) > +#define SCG_DDRCCR_DDRCS_MASK ((0x1UL) << SCG_DDRCCR_DDRCS_SHIFT) > + > +#define SCG_DDRCCR_DDRDIV_SHIFT (0) > +#define SCG_DDRCCR_DDRDIV_MASK ((0x7UL) << SCG_DDRCCR_DDRDIV_SHIFT) > + > +/* SCG NIC Clock Control Register */ > +#define SCG_NICCCR_NICCS_SHIFT (28) > +#define SCG_NICCCR_NICCS_MASK ((0x1UL) << SCG_NICCCR_NICCS_SHIFT) > + > +#define SCG_NICCCR_NIC0_DIV_SHIFT (24) > +#define SCG_NICCCR_NIC0_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC0_DIV_SHIFT) > + > +#define SCG_NICCCR_GPU_DIV_SHIFT (20) > +#define SCG_NICCCR_GPU_DIV_MASK ((0xFUL) << SCG_NICCCR_GPU_DIV_SHIFT) > + > +#define SCG_NICCCR_NIC1_DIV_SHIFT (16) > +#define SCG_NICCCR_NIC1_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIV_SHIFT) > + > +#define SCG_NICCCR_NIC1_DIVEXT_SHIFT (8) > +#define SCG_NICCCR_NIC1_DIVEXT_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVEXT_SHIFT) > + > +#define SCG_NICCCR_NIC1_DIVBUS_SHIFT (4) > +#define SCG_NICCCR_NIC1_DIVBUS_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVBUS_SHIFT) > + > +/* SCG NIC clock status register */ > +#define SCG_NICCSR_NICCS_SHIFT (28) > +#define SCG_NICCSR_NICCS_MASK ((0x1UL) << SCG_NICCSR_NICCS_SHIFT) > + > +#define SCG_NICCSR_NIC0DIV_SHIFT (24) > +#define SCG_NICCSR_NIC0DIV_MASK ((0xFUL) << SCG_NICCSR_NIC0DIV_SHIFT) > +#define SCG_NICCSR_GPUDIV_SHIFT (20) > +#define SCG_NICCSR_GPUDIV_MASK ((0xFUL) << SCG_NICCSR_GPUDIV_SHIFT) > +#define SCG_NICCSR_NIC1DIV_SHIFT (16) > +#define SCG_NICCSR_NIC1DIV_MASK ((0xFUL) << SCG_NICCSR_NIC1DIV_SHIFT) > +#define SCG_NICCSR_NIC1EXTDIV_SHIFT (8) > +#define SCG_NICCSR_NIC1EXTDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1EXTDIV_SHIFT) > +#define SCG_NICCSR_NIC1BUSDIV_SHIFT (4) > +#define SCG_NICCSR_NIC1BUSDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1BUSDIV_SHIFT) > + > +/* SCG Slow IRC Control Status Register */ > +#define SCG_SIRC_CSR_SIRCVLD_SHIFT (24) > +#define SCG_SIRC_CSR_SIRCVLD_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCVLD_SHIFT) > + > +#define SCG_SIRC_CSR_SIRCEN_SHIFT (0) > +#define SCG_SIRC_CSR_SIRCEN_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCEN_SHIFT) > + > +/* SCG Slow IRC Configuration Register */ > +#define SCG_SIRCCFG_RANGE_SHIFT (0) > +#define SCG_SIRCCFG_RANGE_MASK ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT) > +#define SCG_SIRCCFG_RANGE_4M ((0x0UL) << SCG_SIRCCFG_RANGE_SHIFT) > +#define SCG_SIRCCFG_RANGE_16M ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT) > + > +/* SCG Slow IRC Divide Register */ > +#define SCG_SIRCDIV_DIV3_SHIFT (16) > +#define SCG_SIRCDIV_DIV3_MASK ((0x7UL) << SCG_SIRCDIV_DIV3_SHIFT) > + > +#define SCG_SIRCDIV_DIV2_SHIFT (8) > +#define SCG_SIRCDIV_DIV2_MASK ((0x7UL) << SCG_SIRCDIV_DIV2_SHIFT) > + > +#define SCG_SIRCDIV_DIV1_SHIFT (0) > +#define SCG_SIRCDIV_DIV1_MASK ((0x7UL) << SCG_SIRCDIV_DIV1_SHIFT) > +/* > + * FIRC/SIRC DIV1 ==> xIRC_PLAT_CLK > + * FIRC/SIRC DIV2 ==> xIRC_BUS_CLK > + * FIRC/SIRC DIV3 ==> xIRC_SLOW_CLK > + */ > + > +/* SCG Fast IRC Control Status Register */ > +#define SCG_FIRC_CSR_FIRCVLD_SHIFT (24) > +#define SCG_FIRC_CSR_FIRCVLD_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCVLD_SHIFT) > + > +#define SCG_FIRC_CSR_FIRCEN_SHIFT (0) > +#define SCG_FIRC_CSR_FIRCEN_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCEN_SHIFT) > + > +/* SCG Fast IRC Divide Register */ > +#define SCG_FIRCDIV_DIV3_SHIFT (16) > +#define SCG_FIRCDIV_DIV3_MASK ((0x7UL) << SCG_FIRCDIV_DIV3_SHIFT) > + > +#define SCG_FIRCDIV_DIV2_SHIFT (8) > +#define SCG_FIRCDIV_DIV2_MASK ((0x7UL) << SCG_FIRCDIV_DIV2_SHIFT) > + > +#define SCG_FIRCDIV_DIV1_SHIFT (0) > +#define SCG_FIRCDIV_DIV1_MASK ((0x7UL) << SCG_FIRCDIV_DIV1_SHIFT) > + > +#define SCG_FIRCCFG_RANGE_SHIFT (0) > +#define SCG_FIRCCFG_RANGE_MASK ((0x3UL) << SCG_FIRCCFG_RANGE_SHIFT) > + > +#define SCG_FIRCCFG_RANGE_SHIFT (0) > +#define SCG_FIRCCFG_RANGE_48M ((0x0UL) << SCG_FIRCCFG_RANGE_SHIFT) > + > +/* SCG System OSC Control Status Register */ > +#define SCG_SOSC_CSR_SOSCVLD_SHIFT (24) > +#define SCG_SOSC_CSR_SOSCVLD_MASK ((0x1UL) << SCG_SOSC_CSR_SOSCVLD_SHIFT) > + > +/* SCG Fast IRC Divide Register */ > +#define SCG_SOSCDIV_DIV3_SHIFT (16) > +#define SCG_SOSCDIV_DIV3_MASK ((0x7UL) << SCG_SOSCDIV_DIV3_SHIFT) > + > +#define SCG_SOSCDIV_DIV2_SHIFT (8) > +#define SCG_SOSCDIV_DIV2_MASK ((0x7UL) << SCG_SOSCDIV_DIV2_SHIFT) > + > +#define SCG_SOSCDIV_DIV1_SHIFT (0) > +#define SCG_SOSCDIV_DIV1_MASK ((0x7UL) << SCG_SOSCDIV_DIV1_SHIFT) > + > +/* SCG RTC OSC Control Status Register */ > +#define SCG_ROSC_CSR_ROSCVLD_SHIFT (24) > +#define SCG_ROSC_CSR_ROSCVLD_MASK ((0x1UL) << SCG_ROSC_CSR_ROSCVLD_SHIFT) > + > +#define SCG_SPLL_CSR_SPLLVLD_SHIFT (24) > +#define SCG_SPLL_CSR_SPLLVLD_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLVLD_SHIFT) > +#define SCG_SPLL_CSR_SPLLEN_SHIFT (0) > +#define SCG_SPLL_CSR_SPLLEN_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLEN_SHIFT) > +#define SCG_APLL_CSR_APLLEN_SHIFT (0) > +#define SCG_APLL_CSR_APLLEN_MASK (0x1UL) > +#define SCG_APLL_CSR_APLLVLD_MASK (0x01000000) > + > +#define SCG_UPLL_CSR_UPLLVLD_MASK (0x01000000) > + > + > +#define SCG_PLL_PFD3_GATE_MASK (0x80000000) > +#define SCG_PLL_PFD2_GATE_MASK (0x00800000) > +#define SCG_PLL_PFD1_GATE_MASK (0x00008000) > +#define SCG_PLL_PFD0_GATE_MASK (0x00000080) > +#define SCG_PLL_PFD3_VALID_MASK (0x40000000) > +#define SCG_PLL_PFD2_VALID_MASK (0x00400000) > +#define SCG_PLL_PFD1_VALID_MASK (0x00004000) > +#define SCG_PLL_PFD0_VALID_MASK (0x00000040) > + > +#define SCG_PLL_PFD0_FRAC_SHIFT (0) > +#define SCG_PLL_PFD0_FRAC_MASK ((0x3F) << SCG_PLL_PFD0_FRAC_SHIFT) > +#define SCG_PLL_PFD1_FRAC_SHIFT (8) > +#define SCG_PLL_PFD1_FRAC_MASK ((0x3F) << SCG_PLL_PFD1_FRAC_SHIFT) > +#define SCG_PLL_PFD2_FRAC_SHIFT (16) > +#define SCG_PLL_PFD2_FRAC_MASK ((0x3F) << SCG_PLL_PFD2_FRAC_SHIFT) > +#define SCG_PLL_PFD3_FRAC_SHIFT (24) > +#define SCG_PLL_PFD3_FRAC_MASK ((0x3F) << SCG_PLL_PFD3_FRAC_SHIFT) > + > +#define SCG_PLL_CFG_POSTDIV2_SHIFT (28) > +#define SCG_PLL_CFG_POSTDIV2_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV2_SHIFT) > +#define SCG_PLL_CFG_POSTDIV1_SHIFT (24) > +#define SCG_PLL_CFG_POSTDIV1_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV1_SHIFT) > +#define SCG_PLL_CFG_MULT_SHIFT (16) > +#define SCG1_SPLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT) > +#define SCG_APLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT) > +#define SCG_PLL_CFG_PFDSEL_SHIFT (14) > +#define SCG_PLL_CFG_PFDSEL_MASK ((0x3UL) << SCG_PLL_CFG_PFDSEL_SHIFT) > +#define SCG_PLL_CFG_PREDIV_SHIFT (8) > +#define SCG_PLL_CFG_PREDIV_MASK ((0x7UL) << SCG_PLL_CFG_PREDIV_SHIFT) > +#define SCG_PLL_CFG_BYPASS_SHIFT (2) > +/* 0: SPLL, 1: bypass */ > +#define SCG_PLL_CFG_BYPASS_MASK ((0x1UL) << SCG_PLL_CFG_BYPASS_SHIFT) > +#define SCG_PLL_CFG_PLLSEL_SHIFT (1) > +/* 0: pll, 1: pfd */ > +#define SCG_PLL_CFG_PLLSEL_MASK ((0x1UL) << SCG_PLL_CFG_PLLSEL_SHIFT) > +#define SCG_PLL_CFG_CLKSRC_SHIFT (0) > +/* 0: Sys-OSC, 1: FIRC */ > +#define SCG_PLL_CFG_CLKSRC_MASK ((0x1UL) << SCG_PLL_CFG_CLKSRC_SHIFT) > +#define SCG0_SPLL_CFG_MULT_SHIFT (17) > +/* 0: Multiplier = 20, 1: Multiplier = 22 */ > +#define SCG0_SPLL_CFG_MULT_MASK ((0x1UL) << SCG0_SPLL_CFG_MULT_SHIFT) > + > +#define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6) > +#define PLL_USB_PWR_MASK (0x01 << 12) > +#define PLL_USB_ENABLE_MASK (0x01 << 13) > +#define PLL_USB_BYPASS_MASK (0x01 << 16) > +#define PLL_USB_REG_ENABLE_MASK (0x01 << 21) > +#define PLL_USB_DIV_SEL_MASK (0x07 << 22) > +#define PLL_USB_LOCK_MASK (0x01 << 31) > + > +enum scg_clk { > + SCG_SOSC_CLK, > + SCG_FIRC_CLK, > + SCG_SIRC_CLK, > + SCG_ROSC_CLK, > + SCG_SIRC_DIV1_CLK, > + SCG_SIRC_DIV2_CLK, > + SCG_SIRC_DIV3_CLK, > + SCG_FIRC_DIV1_CLK, > + SCG_FIRC_DIV2_CLK, > + SCG_FIRC_DIV3_CLK, > + SCG_SOSC_DIV1_CLK, > + SCG_SOSC_DIV2_CLK, > + SCG_SOSC_DIV3_CLK, > + SCG_CORE_CLK, > + SCG_BUS_CLK, > + SCG_SPLL_PFD0_CLK, > + SCG_SPLL_PFD1_CLK, > + SCG_SPLL_PFD2_CLK, > + SCG_SPLL_PFD3_CLK, > + SCG_DDR_CLK, > + SCG_NIC0_CLK, > + SCG_GPU_CLK, > + SCG_NIC1_CLK, > + SCG_NIC1_BUS_CLK, > + SCG_NIC1_EXT_CLK, > + SCG_APLL_PFD0_CLK, > + SCG_APLL_PFD1_CLK, > + SCG_APLL_PFD2_CLK, > + SCG_APLL_PFD3_CLK, > + USB_PLL_OUT, > + MIPI_PLL_OUT > +}; > + > +enum scg_sys_src { > + SCG_SCS_SYS_OSC = 1, > + SCG_SCS_SLOW_IRC, > + SCG_SCS_FAST_IRC, > + SCG_SCS_RTC_OSC, > + SCG_SCS_AUX_PLL, > + SCG_SCS_SYS_PLL, > + SCG_SCS_USBPHY_PLL, > +}; > + > +/* PLL supported by i.mx7ulp */ > +enum pll_clocks { > + PLL_M4_SPLL, /* M4 SPLL */ > + PLL_M4_APLL, /* M4 APLL*/ > + PLL_A7_SPLL, /* A7 SPLL */ > + PLL_A7_APLL, /* A7 APLL */ > + PLL_USB, /* USB PLL*/ > + PLL_MIPI, /* MIPI PLL */ > +}; > + > +typedef struct scg_regs { > + u32 verid; /* VERSION_ID */ > + u32 param; /* PARAMETER */ > + u32 rsvd11[2]; > + > + u32 csr; /* Clock Status Register */ > + u32 rccr; /* Run Clock Control Register */ > + u32 vccr; /* VLPR Clock Control Register */ > + u32 hccr; /* HSRUN Clock Control Register */ > + u32 clkoutcnfg; /* SCG CLKOUT Configuration Register */ > + u32 rsvd12[3]; > + u32 ddrccr; /* SCG DDR Clock Control Register */ > + u32 rsvd13[3]; > + u32 nicccr; /* NIC Clock Control Register */ > + u32 niccsr; /* NIC Clock Status Register */ > + u32 rsvd10[46]; > + > + u32 sosccsr; /* System OSC Control Status Register, offset 0x100 */ > + u32 soscdiv; /* System OSC Divide Register */ > + u32 sosccfg; /* System Oscillator Configuration Register */ > + u32 sosctest; /* System Oscillator Test Register */ > + u32 rsvd20[60]; > + > + u32 sirccsr; /* Slow IRC Control Status Register, offset 0x200 */ > + u32 sircdiv; /* Slow IRC Divide Register */ > + u32 sirccfg; /* Slow IRC Configuration Register */ > + u32 sirctrim; /* Slow IRC Trim Register */ > + u32 loptrim; /* Low Power Oscillator Trim Register */ > + u32 sirctest; /* Slow IRC Test Register */ > + u32 rsvd30[58]; > + > + u32 firccsr; /* Fast IRC Control Status Register, offset 0x300 */ > + u32 fircdiv; > + u32 firccfg; > + u32 firctcfg; /* Fast IRC Trim Configuration Register */ > + u32 firctriml; /* Fast IRC Trim Low Register */ > + u32 firctrimh; > + u32 fircstat; /* Fast IRC Status Register */ > + u32 firctest; /* Fast IRC Test Register */ > + u32 rsvd40[56]; > + > + u32 rtccsr; /* RTC OSC Control Status Register, offset 0x400 */ > + u32 rsvd50[63]; > + > + u32 apllcsr; /* Auxiliary PLL Control Status Register, offset 0x500 */ > + u32 aplldiv; /* Auxiliary PLL Divider Register */ > + u32 apllcfg; /* Auxiliary PLL Configuration Register */ > + u32 apllpfd; /* Auxiliary PLL PFD Register */ > + u32 apllnum; /* Auxiliary PLL Numerator Register */ > + u32 aplldenom; /* Auxiliary PLL Denominator Register */ > + u32 apllss; /* Auxiliary PLL Spread Spectrum Register */ > + u32 rsvd60[55]; > + u32 apllock_cnfg; /* Auxiliary PLL LOCK Configuration Register */ > + u32 rsvd61[1]; > + > + u32 spllcsr; /* System PLL Control Status Register, offset 0x600 */ > + u32 splldiv; /* System PLL Divide Register */ > + u32 spllcfg; /* System PLL Configuration Register */ > + u32 spllpfd; /* System PLL Test Register */ > + u32 spllnum; /* System PLL Numerator Register */ > + u32 splldenom; /* System PLL Denominator Register */ > + u32 spllss; /* System PLL Spread Spectrum Register */ > + u32 rsvd70[55]; > + u32 spllock_cnfg; /* System PLL LOCK Configuration Register */ > + u32 rsvd71[1]; > + > + u32 upllcsr; /* USB PLL Control Status Register, offset 0x700 */ > + u32 uplldiv; /* USB PLL Divide Register */ > + u32 upllcfg; /* USB PLL Configuration Register */ > +} scg_t, *scg_p; > + > +u32 scg_clk_get_rate(enum scg_clk clk); > +int scg_enable_pll_pfd(enum scg_clk clk, u32 frac); > +int scg_enable_usb_pll(bool usb_control); > +u32 decode_pll(enum pll_clocks pll); > + > +void scg_a7_rccr_init(void); > +void scg_a7_spll_init(void); > +void scg_a7_ddrclk_init(void); > +void scg_a7_apll_init(void); > +void scg_a7_firc_init(void); > +void scg_a7_nicclk_init(void); > +void scg_a7_sys_clk_sel(enum scg_sys_src clk); > +void scg_a7_info(void); > +void scg_a7_soscdiv_init(void); > + > +#endif > Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 05/20] imx: mx7ulp: Add soc level initialization codes and functions 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (3 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 04/20] imx: mx7ulp: Add clock framework and functions Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2017-02-12 9:19 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 06/20] imx: mx7ulp: handle all the lpuarts in get_lpuart_clk Peng Fan ` (15 subsequent siblings) 20 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Implement soc level functions to get cpu rev, reset cause, enable cache, etc. We will disable the wdog and init clocks in s_init at very early u-boot phase. Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev is hard coded to a fixed value. This may change in future. Reuse some code in imx-common. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: Reuse code in imx-common arch/arm/Makefile | 2 +- arch/arm/cpu/armv7/mx7ulp/Makefile | 2 +- arch/arm/cpu/armv7/mx7ulp/soc.c | 274 +++++++++++++++++++++++++++ arch/arm/imx-common/Makefile | 4 + arch/arm/include/asm/arch-imx/cpu.h | 2 + arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 5 + arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 21 ++ 7 files changed, 308 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/mx7ulp/soc.c create mode 100644 arch/arm/include/asm/arch-mx7ulp/sys_proto.h diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ef4f69d..0921a66 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -99,7 +99,7 @@ ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 libs-y += arch/arm/imx-common/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35 mxs vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610)) libs-y += arch/arm/imx-common/ endif endif diff --git a/arch/arm/cpu/armv7/mx7ulp/Makefile b/arch/arm/cpu/armv7/mx7ulp/Makefile index 6f37e8c..0248ea8 100644 --- a/arch/arm/cpu/armv7/mx7ulp/Makefile +++ b/arch/arm/cpu/armv7/mx7ulp/Makefile @@ -5,4 +5,4 @@ # # -obj-y := clock.o iomux.o pcc.o scg.o +obj-y := soc.o clock.o iomux.o pcc.o scg.o diff --git a/arch/arm/cpu/armv7/mx7ulp/soc.c b/arch/arm/cpu/armv7/mx7ulp/soc.c new file mode 100644 index 0000000..d04edc5 --- /dev/null +++ b/arch/arm/cpu/armv7/mx7ulp/soc.c @@ -0,0 +1,274 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +static char *get_reset_cause(char *); + +u32 get_cpu_rev(void) +{ + /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */ + return (MXC_CPU_MX7ULP << 12) | (1 << 4); +} + +#ifdef CONFIG_REVISION_TAG +u32 __weak get_board_rev(void) +{ + return get_cpu_rev(); +} +#endif + +enum bt_mode get_boot_mode(void) +{ + u32 bt0_cfg = 0; + + bt0_cfg = readl(CMC0_RBASE + 0x40); + bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK); + + if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) { + /* No low power boot */ + if (bt0_cfg & BT0CFG_DUALBOOT_MASK) + return DUAL_BOOT; + else + return SINGLE_BOOT; + } + + return LOW_POWER_BOOT; +} + +int arch_cpu_init(void) +{ + return 0; +} + +#ifdef CONFIG_BOARD_POSTCLK_INIT +int board_postclk_init(void) +{ + return 0; +} +#endif + +#define UNLOCK_WORD0 0xC520 /* 1st unlock word */ +#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */ +#define REFRESH_WORD0 0xA602 /* 1st refresh word */ +#define REFRESH_WORD1 0xB480 /* 2nd refresh word */ + +static void disable_wdog(u32 wdog_base) +{ + writel(UNLOCK_WORD0, (wdog_base + 0x04)); + writel(UNLOCK_WORD1, (wdog_base + 0x04)); + writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */ + writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */ + writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */ + + writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */ + writel(REFRESH_WORD1, (wdog_base + 0x04)); +} + +void init_wdog(void) +{ + /* + * ROM will configure WDOG1, disable it or enable it + * depending on FUSE. The update bit is set for reconfigurable. + * We have to use unlock sequence to reconfigure it. + * WDOG2 is not touched by ROM, so it will have default value + * which is enabled. We can directly configure it. + * To simplify the codes, we still use same reconfigure + * process as WDOG1. Because the update bit is not set for + * WDOG2, the unlock sequence won't take effect really. + * It actually directly configure the wdog. + * In this function, we will disable both WDOG1 and WDOG2, + * and set update bit for both. So that kernel can reconfigure them. + */ + disable_wdog(WDG1_RBASE); + disable_wdog(WDG2_RBASE); +} + + +void s_init(void) +{ + /* Disable wdog */ + init_wdog(); + + /* clock configuration. */ + clock_init(); + + return; +} + +#ifndef CONFIG_ULP_WATCHDOG +void reset_cpu(ulong addr) +{ + setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET); + while (1) + ; +} +#endif + +#if defined(CONFIG_DISPLAY_CPUINFO) +const char *get_imx_type(u32 imxtype) +{ +#ifdef CONFIG_MXC_OCOTP + + u8 uid[8]; + u32 val; + + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[0]; + struct fuse_bank1_regs *fuse = + (struct fuse_bank1_regs *)bank->fuse_regs; + + val = readl(&fuse->cfg0); + *uid = val & 0xFF; + *(uid + 1) = (val & 0xFF00) >> 8; + + val = readl(&fuse->cfg1); + *(uid + 2) = val & 0xFF; + *(uid + 3) = (val & 0xFF00) >> 8; + + val = readl(&fuse->cfg2); + *(uid + 4) = val & 0xFF; + *(uid + 5) = (val & 0xFF00) >> 8; + + val = readl(&fuse->cfg3); + *(uid + 6) = val & 0xFF; + *(uid + 7) = (val & 0xFF00) >> 8; + + debug("UID = %02X %02X %02X %02X %02X %02X %02X %02X\r\n", + uid[0], uid[1], uid[2], uid[3], uid[4], uid[5], uid[6], uid[7]); + +#endif + return "7ULP"; +} + +int print_cpuinfo(void) +{ + u32 cpurev; + char cause[18]; + + cpurev = get_cpu_rev(); + + printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", + get_imx_type((cpurev & 0xFF000) >> 12), + (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + + printf("Reset cause: %s\n", get_reset_cause(cause)); + + printf("Boot mode: "); + switch (get_boot_mode()) { + case LOW_POWER_BOOT: + printf("Low power boot\n"); + break; + case DUAL_BOOT: + printf("Dual boot\n"); + break; + case SINGLE_BOOT: + default: + printf("Single boot\n"); + break; + } + + return 0; +} +#endif + +#define CMC_SRS_TAMPER (1 << 31) +#define CMC_SRS_SECURITY (1 << 30) +#define CMC_SRS_TZWDG (1 << 29) +#define CMC_SRS_JTAG_RST (1 << 28) +#define CMC_SRS_CORE1 (1 << 16) +#define CMC_SRS_LOCKUP (1 << 15) +#define CMC_SRS_SW (1 << 14) +#define CMC_SRS_WDG (1 << 13) +#define CMC_SRS_PIN_RESET (1 << 8) +#define CMC_SRS_WARM (1 << 4) +#define CMC_SRS_HVD (1 << 3) +#define CMC_SRS_LVD (1 << 2) +#define CMC_SRS_POR (1 << 1) +#define CMC_SRS_WUP (1 << 0) + +static u32 reset_cause = -1; + +static char *get_reset_cause(char *ret) +{ + u32 cause1, cause = 0, srs = 0; + u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28); + u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20); + + if (!ret) + return "null"; + + srs = readl(reg_srs); + cause1 = readl(reg_ssrs); + writel(cause1, reg_ssrs); + + reset_cause = cause1; + + cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM); + + switch (cause) { + case CMC_SRS_POR: + sprintf(ret, "%s", "POR"); + break; + case CMC_SRS_WUP: + sprintf(ret, "%s", "WUP"); + break; + case CMC_SRS_WARM: + cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW | + CMC_SRS_JTAG_RST); + switch (cause) { + case CMC_SRS_WDG: + sprintf(ret, "%s", "WARM-WDG"); + break; + case CMC_SRS_SW: + sprintf(ret, "%s", "WARM-SW"); + break; + case CMC_SRS_JTAG_RST: + sprintf(ret, "%s", "WARM-JTAG"); + break; + default: + sprintf(ret, "%s", "WARM-UNKN"); + break; + } + break; + default: + sprintf(ret, "%s-%X", "UNKN", cause1); + break; + } + + debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1); + return ret; +} + +u32 get_imx_reset_cause(void) +{ + return reset_cause; +} + +#ifdef CONFIG_ENV_IS_IN_MMC +__weak int board_mmc_get_env_dev(int devno) +{ + return CONFIG_SYS_MMC_ENV_DEV; +} + +int mmc_get_env_dev(void) +{ + int devno = 0; + u32 bt1_cfg = 0; + + /* If not boot from sd/mmc, use default value */ + if (get_boot_mode() == LOW_POWER_BOOT) + return CONFIG_SYS_MMC_ENV_DEV; + + bt1_cfg = readl(CMC1_RBASE + 0x40); + devno = (bt1_cfg >> 9) & 0x7; + + return board_mmc_get_env_dev(devno); +} +#endif diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 1873185..68ee60f 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -31,6 +31,10 @@ obj-$(CONFIG_IMX_RDC) += rdc-sema.o obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o obj-$(CONFIG_SECURE_BOOT) += hab.o endif +ifeq ($(SOC),$(filter $(SOC),mx7ulp)) +obj-y += cache.o +obj-$(CONFIG_SECURE_BOOT) += hab.o +endif ifeq ($(SOC),$(filter $(SOC),vf610)) obj-y += ddrmc-vf610.o endif diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 8bd1421..b052406 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -25,10 +25,12 @@ #define MXC_CPU_MX6QP 0x69 #define MXC_CPU_MX7S 0x71 /* dummy ID */ #define MXC_CPU_MX7D 0x72 +#define MXC_CPU_MX7ULP 0x81 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 +#define MXC_SOC_MX7ULP 0x80 /* dummy */ #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index 30d0ba4..cdfbe2e 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -97,6 +97,11 @@ #define CORE_B_ROM_SIZE (SZ_32K + SZ_64K) #define CORE_B_ROM_BASE (0x00000000) +#define ROMCP_ARB_BASE_ADDR CORE_B_ROM_BASE +#define ROMCP_ARB_END_ADDR CORE_B_ROM_SIZE +#define IRAM_BASE_ADDR OCRAM_0_BASE +#define IRAM_SIZE (SZ_128K + SZ_128K) + #define IOMUXC_PCR_MUX_ALT0 (0<<8) #define IOMUXC_PCR_MUX_ALT1 (1<<8) #define IOMUXC_PCR_MUX_ALT2 (2<<8) diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h new file mode 100644 index 0000000..d01748f --- /dev/null +++ b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SYS_PROTO_MX7ULP_H_ +#define _SYS_PROTO_MX7ULP_H_ + +#include <asm/imx-common/sys_proto.h> + +#define BT0CFG_LPBOOT_MASK 0x1 +#define BT0CFG_DUALBOOT_MASK 0x2 + +enum bt_mode { + LOW_POWER_BOOT, /* LP_BT = 1 */ + DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */ + SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */ +}; + +#endif -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 05/20] imx: mx7ulp: Add soc level initialization codes and functions 2016-12-27 10:04 ` [U-Boot] [PATCH V2 05/20] imx: mx7ulp: Add soc level initialization codes " Peng Fan @ 2017-02-12 9:19 ` Stefano Babic 2017-02-22 6:48 ` Peng Fan 0 siblings, 1 reply; 48+ messages in thread From: Stefano Babic @ 2017-02-12 9:19 UTC (permalink / raw) To: u-boot Hi Peng, On 27/12/2016 11:04, Peng Fan wrote: > Implement soc level functions to get cpu rev, reset cause, enable cache, > etc. We will disable the wdog and init clocks in s_init at very early u-boot > phase. > > Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev > is hard coded to a fixed value. This may change in future. > ok, understood, noted > Reuse some code in imx-common. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Signed-off-by: Ye Li <ye.li@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > Reuse code in imx-common > > arch/arm/Makefile | 2 +- > arch/arm/cpu/armv7/mx7ulp/Makefile | 2 +- > arch/arm/cpu/armv7/mx7ulp/soc.c | 274 +++++++++++++++++++++++++++ > arch/arm/imx-common/Makefile | 4 + > arch/arm/include/asm/arch-imx/cpu.h | 2 + > arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 5 + > arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 21 ++ > 7 files changed, 308 insertions(+), 2 deletions(-) > create mode 100644 arch/arm/cpu/armv7/mx7ulp/soc.c > create mode 100644 arch/arm/include/asm/arch-mx7ulp/sys_proto.h > > diff --git a/arch/arm/Makefile b/arch/arm/Makefile > index ef4f69d..0921a66 100644 > --- a/arch/arm/Makefile > +++ b/arch/arm/Makefile > @@ -99,7 +99,7 @@ ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 > libs-y += arch/arm/imx-common/ > endif > else > -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35 mxs vf610)) > +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610)) > libs-y += arch/arm/imx-common/ > endif > endif > diff --git a/arch/arm/cpu/armv7/mx7ulp/Makefile b/arch/arm/cpu/armv7/mx7ulp/Makefile > index 6f37e8c..0248ea8 100644 > --- a/arch/arm/cpu/armv7/mx7ulp/Makefile > +++ b/arch/arm/cpu/armv7/mx7ulp/Makefile > @@ -5,4 +5,4 @@ > # > # > > -obj-y := clock.o iomux.o pcc.o scg.o > +obj-y := soc.o clock.o iomux.o pcc.o scg.o > diff --git a/arch/arm/cpu/armv7/mx7ulp/soc.c b/arch/arm/cpu/armv7/mx7ulp/soc.c > new file mode 100644 > index 0000000..d04edc5 > --- /dev/null > +++ b/arch/arm/cpu/armv7/mx7ulp/soc.c > @@ -0,0 +1,274 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > +#include <asm/io.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/imx-regs.h> > +#include <asm/arch/sys_proto.h> > + > +static char *get_reset_cause(char *); > + > +u32 get_cpu_rev(void) > +{ > + /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */ > + return (MXC_CPU_MX7ULP << 12) | (1 << 4); > +} > + > +#ifdef CONFIG_REVISION_TAG > +u32 __weak get_board_rev(void) > +{ > + return get_cpu_rev(); > +} > +#endif > + > +enum bt_mode get_boot_mode(void) > +{ > + u32 bt0_cfg = 0; > + > + bt0_cfg = readl(CMC0_RBASE + 0x40); > + bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK); > + > + if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) { > + /* No low power boot */ > + if (bt0_cfg & BT0CFG_DUALBOOT_MASK) > + return DUAL_BOOT; > + else > + return SINGLE_BOOT; > + } > + > + return LOW_POWER_BOOT; > +} > + > +int arch_cpu_init(void) > +{ > + return 0; > +} > + > +#ifdef CONFIG_BOARD_POSTCLK_INIT > +int board_postclk_init(void) > +{ > + return 0; > +} > +#endif > + > +#define UNLOCK_WORD0 0xC520 /* 1st unlock word */ > +#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */ > +#define REFRESH_WORD0 0xA602 /* 1st refresh word */ > +#define REFRESH_WORD1 0xB480 /* 2nd refresh word */ > + > +static void disable_wdog(u32 wdog_base) > +{ > + writel(UNLOCK_WORD0, (wdog_base + 0x04)); > + writel(UNLOCK_WORD1, (wdog_base + 0x04)); > + writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */ > + writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */ > + writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */ > + > + writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */ > + writel(REFRESH_WORD1, (wdog_base + 0x04)); > +} > + > +void init_wdog(void) > +{ > + /* > + * ROM will configure WDOG1, disable it or enable it > + * depending on FUSE. The update bit is set for reconfigurable. > + * We have to use unlock sequence to reconfigure it. > + * WDOG2 is not touched by ROM, so it will have default value > + * which is enabled. We can directly configure it. > + * To simplify the codes, we still use same reconfigure > + * process as WDOG1. Because the update bit is not set for > + * WDOG2, the unlock sequence won't take effect really. > + * It actually directly configure the wdog. > + * In this function, we will disable both WDOG1 and WDOG2, > + * and set update bit for both. So that kernel can reconfigure them. > + */ > + disable_wdog(WDG1_RBASE); > + disable_wdog(WDG2_RBASE); > +} > + > + > +void s_init(void) > +{ > + /* Disable wdog */ > + init_wdog(); > + > + /* clock configuration. */ > + clock_init(); > + > + return; > +} > + > +#ifndef CONFIG_ULP_WATCHDOG > +void reset_cpu(ulong addr) > +{ > + setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET); > + while (1) > + ; > +} > +#endif > + > +#if defined(CONFIG_DISPLAY_CPUINFO) > +const char *get_imx_type(u32 imxtype) > +{ > +#ifdef CONFIG_MXC_OCOTP > + > + u8 uid[8]; > + u32 val; > + > + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; > + struct fuse_bank *bank = &ocotp->bank[0]; > + struct fuse_bank1_regs *fuse = > + (struct fuse_bank1_regs *)bank->fuse_regs; > + > + val = readl(&fuse->cfg0); > + *uid = val & 0xFF; > + *(uid + 1) = (val & 0xFF00) >> 8; > + > + val = readl(&fuse->cfg1); > + *(uid + 2) = val & 0xFF; > + *(uid + 3) = (val & 0xFF00) >> 8; > + > + val = readl(&fuse->cfg2); > + *(uid + 4) = val & 0xFF; > + *(uid + 5) = (val & 0xFF00) >> 8; > + > + val = readl(&fuse->cfg3); > + *(uid + 6) = val & 0xFF; > + *(uid + 7) = (val & 0xFF00) >> 8; I think it can be better described here, at least what you want to read for fuse->cfg0..cfg3. > + > + debug("UID = %02X %02X %02X %02X %02X %02X %02X %02X\r\n", > + uid[0], uid[1], uid[2], uid[3], uid[4], uid[5], uid[6], uid[7]); > + > +#endif > + return "7ULP"; > +} > + > +int print_cpuinfo(void) > +{ > + u32 cpurev; > + char cause[18]; > + > + cpurev = get_cpu_rev(); > + > + printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", > + get_imx_type((cpurev & 0xFF000) >> 12), > + (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, > + mxc_get_clock(MXC_ARM_CLK) / 1000000); > + > + printf("Reset cause: %s\n", get_reset_cause(cause)); > + > + printf("Boot mode: "); > + switch (get_boot_mode()) { > + case LOW_POWER_BOOT: > + printf("Low power boot\n"); > + break; > + case DUAL_BOOT: > + printf("Dual boot\n"); > + break; > + case SINGLE_BOOT: > + default: > + printf("Single boot\n"); > + break; > + } > + > + return 0; > +} > +#endif > + > +#define CMC_SRS_TAMPER (1 << 31) > +#define CMC_SRS_SECURITY (1 << 30) > +#define CMC_SRS_TZWDG (1 << 29) > +#define CMC_SRS_JTAG_RST (1 << 28) > +#define CMC_SRS_CORE1 (1 << 16) > +#define CMC_SRS_LOCKUP (1 << 15) > +#define CMC_SRS_SW (1 << 14) > +#define CMC_SRS_WDG (1 << 13) > +#define CMC_SRS_PIN_RESET (1 << 8) > +#define CMC_SRS_WARM (1 << 4) > +#define CMC_SRS_HVD (1 << 3) > +#define CMC_SRS_LVD (1 << 2) > +#define CMC_SRS_POR (1 << 1) > +#define CMC_SRS_WUP (1 << 0) > + > +static u32 reset_cause = -1; > + > +static char *get_reset_cause(char *ret) > +{ > + u32 cause1, cause = 0, srs = 0; > + u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28); > + u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20); > + > + if (!ret) > + return "null"; > + > + srs = readl(reg_srs); > + cause1 = readl(reg_ssrs); > + writel(cause1, reg_ssrs); > + > + reset_cause = cause1; > + > + cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM); > + > + switch (cause) { > + case CMC_SRS_POR: > + sprintf(ret, "%s", "POR"); > + break; > + case CMC_SRS_WUP: > + sprintf(ret, "%s", "WUP"); > + break; > + case CMC_SRS_WARM: > + cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW | > + CMC_SRS_JTAG_RST); > + switch (cause) { > + case CMC_SRS_WDG: > + sprintf(ret, "%s", "WARM-WDG"); > + break; > + case CMC_SRS_SW: > + sprintf(ret, "%s", "WARM-SW"); > + break; > + case CMC_SRS_JTAG_RST: > + sprintf(ret, "%s", "WARM-JTAG"); > + break; > + default: > + sprintf(ret, "%s", "WARM-UNKN"); > + break; > + } > + break; > + default: > + sprintf(ret, "%s-%X", "UNKN", cause1); > + break; > + } > + > + debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1); > + return ret; > +} > + > +u32 get_imx_reset_cause(void) > +{ > + return reset_cause; Why do you stored it ain a static variable ? Is it read just once from registers ? > +} > + > +#ifdef CONFIG_ENV_IS_IN_MMC > +__weak int board_mmc_get_env_dev(int devno) > +{ > + return CONFIG_SYS_MMC_ENV_DEV; > +} > + > +int mmc_get_env_dev(void) > +{ > + int devno = 0; > + u32 bt1_cfg = 0; > + > + /* If not boot from sd/mmc, use default value */ > + if (get_boot_mode() == LOW_POWER_BOOT) > + return CONFIG_SYS_MMC_ENV_DEV; > + > + bt1_cfg = readl(CMC1_RBASE + 0x40); > + devno = (bt1_cfg >> 9) & 0x7; > + > + return board_mmc_get_env_dev(devno); > +} > +#endif > diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile > index 1873185..68ee60f 100644 > --- a/arch/arm/imx-common/Makefile > +++ b/arch/arm/imx-common/Makefile > @@ -31,6 +31,10 @@ obj-$(CONFIG_IMX_RDC) += rdc-sema.o > obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o > obj-$(CONFIG_SECURE_BOOT) += hab.o > endif > +ifeq ($(SOC),$(filter $(SOC),mx7ulp)) > +obj-y += cache.o > +obj-$(CONFIG_SECURE_BOOT) += hab.o > +endif > ifeq ($(SOC),$(filter $(SOC),vf610)) > obj-y += ddrmc-vf610.o > endif > diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h > index 8bd1421..b052406 100644 > --- a/arch/arm/include/asm/arch-imx/cpu.h > +++ b/arch/arm/include/asm/arch-imx/cpu.h > @@ -25,10 +25,12 @@ > #define MXC_CPU_MX6QP 0x69 > #define MXC_CPU_MX7S 0x71 /* dummy ID */ > #define MXC_CPU_MX7D 0x72 > +#define MXC_CPU_MX7ULP 0x81 /* Temporally hard code */ ok > #define MXC_CPU_VF610 0xF6 /* dummy ID */ > > #define MXC_SOC_MX6 0x60 > #define MXC_SOC_MX7 0x70 > +#define MXC_SOC_MX7ULP 0x80 /* dummy */ > > #define CHIP_REV_1_0 0x10 > #define CHIP_REV_1_1 0x11 > diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h > index 30d0ba4..cdfbe2e 100644 > --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h > @@ -97,6 +97,11 @@ > #define CORE_B_ROM_SIZE (SZ_32K + SZ_64K) > #define CORE_B_ROM_BASE (0x00000000) > > +#define ROMCP_ARB_BASE_ADDR CORE_B_ROM_BASE > +#define ROMCP_ARB_END_ADDR CORE_B_ROM_SIZE > +#define IRAM_BASE_ADDR OCRAM_0_BASE > +#define IRAM_SIZE (SZ_128K + SZ_128K) > + Why is it here and not in Patch 2/20 ? > #define IOMUXC_PCR_MUX_ALT0 (0<<8) > #define IOMUXC_PCR_MUX_ALT1 (1<<8) > #define IOMUXC_PCR_MUX_ALT2 (2<<8) > diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h > new file mode 100644 > index 0000000..d01748f > --- /dev/null > +++ b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h > @@ -0,0 +1,21 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef _SYS_PROTO_MX7ULP_H_ > +#define _SYS_PROTO_MX7ULP_H_ > + > +#include <asm/imx-common/sys_proto.h> > + > +#define BT0CFG_LPBOOT_MASK 0x1 > +#define BT0CFG_DUALBOOT_MASK 0x2 > + > +enum bt_mode { > + LOW_POWER_BOOT, /* LP_BT = 1 */ > + DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */ > + SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */ > +}; > + > +#endif > Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 05/20] imx: mx7ulp: Add soc level initialization codes and functions 2017-02-12 9:19 ` Stefano Babic @ 2017-02-22 6:48 ` Peng Fan 0 siblings, 0 replies; 48+ messages in thread From: Peng Fan @ 2017-02-22 6:48 UTC (permalink / raw) To: u-boot On Sun, Feb 12, 2017 at 10:19:41AM +0100, Stefano Babic wrote: >Hi Peng, > >On 27/12/2016 11:04, Peng Fan wrote: >> Implement soc level functions to get cpu rev, reset cause, enable cache, >> etc. We will disable the wdog and init clocks in s_init at very early u-boot >> phase. >> >> Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev >> is hard coded to a fixed value. This may change in future. >> > >ok, understood, noted > >> Reuse some code in imx-common. >> >> Signed-off-by: Peng Fan <peng.fan@nxp.com> >> Signed-off-by: Ye Li <ye.li@nxp.com> >> Cc: Stefano Babic <sbabic@denx.de> >> --- >> [.......] >> + >> +#if defined(CONFIG_DISPLAY_CPUINFO) >> +const char *get_imx_type(u32 imxtype) >> +{ >> +#ifdef CONFIG_MXC_OCOTP >> + >> + u8 uid[8]; >> + u32 val; >> + >> + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; >> + struct fuse_bank *bank = &ocotp->bank[0]; >> + struct fuse_bank1_regs *fuse = >> + (struct fuse_bank1_regs *)bank->fuse_regs; >> + >> + val = readl(&fuse->cfg0); >> + *uid = val & 0xFF; >> + *(uid + 1) = (val & 0xFF00) >> 8; >> + >> + val = readl(&fuse->cfg1); >> + *(uid + 2) = val & 0xFF; >> + *(uid + 3) = (val & 0xFF00) >> 8; >> + >> + val = readl(&fuse->cfg2); >> + *(uid + 4) = val & 0xFF; >> + *(uid + 5) = (val & 0xFF00) >> 8; >> + >> + val = readl(&fuse->cfg3); >> + *(uid + 6) = val & 0xFF; >> + *(uid + 7) = (val & 0xFF00) >> 8; > >I think it can be better described here, at least what you want to read >for fuse->cfg0..cfg3. Discard in V3. > >> + >> + debug("UID = %02X %02X %02X %02X %02X %02X %02X %02X\r\n", >> + uid[0], uid[1], uid[2], uid[3], uid[4], uid[5], uid[6], uid[7]); >> + >> +#endif >> + return "7ULP"; >> +} >> + [.....] >> + >> +u32 get_imx_reset_cause(void) >> +{ >> + return reset_cause; > >Why do you stored it ain a static variable ? Is it read just once from >registers ? This function could be removed, it reuses the one in imx-common.c > >> +} >> + >> +#ifdef CONFIG_ENV_IS_IN_MMC >> +__weak int board_mmc_get_env_dev(int devno) >> +{ >> + return CONFIG_SYS_MMC_ENV_DEV; >> +} >> + >> +int mmc_get_env_dev(void) >> +{ >> + int devno = 0; >> + u32 bt1_cfg = 0; >> + >> + /* If not boot from sd/mmc, use default value */ >> + if (get_boot_mode() == LOW_POWER_BOOT) >> + return CONFIG_SYS_MMC_ENV_DEV; >> + >> + bt1_cfg = readl(CMC1_RBASE + 0x40); >> + devno = (bt1_cfg >> 9) & 0x7; >> + >> + return board_mmc_get_env_dev(devno); >> +} >> +#endif >> diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile >> index 1873185..68ee60f 100644 >> --- a/arch/arm/imx-common/Makefile >> +++ b/arch/arm/imx-common/Makefile >> @@ -31,6 +31,10 @@ obj-$(CONFIG_IMX_RDC) += rdc-sema.o >> obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o >> obj-$(CONFIG_SECURE_BOOT) += hab.o >> endif >> +ifeq ($(SOC),$(filter $(SOC),mx7ulp)) >> +obj-y += cache.o >> +obj-$(CONFIG_SECURE_BOOT) += hab.o >> +endif >> ifeq ($(SOC),$(filter $(SOC),vf610)) >> obj-y += ddrmc-vf610.o >> endif >> diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h >> index 8bd1421..b052406 100644 >> --- a/arch/arm/include/asm/arch-imx/cpu.h >> +++ b/arch/arm/include/asm/arch-imx/cpu.h >> @@ -25,10 +25,12 @@ >> #define MXC_CPU_MX6QP 0x69 >> #define MXC_CPU_MX7S 0x71 /* dummy ID */ >> #define MXC_CPU_MX7D 0x72 >> +#define MXC_CPU_MX7ULP 0x81 /* Temporally hard code */ > >ok > >> #define MXC_CPU_VF610 0xF6 /* dummy ID */ >> >> #define MXC_SOC_MX6 0x60 >> #define MXC_SOC_MX7 0x70 >> +#define MXC_SOC_MX7ULP 0x80 /* dummy */ >> >> #define CHIP_REV_1_0 0x10 >> #define CHIP_REV_1_1 0x11 >> diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h >> index 30d0ba4..cdfbe2e 100644 >> --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h >> +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h >> @@ -97,6 +97,11 @@ >> #define CORE_B_ROM_SIZE (SZ_32K + SZ_64K) >> #define CORE_B_ROM_BASE (0x00000000) >> >> +#define ROMCP_ARB_BASE_ADDR CORE_B_ROM_BASE >> +#define ROMCP_ARB_END_ADDR CORE_B_ROM_SIZE >> +#define IRAM_BASE_ADDR OCRAM_0_BASE >> +#define IRAM_SIZE (SZ_128K + SZ_128K) >> + > >Why is it here and not in Patch 2/20 ? Move the 2/20 in V3. Thanks, Peng. ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 06/20] imx: mx7ulp: handle all the lpuarts in get_lpuart_clk 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (4 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 05/20] imx: mx7ulp: Add soc level initialization codes " Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2017-02-12 9:20 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 07/20] imx: mx7ulp: Implement the clock functions for i2c driver Peng Fan ` (14 subsequent siblings) 20 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Add handle the lpuarts in get_lpuart_clk. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: None arch/arm/cpu/armv7/mx7ulp/clock.c | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/mx7ulp/clock.c b/arch/arm/cpu/armv7/mx7ulp/clock.c index 534f632..0c34d88 100644 --- a/arch/arm/cpu/armv7/mx7ulp/clock.c +++ b/arch/arm/cpu/armv7/mx7ulp/clock.c @@ -42,7 +42,35 @@ static u32 get_ipg_clk(void) u32 get_lpuart_clk(void) { - return pcc_clock_get_rate(PER_CLK_LPUART4); + int index = 0; + + const u32 lpuart_array[] = { + LPUART0_RBASE, + LPUART1_RBASE, + LPUART2_RBASE, + LPUART3_RBASE, + LPUART4_RBASE, + LPUART5_RBASE, + LPUART6_RBASE, + LPUART7_RBASE, + }; + + const enum pcc_clk lpuart_pcc_clks[] = { + PER_CLK_LPUART4, + PER_CLK_LPUART5, + PER_CLK_LPUART6, + PER_CLK_LPUART7, + }; + + for (index = 0; index < 8; index++) { + if (lpuart_array[index] == LPUART_BASE) + break; + } + + if (index < 4 || index > 7) + return 0; + + return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]); } unsigned int mxc_get_clock(enum mxc_clock clk) @@ -59,7 +87,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_I2C_CLK: return pcc_clock_get_rate(PER_CLK_LPI2C4); case MXC_UART_CLK: - return pcc_clock_get_rate(PER_CLK_LPUART4); + return get_lpuart_clk(); case MXC_ESDHC_CLK: return pcc_clock_get_rate(PER_CLK_USDHC0); case MXC_ESDHC2_CLK: @@ -264,7 +292,7 @@ int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000); printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); - printf("UART %8d kHz\n", pcc_clock_get_rate(PER_CLK_LPUART4) / 1000); + printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 06/20] imx: mx7ulp: handle all the lpuarts in get_lpuart_clk 2016-12-27 10:04 ` [U-Boot] [PATCH V2 06/20] imx: mx7ulp: handle all the lpuarts in get_lpuart_clk Peng Fan @ 2017-02-12 9:20 ` Stefano Babic 0 siblings, 0 replies; 48+ messages in thread From: Stefano Babic @ 2017-02-12 9:20 UTC (permalink / raw) To: u-boot On 27/12/2016 11:04, Peng Fan wrote: > Add handle the lpuarts in get_lpuart_clk. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Signed-off-by: Ye Li <ye.li@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > None > > arch/arm/cpu/armv7/mx7ulp/clock.c | 34 +++++++++++++++++++++++++++++++--- > 1 file changed, 31 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/cpu/armv7/mx7ulp/clock.c b/arch/arm/cpu/armv7/mx7ulp/clock.c > index 534f632..0c34d88 100644 > --- a/arch/arm/cpu/armv7/mx7ulp/clock.c > +++ b/arch/arm/cpu/armv7/mx7ulp/clock.c > @@ -42,7 +42,35 @@ static u32 get_ipg_clk(void) > > u32 get_lpuart_clk(void) > { > - return pcc_clock_get_rate(PER_CLK_LPUART4); > + int index = 0; > + > + const u32 lpuart_array[] = { > + LPUART0_RBASE, > + LPUART1_RBASE, > + LPUART2_RBASE, > + LPUART3_RBASE, > + LPUART4_RBASE, > + LPUART5_RBASE, > + LPUART6_RBASE, > + LPUART7_RBASE, > + }; > + > + const enum pcc_clk lpuart_pcc_clks[] = { > + PER_CLK_LPUART4, > + PER_CLK_LPUART5, > + PER_CLK_LPUART6, > + PER_CLK_LPUART7, > + }; > + > + for (index = 0; index < 8; index++) { > + if (lpuart_array[index] == LPUART_BASE) > + break; > + } > + > + if (index < 4 || index > 7) > + return 0; > + > + return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]); > } > > unsigned int mxc_get_clock(enum mxc_clock clk) > @@ -59,7 +87,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) > case MXC_I2C_CLK: > return pcc_clock_get_rate(PER_CLK_LPI2C4); > case MXC_UART_CLK: > - return pcc_clock_get_rate(PER_CLK_LPUART4); > + return get_lpuart_clk(); > case MXC_ESDHC_CLK: > return pcc_clock_get_rate(PER_CLK_USDHC0); > case MXC_ESDHC2_CLK: > @@ -264,7 +292,7 @@ int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) > > printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000); > printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); > - printf("UART %8d kHz\n", pcc_clock_get_rate(PER_CLK_LPUART4) / 1000); > + printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); > printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); > printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); > printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); > As far as I understand, you can better squash this patch with 4/20 Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 07/20] imx: mx7ulp: Implement the clock functions for i2c driver 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (5 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 06/20] imx: mx7ulp: handle all the lpuarts in get_lpuart_clk Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2017-02-12 9:20 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 08/20] gpio: Add Rapid GPIO2P driver for i.MX7ULP Peng Fan ` (13 subsequent siblings) 20 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot From: Ye Li <ye.li@nxp.com> Implement the i2c clock enable and get function for mx7ulp. These functions are required by imx_lpi2c driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: None arch/arm/cpu/armv7/mx7ulp/clock.c | 40 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx7ulp/clock.h | 4 ++++ 2 files changed, 44 insertions(+) diff --git a/arch/arm/cpu/armv7/mx7ulp/clock.c b/arch/arm/cpu/armv7/mx7ulp/clock.c index 0c34d88..30db67d 100644 --- a/arch/arm/cpu/armv7/mx7ulp/clock.c +++ b/arch/arm/cpu/armv7/mx7ulp/clock.c @@ -73,6 +73,46 @@ u32 get_lpuart_clk(void) return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]); } +#ifdef CONFIG_SYS_LPI2C_IMX +int enable_i2c_clk(unsigned char enable, unsigned i2c_num) +{ + /* Set parent to FIRC DIV2 clock */ + const enum pcc_clk lpi2c_pcc_clks[] = { + PER_CLK_LPI2C4, + PER_CLK_LPI2C5, + PER_CLK_LPI2C6, + PER_CLK_LPI2C7, + }; + + if (i2c_num < 4 || i2c_num > 7) + return -EINVAL; + + if (enable) { + pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false); + pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4], SCG_FIRC_DIV2_CLK); + pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], true); + } else { + pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false); + } + return 0; +} + +u32 imx_get_i2cclk(unsigned i2c_num) +{ + const enum pcc_clk lpi2c_pcc_clks[] = { + PER_CLK_LPI2C4, + PER_CLK_LPI2C5, + PER_CLK_LPI2C6, + PER_CLK_LPI2C7, + }; + + if (i2c_num < 4 || i2c_num > 7) + return 0; + + return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4]); +} +#endif + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h index f21052e..ebf32c6 100644 --- a/arch/arm/include/asm/arch-mx7ulp/clock.h +++ b/arch/arm/include/asm/arch-mx7ulp/clock.h @@ -27,6 +27,10 @@ enum mxc_clock { u32 mxc_get_clock(enum mxc_clock clk); u32 get_lpuart_clk(void); +#ifdef CONFIG_SYS_LPI2C_IMX +int enable_i2c_clk(unsigned char enable, unsigned i2c_num); +u32 imx_get_i2cclk(unsigned i2c_num); +#endif #ifdef CONFIG_MXC_OCOTP void enable_ocotp_clk(unsigned char enable); #endif -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 07/20] imx: mx7ulp: Implement the clock functions for i2c driver 2016-12-27 10:04 ` [U-Boot] [PATCH V2 07/20] imx: mx7ulp: Implement the clock functions for i2c driver Peng Fan @ 2017-02-12 9:20 ` Stefano Babic 0 siblings, 0 replies; 48+ messages in thread From: Stefano Babic @ 2017-02-12 9:20 UTC (permalink / raw) To: u-boot On 27/12/2016 11:04, Peng Fan wrote: > From: Ye Li <ye.li@nxp.com> > > Implement the i2c clock enable and get function for mx7ulp. These > functions are required by imx_lpi2c driver. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Signed-off-by: Ye Li <ye.li@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > None > > arch/arm/cpu/armv7/mx7ulp/clock.c | 40 ++++++++++++++++++++++++++++++++ > arch/arm/include/asm/arch-mx7ulp/clock.h | 4 ++++ > 2 files changed, 44 insertions(+) > > diff --git a/arch/arm/cpu/armv7/mx7ulp/clock.c b/arch/arm/cpu/armv7/mx7ulp/clock.c > index 0c34d88..30db67d 100644 > --- a/arch/arm/cpu/armv7/mx7ulp/clock.c > +++ b/arch/arm/cpu/armv7/mx7ulp/clock.c > @@ -73,6 +73,46 @@ u32 get_lpuart_clk(void) > return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]); > } > > +#ifdef CONFIG_SYS_LPI2C_IMX > +int enable_i2c_clk(unsigned char enable, unsigned i2c_num) > +{ > + /* Set parent to FIRC DIV2 clock */ > + const enum pcc_clk lpi2c_pcc_clks[] = { > + PER_CLK_LPI2C4, > + PER_CLK_LPI2C5, > + PER_CLK_LPI2C6, > + PER_CLK_LPI2C7, > + }; > + > + if (i2c_num < 4 || i2c_num > 7) > + return -EINVAL; > + > + if (enable) { > + pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false); > + pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4], SCG_FIRC_DIV2_CLK); > + pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], true); > + } else { > + pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false); > + } > + return 0; > +} > + > +u32 imx_get_i2cclk(unsigned i2c_num) > +{ > + const enum pcc_clk lpi2c_pcc_clks[] = { > + PER_CLK_LPI2C4, > + PER_CLK_LPI2C5, > + PER_CLK_LPI2C6, > + PER_CLK_LPI2C7, > + }; > + > + if (i2c_num < 4 || i2c_num > 7) > + return 0; > + > + return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4]); > +} > +#endif > + > unsigned int mxc_get_clock(enum mxc_clock clk) > { > switch (clk) { > diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h > index f21052e..ebf32c6 100644 > --- a/arch/arm/include/asm/arch-mx7ulp/clock.h > +++ b/arch/arm/include/asm/arch-mx7ulp/clock.h > @@ -27,6 +27,10 @@ enum mxc_clock { > > u32 mxc_get_clock(enum mxc_clock clk); > u32 get_lpuart_clk(void); > +#ifdef CONFIG_SYS_LPI2C_IMX > +int enable_i2c_clk(unsigned char enable, unsigned i2c_num); > +u32 imx_get_i2cclk(unsigned i2c_num); > +#endif > #ifdef CONFIG_MXC_OCOTP > void enable_ocotp_clk(unsigned char enable); > #endif > Reviewed-by : Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 08/20] gpio: Add Rapid GPIO2P driver for i.MX7ULP 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (6 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 07/20] imx: mx7ulp: Implement the clock functions for i2c driver Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2017-02-12 9:21 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 09/20] mxc_ocotp: Update driver to support OCOTP controller on i.MX7ULP Peng Fan ` (12 subsequent siblings) 20 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Add the imx_rgpio2p driver for Rapid GPIO2P controllers on i.MX7ULP. Have added all ports on RGPIO2P_0 and RGPIO2P_1. The configurations CONFIG_IMX_RGPIO2P and CONFIG_DM_GPIO must be set to y to enable the drivers. To use the GPIO function, the IBE and OBE needs to set in IOMUXC. We did not set the bits in driver, but leave them to IOMUXC settings of the GPIO pins. User should use IMX_GPIO_NR to generate the GPIO number for gpio APIs access. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: None arch/arm/include/asm/arch-mx7ulp/gpio.h | 22 ++++ drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/imx_rgpio2p.c | 224 ++++++++++++++++++++++++++++++++ 4 files changed, 254 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx7ulp/gpio.h create mode 100644 drivers/gpio/imx_rgpio2p.c diff --git a/arch/arm/include/asm/arch-mx7ulp/gpio.h b/arch/arm/include/asm/arch-mx7ulp/gpio.h new file mode 100644 index 0000000..fe41101 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7ulp/gpio.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MX7ULP_GPIO_H +#define __ASM_ARCH_MX7ULP_GPIO_H + +struct gpio_regs { + u32 gpio_pdor; + u32 gpio_psor; + u32 gpio_pcor; + u32 gpio_ptor; + u32 gpio_pdir; + u32 gpio_pddr; + u32 gpio_gacr; +}; + +#define IMX_GPIO_NR(port, index) ((((port)-1)*32)+((index)&31)) + +#endif /* __ASM_ARCH_MX7ULP_GPIO_H */ diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8d9ab52..dc4108f 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -48,6 +48,13 @@ config INTEL_BROADWELL_GPIO driver from the common Intel ICH6 driver. It supports a total of 95 GPIOs which can be configured from the device tree. +config IMX_RGPIO2P + bool "i.MX7ULP RGPIO2P driver" + depends on DM + default n + help + This driver supports i.MX7ULP Rapid GPIO2P controller. + config LPC32XX_GPIO bool "LPC32XX GPIO driver" depends on DM diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 8939226..27f8068 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o +obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o obj-$(CONFIG_MSM_GPIO) += msm_gpio.o diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c new file mode 100644 index 0000000..886b161 --- /dev/null +++ b/drivers/gpio/imx_rgpio2p.c @@ -0,0 +1,224 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * RGPIO2P driver for the Freescale i.MX7ULP. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <malloc.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum imx_rgpio2p_direction { + IMX_RGPIO2P_DIRECTION_IN, + IMX_RGPIO2P_DIRECTION_OUT, +}; + +#define GPIO_PER_BANK 32 + +struct imx_rgpio2p_data { + struct gpio_regs *regs; +}; + +struct imx_rgpio2p_plat { + int bank_index; + struct gpio_regs *regs; +}; + +static int imx_rgpio2p_is_output(struct gpio_regs *regs, int offset) +{ + u32 val; + + val = readl(®s->gpio_pddr); + + return val & (1 << offset) ? 1 : 0; +} + +static void imx_rgpio2p_bank_direction(struct gpio_regs *regs, int offset, + enum imx_rgpio2p_direction direction) +{ + u32 l; + + l = readl(®s->gpio_pddr); + + switch (direction) { + case IMX_RGPIO2P_DIRECTION_OUT: + l |= 1 << offset; + break; + case IMX_RGPIO2P_DIRECTION_IN: + l &= ~(1 << offset); + } + writel(l, ®s->gpio_pddr); +} + +static void imx_rgpio2p_bank_set_value(struct gpio_regs *regs, int offset, + int value) +{ + if (value) + writel((1 << offset), ®s->gpio_psor); + else + writel((1 << offset), ®s->gpio_pcor); +} + +static int imx_rgpio2p_bank_get_value(struct gpio_regs *regs, int offset) +{ + return (readl(®s->gpio_pdir) >> offset) & 0x01; +} + +static int imx_rgpio2p_direction_input(struct udevice *dev, unsigned offset) +{ + struct imx_rgpio2p_data *bank = dev_get_priv(dev); + + /* Configure GPIO direction as input. */ + imx_rgpio2p_bank_direction(bank->regs, offset, IMX_RGPIO2P_DIRECTION_IN); + + return 0; +} + +static int imx_rgpio2p_direction_output(struct udevice *dev, unsigned offset, + int value) +{ + struct imx_rgpio2p_data *bank = dev_get_priv(dev); + + /* Configure GPIO output value. */ + imx_rgpio2p_bank_set_value(bank->regs, offset, value); + + /* Configure GPIO direction as output. */ + imx_rgpio2p_bank_direction(bank->regs, offset, IMX_RGPIO2P_DIRECTION_OUT); + + return 0; +} + +static int imx_rgpio2p_get_value(struct udevice *dev, unsigned offset) +{ + struct imx_rgpio2p_data *bank = dev_get_priv(dev); + + return imx_rgpio2p_bank_get_value(bank->regs, offset); +} + +static int imx_rgpio2p_set_value(struct udevice *dev, unsigned offset, + int value) +{ + struct imx_rgpio2p_data *bank = dev_get_priv(dev); + + imx_rgpio2p_bank_set_value(bank->regs, offset, value); + + return 0; +} + +static int imx_rgpio2p_get_function(struct udevice *dev, unsigned offset) +{ + struct imx_rgpio2p_data *bank = dev_get_priv(dev); + + /* GPIOF_FUNC is not implemented yet */ + if (imx_rgpio2p_is_output(bank->regs, offset)) + return GPIOF_OUTPUT; + else + return GPIOF_INPUT; +} + +static const struct dm_gpio_ops imx_rgpio2p_ops = { + .direction_input = imx_rgpio2p_direction_input, + .direction_output = imx_rgpio2p_direction_output, + .get_value = imx_rgpio2p_get_value, + .set_value = imx_rgpio2p_set_value, + .get_function = imx_rgpio2p_get_function, +}; + +static int imx_rgpio2p_probe(struct udevice *dev) +{ + struct imx_rgpio2p_data *bank = dev_get_priv(dev); + struct imx_rgpio2p_plat *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + int banknum; + char name[18], *str; + + banknum = plat->bank_index; + sprintf(name, "GPIO%d_", banknum + 1); + str = strdup(name); + if (!str) + return -ENOMEM; + uc_priv->bank_name = str; + uc_priv->gpio_count = GPIO_PER_BANK; + bank->regs = plat->regs; + + return 0; +} + +static int imx_rgpio2p_bind(struct udevice *dev) +{ + struct imx_rgpio2p_plat *plat = dev->platdata; + fdt_addr_t addr; + + /* + * If platdata already exsits, directly return. + * Actually only when DT is not supported, platdata + * is statically initialized in U_BOOT_DEVICES.Here + * will return. + */ + if (plat) + return 0; + + addr = dev_get_addr_index(dev, 1); + if (addr == FDT_ADDR_T_NONE) + return -ENODEV; + + /* + * TODO: + * When every board is converted to driver model and DT is supported, + * this can be done by auto-alloc feature, but not using calloc + * to alloc memory for platdata. + */ + plat = calloc(1, sizeof(*plat)); + if (!plat) + return -ENOMEM; + + plat->regs = (struct gpio_regs *)addr; + plat->bank_index = dev->req_seq; + dev->platdata = plat; + + return 0; +} + + +static const struct udevice_id imx_rgpio2p_ids[] = { + { .compatible = "fsl,imx7ulp-gpio" }, + { } +}; + +U_BOOT_DRIVER(imx_rgpio2p) = { + .name = "imx_rgpio2p", + .id = UCLASS_GPIO, + .ops = &imx_rgpio2p_ops, + .probe = imx_rgpio2p_probe, + .priv_auto_alloc_size = sizeof(struct imx_rgpio2p_plat), + .of_match = imx_rgpio2p_ids, + .bind = imx_rgpio2p_bind, +}; + +#if !CONFIG_IS_ENABLED(OF_CONTROL) +static const struct imx_rgpio2p_plat imx_plat[] = { + { 0, (struct gpio_regs *)RGPIO2P_GPIO1_BASE_ADDR }, + { 1, (struct gpio_regs *)RGPIO2P_GPIO2_BASE_ADDR }, + { 2, (struct gpio_regs *)RGPIO2P_GPIO3_BASE_ADDR }, + { 3, (struct gpio_regs *)RGPIO2P_GPIO4_BASE_ADDR }, + { 4, (struct gpio_regs *)RGPIO2P_GPIO5_BASE_ADDR }, + { 5, (struct gpio_regs *)RGPIO2P_GPIO6_BASE_ADDR }, +}; + +U_BOOT_DEVICES(imx_rgpio2ps) = { + { "imx_rgpio2p", &imx_plat[0] }, + { "imx_rgpio2p", &imx_plat[1] }, + { "imx_rgpio2p", &imx_plat[2] }, + { "imx_rgpio2p", &imx_plat[3] }, + { "imx_rgpio2p", &imx_plat[4] }, + { "imx_rgpio2p", &imx_plat[5] }, +}; +#endif -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 08/20] gpio: Add Rapid GPIO2P driver for i.MX7ULP 2016-12-27 10:04 ` [U-Boot] [PATCH V2 08/20] gpio: Add Rapid GPIO2P driver for i.MX7ULP Peng Fan @ 2017-02-12 9:21 ` Stefano Babic 0 siblings, 0 replies; 48+ messages in thread From: Stefano Babic @ 2017-02-12 9:21 UTC (permalink / raw) To: u-boot On 27/12/2016 11:04, Peng Fan wrote: > Add the imx_rgpio2p driver for Rapid GPIO2P controllers on i.MX7ULP. > Have added all ports on RGPIO2P_0 and RGPIO2P_1. > > The configurations CONFIG_IMX_RGPIO2P and CONFIG_DM_GPIO must be set > to y to enable the drivers. > > To use the GPIO function, the IBE and OBE needs to set in IOMUXC. > We did not set the bits in driver, but leave them to IOMUXC settings > of the GPIO pins. User should use IMX_GPIO_NR to generate the GPIO number > for gpio APIs access. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Signed-off-by: Ye Li <ye.li@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > None > > arch/arm/include/asm/arch-mx7ulp/gpio.h | 22 ++++ > drivers/gpio/Kconfig | 7 + > drivers/gpio/Makefile | 1 + > drivers/gpio/imx_rgpio2p.c | 224 ++++++++++++++++++++++++++++++++ > 4 files changed, 254 insertions(+) > create mode 100644 arch/arm/include/asm/arch-mx7ulp/gpio.h > create mode 100644 drivers/gpio/imx_rgpio2p.c > > diff --git a/arch/arm/include/asm/arch-mx7ulp/gpio.h b/arch/arm/include/asm/arch-mx7ulp/gpio.h > new file mode 100644 > index 0000000..fe41101 > --- /dev/null > +++ b/arch/arm/include/asm/arch-mx7ulp/gpio.h > @@ -0,0 +1,22 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __ASM_ARCH_MX7ULP_GPIO_H > +#define __ASM_ARCH_MX7ULP_GPIO_H > + > +struct gpio_regs { > + u32 gpio_pdor; > + u32 gpio_psor; > + u32 gpio_pcor; > + u32 gpio_ptor; > + u32 gpio_pdir; > + u32 gpio_pddr; > + u32 gpio_gacr; > +}; > + > +#define IMX_GPIO_NR(port, index) ((((port)-1)*32)+((index)&31)) > + > +#endif /* __ASM_ARCH_MX7ULP_GPIO_H */ > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig > index 8d9ab52..dc4108f 100644 > --- a/drivers/gpio/Kconfig > +++ b/drivers/gpio/Kconfig > @@ -48,6 +48,13 @@ config INTEL_BROADWELL_GPIO > driver from the common Intel ICH6 driver. It supports a total of > 95 GPIOs which can be configured from the device tree. > > +config IMX_RGPIO2P > + bool "i.MX7ULP RGPIO2P driver" > + depends on DM > + default n > + help > + This driver supports i.MX7ULP Rapid GPIO2P controller. > + > config LPC32XX_GPIO > bool "LPC32XX GPIO driver" > depends on DM > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile > index 8939226..27f8068 100644 > --- a/drivers/gpio/Makefile > +++ b/drivers/gpio/Makefile > @@ -53,6 +53,7 @@ obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o > obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o > obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o > obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o > +obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o > obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o > obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o > obj-$(CONFIG_MSM_GPIO) += msm_gpio.o > diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c > new file mode 100644 > index 0000000..886b161 > --- /dev/null > +++ b/drivers/gpio/imx_rgpio2p.c > @@ -0,0 +1,224 @@ > +/* > + * Copyright 2016 Freescale Semiconductor, Inc. > + * > + * RGPIO2P driver for the Freescale i.MX7ULP. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <dm.h> > +#include <errno.h> > +#include <fdtdec.h> > +#include <asm/gpio.h> > +#include <asm/io.h> > +#include <malloc.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +enum imx_rgpio2p_direction { > + IMX_RGPIO2P_DIRECTION_IN, > + IMX_RGPIO2P_DIRECTION_OUT, > +}; > + > +#define GPIO_PER_BANK 32 > + > +struct imx_rgpio2p_data { > + struct gpio_regs *regs; > +}; > + > +struct imx_rgpio2p_plat { > + int bank_index; > + struct gpio_regs *regs; > +}; > + > +static int imx_rgpio2p_is_output(struct gpio_regs *regs, int offset) > +{ > + u32 val; > + > + val = readl(®s->gpio_pddr); > + > + return val & (1 << offset) ? 1 : 0; > +} > + > +static void imx_rgpio2p_bank_direction(struct gpio_regs *regs, int offset, > + enum imx_rgpio2p_direction direction) > +{ > + u32 l; > + > + l = readl(®s->gpio_pddr); > + > + switch (direction) { > + case IMX_RGPIO2P_DIRECTION_OUT: > + l |= 1 << offset; > + break; > + case IMX_RGPIO2P_DIRECTION_IN: > + l &= ~(1 << offset); > + } > + writel(l, ®s->gpio_pddr); > +} > + > +static void imx_rgpio2p_bank_set_value(struct gpio_regs *regs, int offset, > + int value) > +{ > + if (value) > + writel((1 << offset), ®s->gpio_psor); > + else > + writel((1 << offset), ®s->gpio_pcor); > +} > + > +static int imx_rgpio2p_bank_get_value(struct gpio_regs *regs, int offset) > +{ > + return (readl(®s->gpio_pdir) >> offset) & 0x01; > +} > + > +static int imx_rgpio2p_direction_input(struct udevice *dev, unsigned offset) > +{ > + struct imx_rgpio2p_data *bank = dev_get_priv(dev); > + > + /* Configure GPIO direction as input. */ > + imx_rgpio2p_bank_direction(bank->regs, offset, IMX_RGPIO2P_DIRECTION_IN); > + > + return 0; > +} > + > +static int imx_rgpio2p_direction_output(struct udevice *dev, unsigned offset, > + int value) > +{ > + struct imx_rgpio2p_data *bank = dev_get_priv(dev); > + > + /* Configure GPIO output value. */ > + imx_rgpio2p_bank_set_value(bank->regs, offset, value); > + > + /* Configure GPIO direction as output. */ > + imx_rgpio2p_bank_direction(bank->regs, offset, IMX_RGPIO2P_DIRECTION_OUT); > + > + return 0; > +} > + > +static int imx_rgpio2p_get_value(struct udevice *dev, unsigned offset) > +{ > + struct imx_rgpio2p_data *bank = dev_get_priv(dev); > + > + return imx_rgpio2p_bank_get_value(bank->regs, offset); > +} > + > +static int imx_rgpio2p_set_value(struct udevice *dev, unsigned offset, > + int value) > +{ > + struct imx_rgpio2p_data *bank = dev_get_priv(dev); > + > + imx_rgpio2p_bank_set_value(bank->regs, offset, value); > + > + return 0; > +} > + > +static int imx_rgpio2p_get_function(struct udevice *dev, unsigned offset) > +{ > + struct imx_rgpio2p_data *bank = dev_get_priv(dev); > + > + /* GPIOF_FUNC is not implemented yet */ > + if (imx_rgpio2p_is_output(bank->regs, offset)) > + return GPIOF_OUTPUT; > + else > + return GPIOF_INPUT; > +} > + > +static const struct dm_gpio_ops imx_rgpio2p_ops = { > + .direction_input = imx_rgpio2p_direction_input, > + .direction_output = imx_rgpio2p_direction_output, > + .get_value = imx_rgpio2p_get_value, > + .set_value = imx_rgpio2p_set_value, > + .get_function = imx_rgpio2p_get_function, > +}; > + > +static int imx_rgpio2p_probe(struct udevice *dev) > +{ > + struct imx_rgpio2p_data *bank = dev_get_priv(dev); > + struct imx_rgpio2p_plat *plat = dev_get_platdata(dev); > + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); > + int banknum; > + char name[18], *str; > + > + banknum = plat->bank_index; > + sprintf(name, "GPIO%d_", banknum + 1); > + str = strdup(name); > + if (!str) > + return -ENOMEM; > + uc_priv->bank_name = str; > + uc_priv->gpio_count = GPIO_PER_BANK; > + bank->regs = plat->regs; > + > + return 0; > +} > + > +static int imx_rgpio2p_bind(struct udevice *dev) > +{ > + struct imx_rgpio2p_plat *plat = dev->platdata; > + fdt_addr_t addr; > + > + /* > + * If platdata already exsits, directly return. > + * Actually only when DT is not supported, platdata > + * is statically initialized in U_BOOT_DEVICES.Here > + * will return. > + */ > + if (plat) > + return 0; > + > + addr = dev_get_addr_index(dev, 1); > + if (addr == FDT_ADDR_T_NONE) > + return -ENODEV; > + > + /* > + * TODO: > + * When every board is converted to driver model and DT is supported, > + * this can be done by auto-alloc feature, but not using calloc > + * to alloc memory for platdata. > + */ > + plat = calloc(1, sizeof(*plat)); > + if (!plat) > + return -ENOMEM; > + > + plat->regs = (struct gpio_regs *)addr; > + plat->bank_index = dev->req_seq; > + dev->platdata = plat; > + > + return 0; > +} > + > + > +static const struct udevice_id imx_rgpio2p_ids[] = { > + { .compatible = "fsl,imx7ulp-gpio" }, > + { } > +}; > + > +U_BOOT_DRIVER(imx_rgpio2p) = { > + .name = "imx_rgpio2p", > + .id = UCLASS_GPIO, > + .ops = &imx_rgpio2p_ops, > + .probe = imx_rgpio2p_probe, > + .priv_auto_alloc_size = sizeof(struct imx_rgpio2p_plat), > + .of_match = imx_rgpio2p_ids, > + .bind = imx_rgpio2p_bind, > +}; > + > +#if !CONFIG_IS_ENABLED(OF_CONTROL) > +static const struct imx_rgpio2p_plat imx_plat[] = { > + { 0, (struct gpio_regs *)RGPIO2P_GPIO1_BASE_ADDR }, > + { 1, (struct gpio_regs *)RGPIO2P_GPIO2_BASE_ADDR }, > + { 2, (struct gpio_regs *)RGPIO2P_GPIO3_BASE_ADDR }, > + { 3, (struct gpio_regs *)RGPIO2P_GPIO4_BASE_ADDR }, > + { 4, (struct gpio_regs *)RGPIO2P_GPIO5_BASE_ADDR }, > + { 5, (struct gpio_regs *)RGPIO2P_GPIO6_BASE_ADDR }, > +}; > + > +U_BOOT_DEVICES(imx_rgpio2ps) = { > + { "imx_rgpio2p", &imx_plat[0] }, > + { "imx_rgpio2p", &imx_plat[1] }, > + { "imx_rgpio2p", &imx_plat[2] }, > + { "imx_rgpio2p", &imx_plat[3] }, > + { "imx_rgpio2p", &imx_plat[4] }, > + { "imx_rgpio2p", &imx_plat[5] }, > +}; > +#endif > Reviewed-by : Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 09/20] mxc_ocotp: Update driver to support OCOTP controller on i.MX7ULP 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (7 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 08/20] gpio: Add Rapid GPIO2P driver for i.MX7ULP Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2017-02-12 9:22 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 10/20] mx7ulp: Add iomux pins header file Peng Fan ` (11 subsequent siblings) 20 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Update the mxc_ocotp driver to support i.MX7ULP. The read/write sequence has some changes due to PDN and OUT_STATUS registers added and TIME register is removed. Also update the bank size and number. Add is_mx7ulp macro in sys_proto.h Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: Add imx_mx7ulp, and small update. arch/arm/include/asm/imx-common/sys_proto.h | 2 ++ drivers/misc/mxc_ocotp.c | 52 ++++++++++++++++++++++++++++- 2 files changed, 53 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h index 539d34b..732b692 100644 --- a/arch/arm/include/asm/imx-common/sys_proto.h +++ b/arch/arm/include/asm/imx-common/sys_proto.h @@ -38,6 +38,8 @@ #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL)) #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) +#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) + u32 get_nr_cpus(void); u32 get_cpu_rev(void); u32 get_cpu_speed_grade_hz(void); diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 0b1c050..88610d6 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -29,6 +29,12 @@ #ifdef CONFIG_MX7 #define BM_CTRL_ADDR 0x0000000f #define BM_CTRL_RELOAD 0x00000400 +#elif defined(CONFIG_MX7ULP) +#define BM_CTRL_ADDR 0x000000FF +#define BM_CTRL_RELOAD 0x00000400 +#define BM_OUT_STATUS_DED 0x00000400 +#define BM_OUT_STATUS_LOCKED 0x00000800 +#define BM_OUT_STATUS_PROGFAIL 0x00001000 #else #define BM_CTRL_ADDR 0x0000007f #endif @@ -70,6 +76,9 @@ #elif defined CONFIG_MX7 #define FUSE_BANK_SIZE 0x40 #define FUSE_BANKS 16 +#elif defined(CONFIG_MX7ULP) +#define FUSE_BANK_SIZE 0x80 +#define FUSE_BANKS 31 #else #error "Unsupported architecture\n" #endif @@ -98,7 +107,7 @@ u32 fuse_bank_physical(int index) { u32 phy_index; - if (is_mx6sl()) { + if (is_mx6sl() || is_mx7ulp()) { phy_index = index; } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) { if ((is_mx6ull() || is_mx6sll()) && index == 8) @@ -187,6 +196,10 @@ static int finish_access(struct ocotp_regs *regs, const char *caller) err = !!(readl(®s->ctrl) & BM_CTRL_ERROR); clear_error(regs); +#ifdef CONFIG_MX7ULP + /* Need to power down the OTP memory */ + writel(1, ®s->pdn); +#endif if (err) { printf("mxc_ocotp %s(): Access protect error\n", caller); return -EIO; @@ -217,6 +230,13 @@ int fuse_read(u32 bank, u32 word, u32 *val) *val = readl(®s->bank[phy_bank].fuse_regs[phy_word << 2]); +#ifdef CONFIG_MX7ULP + if (readl(®s->out_status) & BM_OUT_STATUS_DED) { + writel(BM_OUT_STATUS_DED, ®s->out_status_clr); + printf("mxc_ocotp %s(): fuse read wrong\n", __func__); + return -EIO; + } +#endif return finish_access(regs, __func__); } @@ -238,6 +258,12 @@ static void set_timing(struct ocotp_regs *regs) clrsetbits_le32(®s->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG, timing); } +#elif defined(CONFIG_MX7ULP) +static void set_timing(struct ocotp_regs *regs) +{ + /* No timing set for MX7ULP */ +} + #else static void set_timing(struct ocotp_regs *regs) { @@ -302,6 +328,14 @@ int fuse_sense(u32 bank, u32 word, u32 *val) *val = readl(®s->read_fuse_data); #endif +#ifdef CONFIG_MX7ULP + if (readl(®s->out_status) & BM_OUT_STATUS_DED) { + writel(BM_OUT_STATUS_DED, ®s->out_status_clr); + printf("mxc_ocotp %s(): fuse read wrong\n", __func__); + return -EIO; + } +#endif + return finish_access(regs, __func__); } @@ -355,6 +389,14 @@ int fuse_prog(u32 bank, u32 word, u32 val) #endif udelay(WRITE_POSTAMBLE_US); +#ifdef CONFIG_MX7ULP + if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) { + writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr); + printf("mxc_ocotp %s(): fuse write is failed\n", __func__); + return -EIO; + } +#endif + return finish_access(regs, __func__); } @@ -374,5 +416,13 @@ int fuse_override(u32 bank, u32 word, u32 val) writel(val, ®s->bank[phy_bank].fuse_regs[phy_word << 2]); +#ifdef CONFIG_MX7ULP + if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) { + writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr); + printf("mxc_ocotp %s(): fuse write is failed\n", __func__); + return -EIO; + } +#endif + return finish_access(regs, __func__); } -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 09/20] mxc_ocotp: Update driver to support OCOTP controller on i.MX7ULP 2016-12-27 10:04 ` [U-Boot] [PATCH V2 09/20] mxc_ocotp: Update driver to support OCOTP controller on i.MX7ULP Peng Fan @ 2017-02-12 9:22 ` Stefano Babic 0 siblings, 0 replies; 48+ messages in thread From: Stefano Babic @ 2017-02-12 9:22 UTC (permalink / raw) To: u-boot On 27/12/2016 11:04, Peng Fan wrote: > Update the mxc_ocotp driver to support i.MX7ULP. > The read/write sequence has some changes due to > PDN and OUT_STATUS registers added and TIME register is > removed. Also update the bank size and number. > > Add is_mx7ulp macro in sys_proto.h > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Signed-off-by: Ye Li <ye.li@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > Add imx_mx7ulp, and small update. > > arch/arm/include/asm/imx-common/sys_proto.h | 2 ++ > drivers/misc/mxc_ocotp.c | 52 ++++++++++++++++++++++++++++- > 2 files changed, 53 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h > index 539d34b..732b692 100644 > --- a/arch/arm/include/asm/imx-common/sys_proto.h > +++ b/arch/arm/include/asm/imx-common/sys_proto.h > @@ -38,6 +38,8 @@ > #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL)) > #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) > > +#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) > + > u32 get_nr_cpus(void); > u32 get_cpu_rev(void); > u32 get_cpu_speed_grade_hz(void); > diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c > index 0b1c050..88610d6 100644 > --- a/drivers/misc/mxc_ocotp.c > +++ b/drivers/misc/mxc_ocotp.c > @@ -29,6 +29,12 @@ > #ifdef CONFIG_MX7 > #define BM_CTRL_ADDR 0x0000000f > #define BM_CTRL_RELOAD 0x00000400 > +#elif defined(CONFIG_MX7ULP) > +#define BM_CTRL_ADDR 0x000000FF > +#define BM_CTRL_RELOAD 0x00000400 > +#define BM_OUT_STATUS_DED 0x00000400 > +#define BM_OUT_STATUS_LOCKED 0x00000800 > +#define BM_OUT_STATUS_PROGFAIL 0x00001000 > #else > #define BM_CTRL_ADDR 0x0000007f > #endif > @@ -70,6 +76,9 @@ > #elif defined CONFIG_MX7 > #define FUSE_BANK_SIZE 0x40 > #define FUSE_BANKS 16 > +#elif defined(CONFIG_MX7ULP) > +#define FUSE_BANK_SIZE 0x80 > +#define FUSE_BANKS 31 > #else > #error "Unsupported architecture\n" > #endif > @@ -98,7 +107,7 @@ u32 fuse_bank_physical(int index) > { > u32 phy_index; > > - if (is_mx6sl()) { > + if (is_mx6sl() || is_mx7ulp()) { > phy_index = index; > } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) { > if ((is_mx6ull() || is_mx6sll()) && index == 8) > @@ -187,6 +196,10 @@ static int finish_access(struct ocotp_regs *regs, const char *caller) > err = !!(readl(®s->ctrl) & BM_CTRL_ERROR); > clear_error(regs); > > +#ifdef CONFIG_MX7ULP > + /* Need to power down the OTP memory */ > + writel(1, ®s->pdn); > +#endif > if (err) { > printf("mxc_ocotp %s(): Access protect error\n", caller); > return -EIO; > @@ -217,6 +230,13 @@ int fuse_read(u32 bank, u32 word, u32 *val) > > *val = readl(®s->bank[phy_bank].fuse_regs[phy_word << 2]); > > +#ifdef CONFIG_MX7ULP > + if (readl(®s->out_status) & BM_OUT_STATUS_DED) { > + writel(BM_OUT_STATUS_DED, ®s->out_status_clr); > + printf("mxc_ocotp %s(): fuse read wrong\n", __func__); > + return -EIO; > + } > +#endif > return finish_access(regs, __func__); > } > > @@ -238,6 +258,12 @@ static void set_timing(struct ocotp_regs *regs) > clrsetbits_le32(®s->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG, > timing); > } > +#elif defined(CONFIG_MX7ULP) > +static void set_timing(struct ocotp_regs *regs) > +{ > + /* No timing set for MX7ULP */ > +} > + > #else > static void set_timing(struct ocotp_regs *regs) > { > @@ -302,6 +328,14 @@ int fuse_sense(u32 bank, u32 word, u32 *val) > *val = readl(®s->read_fuse_data); > #endif > > +#ifdef CONFIG_MX7ULP > + if (readl(®s->out_status) & BM_OUT_STATUS_DED) { > + writel(BM_OUT_STATUS_DED, ®s->out_status_clr); > + printf("mxc_ocotp %s(): fuse read wrong\n", __func__); > + return -EIO; > + } > +#endif > + > return finish_access(regs, __func__); > } > > @@ -355,6 +389,14 @@ int fuse_prog(u32 bank, u32 word, u32 val) > #endif > udelay(WRITE_POSTAMBLE_US); > > +#ifdef CONFIG_MX7ULP > + if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) { > + writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr); > + printf("mxc_ocotp %s(): fuse write is failed\n", __func__); > + return -EIO; > + } > +#endif > + > return finish_access(regs, __func__); > } > > @@ -374,5 +416,13 @@ int fuse_override(u32 bank, u32 word, u32 val) > > writel(val, ®s->bank[phy_bank].fuse_regs[phy_word << 2]); > > +#ifdef CONFIG_MX7ULP > + if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) { > + writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr); > + printf("mxc_ocotp %s(): fuse write is failed\n", __func__); > + return -EIO; > + } > +#endif > + > return finish_access(regs, __func__); > } > Reviewed-by : Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 10/20] mx7ulp: Add iomux pins header file 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (8 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 09/20] mxc_ocotp: Update driver to support OCOTP controller on i.MX7ULP Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2016-12-27 10:04 ` [U-Boot] [PATCH V2 11/20] wdog: Add the watchdog driver for MX7ULP Peng Fan ` (10 subsequent siblings) 20 siblings, 0 replies; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot From: Ye Li <ye.li@nxp.com> Add the iomux pins header file from iomux tool team. Change the IOMUXC0 pins to add IOMUX_CONFIG_MPORTS flags. Note: The IOMUXC0 offset provided in this file is from 0xD000, this is not aligned with IOMUXC0 base address. We have adjusted the IOMUXC0 base address to aligin with it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: None arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h | 910 +++++++++++++++++++++++++ 1 file changed, 910 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h diff --git a/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h b/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h new file mode 100644 index 0000000..4e4740c --- /dev/null +++ b/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h @@ -0,0 +1,910 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_IMX7ULP_PINS_H__ +#define __ASM_ARCH_IMX7ULP_PINS_H__ + +#include <asm/arch/iomux.h> + +enum { + MX7ULP_PAD_PTA0__CMP0_IN1_3V = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA0__PTA0 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA0__LPSPI0_PCS1 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x2, 0), + MX7ULP_PAD_PTA0__LPUART0_CTS_b = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x2, 0), + MX7ULP_PAD_PTA0__LPI2C0_SCL = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x2, 0), + MX7ULP_PAD_PTA0__TPM0_CLKIN = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x2, 0), + MX7ULP_PAD_PTA0__I2S0_RX_BCLK = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x2, 0), + MX7ULP_PAD_PTA0__LLWU0_P0 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA1__CMP0_IN2_3V = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA1__PTA1 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA1__LPSPI0_PCS2 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x1, 0), + MX7ULP_PAD_PTA1__LPUART0_RTS_b = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA1__LPI2C0_SDA = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x1, 0), + MX7ULP_PAD_PTA1__TPM0_CH0 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x1, 0), + MX7ULP_PAD_PTA1__I2S0_RX_FS = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x1, 0), + MX7ULP_PAD_PTA2__CMP1_IN2_3V = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA2__PTA2 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA2__LPSPI0_PCS3 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x1, 0), + MX7ULP_PAD_PTA2__LPUART0_TX = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x1, 0), + MX7ULP_PAD_PTA2__LPI2C0_HREQ = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x1, 0), + MX7ULP_PAD_PTA2__TPM0_CH1 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x1, 0), + MX7ULP_PAD_PTA2__I2S0_RXD0 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x1, 0), + MX7ULP_PAD_PTA3__CMP1_IN4_3V = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA3__PTA3 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA3__LPSPI0_PCS0 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x1, 0), + MX7ULP_PAD_PTA3__LPUART0_RX = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x1, 0), + MX7ULP_PAD_PTA3__TPM0_CH2 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x1, 0), + MX7ULP_PAD_PTA3__I2S0_RXD1 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E0, 0x1, 0), + MX7ULP_PAD_PTA3__CMP0_OUT = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA3__LLWU0_P1 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA4__ADC1_CH3A = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA4__PTA4 = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA4__LPSPI0_SIN = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x1, 0), + MX7ULP_PAD_PTA4__LPUART1_CTS_b = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x1, 0), + MX7ULP_PAD_PTA4__LPI2C1_SCL = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x1, 0), + MX7ULP_PAD_PTA4__TPM0_CH3 = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x1, 0), + MX7ULP_PAD_PTA4__I2S0_MCLK = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x1, 0), + MX7ULP_PAD_PTA5__ADC1_CH3B = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA5__PTA5 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA5__LPSPI0_SOUT = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x1, 0), + MX7ULP_PAD_PTA5__LPUART1_RTS_b = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA5__LPI2C1_SDA = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x1, 0), + MX7ULP_PAD_PTA5__TPM0_CH4 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x1, 0), + MX7ULP_PAD_PTA5__I2S0_TX_BCLK = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C0, 0x1, 0), + MX7ULP_PAD_PTA6__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA6__PTA6 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA6__LPSPI0_SCK = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x1, 0), + MX7ULP_PAD_PTA6__LPUART1_TX = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x1, 0), + MX7ULP_PAD_PTA6__LPI2C1_HREQ = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x1, 0), + MX7ULP_PAD_PTA6__TPM0_CH5 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x6, 0xD14C, 0x1, 0), + MX7ULP_PAD_PTA6__I2S0_TX_FS = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x1, 0), + MX7ULP_PAD_PTA7__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA7__PTA7 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA7__LPUART1_RX = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x1, 0), + MX7ULP_PAD_PTA7__TPM1_CH1 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x1, 0), + MX7ULP_PAD_PTA7__I2S0_TXD0 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA8__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA8__PTA8 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA8__LPSPI1_PCS1 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x1, 0), + MX7ULP_PAD_PTA8__LPUART2_CTS_b = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x1, 0), + MX7ULP_PAD_PTA8__LPI2C2_SCL = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x1, 0), + MX7ULP_PAD_PTA8__TPM1_CLKIN = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x1, 0), + MX7ULP_PAD_PTA8__I2S0_TXD1 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA9__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA9__PTA9 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA9__LPSPI1_PCS2 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x1, 0), + MX7ULP_PAD_PTA9__LPUART2_RTS_b = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA9__LPI2C2_SDA = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x1, 0), + MX7ULP_PAD_PTA9__TPM1_CH0 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x1, 0), + MX7ULP_PAD_PTA9__NMI0_b = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA10__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA10__PTA10 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA10__LPSPI1_PCS3 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x1, 0), + MX7ULP_PAD_PTA10__LPUART2_TX = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x1, 0), + MX7ULP_PAD_PTA10__LPI2C2_HREQ = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x1, 0), + MX7ULP_PAD_PTA10__TPM2_CLKIN = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x1, 0), + MX7ULP_PAD_PTA10__I2S0_RX_BCLK = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x1, 0), + MX7ULP_PAD_PTA11__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA11__PTA11 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA11__LPUART2_RX = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x1, 0), + MX7ULP_PAD_PTA11__TPM2_CH0 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x1, 0), + MX7ULP_PAD_PTA11__I2S0_RX_FS = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x2, 0), + MX7ULP_PAD_PTA12__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA12__PTA12 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA12__LPSPI1_SIN = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x1, 0), + MX7ULP_PAD_PTA12__LPUART3_CTS_b = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x1, 0), + MX7ULP_PAD_PTA12__LPI2C3_SCL = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x1, 0), + MX7ULP_PAD_PTA12__TPM2_CH1 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x1, 0), + MX7ULP_PAD_PTA12__I2S0_RXD0 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x2, 0), + MX7ULP_PAD_PTA13__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA13__PTA13 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA13__LPSPI1_SOUT = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x2, 0), + MX7ULP_PAD_PTA13__LPUART3_RTS_b = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA13__LPI2C3_SDA = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x2, 0), + MX7ULP_PAD_PTA13__TPM3_CLKIN = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x1, 0), + MX7ULP_PAD_PTA13__I2S0_RXD1 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E0, 0x2, 0), + MX7ULP_PAD_PTA13__CMP0_OUT = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA13__LLWU0_P2 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA14__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA14__PTA14 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA14__LPSPI1_SCK = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x2, 0), + MX7ULP_PAD_PTA14__LPUART3_TX = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x2, 0), + MX7ULP_PAD_PTA14__LPI2C3_HREQ = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x2, 0), + MX7ULP_PAD_PTA14__TPM3_CH0 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x1, 0), + MX7ULP_PAD_PTA14__I2S0_MCLK = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x2, 0), + MX7ULP_PAD_PTA14__LLWU0_P3 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA15__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA15__PTA15 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA15__LPSPI1_PCS0 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x1, 0), + MX7ULP_PAD_PTA15__LPUART3_RX = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x1, 0), + MX7ULP_PAD_PTA15__TPM3_CH1 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x1, 0), + MX7ULP_PAD_PTA15__I2S0_TX_BCLK = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C0, 0x2, 0), + MX7ULP_PAD_PTA16__CMP1_IN5_3V = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA16__PTA16 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA16__FXIO0_D0 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA16__LPSPI0_SOUT = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x2, 0), + MX7ULP_PAD_PTA16__LPUART0_CTS_b = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x1, 0), + MX7ULP_PAD_PTA16__LPI2C0_SCL = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x1, 0), + MX7ULP_PAD_PTA16__TPM3_CH2 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x6, 0xD168, 0x1, 0), + MX7ULP_PAD_PTA16__I2S0_TX_FS = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x2, 0), + MX7ULP_PAD_PTA17__CMP1_IN6_3V = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA17__PTA17 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA17__FXIO0_D1 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA17__LPSPI0_SCK = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x2, 0), + MX7ULP_PAD_PTA17__LPUART0_RTS_b = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA17__LPI2C0_SDA = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x2, 0), + MX7ULP_PAD_PTA17__TPM3_CH3 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x6, 0xD16C, 0x1, 0), + MX7ULP_PAD_PTA17__I2S0_TXD0 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA18__CMP1_IN1_3V = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA18__PTA18 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA18__FXIO0_D2 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA18__LPSPI0_PCS0 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x2, 0), + MX7ULP_PAD_PTA18__LPUART0_TX = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x2, 0), + MX7ULP_PAD_PTA18__LPI2C0_HREQ = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x2, 0), + MX7ULP_PAD_PTA18__TPM3_CH4 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x6, 0xD170, 0x1, 0), + MX7ULP_PAD_PTA18__I2S0_TXD1 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA18__LLWU0_P4 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA19__CMP1_IN3_3V = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA19__PTA19 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA19__FXIO0_D3 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA19__LPUART0_RX = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x2, 0), + MX7ULP_PAD_PTA19__TPM3_CH5 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x6, 0xD174, 0x1, 0), + MX7ULP_PAD_PTA19__I2S1_RX_BCLK = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1CC, 0x1, 0), + MX7ULP_PAD_PTA19__LPTMR0_ALT3 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA19__LLWU0_P5 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA20__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA20__PTA20 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA20__FXIO0_D4 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA20__LPSPI0_SIN = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x2, 0), + MX7ULP_PAD_PTA20__LPUART1_CTS_b = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x2, 0), + MX7ULP_PAD_PTA20__LPI2C1_SCL = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x2, 0), + MX7ULP_PAD_PTA20__TPM0_CLKIN = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x1, 0), + MX7ULP_PAD_PTA20__I2S1_RX_FS = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D0, 0x1, 0), + MX7ULP_PAD_PTA21__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA21__PTA21 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA21__FXIO0_D5 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA21__LPSPI0_PCS1 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x1, 0), + MX7ULP_PAD_PTA21__LPUART1_RTS_b = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA21__LPI2C1_SDA = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x2, 0), + MX7ULP_PAD_PTA21__TPM0_CH0 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x2, 0), + MX7ULP_PAD_PTA21__I2S1_RXD0 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E4, 0x1, 0), + MX7ULP_PAD_PTA22__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA22__PTA22 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA22__FXIO0_D6 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA22__LPSPI0_PCS2 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x2, 0), + MX7ULP_PAD_PTA22__LPUART1_TX = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x2, 0), + MX7ULP_PAD_PTA22__LPI2C1_HREQ = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x2, 0), + MX7ULP_PAD_PTA22__TPM0_CH1 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x2, 0), + MX7ULP_PAD_PTA22__I2S1_RXD1 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E8, 0x1, 0), + MX7ULP_PAD_PTA22__LPTMR0_ALT2 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA22__EWM_OUT_b = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA23__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA23__PTA23 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA23__FXIO0_D7 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA23__LPSPI0_PCS3 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x2, 0), + MX7ULP_PAD_PTA23__LPUART1_RX = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x2, 0), + MX7ULP_PAD_PTA23__TPM0_CH2 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x2, 0), + MX7ULP_PAD_PTA23__I2S1_MCLK = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C8, 0x1, 0), + MX7ULP_PAD_PTA23__LLWU0_P6 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA24__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA24__PTA24 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA24__FXIO0_D8 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA24__LPSPI1_PCS1 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x2, 0), + MX7ULP_PAD_PTA24__LPUART2_CTS_b = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x2, 0), + MX7ULP_PAD_PTA24__LPI2C2_SCL = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x2, 0), + MX7ULP_PAD_PTA24__TPM0_CH3 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x2, 0), + MX7ULP_PAD_PTA24__I2S1_TX_BCLK = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D4, 0x1, 0), + MX7ULP_PAD_PTA25__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA25__PTA25 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA25__FXIO0_D9 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA25__LPSPI1_PCS2 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x2, 0), + MX7ULP_PAD_PTA25__LPUART2_RTS_b = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA25__LPI2C2_SDA = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x2, 0), + MX7ULP_PAD_PTA25__TPM0_CH4 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x2, 0), + MX7ULP_PAD_PTA25__I2S1_TX_FS = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x1, 0), + MX7ULP_PAD_PTA26__PTA26 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA26__JTAG_TMS_SWD_DIO = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA26__FXIO0_D10 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA26__LPSPI1_PCS3 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x2, 0), + MX7ULP_PAD_PTA26__LPUART2_TX = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x2, 0), + MX7ULP_PAD_PTA26__LPI2C2_HREQ = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x2, 0), + MX7ULP_PAD_PTA26__TPM0_CH5 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x6, 0xD14C, 0x2, 0), + MX7ULP_PAD_PTA26__I2S1_RXD2 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x7, 0xD1EC, 0x1, 0), + MX7ULP_PAD_PTA27__PTA27 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA27__JTAG_TDO = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA27__FXIO0_D11 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA27__LPUART2_RX = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x2, 0), + MX7ULP_PAD_PTA27__TPM1_CH1 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x2, 0), + MX7ULP_PAD_PTA27__I2S1_RXD3 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1F0, 0x1, 0), + MX7ULP_PAD_PTA28__PTA28 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA28__JTAG_TDI = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA28__FXIO0_D12 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA28__LPSPI1_SIN = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x2, 0), + MX7ULP_PAD_PTA28__LPUART3_CTS_b = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x2, 0), + MX7ULP_PAD_PTA28__LPI2C3_SCL = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x2, 0), + MX7ULP_PAD_PTA28__TPM1_CLKIN = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x2, 0), + MX7ULP_PAD_PTA28__I2S1_TXD2 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA29__PTA29 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA29__JTAG_TCLK_SWD_CLK = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA29__FXIO0_D13 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA29__LPSPI1_SOUT = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x1, 0), + MX7ULP_PAD_PTA29__LPUART3_RTS_b = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA29__LPI2C3_SDA = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x1, 0), + MX7ULP_PAD_PTA29__TPM1_CH0 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x2, 0), + MX7ULP_PAD_PTA29__I2S1_TXD3 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA30__ADC0_CH1A = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA30__PTA30 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA30__FXIO0_D14 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA30__LPSPI1_SCK = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x1, 0), + MX7ULP_PAD_PTA30__LPUART3_TX = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x1, 0), + MX7ULP_PAD_PTA30__LPI2C3_HREQ = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x1, 0), + MX7ULP_PAD_PTA30__TPM2_CLKIN = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x2, 0), + MX7ULP_PAD_PTA30__I2S1_TXD0 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA30__JTAG_TRST_b = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA31__ADC0_CH1B = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA31__PTA31 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA31__FXIO0_D15 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA31__LPSPI1_PCS0 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x2, 0), + MX7ULP_PAD_PTA31__LPUART3_RX = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x2, 0), + MX7ULP_PAD_PTA31__TPM2_CH0 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x2, 0), + MX7ULP_PAD_PTA31__I2S1_TXD1 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA31__LPTMR0_ALT1 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA31__EWM_IN = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xc, 0xD228, 0x1, 0), + MX7ULP_PAD_PTA31__LLWU0_P7 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB0__ADC0_CH0A = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB0__PTB0 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB0__FXIO0_D16 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB0__LPSPI0_SIN = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x3, 0), + MX7ULP_PAD_PTB0__LPUART0_TX = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x3, 0), + MX7ULP_PAD_PTB0__TPM2_CH1 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x2, 0), + MX7ULP_PAD_PTB0__CLKOUT0 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB0__CMP1_OUT = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB0__EWM_OUT_b = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB1__ADC0_CH0B = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB1__PTB1 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB1__FXIO0_D17 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB1__LPSPI0_SOUT = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x3, 0), + MX7ULP_PAD_PTB1__LPUART0_RX = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x3, 0), + MX7ULP_PAD_PTB1__TPM3_CLKIN = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x3, 0), + MX7ULP_PAD_PTB1__I2S1_TX_BCLK = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D4, 0x2, 0), + MX7ULP_PAD_PTB1__RTC_CLKOUT = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB1__EWM_IN = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xc, 0xD228, 0x2, 0), + MX7ULP_PAD_PTB1__LLWU0_P8 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB2__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB2__PTB2 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB2__FXIO0_D18 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB2__LPSPI0_SCK = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x3, 0), + MX7ULP_PAD_PTB2__LPUART1_TX = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x3, 0), + MX7ULP_PAD_PTB2__TPM3_CH0 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x2, 0), + MX7ULP_PAD_PTB2__I2S1_TX_FS = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x2, 0), + MX7ULP_PAD_PTB2__TRACE_CLKOUT = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__PTB3 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__FXIO0_D19 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__LPSPI0_PCS0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x3, 0), + MX7ULP_PAD_PTB3__LPUART1_RX = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x3, 0), + MX7ULP_PAD_PTB3__TPM3_CH1 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x2, 0), + MX7ULP_PAD_PTB3__I2S1_TXD0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__TRACE_D0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__LPTMR1_ALT2 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__LLWU0_P9 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB4__PTB4 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB4__FXIO0_D20 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB4__LPSPI0_PCS1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x3, 0), + MX7ULP_PAD_PTB4__LPUART2_TX = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x3, 0), + MX7ULP_PAD_PTB4__LPI2C0_HREQ = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x3, 0), + MX7ULP_PAD_PTB4__TPM3_CH2 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x6, 0xD168, 0x2, 0), + MX7ULP_PAD_PTB4__I2S1_TXD1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB4__QSPIA_DATA7 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB4__TRACE_D1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB5__PTB5 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB5__FXIO0_D21 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB5__LPSPI0_PCS2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x3, 0), + MX7ULP_PAD_PTB5__LPUART2_RX = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x3, 0), + MX7ULP_PAD_PTB5__LPI2C1_HREQ = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x3, 0), + MX7ULP_PAD_PTB5__TPM3_CH3 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x6, 0xD16C, 0x2, 0), + MX7ULP_PAD_PTB5__I2S1_TXD2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB5__QSPIA_DATA6 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB5__TRACE_D2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__ADC1_CH1A = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__PTB6 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__FXIO0_D22 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__LPSPI0_PCS3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x3, 0), + MX7ULP_PAD_PTB6__LPUART3_TX = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x3, 0), + MX7ULP_PAD_PTB6__LPI2C0_SCL = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x3, 0), + MX7ULP_PAD_PTB6__TPM3_CH4 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x6, 0xD170, 0x2, 0), + MX7ULP_PAD_PTB6__I2S1_TXD3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__QSPIA_DATA5 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__TRACE_D3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__LPTMR1_ALT3 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB6__LLWU0_P10 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB7__ADC1_CH1B = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB7__PTB7 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB7__FXIO0_D23 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB7__LPSPI1_SIN = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x3, 0), + MX7ULP_PAD_PTB7__LPUART3_RX = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x3, 0), + MX7ULP_PAD_PTB7__LPI2C0_SDA = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x3, 0), + MX7ULP_PAD_PTB7__TPM3_CH5 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x6, 0xD174, 0x2, 0), + MX7ULP_PAD_PTB7__I2S1_MCLK = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C8, 0x2, 0), + MX7ULP_PAD_PTB7__QSPIA_SS1_B = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB7__CMP1_OUT = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB7__LLWU0_P11 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB8__ADC0_CH14A_CMP0_IN0 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB8__PTB8 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB8__FXIO0_D24 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB8__LPSPI1_SOUT = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x3, 0), + MX7ULP_PAD_PTB8__LPI2C1_SCL = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x3, 0), + MX7ULP_PAD_PTB8__TPM0_CLKIN = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x3, 0), + MX7ULP_PAD_PTB8__I2S1_RX_BCLK = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x7, 0xD1CC, 0x2, 0), + MX7ULP_PAD_PTB8__QSPIA_SS0_B = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB8__RTC_CLKOUT = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB9__ADC0_CH14B_CMP0_IN2 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB9__PTB9 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB9__FXIO0_D25 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB9__LPSPI1_SCK = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x3, 0), + MX7ULP_PAD_PTB9__LPI2C1_SDA = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x3, 0), + MX7ULP_PAD_PTB9__TPM0_CH0 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x3, 0), + MX7ULP_PAD_PTB9__I2S1_RX_FS = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D0, 0x2, 0), + MX7ULP_PAD_PTB9__QSPIA_DQS = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB9__LLWU0_P12 = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB10__CMP0_IN1 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB10__PTB10 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB10__FXIO0_D26 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB10__LPSPI1_PCS0 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x3, 0), + MX7ULP_PAD_PTB10__LPI2C2_SCL = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x3, 0), + MX7ULP_PAD_PTB10__TPM0_CH1 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x3, 0), + MX7ULP_PAD_PTB10__I2S1_RXD0 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E4, 0x2, 0), + MX7ULP_PAD_PTB10__TRACE_D4 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB11__CMP0_IN3 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB11__PTB11 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB11__FXIO0_D27 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB11__LPSPI1_PCS1 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x3, 0), + MX7ULP_PAD_PTB11__LPI2C2_SDA = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x3, 0), + MX7ULP_PAD_PTB11__TPM1_CLKIN = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x3, 0), + MX7ULP_PAD_PTB11__I2S1_RXD1 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E8, 0x2, 0), + MX7ULP_PAD_PTB11__TRACE_D5 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB12__ADC1_CH13A_CMP1_IN0 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB12__PTB12 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB12__FXIO0_D28 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB12__LPSPI1_PCS2 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x3, 0), + MX7ULP_PAD_PTB12__LPI2C3_SCL = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x3, 0), + MX7ULP_PAD_PTB12__TPM1_CH0 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x3, 0), + MX7ULP_PAD_PTB12__I2S1_RXD2 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x7, 0xD1EC, 0x2, 0), + MX7ULP_PAD_PTB12__TRACE_D6 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB13__ADC1_CH13B_CMP1_IN1 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB13__PTB13 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB13__FXIO0_D29 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB13__LPSPI1_PCS3 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x3, 0), + MX7ULP_PAD_PTB13__LPI2C3_SDA = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x3, 0), + MX7ULP_PAD_PTB13__TPM1_CH1 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x3, 0), + MX7ULP_PAD_PTB13__I2S1_RXD3 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x7, 0xD1F0, 0x2, 0), + MX7ULP_PAD_PTB13__QSPIA_DATA4 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB13__TRACE_D7 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__ADC1_CH2A = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__PTB14 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__FXIO0_D30 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__LPI2C2_HREQ = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x3, 0), + MX7ULP_PAD_PTB14__TPM2_CLKIN = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x3, 0), + MX7ULP_PAD_PTB14__QSPIA_SS1_B = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__QSPIA_SCLK_b = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__LLWU0_P13 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB15__ADC1_CH2B = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB15__PTB15 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB15__FXIO0_D31 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB15__LPI2C3_HREQ = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x3, 0), + MX7ULP_PAD_PTB15__TPM2_CH0 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x3, 0), + MX7ULP_PAD_PTB15__QSPIA_SCLK = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB16__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB16__PTB16 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB16__TPM2_CH1 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x3, 0), + MX7ULP_PAD_PTB16__QSPIA_DATA3 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB16__LLWU0_P14 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB17__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB17__PTB17 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB17__TPM3_CLKIN = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x2, 0), + MX7ULP_PAD_PTB17__QSPIA_DATA2 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB18__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB18__PTB18 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB18__TPM3_CH0 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x3, 0), + MX7ULP_PAD_PTB18__QSPIA_DATA1 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB19__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB19__PTB19 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB19__TPM3_CH1 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x3, 0), + MX7ULP_PAD_PTB19__QSPIA_DATA0 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB19__USB0_ID = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB19__LLWU0_P15 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC0__PTC0 = IOMUX_PAD(0x0000, 0x0000, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC0__LPUART4_CTS_b = IOMUX_PAD(0x0000, 0x0000, 0x4, 0x0244, 0x1, 0), + MX7ULP_PAD_PTC0__LPI2C4_SCL = IOMUX_PAD(0x0000, 0x0000, 0x5, 0x0278, 0x1, 0), + MX7ULP_PAD_PTC0__TPM4_CLKIN = IOMUX_PAD(0x0000, 0x0000, 0x6, 0x0298, 0x1, 0), + MX7ULP_PAD_PTC0__FB_AD0 = IOMUX_PAD(0x0000, 0x0000, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC0__TRACE_D15 = IOMUX_PAD(0x0000, 0x0000, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC0__DEBUG_MUX0 = IOMUX_PAD(0x0000, 0x0000, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC1__PTC1 = IOMUX_PAD(0x0004, 0x0004, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC1__LPUART4_RTS_b = IOMUX_PAD(0x0004, 0x0004, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC1__LPI2C4_SDA = IOMUX_PAD(0x0004, 0x0004, 0x5, 0x027C, 0x1, 0), + MX7ULP_PAD_PTC1__TPM4_CH0 = IOMUX_PAD(0x0004, 0x0004, 0x6, 0x0280, 0x1, 0), + MX7ULP_PAD_PTC1__FB_AD1 = IOMUX_PAD(0x0004, 0x0004, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC1__TRACE_D14 = IOMUX_PAD(0x0004, 0x0004, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC1__DEBUG_MUX1 = IOMUX_PAD(0x0004, 0x0004, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC2__PTC2 = IOMUX_PAD(0x0008, 0x0008, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC2__LPUART4_TX = IOMUX_PAD(0x0008, 0x0008, 0x4, 0x024C, 0x1, 0), + MX7ULP_PAD_PTC2__LPI2C4_HREQ = IOMUX_PAD(0x0008, 0x0008, 0x5, 0x0274, 0x1, 0), + MX7ULP_PAD_PTC2__TPM4_CH1 = IOMUX_PAD(0x0008, 0x0008, 0x6, 0x0284, 0x1, 0), + MX7ULP_PAD_PTC2__FB_AD2 = IOMUX_PAD(0x0008, 0x0008, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC2__TRACE_D13 = IOMUX_PAD(0x0008, 0x0008, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC2__DEBUG_MUX2 = IOMUX_PAD(0x0008, 0x0008, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC3__PTC3 = IOMUX_PAD(0x000C, 0x000C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC3__LPUART4_RX = IOMUX_PAD(0x000C, 0x000C, 0x4, 0x0248, 0x1, 0), + MX7ULP_PAD_PTC3__TPM4_CH2 = IOMUX_PAD(0x000C, 0x000C, 0x6, 0x0288, 0x1, 0), + MX7ULP_PAD_PTC3__FB_AD3 = IOMUX_PAD(0x000C, 0x000C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC3__TRACE_D12 = IOMUX_PAD(0x000C, 0x000C, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC3__DEBUG_MUX3 = IOMUX_PAD(0x000C, 0x000C, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC4__PTC4 = IOMUX_PAD(0x0010, 0x0010, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC4__FXIO1_D0 = IOMUX_PAD(0x0010, 0x0010, 0x2, 0x0204, 0x1, 0), + MX7ULP_PAD_PTC4__LPSPI2_PCS1 = IOMUX_PAD(0x0010, 0x0010, 0x3, 0x02A0, 0x1, 0), + MX7ULP_PAD_PTC4__LPUART5_CTS_b = IOMUX_PAD(0x0010, 0x0010, 0x4, 0x0250, 0x1, 0), + MX7ULP_PAD_PTC4__LPI2C5_SCL = IOMUX_PAD(0x0010, 0x0010, 0x5, 0x02BC, 0x1, 0), + MX7ULP_PAD_PTC4__TPM4_CH3 = IOMUX_PAD(0x0010, 0x0010, 0x6, 0x028C, 0x1, 0), + MX7ULP_PAD_PTC4__FB_AD4 = IOMUX_PAD(0x0010, 0x0010, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC4__TRACE_D11 = IOMUX_PAD(0x0010, 0x0010, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC4__DEBUG_MUX4 = IOMUX_PAD(0x0010, 0x0010, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC5__PTC5 = IOMUX_PAD(0x0014, 0x0014, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC5__FXIO1_D1 = IOMUX_PAD(0x0014, 0x0014, 0x2, 0x0208, 0x1, 0), + MX7ULP_PAD_PTC5__LPSPI2_PCS2 = IOMUX_PAD(0x0014, 0x0014, 0x3, 0x02A4, 0x1, 0), + MX7ULP_PAD_PTC5__LPUART5_RTS_b = IOMUX_PAD(0x0014, 0x0014, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC5__LPI2C5_SDA = IOMUX_PAD(0x0014, 0x0014, 0x5, 0x02C0, 0x1, 0), + MX7ULP_PAD_PTC5__TPM4_CH4 = IOMUX_PAD(0x0014, 0x0014, 0x6, 0x0290, 0x1, 0), + MX7ULP_PAD_PTC5__FB_AD5 = IOMUX_PAD(0x0014, 0x0014, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC5__TRACE_D10 = IOMUX_PAD(0x0014, 0x0014, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC5__DEBUG_MUX5 = IOMUX_PAD(0x0014, 0x0014, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC6__PTC6 = IOMUX_PAD(0x0018, 0x0018, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC6__FXIO1_D2 = IOMUX_PAD(0x0018, 0x0018, 0x2, 0x020C, 0x1, 0), + MX7ULP_PAD_PTC6__LPSPI2_PCS3 = IOMUX_PAD(0x0018, 0x0018, 0x3, 0x02A8, 0x1, 0), + MX7ULP_PAD_PTC6__LPUART5_TX = IOMUX_PAD(0x0018, 0x0018, 0x4, 0x0258, 0x1, 0), + MX7ULP_PAD_PTC6__LPI2C5_HREQ = IOMUX_PAD(0x0018, 0x0018, 0x5, 0x02B8, 0x1, 0), + MX7ULP_PAD_PTC6__TPM4_CH5 = IOMUX_PAD(0x0018, 0x0018, 0x6, 0x0294, 0x1, 0), + MX7ULP_PAD_PTC6__FB_AD6 = IOMUX_PAD(0x0018, 0x0018, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC6__TRACE_D9 = IOMUX_PAD(0x0018, 0x0018, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC6__DEBUG_MUX6 = IOMUX_PAD(0x0018, 0x0018, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC7__PTC7 = IOMUX_PAD(0x001C, 0x001C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC7__FXIO1_D3 = IOMUX_PAD(0x001C, 0x001C, 0x2, 0x0210, 0x1, 0), + MX7ULP_PAD_PTC7__LPUART5_RX = IOMUX_PAD(0x001C, 0x001C, 0x4, 0x0254, 0x1, 0), + MX7ULP_PAD_PTC7__TPM5_CH1 = IOMUX_PAD(0x001C, 0x001C, 0x6, 0x02C8, 0x1, 0), + MX7ULP_PAD_PTC7__FB_AD7 = IOMUX_PAD(0x001C, 0x001C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC7__TRACE_D8 = IOMUX_PAD(0x001C, 0x001C, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC7__DEBUG_MUX7 = IOMUX_PAD(0x001C, 0x001C, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC8__PTC8 = IOMUX_PAD(0x0020, 0x0020, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC8__FXIO1_D4 = IOMUX_PAD(0x0020, 0x0020, 0x2, 0x0214, 0x1, 0), + MX7ULP_PAD_PTC8__LPSPI2_SIN = IOMUX_PAD(0x0020, 0x0020, 0x3, 0x02B0, 0x1, 0), + MX7ULP_PAD_PTC8__LPUART6_CTS_b = IOMUX_PAD(0x0020, 0x0020, 0x4, 0x025C, 0x1, 0), + MX7ULP_PAD_PTC8__LPI2C6_SCL = IOMUX_PAD(0x0020, 0x0020, 0x5, 0x02FC, 0x1, 0), + MX7ULP_PAD_PTC8__TPM5_CLKIN = IOMUX_PAD(0x0020, 0x0020, 0x6, 0x02CC, 0x1, 0), + MX7ULP_PAD_PTC8__FB_AD8 = IOMUX_PAD(0x0020, 0x0020, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC8__TRACE_D7 = IOMUX_PAD(0x0020, 0x0020, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC8__DEBUG_MUX8 = IOMUX_PAD(0x0020, 0x0020, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC9__PTC9 = IOMUX_PAD(0x0024, 0x0024, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC9__FXIO1_D5 = IOMUX_PAD(0x0024, 0x0024, 0x2, 0x0218, 0x1, 0), + MX7ULP_PAD_PTC9__LPSPI2_SOUT = IOMUX_PAD(0x0024, 0x0024, 0x3, 0x02B4, 0x1, 0), + MX7ULP_PAD_PTC9__LPUART6_RTS_b = IOMUX_PAD(0x0024, 0x0024, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC9__LPI2C6_SDA = IOMUX_PAD(0x0024, 0x0024, 0x5, 0x0300, 0x1, 0), + MX7ULP_PAD_PTC9__TPM5_CH0 = IOMUX_PAD(0x0024, 0x0024, 0x6, 0x02C4, 0x1, 0), + MX7ULP_PAD_PTC9__FB_AD9 = IOMUX_PAD(0x0024, 0x0024, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC9__TRACE_D6 = IOMUX_PAD(0x0024, 0x0024, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC9__DEBUG_MUX9 = IOMUX_PAD(0x0024, 0x0024, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC10__PTC10 = IOMUX_PAD(0x0028, 0x0028, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC10__FXIO1_D6 = IOMUX_PAD(0x0028, 0x0028, 0x2, 0x021C, 0x1, 0), + MX7ULP_PAD_PTC10__LPSPI2_SCK = IOMUX_PAD(0x0028, 0x0028, 0x3, 0x02AC, 0x1, 0), + MX7ULP_PAD_PTC10__LPUART6_TX = IOMUX_PAD(0x0028, 0x0028, 0x4, 0x0264, 0x1, 0), + MX7ULP_PAD_PTC10__LPI2C6_HREQ = IOMUX_PAD(0x0028, 0x0028, 0x5, 0x02F8, 0x1, 0), + MX7ULP_PAD_PTC10__TPM7_CH3 = IOMUX_PAD(0x0028, 0x0028, 0x6, 0x02E8, 0x1, 0), + MX7ULP_PAD_PTC10__FB_AD10 = IOMUX_PAD(0x0028, 0x0028, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC10__TRACE_D5 = IOMUX_PAD(0x0028, 0x0028, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC10__DEBUG_MUX10 = IOMUX_PAD(0x0028, 0x0028, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC11__PTC11 = IOMUX_PAD(0x002C, 0x002C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC11__FXIO1_D7 = IOMUX_PAD(0x002C, 0x002C, 0x2, 0x0220, 0x1, 0), + MX7ULP_PAD_PTC11__LPSPI2_PCS0 = IOMUX_PAD(0x002C, 0x002C, 0x3, 0x029C, 0x1, 0), + MX7ULP_PAD_PTC11__LPUART6_RX = IOMUX_PAD(0x002C, 0x002C, 0x4, 0x0260, 0x1, 0), + MX7ULP_PAD_PTC11__TPM7_CH4 = IOMUX_PAD(0x002C, 0x002C, 0x6, 0x02EC, 0x1, 0), + MX7ULP_PAD_PTC11__FB_AD11 = IOMUX_PAD(0x002C, 0x002C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC11__TRACE_D4 = IOMUX_PAD(0x002C, 0x002C, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC11__DEBUG_MUX11 = IOMUX_PAD(0x002C, 0x002C, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC12__PTC12 = IOMUX_PAD(0x0030, 0x0030, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC12__FXIO1_D8 = IOMUX_PAD(0x0030, 0x0030, 0x2, 0x0224, 0x1, 0), + MX7ULP_PAD_PTC12__LPSPI3_PCS1 = IOMUX_PAD(0x0030, 0x0030, 0x3, 0x0314, 0x1, 0), + MX7ULP_PAD_PTC12__LPUART7_CTS_b = IOMUX_PAD(0x0030, 0x0030, 0x4, 0x0268, 0x1, 0), + MX7ULP_PAD_PTC12__LPI2C7_SCL = IOMUX_PAD(0x0030, 0x0030, 0x5, 0x0308, 0x1, 0), + MX7ULP_PAD_PTC12__TPM7_CH5 = IOMUX_PAD(0x0030, 0x0030, 0x6, 0x02F0, 0x1, 0), + MX7ULP_PAD_PTC12__FB_AD12 = IOMUX_PAD(0x0030, 0x0030, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC12__TRACE_D3 = IOMUX_PAD(0x0030, 0x0030, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC12__DEBUG_MUX12 = IOMUX_PAD(0x0030, 0x0030, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC13__PTC13 = IOMUX_PAD(0x0034, 0x0034, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC13__FXIO1_D9 = IOMUX_PAD(0x0034, 0x0034, 0x2, 0x0228, 0x1, 0), + MX7ULP_PAD_PTC13__LPSPI3_PCS2 = IOMUX_PAD(0x0034, 0x0034, 0x3, 0x0318, 0x1, 0), + MX7ULP_PAD_PTC13__LPUART7_RTS_b = IOMUX_PAD(0x0034, 0x0034, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC13__LPI2C7_SDA = IOMUX_PAD(0x0034, 0x0034, 0x5, 0x030C, 0x1, 0), + MX7ULP_PAD_PTC13__TPM7_CLKIN = IOMUX_PAD(0x0034, 0x0034, 0x6, 0x02F4, 0x1, 0), + MX7ULP_PAD_PTC13__FB_AD13 = IOMUX_PAD(0x0034, 0x0034, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC13__TRACE_D2 = IOMUX_PAD(0x0034, 0x0034, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC13__DEBUG_MUX13 = IOMUX_PAD(0x0034, 0x0034, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC14__PTC14 = IOMUX_PAD(0x0038, 0x0038, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC14__FXIO1_D10 = IOMUX_PAD(0x0038, 0x0038, 0x2, 0x022C, 0x1, 0), + MX7ULP_PAD_PTC14__LPSPI3_PCS3 = IOMUX_PAD(0x0038, 0x0038, 0x3, 0x031C, 0x1, 0), + MX7ULP_PAD_PTC14__LPUART7_TX = IOMUX_PAD(0x0038, 0x0038, 0x4, 0x0270, 0x1, 0), + MX7ULP_PAD_PTC14__LPI2C7_HREQ = IOMUX_PAD(0x0038, 0x0038, 0x5, 0x0304, 0x1, 0), + MX7ULP_PAD_PTC14__TPM7_CH0 = IOMUX_PAD(0x0038, 0x0038, 0x6, 0x02DC, 0x1, 0), + MX7ULP_PAD_PTC14__FB_AD14 = IOMUX_PAD(0x0038, 0x0038, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC14__TRACE_D1 = IOMUX_PAD(0x0038, 0x0038, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC14__DEBUG_MUX14 = IOMUX_PAD(0x0038, 0x0038, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC15__PTC15 = IOMUX_PAD(0x003C, 0x003C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC15__FXIO1_D11 = IOMUX_PAD(0x003C, 0x003C, 0x2, 0x0230, 0x1, 0), + MX7ULP_PAD_PTC15__LPUART7_RX = IOMUX_PAD(0x003C, 0x003C, 0x4, 0x026C, 0x1, 0), + MX7ULP_PAD_PTC15__TPM7_CH1 = IOMUX_PAD(0x003C, 0x003C, 0x6, 0x02E0, 0x1, 0), + MX7ULP_PAD_PTC15__FB_AD15 = IOMUX_PAD(0x003C, 0x003C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC15__TRACE_D0 = IOMUX_PAD(0x003C, 0x003C, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC15__DEBUG_MUX15 = IOMUX_PAD(0x003C, 0x003C, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC16__PTC16 = IOMUX_PAD(0x0040, 0x0040, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC16__FXIO1_D12 = IOMUX_PAD(0x0040, 0x0040, 0x2, 0x0234, 0x1, 0), + MX7ULP_PAD_PTC16__LPSPI3_SIN = IOMUX_PAD(0x0040, 0x0040, 0x3, 0x0324, 0x1, 0), + MX7ULP_PAD_PTC16__TPM7_CH2 = IOMUX_PAD(0x0040, 0x0040, 0x6, 0x02E4, 0x1, 0), + MX7ULP_PAD_PTC16__FB_ALE_FB_CS1_b_FB_TS_b = IOMUX_PAD(0x0040, 0x0040, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC16__TRACE_CLKOUT = IOMUX_PAD(0x0040, 0x0040, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC16__USB1_ULPI_OC2 = IOMUX_PAD(0x0040, 0x0040, 0xb, 0x0334, 0x1, 0), + MX7ULP_PAD_PTC17__PTC17 = IOMUX_PAD(0x0044, 0x0044, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC17__FXIO1_D13 = IOMUX_PAD(0x0044, 0x0044, 0x2, 0x0238, 0x1, 0), + MX7ULP_PAD_PTC17__LPSPI3_SOUT = IOMUX_PAD(0x0044, 0x0044, 0x3, 0x0328, 0x1, 0), + MX7ULP_PAD_PTC17__TPM6_CLKIN = IOMUX_PAD(0x0044, 0x0044, 0x6, 0x02D8, 0x1, 0), + MX7ULP_PAD_PTC17__FB_CS0_b = IOMUX_PAD(0x0044, 0x0044, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC17__DEBUG_MUX16 = IOMUX_PAD(0x0044, 0x0044, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC18__PTC18 = IOMUX_PAD(0x0048, 0x0048, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC18__FXIO1_D14 = IOMUX_PAD(0x0048, 0x0048, 0x2, 0x023C, 0x1, 0), + MX7ULP_PAD_PTC18__LPSPI3_SCK = IOMUX_PAD(0x0048, 0x0048, 0x3, 0x0320, 0x1, 0), + MX7ULP_PAD_PTC18__TPM6_CH0 = IOMUX_PAD(0x0048, 0x0048, 0x6, 0x02D0, 0x1, 0), + MX7ULP_PAD_PTC18__FB_OE_b = IOMUX_PAD(0x0048, 0x0048, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC18__DEBUG_MUX17 = IOMUX_PAD(0x0048, 0x0048, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC19__PTC19 = IOMUX_PAD(0x004C, 0x004C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC19__FXIO1_D15 = IOMUX_PAD(0x004C, 0x004C, 0x2, 0x0240, 0x1, 0), + MX7ULP_PAD_PTC19__LPSPI3_PCS0 = IOMUX_PAD(0x004C, 0x004C, 0x3, 0x0310, 0x1, 0), + MX7ULP_PAD_PTC19__TPM6_CH1 = IOMUX_PAD(0x004C, 0x004C, 0x6, 0x02D4, 0x1, 0), + MX7ULP_PAD_PTC19__FB_A16 = IOMUX_PAD(0x004C, 0x004C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC19__USB1_ULPI_PWR2 = IOMUX_PAD(0x004C, 0x004C, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD0__PTD0 = IOMUX_PAD(0x0080, 0x0080, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD0__SDHC0_RESET_b = IOMUX_PAD(0x0080, 0x0080, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD0__DEBUG_MUX18 = IOMUX_PAD(0x0080, 0x0080, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD1__PTD1 = IOMUX_PAD(0x0084, 0x0084, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD1__SDHC0_CMD = IOMUX_PAD(0x0084, 0x0084, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD1__DEBUG_MUX19 = IOMUX_PAD(0x0084, 0x0084, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD2__PTD2 = IOMUX_PAD(0x0088, 0x0088, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD2__SDHC0_CLK = IOMUX_PAD(0x0088, 0x0088, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD2__DEBUG_MUX20 = IOMUX_PAD(0x0088, 0x0088, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD3__PTD3 = IOMUX_PAD(0x008C, 0x008C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD3__SDHC0_D7 = IOMUX_PAD(0x008C, 0x008C, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD3__DEBUG_MUX21 = IOMUX_PAD(0x008C, 0x008C, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD4__PTD4 = IOMUX_PAD(0x0090, 0x0090, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD4__SDHC0_D6 = IOMUX_PAD(0x0090, 0x0090, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD4__DEBUG_MUX22 = IOMUX_PAD(0x0090, 0x0090, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD5__PTD5 = IOMUX_PAD(0x0094, 0x0094, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD5__SDHC0_D5 = IOMUX_PAD(0x0094, 0x0094, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD5__DEBUG_MUX23 = IOMUX_PAD(0x0094, 0x0094, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD6__PTD6 = IOMUX_PAD(0x0098, 0x0098, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD6__SDHC0_D4 = IOMUX_PAD(0x0098, 0x0098, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD6__DEBUG_MUX24 = IOMUX_PAD(0x0098, 0x0098, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD7__PTD7 = IOMUX_PAD(0x009C, 0x009C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD7__SDHC0_D3 = IOMUX_PAD(0x009C, 0x009C, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD7__DEBUG_MUX25 = IOMUX_PAD(0x009C, 0x009C, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD8__PTD8 = IOMUX_PAD(0x00A0, 0x00A0, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD8__TPM4_CLKIN = IOMUX_PAD(0x00A0, 0x00A0, 0x6, 0x0298, 0x2, 0), + MX7ULP_PAD_PTD8__SDHC0_D2 = IOMUX_PAD(0x00A0, 0x00A0, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD8__DEBUG_MUX26 = IOMUX_PAD(0x00A0, 0x00A0, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD9__PTD9 = IOMUX_PAD(0x00A4, 0x00A4, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD9__TPM4_CH0 = IOMUX_PAD(0x00A4, 0x00A4, 0x6, 0x0280, 0x2, 0), + MX7ULP_PAD_PTD9__SDHC0_D1 = IOMUX_PAD(0x00A4, 0x00A4, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD9__DEBUG_MUX27 = IOMUX_PAD(0x00A4, 0x00A4, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD10__PTD10 = IOMUX_PAD(0x00A8, 0x00A8, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD10__TPM4_CH1 = IOMUX_PAD(0x00A8, 0x00A8, 0x6, 0x0284, 0x2, 0), + MX7ULP_PAD_PTD10__SDHC0_D0 = IOMUX_PAD(0x00A8, 0x00A8, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD10__DEBUG_MUX28 = IOMUX_PAD(0x00A8, 0x00A8, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD11__PTD11 = IOMUX_PAD(0x00AC, 0x00AC, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD11__TPM4_CH2 = IOMUX_PAD(0x00AC, 0x00AC, 0x6, 0x0288, 0x2, 0), + MX7ULP_PAD_PTD11__SDHC0_DQS = IOMUX_PAD(0x00AC, 0x00AC, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD11__DEBUG_MUX29 = IOMUX_PAD(0x00AC, 0x00AC, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE0__PTE0 = IOMUX_PAD(0x0100, 0x0100, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE0__FXIO1_D31 = IOMUX_PAD(0x0100, 0x0100, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE0__LPSPI2_PCS1 = IOMUX_PAD(0x0100, 0x0100, 0x3, 0x02A0, 0x2, 0), + MX7ULP_PAD_PTE0__LPUART4_CTS_b = IOMUX_PAD(0x0100, 0x0100, 0x4, 0x0244, 0x2, 0), + MX7ULP_PAD_PTE0__LPI2C4_SCL = IOMUX_PAD(0x0100, 0x0100, 0x5, 0x0278, 0x2, 0), + MX7ULP_PAD_PTE0__SDHC1_D1 = IOMUX_PAD(0x0100, 0x0100, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE0__FB_A25 = IOMUX_PAD(0x0100, 0x0100, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE0__DEBUG_MUX30 = IOMUX_PAD(0x0100, 0x0100, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE1__PTE1 = IOMUX_PAD(0x0104, 0x0104, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE1__FXIO1_D30 = IOMUX_PAD(0x0104, 0x0104, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE1__LPSPI2_PCS2 = IOMUX_PAD(0x0104, 0x0104, 0x3, 0x02A4, 0x2, 0), + MX7ULP_PAD_PTE1__LPUART4_RTS_b = IOMUX_PAD(0x0104, 0x0104, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE1__LPI2C4_SDA = IOMUX_PAD(0x0104, 0x0104, 0x5, 0x027C, 0x2, 0), + MX7ULP_PAD_PTE1__SDHC1_D0 = IOMUX_PAD(0x0104, 0x0104, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE1__FB_A26 = IOMUX_PAD(0x0104, 0x0104, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE1__DEBUG_MUX31 = IOMUX_PAD(0x0104, 0x0104, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE2__PTE2 = IOMUX_PAD(0x0108, 0x0108, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE2__FXIO1_D29 = IOMUX_PAD(0x0108, 0x0108, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE2__LPSPI2_PCS3 = IOMUX_PAD(0x0108, 0x0108, 0x3, 0x02A8, 0x2, 0), + MX7ULP_PAD_PTE2__LPUART4_TX = IOMUX_PAD(0x0108, 0x0108, 0x4, 0x024C, 0x2, 0), + MX7ULP_PAD_PTE2__LPI2C4_HREQ = IOMUX_PAD(0x0108, 0x0108, 0x5, 0x0274, 0x2, 0), + MX7ULP_PAD_PTE2__SDHC1_CLK = IOMUX_PAD(0x0108, 0x0108, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE2__DEBUG_MUX32 = IOMUX_PAD(0x0108, 0x0108, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE3__PTE3 = IOMUX_PAD(0x010C, 0x010C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE3__FXIO1_D28 = IOMUX_PAD(0x010C, 0x010C, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE3__LPUART4_RX = IOMUX_PAD(0x010C, 0x010C, 0x4, 0x0248, 0x2, 0), + MX7ULP_PAD_PTE3__TPM5_CH1 = IOMUX_PAD(0x010C, 0x010C, 0x6, 0x02C8, 0x2, 0), + MX7ULP_PAD_PTE3__SDHC1_CMD = IOMUX_PAD(0x010C, 0x010C, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE3__DEBUG_MUX33 = IOMUX_PAD(0x010C, 0x010C, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE4__PTE4 = IOMUX_PAD(0x0110, 0x0110, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE4__FXIO1_D27 = IOMUX_PAD(0x0110, 0x0110, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE4__LPSPI2_SIN = IOMUX_PAD(0x0110, 0x0110, 0x3, 0x02B0, 0x2, 0), + MX7ULP_PAD_PTE4__LPUART5_CTS_b = IOMUX_PAD(0x0110, 0x0110, 0x4, 0x0250, 0x2, 0), + MX7ULP_PAD_PTE4__LPI2C5_SCL = IOMUX_PAD(0x0110, 0x0110, 0x5, 0x02BC, 0x2, 0), + MX7ULP_PAD_PTE4__TPM5_CLKIN = IOMUX_PAD(0x0110, 0x0110, 0x6, 0x02CC, 0x2, 0), + MX7ULP_PAD_PTE4__SDHC1_D3 = IOMUX_PAD(0x0110, 0x0110, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE5__PTE5 = IOMUX_PAD(0x0114, 0x0114, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE5__FXIO1_D26 = IOMUX_PAD(0x0114, 0x0114, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE5__LPSPI2_SOUT = IOMUX_PAD(0x0114, 0x0114, 0x3, 0x02B4, 0x2, 0), + MX7ULP_PAD_PTE5__LPUART5_RTS_b = IOMUX_PAD(0x0114, 0x0114, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE5__LPI2C5_SDA = IOMUX_PAD(0x0114, 0x0114, 0x5, 0x02C0, 0x2, 0), + MX7ULP_PAD_PTE5__TPM5_CH0 = IOMUX_PAD(0x0114, 0x0114, 0x6, 0x02C4, 0x2, 0), + MX7ULP_PAD_PTE5__SDHC1_D2 = IOMUX_PAD(0x0114, 0x0114, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE6__PTE6 = IOMUX_PAD(0x0118, 0x0118, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE6__FXIO1_D25 = IOMUX_PAD(0x0118, 0x0118, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE6__LPSPI2_SCK = IOMUX_PAD(0x0118, 0x0118, 0x3, 0x02AC, 0x2, 0), + MX7ULP_PAD_PTE6__LPUART5_TX = IOMUX_PAD(0x0118, 0x0118, 0x4, 0x0258, 0x2, 0), + MX7ULP_PAD_PTE6__LPI2C5_HREQ = IOMUX_PAD(0x0118, 0x0118, 0x5, 0x02B8, 0x2, 0), + MX7ULP_PAD_PTE6__TPM7_CH3 = IOMUX_PAD(0x0118, 0x0118, 0x6, 0x02E8, 0x2, 0), + MX7ULP_PAD_PTE6__SDHC1_D4 = IOMUX_PAD(0x0118, 0x0118, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE6__FB_A17 = IOMUX_PAD(0x0118, 0x0118, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE6__USB0_OC = IOMUX_PAD(0x0118, 0x0118, 0xb, 0x0330, 0x1, 0), + MX7ULP_PAD_PTE7__PTE7 = IOMUX_PAD(0x011C, 0x011C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE7__FXIO1_D24 = IOMUX_PAD(0x011C, 0x011C, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE7__LPSPI2_PCS0 = IOMUX_PAD(0x011C, 0x011C, 0x3, 0x029C, 0x2, 0), + MX7ULP_PAD_PTE7__LPUART5_RX = IOMUX_PAD(0x011C, 0x011C, 0x4, 0x0254, 0x2, 0), + MX7ULP_PAD_PTE7__TPM7_CH4 = IOMUX_PAD(0x011C, 0x011C, 0x6, 0x02EC, 0x2, 0), + MX7ULP_PAD_PTE7__SDHC1_D5 = IOMUX_PAD(0x011C, 0x011C, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE7__FB_A18 = IOMUX_PAD(0x011C, 0x011C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE7__TRACE_D7 = IOMUX_PAD(0x011C, 0x011C, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE7__USB0_PWR = IOMUX_PAD(0x011C, 0x011C, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE7__VIU_FID = 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IOMUX_PAD(0x0134, 0x0134, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE13__VIU_D21 = IOMUX_PAD(0x0134, 0x0134, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE14__PTE14 = IOMUX_PAD(0x0138, 0x0138, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE14__FXIO1_D17 = IOMUX_PAD(0x0138, 0x0138, 0x2, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE14__LPSPI3_SCK = IOMUX_PAD(0x0138, 0x0138, 0x3, 0x0320, 0x2, 0), + MX7ULP_PAD_PTE14__LPUART7_TX = IOMUX_PAD(0x0138, 0x0138, 0x4, 0x0270, 0x2, 0), + MX7ULP_PAD_PTE14__LPI2C7_HREQ = IOMUX_PAD(0x0138, 0x0138, 0x5, 0x0304, 0x2, 0), + MX7ULP_PAD_PTE14__TPM6_CH0 = IOMUX_PAD(0x0138, 0x0138, 0x6, 0x02D0, 0x2, 0), + MX7ULP_PAD_PTE14__SDHC1_VS = IOMUX_PAD(0x0138, 0x0138, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE14__FB_A23 = IOMUX_PAD(0x0138, 0x0138, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE14__TRACE_D0 = IOMUX_PAD(0x0138, 0x0138, 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE14__USB0_OC = IOMUX_PAD(0x0138, 0x0138, 0xb, 0x0330, 0x2, 0), + MX7ULP_PAD_PTE14__VIU_D22 = IOMUX_PAD(0x0138, 0x0138, 0xc, 0x0000, 0x0, 0), + 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0x0180, 0x6, 0x0298, 0x3, 0), + MX7ULP_PAD_PTF0__FB_RW_b = IOMUX_PAD(0x0180, 0x0180, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF0__VIU_DE = IOMUX_PAD(0x0180, 0x0180, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF1__PTF1 = IOMUX_PAD(0x0184, 0x0184, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF1__LPUART4_RTS_b = IOMUX_PAD(0x0184, 0x0184, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF1__LPI2C4_SDA = IOMUX_PAD(0x0184, 0x0184, 0x5, 0x027C, 0x3, 0), + MX7ULP_PAD_PTF1__TPM4_CH0 = IOMUX_PAD(0x0184, 0x0184, 0x6, 0x0280, 0x3, 0), + MX7ULP_PAD_PTF1__CLKOUT = IOMUX_PAD(0x0184, 0x0184, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF1__VIU_HSYNC = IOMUX_PAD(0x0184, 0x0184, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF2__PTF2 = IOMUX_PAD(0x0188, 0x0188, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF2__LPUART4_TX = IOMUX_PAD(0x0188, 0x0188, 0x4, 0x024C, 0x3, 0), + MX7ULP_PAD_PTF2__LPI2C4_HREQ = IOMUX_PAD(0x0188, 0x0188, 0x5, 0x0274, 0x3, 0), + MX7ULP_PAD_PTF2__TPM4_CH1 = IOMUX_PAD(0x0188, 0x0188, 0x6, 0x0284, 0x3, 0), + MX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_b_FB_BE23_16_BLS15_8_b = IOMUX_PAD(0x0188, 0x0188, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF2__VIU_VSYNC = IOMUX_PAD(0x0188, 0x0188, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF3__PTF3 = IOMUX_PAD(0x018C, 0x018C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF3__LPUART4_RX = IOMUX_PAD(0x018C, 0x018C, 0x4, 0x0248, 0x3, 0), + MX7ULP_PAD_PTF3__TPM4_CH2 = IOMUX_PAD(0x018C, 0x018C, 0x6, 0x0288, 0x3, 0), + MX7ULP_PAD_PTF3__FB_AD16 = IOMUX_PAD(0x018C, 0x018C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF3__VIU_PCLK = IOMUX_PAD(0x018C, 0x018C, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF4__PTF4 = IOMUX_PAD(0x0190, 0x0190, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF4__FXIO1_D0 = IOMUX_PAD(0x0190, 0x0190, 0x2, 0x0204, 0x2, 0), + MX7ULP_PAD_PTF4__LPSPI2_PCS1 = IOMUX_PAD(0x0190, 0x0190, 0x3, 0x02A0, 0x3, 0), + MX7ULP_PAD_PTF4__LPUART5_CTS_b = IOMUX_PAD(0x0190, 0x0190, 0x4, 0x0250, 0x3, 0), + MX7ULP_PAD_PTF4__LPI2C5_SCL = IOMUX_PAD(0x0190, 0x0190, 0x5, 0x02BC, 0x3, 0), + MX7ULP_PAD_PTF4__TPM4_CH3 = IOMUX_PAD(0x0190, 0x0190, 0x6, 0x028C, 0x2, 0), + MX7ULP_PAD_PTF4__FB_AD17 = IOMUX_PAD(0x0190, 0x0190, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF4__VIU_D0 = IOMUX_PAD(0x0190, 0x0190, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF5__PTF5 = IOMUX_PAD(0x0194, 0x0194, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF5__FXIO1_D1 = IOMUX_PAD(0x0194, 0x0194, 0x2, 0x0208, 0x2, 0), + MX7ULP_PAD_PTF5__LPSPI2_PCS2 = IOMUX_PAD(0x0194, 0x0194, 0x3, 0x02A4, 0x3, 0), + MX7ULP_PAD_PTF5__LPUART5_RTS_b = IOMUX_PAD(0x0194, 0x0194, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF5__LPI2C5_SDA = IOMUX_PAD(0x0194, 0x0194, 0x5, 0x02C0, 0x3, 0), + MX7ULP_PAD_PTF5__TPM4_CH4 = IOMUX_PAD(0x0194, 0x0194, 0x6, 0x0290, 0x2, 0), + MX7ULP_PAD_PTF5__FB_AD18 = IOMUX_PAD(0x0194, 0x0194, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF5__VIU_D1 = IOMUX_PAD(0x0194, 0x0194, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF6__PTF6 = IOMUX_PAD(0x0198, 0x0198, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF6__FXIO1_D2 = IOMUX_PAD(0x0198, 0x0198, 0x2, 0x020C, 0x2, 0), + MX7ULP_PAD_PTF6__LPSPI2_PCS3 = IOMUX_PAD(0x0198, 0x0198, 0x3, 0x02A8, 0x3, 0), + MX7ULP_PAD_PTF6__LPUART5_TX = IOMUX_PAD(0x0198, 0x0198, 0x4, 0x0258, 0x3, 0), + MX7ULP_PAD_PTF6__LPI2C5_HREQ = IOMUX_PAD(0x0198, 0x0198, 0x5, 0x02B8, 0x3, 0), + MX7ULP_PAD_PTF6__TPM4_CH5 = IOMUX_PAD(0x0198, 0x0198, 0x6, 0x0294, 0x2, 0), + MX7ULP_PAD_PTF6__FB_AD19 = IOMUX_PAD(0x0198, 0x0198, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF6__VIU_D2 = IOMUX_PAD(0x0198, 0x0198, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF7__PTF7 = IOMUX_PAD(0x019C, 0x019C, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF7__FXIO1_D3 = IOMUX_PAD(0x019C, 0x019C, 0x2, 0x0210, 0x2, 0), + MX7ULP_PAD_PTF7__LPUART5_RX = IOMUX_PAD(0x019C, 0x019C, 0x4, 0x0254, 0x3, 0), + MX7ULP_PAD_PTF7__TPM5_CH1 = IOMUX_PAD(0x019C, 0x019C, 0x6, 0x02C8, 0x3, 0), + MX7ULP_PAD_PTF7__FB_AD20 = IOMUX_PAD(0x019C, 0x019C, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF7__VIU_D3 = IOMUX_PAD(0x019C, 0x019C, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF8__PTF8 = IOMUX_PAD(0x01A0, 0x01A0, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF8__FXIO1_D4 = IOMUX_PAD(0x01A0, 0x01A0, 0x2, 0x0214, 0x2, 0), + MX7ULP_PAD_PTF8__LPSPI2_SIN = IOMUX_PAD(0x01A0, 0x01A0, 0x3, 0x02B0, 0x3, 0), + MX7ULP_PAD_PTF8__LPUART6_CTS_b = IOMUX_PAD(0x01A0, 0x01A0, 0x4, 0x025C, 0x3, 0), + MX7ULP_PAD_PTF8__LPI2C6_SCL = IOMUX_PAD(0x01A0, 0x01A0, 0x5, 0x02FC, 0x3, 0), + MX7ULP_PAD_PTF8__TPM5_CLKIN = IOMUX_PAD(0x01A0, 0x01A0, 0x6, 0x02CC, 0x3, 0), + MX7ULP_PAD_PTF8__FB_AD21 = IOMUX_PAD(0x01A0, 0x01A0, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF8__USB1_ULPI_CLK = IOMUX_PAD(0x01A0, 0x01A0, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF8__VIU_D4 = IOMUX_PAD(0x01A0, 0x01A0, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF9__PTF9 = IOMUX_PAD(0x01A4, 0x01A4, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF9__FXIO1_D5 = IOMUX_PAD(0x01A4, 0x01A4, 0x2, 0x0218, 0x2, 0), + MX7ULP_PAD_PTF9__LPSPI2_SOUT = IOMUX_PAD(0x01A4, 0x01A4, 0x3, 0x02B4, 0x3, 0), + MX7ULP_PAD_PTF9__LPUART6_RTS_b = IOMUX_PAD(0x01A4, 0x01A4, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF9__LPI2C6_SDA = IOMUX_PAD(0x01A4, 0x01A4, 0x5, 0x0300, 0x3, 0), + MX7ULP_PAD_PTF9__TPM5_CH0 = IOMUX_PAD(0x01A4, 0x01A4, 0x6, 0x02C4, 0x3, 0), + MX7ULP_PAD_PTF9__FB_AD22 = IOMUX_PAD(0x01A4, 0x01A4, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF9__USB1_ULPI_NXT = IOMUX_PAD(0x01A4, 0x01A4, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF9__VIU_D5 = IOMUX_PAD(0x01A4, 0x01A4, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF10__PTF10 = IOMUX_PAD(0x01A8, 0x01A8, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF10__FXIO1_D6 = IOMUX_PAD(0x01A8, 0x01A8, 0x2, 0x021C, 0x2, 0), + MX7ULP_PAD_PTF10__LPSPI2_SCK = IOMUX_PAD(0x01A8, 0x01A8, 0x3, 0x02AC, 0x3, 0), + MX7ULP_PAD_PTF10__LPUART6_TX = IOMUX_PAD(0x01A8, 0x01A8, 0x4, 0x0264, 0x3, 0), + MX7ULP_PAD_PTF10__LPI2C6_HREQ = IOMUX_PAD(0x01A8, 0x01A8, 0x5, 0x02F8, 0x3, 0), + MX7ULP_PAD_PTF10__TPM7_CH3 = IOMUX_PAD(0x01A8, 0x01A8, 0x6, 0x02E8, 0x3, 0), + MX7ULP_PAD_PTF10__FB_AD23 = IOMUX_PAD(0x01A8, 0x01A8, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF10__USB1_ULPI_STP = IOMUX_PAD(0x01A8, 0x01A8, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF10__VIU_D6 = IOMUX_PAD(0x01A8, 0x01A8, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF11__PTF11 = IOMUX_PAD(0x01AC, 0x01AC, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF11__FXIO1_D7 = IOMUX_PAD(0x01AC, 0x01AC, 0x2, 0x0220, 0x2, 0), + MX7ULP_PAD_PTF11__LPSPI2_PCS0 = IOMUX_PAD(0x01AC, 0x01AC, 0x3, 0x029C, 0x3, 0), + MX7ULP_PAD_PTF11__LPUART6_RX = IOMUX_PAD(0x01AC, 0x01AC, 0x4, 0x0260, 0x3, 0), + MX7ULP_PAD_PTF11__TPM7_CH4 = IOMUX_PAD(0x01AC, 0x01AC, 0x6, 0x02EC, 0x3, 0), + MX7ULP_PAD_PTF11__FB_CS4_b_FB_TSIZ0_FB_BE31_24_BLS7_0_b = IOMUX_PAD(0x01AC, 0x01AC, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF11__USB1_ULPI_DIR = IOMUX_PAD(0x01AC, 0x01AC, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF11__VIU_D7 = IOMUX_PAD(0x01AC, 0x01AC, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF12__PTF12 = IOMUX_PAD(0x01B0, 0x01B0, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF12__FXIO1_D8 = IOMUX_PAD(0x01B0, 0x01B0, 0x2, 0x0224, 0x2, 0), + MX7ULP_PAD_PTF12__LPSPI3_PCS1 = IOMUX_PAD(0x01B0, 0x01B0, 0x3, 0x0314, 0x3, 0), + MX7ULP_PAD_PTF12__LPUART7_CTS_b = IOMUX_PAD(0x01B0, 0x01B0, 0x4, 0x0268, 0x3, 0), + MX7ULP_PAD_PTF12__LPI2C7_SCL = IOMUX_PAD(0x01B0, 0x01B0, 0x5, 0x0308, 0x3, 0), + MX7ULP_PAD_PTF12__TPM7_CH5 = IOMUX_PAD(0x01B0, 0x01B0, 0x6, 0x02F0, 0x3, 0), + MX7ULP_PAD_PTF12__FB_AD24 = IOMUX_PAD(0x01B0, 0x01B0, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF12__USB1_ULPI_DATA0 = IOMUX_PAD(0x01B0, 0x01B0, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF12__VIU_D8 = IOMUX_PAD(0x01B0, 0x01B0, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF13__PTF13 = IOMUX_PAD(0x01B4, 0x01B4, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF13__FXIO1_D9 = IOMUX_PAD(0x01B4, 0x01B4, 0x2, 0x0228, 0x2, 0), + MX7ULP_PAD_PTF13__LPSPI3_PCS2 = IOMUX_PAD(0x01B4, 0x01B4, 0x3, 0x0318, 0x3, 0), + MX7ULP_PAD_PTF13__LPUART7_RTS_b = IOMUX_PAD(0x01B4, 0x01B4, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF13__LPI2C7_SDA = IOMUX_PAD(0x01B4, 0x01B4, 0x5, 0x030C, 0x3, 0), + MX7ULP_PAD_PTF13__TPM7_CLKIN = IOMUX_PAD(0x01B4, 0x01B4, 0x6, 0x02F4, 0x3, 0), + MX7ULP_PAD_PTF13__FB_AD25 = IOMUX_PAD(0x01B4, 0x01B4, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF13__USB1_ULPI_DATA1 = IOMUX_PAD(0x01B4, 0x01B4, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF13__VIU_D9 = IOMUX_PAD(0x01B4, 0x01B4, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF14__PTF14 = IOMUX_PAD(0x01B8, 0x01B8, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF14__FXIO1_D10 = IOMUX_PAD(0x01B8, 0x01B8, 0x2, 0x022C, 0x2, 0), + MX7ULP_PAD_PTF14__LPSPI3_PCS3 = IOMUX_PAD(0x01B8, 0x01B8, 0x3, 0x031C, 0x3, 0), + MX7ULP_PAD_PTF14__LPUART7_TX = IOMUX_PAD(0x01B8, 0x01B8, 0x4, 0x0270, 0x3, 0), + MX7ULP_PAD_PTF14__LPI2C7_HREQ = IOMUX_PAD(0x01B8, 0x01B8, 0x5, 0x0304, 0x3, 0), + MX7ULP_PAD_PTF14__TPM7_CH0 = IOMUX_PAD(0x01B8, 0x01B8, 0x6, 0x02DC, 0x3, 0), + MX7ULP_PAD_PTF14__FB_AD26 = IOMUX_PAD(0x01B8, 0x01B8, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF14__USB1_ULPI_DATA2 = IOMUX_PAD(0x01B8, 0x01B8, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF14__VIU_D10 = IOMUX_PAD(0x01B8, 0x01B8, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF15__PTF15 = IOMUX_PAD(0x01BC, 0x01BC, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF15__FXIO1_D11 = IOMUX_PAD(0x01BC, 0x01BC, 0x2, 0x0230, 0x2, 0), + MX7ULP_PAD_PTF15__LPUART7_RX = IOMUX_PAD(0x01BC, 0x01BC, 0x4, 0x026C, 0x3, 0), + MX7ULP_PAD_PTF15__TPM7_CH1 = IOMUX_PAD(0x01BC, 0x01BC, 0x6, 0x02E0, 0x3, 0), + MX7ULP_PAD_PTF15__FB_AD27 = IOMUX_PAD(0x01BC, 0x01BC, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF15__USB1_ULPI_DATA3 = IOMUX_PAD(0x01BC, 0x01BC, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF15__VIU_D11 = IOMUX_PAD(0x01BC, 0x01BC, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF16__PTF16 = IOMUX_PAD(0x01C0, 0x01C0, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF16__USB1_ULPI_DATA4 = IOMUX_PAD(0x01C0, 0x01C0, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF16__VIU_D12 = IOMUX_PAD(0x01C0, 0x01C0, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF16__FXIO1_D12 = IOMUX_PAD(0x01C0, 0x01C0, 0x2, 0x0234, 0x2, 0), + MX7ULP_PAD_PTF16__LPSPI3_SIN = IOMUX_PAD(0x01C0, 0x01C0, 0x3, 0x0324, 0x3, 0), + MX7ULP_PAD_PTF16__TPM7_CH2 = IOMUX_PAD(0x01C0, 0x01C0, 0x6, 0x02E4, 0x3, 0), + MX7ULP_PAD_PTF16__FB_AD28 = IOMUX_PAD(0x01C0, 0x01C0, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF17__PTF17 = IOMUX_PAD(0x01C4, 0x01C4, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF17__USB1_ULPI_DATA5 = IOMUX_PAD(0x01C4, 0x01C4, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF17__VIU_D13 = IOMUX_PAD(0x01C4, 0x01C4, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF17__FXIO1_D13 = IOMUX_PAD(0x01C4, 0x01C4, 0x2, 0x0238, 0x2, 0), + MX7ULP_PAD_PTF17__LPSPI3_SOUT = IOMUX_PAD(0x01C4, 0x01C4, 0x3, 0x0328, 0x3, 0), + MX7ULP_PAD_PTF17__TPM6_CLKIN = IOMUX_PAD(0x01C4, 0x01C4, 0x6, 0x02D8, 0x3, 0), + MX7ULP_PAD_PTF17__FB_AD29 = IOMUX_PAD(0x01C4, 0x01C4, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF18__PTF18 = IOMUX_PAD(0x01C8, 0x01C8, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF18__USB1_ULPI_DATA6 = IOMUX_PAD(0x01C8, 0x01C8, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF18__VIU_D14 = IOMUX_PAD(0x01C8, 0x01C8, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF18__FXIO1_D14 = IOMUX_PAD(0x01C8, 0x01C8, 0x2, 0x023C, 0x2, 0), + MX7ULP_PAD_PTF18__LPSPI3_SCK = IOMUX_PAD(0x01C8, 0x01C8, 0x3, 0x0320, 0x3, 0), + MX7ULP_PAD_PTF18__TPM6_CH0 = IOMUX_PAD(0x01C8, 0x01C8, 0x6, 0x02D0, 0x3, 0), + MX7ULP_PAD_PTF18__FB_AD30 = IOMUX_PAD(0x01C8, 0x01C8, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF19__PTF19 = IOMUX_PAD(0x01CC, 0x01CC, 0x1, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF19__USB1_ULPI_DATA7 = IOMUX_PAD(0x01CC, 0x01CC, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF19__VIU_D15 = IOMUX_PAD(0x01CC, 0x01CC, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF19__FXIO1_D15 = IOMUX_PAD(0x01CC, 0x01CC, 0x2, 0x0240, 0x2, 0), + MX7ULP_PAD_PTF19__LPSPI3_PCS0 = IOMUX_PAD(0x01CC, 0x01CC, 0x3, 0x0310, 0x3, 0), + MX7ULP_PAD_PTF19__TPM6_CH1 = IOMUX_PAD(0x01CC, 0x01CC, 0x6, 0x02D4, 0x3, 0), + MX7ULP_PAD_PTF19__FB_AD31 = IOMUX_PAD(0x01CC, 0x01CC, 0x9, 0x0000, 0x0, 0), +}; +#endif /* __ASM_ARCH_IMX7ULP_PINS_H__ */ -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 11/20] wdog: Add the watchdog driver for MX7ULP. 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (9 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 10/20] mx7ulp: Add iomux pins header file Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2017-02-12 9:25 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 12/20] pinctrl: Add i.MX7ULP pinctrl driver Peng Fan ` (9 subsequent siblings) 20 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot From: Ye Li <ye.li@nxp.com> This driver implements the HW WATCHDOG functions. Which needs to set CONFIG_HW_WATCHDOG to use them. This is disabled by default for mx7ulp. Use watchdog for reset cpu. Implement this in the driver. Need to define CONFIG_ULP_WATCHDOG to build it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: Add License drivers/watchdog/Kconfig | 8 ++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/ulp_wdog.c | 98 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 107 insertions(+) create mode 100644 drivers/watchdog/ulp_wdog.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index e69de29..dbdaafc 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -0,0 +1,8 @@ +menu "WATCHDOG support" + +config ULP_WATCHDOG + bool "i.MX7ULP watchdog" + help + Say Y here to enable i.MX7ULP watchdog driver. + +endmenu diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index a007ae8..dea1836 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o +obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c new file mode 100644 index 0000000..72ec694 --- /dev/null +++ b/drivers/watchdog/ulp_wdog.c @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> + +/* + * MX7ULP WDOG Register Map + */ +struct wdog_regs { + u8 cs1; + u8 cs2; + u16 reserve0; + u32 cnt; + u32 toval; + u32 win; +}; + +#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500 +#endif + +#define REFRESH_WORD0 0xA602 /* 1st refresh word */ +#define REFRESH_WORD1 0xB480 /* 2nd refresh word */ + +#define UNLOCK_WORD0 0xC520 /* 1st unlock word */ +#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */ + +#define WDGCS1_WDGE (1<<7) +#define WDGCS1_WDGUPDATE (1<<5) + +#define WDGCS2_FLG (1<<6) + +#define WDG_BUS_CLK (0x0) +#define WDG_LPO_CLK (0x1) +#define WDG_32KHZ_CLK (0x2) +#define WDG_EXT_CLK (0x3) + +DECLARE_GLOBAL_DATA_PTR; + +void hw_watchdog_set_timeout(u16 val) +{ + /* setting timeout value */ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; + + writel(val, &wdog->toval); +} + +void hw_watchdog_reset(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; + + writel(REFRESH_WORD0, &wdog->cnt); + writel(REFRESH_WORD1, &wdog->cnt); +} + +void hw_watchdog_init(void) +{ + u8 val; + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; + + writel(UNLOCK_WORD0, &wdog->cnt); + writel(UNLOCK_WORD1, &wdog->cnt); + + val = readb(&wdog->cs2); + val |= WDGCS2_FLG; + writeb(val, &wdog->cs2); + + hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS); + writel(0, &wdog->win); + + writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ + writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */ + + hw_watchdog_reset(); +} + +void reset_cpu(ulong addr) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; + + writel(UNLOCK_WORD0, &wdog->cnt); + writel(UNLOCK_WORD1, &wdog->cnt); + + hw_watchdog_set_timeout(5); /* 5ms timeout */ + writel(0, &wdog->win); + + writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ + writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */ + + hw_watchdog_reset(); + + while (1); +} -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 11/20] wdog: Add the watchdog driver for MX7ULP. 2016-12-27 10:04 ` [U-Boot] [PATCH V2 11/20] wdog: Add the watchdog driver for MX7ULP Peng Fan @ 2017-02-12 9:25 ` Stefano Babic 2017-02-22 6:59 ` Peng Fan 0 siblings, 1 reply; 48+ messages in thread From: Stefano Babic @ 2017-02-12 9:25 UTC (permalink / raw) To: u-boot On 27/12/2016 11:04, Peng Fan wrote: > From: Ye Li <ye.li@nxp.com> > > This driver implements the HW WATCHDOG functions. Which needs > to set CONFIG_HW_WATCHDOG to use them. This is disabled by default for > mx7ulp. > > Use watchdog for reset cpu. Implement this in the driver. > Need to define CONFIG_ULP_WATCHDOG to build it. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Signed-off-by: Ye Li <ye.li@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > Add License > > drivers/watchdog/Kconfig | 8 ++++ > drivers/watchdog/Makefile | 1 + > drivers/watchdog/ulp_wdog.c | 98 +++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 107 insertions(+) > create mode 100644 drivers/watchdog/ulp_wdog.c > > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > index e69de29..dbdaafc 100644 > --- a/drivers/watchdog/Kconfig > +++ b/drivers/watchdog/Kconfig > @@ -0,0 +1,8 @@ > +menu "WATCHDOG support" > + > +config ULP_WATCHDOG > + bool "i.MX7ULP watchdog" > + help > + Say Y here to enable i.MX7ULP watchdog driver. > + > +endmenu > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile > index a007ae8..dea1836 100644 > --- a/drivers/watchdog/Makefile > +++ b/drivers/watchdog/Makefile > @@ -15,3 +15,4 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o > obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o > obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o > obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o > +obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o > diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c > new file mode 100644 > index 0000000..72ec694 > --- /dev/null > +++ b/drivers/watchdog/ulp_wdog.c > @@ -0,0 +1,98 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/arch/imx-regs.h> > + > +/* > + * MX7ULP WDOG Register Map > + */ > +struct wdog_regs { > + u8 cs1; > + u8 cs2; > + u16 reserve0; > + u32 cnt; > + u32 toval; > + u32 win; > +}; > + > +#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS > +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500 > +#endif > + > +#define REFRESH_WORD0 0xA602 /* 1st refresh word */ > +#define REFRESH_WORD1 0xB480 /* 2nd refresh word */ > + > +#define UNLOCK_WORD0 0xC520 /* 1st unlock word */ > +#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */ > + > +#define WDGCS1_WDGE (1<<7) > +#define WDGCS1_WDGUPDATE (1<<5) > + > +#define WDGCS2_FLG (1<<6) > + > +#define WDG_BUS_CLK (0x0) > +#define WDG_LPO_CLK (0x1) > +#define WDG_32KHZ_CLK (0x2) > +#define WDG_EXT_CLK (0x3) > + > +DECLARE_GLOBAL_DATA_PTR; > + > +void hw_watchdog_set_timeout(u16 val) > +{ > + /* setting timeout value */ > + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; > + > + writel(val, &wdog->toval); > +} > + > +void hw_watchdog_reset(void) > +{ > + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; > + > + writel(REFRESH_WORD0, &wdog->cnt); > + writel(REFRESH_WORD1, &wdog->cnt); > +} > + > +void hw_watchdog_init(void) > +{ > + u8 val; > + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; > + > + writel(UNLOCK_WORD0, &wdog->cnt); > + writel(UNLOCK_WORD1, &wdog->cnt); > + > + val = readb(&wdog->cs2); > + val |= WDGCS2_FLG; > + writeb(val, &wdog->cs2); > + > + hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS); > + writel(0, &wdog->win); > + > + writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ > + writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */ > + > + hw_watchdog_reset(); > +} > + > +void reset_cpu(ulong addr) > +{ > + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; > + > + writel(UNLOCK_WORD0, &wdog->cnt); > + writel(UNLOCK_WORD1, &wdog->cnt); > + > + hw_watchdog_set_timeout(5); /* 5ms timeout */ > + writel(0, &wdog->win); > + > + writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ > + writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */ > + > + hw_watchdog_reset(); > + > + while (1); > +} > This goes into drivers/watchdog, and it slightly differs from the implementation in imx-watchdog.c. Code is quite simple, too, I think it could be merged into the same file. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 11/20] wdog: Add the watchdog driver for MX7ULP. 2017-02-12 9:25 ` Stefano Babic @ 2017-02-22 6:59 ` Peng Fan 2017-02-22 8:18 ` Stefano Babic 0 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2017-02-22 6:59 UTC (permalink / raw) To: u-boot On Sun, Feb 12, 2017 at 10:25:02AM +0100, Stefano Babic wrote: > > >On 27/12/2016 11:04, Peng Fan wrote: >> From: Ye Li <ye.li@nxp.com> >> >> This driver implements the HW WATCHDOG functions. Which needs >> to set CONFIG_HW_WATCHDOG to use them. This is disabled by default for >> mx7ulp. >> >> Use watchdog for reset cpu. Implement this in the driver. >> Need to define CONFIG_ULP_WATCHDOG to build it. >> >> Signed-off-by: Peng Fan <peng.fan@nxp.com> >> Signed-off-by: Ye Li <ye.li@nxp.com> >> Cc: Stefano Babic <sbabic@denx.de> >> --- >> >> V2: >> Add License >> >> drivers/watchdog/Kconfig | 8 ++++ >> drivers/watchdog/Makefile | 1 + >> drivers/watchdog/ulp_wdog.c | 98 +++++++++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 107 insertions(+) >> create mode 100644 drivers/watchdog/ulp_wdog.c >> >> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig >> index e69de29..dbdaafc 100644 >> --- a/drivers/watchdog/Kconfig >> +++ b/drivers/watchdog/Kconfig >> @@ -0,0 +1,8 @@ >> +menu "WATCHDOG support" >> + >> +config ULP_WATCHDOG >> + bool "i.MX7ULP watchdog" >> + help >> + Say Y here to enable i.MX7ULP watchdog driver. >> + >> +endmenu >> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile >> index a007ae8..dea1836 100644 >> --- a/drivers/watchdog/Makefile >> +++ b/drivers/watchdog/Makefile >> @@ -15,3 +15,4 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o >> obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o >> obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o >> obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o >> +obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o >> diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c >> new file mode 100644 >> index 0000000..72ec694 >> --- /dev/null >> +++ b/drivers/watchdog/ulp_wdog.c >> @@ -0,0 +1,98 @@ >> +/* >> + * Copyright (C) 2016 Freescale Semiconductor, Inc. >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#include <common.h> >> +#include <asm/io.h> >> +#include <asm/arch/imx-regs.h> >> + >> +/* >> + * MX7ULP WDOG Register Map >> + */ >> +struct wdog_regs { >> + u8 cs1; >> + u8 cs2; >> + u16 reserve0; >> + u32 cnt; >> + u32 toval; >> + u32 win; >> +}; >> + >> +#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS >> +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500 >> +#endif >> + >> +#define REFRESH_WORD0 0xA602 /* 1st refresh word */ >> +#define REFRESH_WORD1 0xB480 /* 2nd refresh word */ >> + >> +#define UNLOCK_WORD0 0xC520 /* 1st unlock word */ >> +#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */ >> + >> +#define WDGCS1_WDGE (1<<7) >> +#define WDGCS1_WDGUPDATE (1<<5) >> + >> +#define WDGCS2_FLG (1<<6) >> + >> +#define WDG_BUS_CLK (0x0) >> +#define WDG_LPO_CLK (0x1) >> +#define WDG_32KHZ_CLK (0x2) >> +#define WDG_EXT_CLK (0x3) >> + >> +DECLARE_GLOBAL_DATA_PTR; >> + >> +void hw_watchdog_set_timeout(u16 val) >> +{ >> + /* setting timeout value */ >> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; >> + >> + writel(val, &wdog->toval); >> +} >> + >> +void hw_watchdog_reset(void) >> +{ >> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; >> + >> + writel(REFRESH_WORD0, &wdog->cnt); >> + writel(REFRESH_WORD1, &wdog->cnt); >> +} >> + >> +void hw_watchdog_init(void) >> +{ >> + u8 val; >> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; >> + >> + writel(UNLOCK_WORD0, &wdog->cnt); >> + writel(UNLOCK_WORD1, &wdog->cnt); >> + >> + val = readb(&wdog->cs2); >> + val |= WDGCS2_FLG; >> + writeb(val, &wdog->cs2); >> + >> + hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS); >> + writel(0, &wdog->win); >> + >> + writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ >> + writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */ >> + >> + hw_watchdog_reset(); >> +} >> + >> +void reset_cpu(ulong addr) >> +{ >> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; >> + >> + writel(UNLOCK_WORD0, &wdog->cnt); >> + writel(UNLOCK_WORD1, &wdog->cnt); >> + >> + hw_watchdog_set_timeout(5); /* 5ms timeout */ >> + writel(0, &wdog->win); >> + >> + writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ >> + writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */ >> + >> + hw_watchdog_reset(); >> + >> + while (1); >> +} >> > >This goes into drivers/watchdog, and it slightly differs from the >implementation in imx-watchdog.c. Code is quite simple, too, I think it >could be merged into the same file. I prefer to keep it in different files, the watchdog ip on i.MX7ULP is a different one. > >Best regards, >Stefano Babic > >-- >===================================================================== >DENX Software Engineering GmbH, Managing Director: Wolfgang Denk >HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany >Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de >===================================================================== >_______________________________________________ >U-Boot mailing list >U-Boot at lists.denx.de >http://lists.denx.de/mailman/listinfo/u-boot ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 11/20] wdog: Add the watchdog driver for MX7ULP. 2017-02-22 6:59 ` Peng Fan @ 2017-02-22 8:18 ` Stefano Babic 0 siblings, 0 replies; 48+ messages in thread From: Stefano Babic @ 2017-02-22 8:18 UTC (permalink / raw) To: u-boot On 22/02/2017 07:59, Peng Fan wrote: > On Sun, Feb 12, 2017 at 10:25:02AM +0100, Stefano Babic wrote: >> >> >> On 27/12/2016 11:04, Peng Fan wrote: >>> From: Ye Li <ye.li@nxp.com> >>> >>> This driver implements the HW WATCHDOG functions. Which needs >>> to set CONFIG_HW_WATCHDOG to use them. This is disabled by default for >>> mx7ulp. >>> >>> Use watchdog for reset cpu. Implement this in the driver. >>> Need to define CONFIG_ULP_WATCHDOG to build it. >>> >>> Signed-off-by: Peng Fan <peng.fan@nxp.com> >>> Signed-off-by: Ye Li <ye.li@nxp.com> >>> Cc: Stefano Babic <sbabic@denx.de> >>> --- >>> >>> V2: >>> Add License >>> >>> drivers/watchdog/Kconfig | 8 ++++ >>> drivers/watchdog/Makefile | 1 + >>> drivers/watchdog/ulp_wdog.c | 98 +++++++++++++++++++++++++++++++++++++++++++++ >>> 3 files changed, 107 insertions(+) >>> create mode 100644 drivers/watchdog/ulp_wdog.c >>> >>> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig >>> index e69de29..dbdaafc 100644 >>> --- a/drivers/watchdog/Kconfig >>> +++ b/drivers/watchdog/Kconfig >>> @@ -0,0 +1,8 @@ >>> +menu "WATCHDOG support" >>> + >>> +config ULP_WATCHDOG >>> + bool "i.MX7ULP watchdog" >>> + help >>> + Say Y here to enable i.MX7ULP watchdog driver. >>> + >>> +endmenu >>> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile >>> index a007ae8..dea1836 100644 >>> --- a/drivers/watchdog/Makefile >>> +++ b/drivers/watchdog/Makefile >>> @@ -15,3 +15,4 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o >>> obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o >>> obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o >>> obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o >>> +obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o >>> diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c >>> new file mode 100644 >>> index 0000000..72ec694 >>> --- /dev/null >>> +++ b/drivers/watchdog/ulp_wdog.c >>> @@ -0,0 +1,98 @@ >>> +/* >>> + * Copyright (C) 2016 Freescale Semiconductor, Inc. >>> + * >>> + * SPDX-License-Identifier: GPL-2.0+ >>> + */ >>> + >>> +#include <common.h> >>> +#include <asm/io.h> >>> +#include <asm/arch/imx-regs.h> >>> + >>> +/* >>> + * MX7ULP WDOG Register Map >>> + */ >>> +struct wdog_regs { >>> + u8 cs1; >>> + u8 cs2; >>> + u16 reserve0; >>> + u32 cnt; >>> + u32 toval; >>> + u32 win; >>> +}; >>> + >>> +#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS >>> +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500 >>> +#endif >>> + >>> +#define REFRESH_WORD0 0xA602 /* 1st refresh word */ >>> +#define REFRESH_WORD1 0xB480 /* 2nd refresh word */ >>> + >>> +#define UNLOCK_WORD0 0xC520 /* 1st unlock word */ >>> +#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */ >>> + >>> +#define WDGCS1_WDGE (1<<7) >>> +#define WDGCS1_WDGUPDATE (1<<5) >>> + >>> +#define WDGCS2_FLG (1<<6) >>> + >>> +#define WDG_BUS_CLK (0x0) >>> +#define WDG_LPO_CLK (0x1) >>> +#define WDG_32KHZ_CLK (0x2) >>> +#define WDG_EXT_CLK (0x3) >>> + >>> +DECLARE_GLOBAL_DATA_PTR; >>> + >>> +void hw_watchdog_set_timeout(u16 val) >>> +{ >>> + /* setting timeout value */ >>> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; >>> + >>> + writel(val, &wdog->toval); >>> +} >>> + >>> +void hw_watchdog_reset(void) >>> +{ >>> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; >>> + >>> + writel(REFRESH_WORD0, &wdog->cnt); >>> + writel(REFRESH_WORD1, &wdog->cnt); >>> +} >>> + >>> +void hw_watchdog_init(void) >>> +{ >>> + u8 val; >>> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; >>> + >>> + writel(UNLOCK_WORD0, &wdog->cnt); >>> + writel(UNLOCK_WORD1, &wdog->cnt); >>> + >>> + val = readb(&wdog->cs2); >>> + val |= WDGCS2_FLG; >>> + writeb(val, &wdog->cs2); >>> + >>> + hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS); >>> + writel(0, &wdog->win); >>> + >>> + writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ >>> + writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */ >>> + >>> + hw_watchdog_reset(); >>> +} >>> + >>> +void reset_cpu(ulong addr) >>> +{ >>> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; >>> + >>> + writel(UNLOCK_WORD0, &wdog->cnt); >>> + writel(UNLOCK_WORD1, &wdog->cnt); >>> + >>> + hw_watchdog_set_timeout(5); /* 5ms timeout */ >>> + writel(0, &wdog->win); >>> + >>> + writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ >>> + writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */ >>> + >>> + hw_watchdog_reset(); >>> + >>> + while (1); >>> +} >>> >> >> This goes into drivers/watchdog, and it slightly differs from the >> implementation in imx-watchdog.c. Code is quite simple, too, I think it >> could be merged into the same file. > > I prefer to keep it in different files, the watchdog ip on i.MX7ULP is a different one. Ok, fine, I do not insist. Then let this into a separate file Best regards, Stefano Babic -- Meet DENX at the Embedded World Trade Show 14 Mar - 16 Mar 2017, Nuremberg Trade Fair Centre, Hall 4, Booth 581 -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 12/20] pinctrl: Add i.MX7ULP pinctrl driver 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (10 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 11/20] wdog: Add the watchdog driver for MX7ULP Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2017-01-12 5:07 ` Simon Glass 2017-02-12 9:25 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 13/20] i2c: lpi2c: add lpi2c driver for i.MX7ULP Peng Fan ` (8 subsequent siblings) 20 siblings, 2 replies; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Add i.MX7ULP pinctrl driver. Select CONFIG_PINCTRL_IMX7ULP to use this driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> --- V2: None drivers/pinctrl/nxp/Kconfig | 14 ++++++++++++ drivers/pinctrl/nxp/Makefile | 1 + drivers/pinctrl/nxp/pinctrl-imx.c | 10 +++++---- drivers/pinctrl/nxp/pinctrl-imx.h | 3 +++ drivers/pinctrl/nxp/pinctrl-imx7ulp.c | 41 +++++++++++++++++++++++++++++++++++ 5 files changed, 65 insertions(+), 4 deletions(-) create mode 100644 drivers/pinctrl/nxp/pinctrl-imx7ulp.c diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index 238f77d..b668359 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -42,3 +42,17 @@ config PINCTRL_IMX7 configuration. This driver is different from the linux one, this is a simple implementation, only parses the 'fsl,pins' property and configure related registers. + +config PINCTRL_IMX7ULP + bool "IMX7ULP pinctrl driver" + depends on ARCH_MX7ULP && PINCTRL_FULL + select DEVRES + select PINCTRL_IMX + help + Say Y here to enable the imx7ulp pinctrl driver + + This provides a simple pinctrl driver for i.MX7ULP SoC familiy. + This feature depends on device tree configuration. This driver + is different from the linux one, this is a simple implementation, + only parses the 'fsl,pins' property and configure related + registers. diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile index e0f7325..c763948 100644 --- a/drivers/pinctrl/nxp/Makefile +++ b/drivers/pinctrl/nxp/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o obj-$(CONFIG_PINCTRL_IMX5) += pinctrl-imx5.o obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o +obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index 949d0f3..eaf2091 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -24,6 +24,7 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) u32 *pin_data; int npins, size, pin_size; int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val; + u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0; int i, j = 0; dev_dbg(dev, "%s: %s\n", __func__, config->name); @@ -97,8 +98,8 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) /* Set Mux */ if (info->flags & SHARE_MUX_CONF_REG) { - clrsetbits_le32(info->base + mux_reg, 0x7 << 20, - mux_mode << 20); + clrsetbits_le32(info->base + mux_reg, info->mux_mask, + mux_mode << mux_shift); } else { writel(mux_mode, info->base + mux_reg); } @@ -154,8 +155,8 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) /* Set config */ if (!(config_val & IMX_NO_PAD_CTL)) { if (info->flags & SHARE_MUX_CONF_REG) { - clrsetbits_le32(info->base + conf_reg, 0xffff, - config_val); + clrsetbits_le32(info->base + conf_reg, + info->mux_mask, config_val); } else { writel(config_val, info->base + conf_reg); } @@ -199,6 +200,7 @@ int imx_pinctrl_probe(struct udevice *dev, return -ENOMEM; priv->info = info; + info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0); /* * Refer to linux documentation for details: * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h index 037c491..a26ba85 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.h +++ b/drivers/pinctrl/nxp/pinctrl-imx.h @@ -11,11 +11,13 @@ * @base: the address to the controller in virtual memory * @input_sel_base: the address of the select input in virtual memory. * @flags: flags specific for each soc + * @mux_mask: Used when SHARE_MUX_CONF_REG flag is added */ struct imx_pinctrl_soc_info { void __iomem *base; void __iomem *input_sel_base; unsigned int flags; + unsigned int mux_mask; }; /** @@ -41,6 +43,7 @@ extern const struct pinctrl_ops imx_pinctrl_ops; #define SHARE_MUX_CONF_REG 0x1 #define ZERO_OFFSET_VALID 0x2 +#define CONFIG_IBE_OBE 0x4 #define IOMUXC_CONFIG_SION (0x1 << 4) diff --git a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c new file mode 100644 index 0000000..5f01175 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Peng Fan <peng.fan@nxp.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm/device.h> +#include <dm/pinctrl.h> + +#include "pinctrl-imx.h" + +static struct imx_pinctrl_soc_info imx7ulp_pinctrl_soc_info = { + .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CONFIG_IBE_OBE, +}; + +static int imx7ulp_pinctrl_probe(struct udevice *dev) +{ + struct imx_pinctrl_soc_info *info = + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); + + return imx_pinctrl_probe(dev, info); +} + +static const struct udevice_id imx7ulp_pinctrl_match[] = { + { .compatible = "fsl,imx7ulp-iomuxc-0", .data = (ulong)&imx7ulp_pinctrl_soc_info }, + { .compatible = "fsl,imx7ulp-iomuxc-1", .data = (ulong)&imx7ulp_pinctrl_soc_info }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(imx7ulp_pinctrl) = { + .name = "imx7ulp-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(imx7ulp_pinctrl_match), + .probe = imx7ulp_pinctrl_probe, + .remove = imx_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), + .ops = &imx_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 12/20] pinctrl: Add i.MX7ULP pinctrl driver 2016-12-27 10:04 ` [U-Boot] [PATCH V2 12/20] pinctrl: Add i.MX7ULP pinctrl driver Peng Fan @ 2017-01-12 5:07 ` Simon Glass 2017-02-12 9:25 ` Stefano Babic 1 sibling, 0 replies; 48+ messages in thread From: Simon Glass @ 2017-01-12 5:07 UTC (permalink / raw) To: u-boot On 27 December 2016 at 03:04, Peng Fan <peng.fan@nxp.com> wrote: > Add i.MX7ULP pinctrl driver. > Select CONFIG_PINCTRL_IMX7ULP to use this driver. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Simon Glass <sjg@chromium.org> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > None > > drivers/pinctrl/nxp/Kconfig | 14 ++++++++++++ > drivers/pinctrl/nxp/Makefile | 1 + > drivers/pinctrl/nxp/pinctrl-imx.c | 10 +++++---- > drivers/pinctrl/nxp/pinctrl-imx.h | 3 +++ > drivers/pinctrl/nxp/pinctrl-imx7ulp.c | 41 +++++++++++++++++++++++++++++++++++ > 5 files changed, 65 insertions(+), 4 deletions(-) > create mode 100644 drivers/pinctrl/nxp/pinctrl-imx7ulp.c Reviewed-by: Simon Glass <sjg@chromium.org> ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 12/20] pinctrl: Add i.MX7ULP pinctrl driver 2016-12-27 10:04 ` [U-Boot] [PATCH V2 12/20] pinctrl: Add i.MX7ULP pinctrl driver Peng Fan 2017-01-12 5:07 ` Simon Glass @ 2017-02-12 9:25 ` Stefano Babic 1 sibling, 0 replies; 48+ messages in thread From: Stefano Babic @ 2017-02-12 9:25 UTC (permalink / raw) To: u-boot On 27/12/2016 11:04, Peng Fan wrote: > Add i.MX7ULP pinctrl driver. > Select CONFIG_PINCTRL_IMX7ULP to use this driver. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Simon Glass <sjg@chromium.org> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > None > > drivers/pinctrl/nxp/Kconfig | 14 ++++++++++++ > drivers/pinctrl/nxp/Makefile | 1 + > drivers/pinctrl/nxp/pinctrl-imx.c | 10 +++++---- > drivers/pinctrl/nxp/pinctrl-imx.h | 3 +++ > drivers/pinctrl/nxp/pinctrl-imx7ulp.c | 41 +++++++++++++++++++++++++++++++++++ > 5 files changed, 65 insertions(+), 4 deletions(-) > create mode 100644 drivers/pinctrl/nxp/pinctrl-imx7ulp.c > > diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig > index 238f77d..b668359 100644 > --- a/drivers/pinctrl/nxp/Kconfig > +++ b/drivers/pinctrl/nxp/Kconfig > @@ -42,3 +42,17 @@ config PINCTRL_IMX7 > configuration. This driver is different from the linux one, > this is a simple implementation, only parses the 'fsl,pins' > property and configure related registers. > + > +config PINCTRL_IMX7ULP > + bool "IMX7ULP pinctrl driver" > + depends on ARCH_MX7ULP && PINCTRL_FULL > + select DEVRES > + select PINCTRL_IMX > + help > + Say Y here to enable the imx7ulp pinctrl driver > + > + This provides a simple pinctrl driver for i.MX7ULP SoC familiy. > + This feature depends on device tree configuration. This driver > + is different from the linux one, this is a simple implementation, > + only parses the 'fsl,pins' property and configure related > + registers. > diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile > index e0f7325..c763948 100644 > --- a/drivers/pinctrl/nxp/Makefile > +++ b/drivers/pinctrl/nxp/Makefile > @@ -2,3 +2,4 @@ obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o > obj-$(CONFIG_PINCTRL_IMX5) += pinctrl-imx5.o > obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o > obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o > +obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o > diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c > index 949d0f3..eaf2091 100644 > --- a/drivers/pinctrl/nxp/pinctrl-imx.c > +++ b/drivers/pinctrl/nxp/pinctrl-imx.c > @@ -24,6 +24,7 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) > u32 *pin_data; > int npins, size, pin_size; > int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val; > + u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0; > int i, j = 0; > > dev_dbg(dev, "%s: %s\n", __func__, config->name); > @@ -97,8 +98,8 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) > > /* Set Mux */ > if (info->flags & SHARE_MUX_CONF_REG) { > - clrsetbits_le32(info->base + mux_reg, 0x7 << 20, > - mux_mode << 20); > + clrsetbits_le32(info->base + mux_reg, info->mux_mask, > + mux_mode << mux_shift); > } else { > writel(mux_mode, info->base + mux_reg); > } > @@ -154,8 +155,8 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) > /* Set config */ > if (!(config_val & IMX_NO_PAD_CTL)) { > if (info->flags & SHARE_MUX_CONF_REG) { > - clrsetbits_le32(info->base + conf_reg, 0xffff, > - config_val); > + clrsetbits_le32(info->base + conf_reg, > + info->mux_mask, config_val); > } else { > writel(config_val, info->base + conf_reg); > } > @@ -199,6 +200,7 @@ int imx_pinctrl_probe(struct udevice *dev, > return -ENOMEM; > priv->info = info; > > + info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0); > /* > * Refer to linux documentation for details: > * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt > diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h > index 037c491..a26ba85 100644 > --- a/drivers/pinctrl/nxp/pinctrl-imx.h > +++ b/drivers/pinctrl/nxp/pinctrl-imx.h > @@ -11,11 +11,13 @@ > * @base: the address to the controller in virtual memory > * @input_sel_base: the address of the select input in virtual memory. > * @flags: flags specific for each soc > + * @mux_mask: Used when SHARE_MUX_CONF_REG flag is added > */ > struct imx_pinctrl_soc_info { > void __iomem *base; > void __iomem *input_sel_base; > unsigned int flags; > + unsigned int mux_mask; > }; > > /** > @@ -41,6 +43,7 @@ extern const struct pinctrl_ops imx_pinctrl_ops; > > #define SHARE_MUX_CONF_REG 0x1 > #define ZERO_OFFSET_VALID 0x2 > +#define CONFIG_IBE_OBE 0x4 > > #define IOMUXC_CONFIG_SION (0x1 << 4) > > diff --git a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c > new file mode 100644 > index 0000000..5f01175 > --- /dev/null > +++ b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c > @@ -0,0 +1,41 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * Peng Fan <peng.fan@nxp.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <dm/device.h> > +#include <dm/pinctrl.h> > + > +#include "pinctrl-imx.h" > + > +static struct imx_pinctrl_soc_info imx7ulp_pinctrl_soc_info = { > + .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CONFIG_IBE_OBE, > +}; > + > +static int imx7ulp_pinctrl_probe(struct udevice *dev) > +{ > + struct imx_pinctrl_soc_info *info = > + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); > + > + return imx_pinctrl_probe(dev, info); > +} > + > +static const struct udevice_id imx7ulp_pinctrl_match[] = { > + { .compatible = "fsl,imx7ulp-iomuxc-0", .data = (ulong)&imx7ulp_pinctrl_soc_info }, > + { .compatible = "fsl,imx7ulp-iomuxc-1", .data = (ulong)&imx7ulp_pinctrl_soc_info }, > + { /* sentinel */ } > +}; > + > +U_BOOT_DRIVER(imx7ulp_pinctrl) = { > + .name = "imx7ulp-pinctrl", > + .id = UCLASS_PINCTRL, > + .of_match = of_match_ptr(imx7ulp_pinctrl_match), > + .probe = imx7ulp_pinctrl_probe, > + .remove = imx_pinctrl_remove, > + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), > + .ops = &imx_pinctrl_ops, > + .flags = DM_FLAG_PRE_RELOC, > +}; > Reviewed-by : Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 13/20] i2c: lpi2c: add lpi2c driver for i.MX7ULP 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (11 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 12/20] pinctrl: Add i.MX7ULP pinctrl driver Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2016-12-27 10:04 ` [U-Boot] [PATCH V2 14/20] serial: lpuart: restructure lpuart driver Peng Fan ` (7 subsequent siblings) 20 siblings, 0 replies; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Add lpi2c driver for i.MX7ULP. Need to enable the two options to use this driver: CONFIG_DM_I2C=y CONFIG_SYS_LPI2C_IMX=y Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> --- V2: None arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h | 520 +++++++++++++++++++++++++++ drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/imx_lpi2c.c | 462 ++++++++++++++++++++++++ 4 files changed, 989 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h create mode 100644 drivers/i2c/imx_lpi2c.c diff --git a/arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h b/arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h new file mode 100644 index 0000000..f1b3113 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h @@ -0,0 +1,520 @@ +/* + * Copyright 2016 Freescale Semiconductors, Inc. + * + * I2CLP driver for i.MX + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#ifndef __IMX_LPI2C_H__ +#define __IMX_LPI2C_H__ + +struct imx_lpi2c_bus { + int index; + ulong base; + ulong driver_data; + int speed; + struct i2c_pads_info *pads_info; + struct udevice *bus; +}; + +struct imx_lpi2c_reg { + u32 verid; + u32 param; + u8 reserved_0[8]; + u32 mcr; + u32 msr; + u32 mier; + u32 mder; + u32 mcfgr0; + u32 mcfgr1; + u32 mcfgr2; + u32 mcfgr3; + u8 reserved_1[16]; + u32 mdmr; + u8 reserved_2[4]; + u32 mccr0; + u8 reserved_3[4]; + u32 mccr1; + u8 reserved_4[4]; + u32 mfcr; + u32 mfsr; + u32 mtdr; + u8 reserved_5[12]; + u32 mrdr; + u8 reserved_6[156]; + u32 scr; + u32 ssr; + u32 sier; + u32 sder; + u8 reserved_7[4]; + u32 scfgr1; + u32 scfgr2; + u8 reserved_8[20]; + u32 samr; + u8 reserved_9[12]; + u32 sasr; + u32 star; + u8 reserved_10[8]; + u32 stdr; + u8 reserved_11[12]; + u32 srdr; +}; + +typedef enum lpi2c_status { + LPI2C_SUCESS = 0, + LPI2C_END_PACKET_ERR, + LPI2C_STOP_ERR, + LPI2C_NAK_ERR, + LPI2C_ARB_LOST_ERR, + LPI2C_FIFO_ERR, + LPI2C_PIN_LOW_TIMEOUT_ERR, + LPI2C_DATA_MATCH_ERR, + LPI2C_BUSY, + LPI2C_IDLE, + LPI2C_BIT_ERR, + LPI2C_NO_TRANS_PROG, + LPI2C_DMA_REQ_FAIL, +} lpi2c_status_t; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) + +/*! @name PARAM - Parameter Register */ +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) + +/*! @name MCR - Master Control Register */ +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) + +/*! @name MSR - Master Status Register */ +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) + +/*! @name MIER - Master Interrupt Enable Register */ +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) + +/*! @name MDER - Master DMA Enable Register */ +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) + +/*! @name MCFGR0 - Master Configuration Register 0 */ +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) + +/*! @name MCFGR1 - Master Configuration Register 1 */ +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) + +/*! @name MCFGR2 - Master Configuration Register 2 */ +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) + +/*! @name MCFGR3 - Master Configuration Register 3 */ +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) + +/*! @name MDMR - Master Data Match Register */ +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) + +/*! @name MCCR0 - Master Clock Configuration Register 0 */ +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) + +/*! @name MCCR1 - Master Clock Configuration Register 1 */ +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) + +/*! @name MFCR - Master FIFO Control Register */ +#define LPI2C_MFCR_TXWATER_MASK (0xFFU) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) +#define LPI2C_MFCR_RXWATER_MASK (0xFF0000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) + +/*! @name MFSR - Master FIFO Status Register */ +#define LPI2C_MFSR_TXCOUNT_MASK (0xFFU) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) +#define LPI2C_MFSR_RXCOUNT_MASK (0xFF0000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) + +/*! @name MTDR - Master Transmit Data Register */ +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) + +/*! @name MRDR - Master Receive Data Register */ +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) + +/*! @name SCR - Slave Control Register */ +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) + +/*! @name SSR - Slave Status Register */ +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) + +/*! @name SIER - Slave Interrupt Enable Register */ +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) +#define LPI2C_SIER_AM1F_MASK (0x2000U) +#define LPI2C_SIER_AM1F_SHIFT (13U) +#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) + +/*! @name SDER - Slave DMA Enable Register */ +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) + +/*! @name SCFGR1 - Slave Configuration Register 1 */ +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) + +/*! @name SCFGR2 - Slave Configuration Register 2 */ +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) + +/*! @name SAMR - Slave Address Match Register */ +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) + +/*! @name SASR - Slave Address Status Register */ +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) + +/*! @name STAR - Slave Transmit ACK Register */ +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) + +/*! @name STDR - Slave Transmit Data Register */ +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) + +/*! @name SRDR - Slave Receive Data Register */ +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) + +#endif /* __ASM_ARCH_IMX_I2C_H__ */ diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 051f911..027a83a 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -109,6 +109,12 @@ config SYS_I2C_INTEL the I2C API meaning that any I2C operations will immediately fail for now. +config SYS_LPI2C_IMX + bool "NXP i.MX LPI2C driver" + depends on ARCH_MX7ULP + help + Add support for the NXP i.MX LPI2C driver. + config SYS_I2C_MXC bool "NXP i.MX I2C driver" depends on MX6 diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 7c86198..2cbe3bc 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o +obj-$(CONFIG_SYS_LPI2C_IMX) += imx_lpi2c.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c new file mode 100644 index 0000000..f792d44 --- /dev/null +++ b/drivers/i2c/imx_lpi2c.c @@ -0,0 +1,462 @@ +/* + * Copyright 2016 Freescale Semiconductors, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/imx_lpi2c.h> +#include <asm/arch/sys_proto.h> +#include <dm.h> +#include <fdtdec.h> +#include <i2c.h> + +DECLARE_GLOBAL_DATA_PTR; +#define LPI2C_FIFO_SIZE 4 +#define LPI2C_TIMEOUT_MS 100 + +/* Weak linked function for overridden by some SoC power function */ +int __weak init_i2c_power(unsigned i2c_num) +{ + return 0; +} + +static int imx_lpci2c_check_busy_bus(struct udevice *bus) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + lpi2c_status_t result = LPI2C_SUCESS; + u32 status; + + status = readl(®s->msr); + + if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK)) + result = LPI2C_BUSY; + + return result; +} + +static int imx_lpci2c_check_clear_error(struct udevice *bus) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + lpi2c_status_t result = LPI2C_SUCESS; + u32 val, status; + + status = readl(®s->msr); + /* errors to check for */ + status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK | + LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK; + + if (status) { + if (status & LPI2C_MSR_PLTF_MASK) + result = LPI2C_PIN_LOW_TIMEOUT_ERR; + else if (status & LPI2C_MSR_ALF_MASK) + result = LPI2C_ARB_LOST_ERR; + else if (status & LPI2C_MSR_NDF_MASK) + result = LPI2C_NAK_ERR; + else if (status & LPI2C_MSR_FEF_MASK) + result = LPI2C_FIFO_ERR; + + /* clear status flags */ + writel(0x7f00, ®s->msr); + /* reset fifos */ + val = readl(®s->mcr); + val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + writel(val, ®s->mcr); + } + + return result; +} + +static int bus_i2c_wait_for_tx_ready(struct udevice *bus) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + lpi2c_status_t result = LPI2C_SUCESS; + u32 txcount = 0; + ulong start_time = get_timer(0); + + do { + txcount = LPI2C_MFSR_TXCOUNT(readl(®s->mfsr)); + txcount = LPI2C_FIFO_SIZE - txcount; + result = imx_lpci2c_check_clear_error(bus); + if (result) { + debug("i2c: wait for tx ready: result 0x%x\n", result); + return result; + } + if (get_timer(start_time) > LPI2C_TIMEOUT_MS) { + debug("i2c: wait for tx ready: timeout\n"); + return -1; + } + } while (!txcount); + + return result; +} + +static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + lpi2c_status_t result = LPI2C_SUCESS; + + /* empty tx */ + if (!len) + return result; + + while (len--) { + result = bus_i2c_wait_for_tx_ready(bus); + if (result) { + debug("i2c: send wait fot tx ready: %d\n", result); + return result; + } + writel(*txbuf++, ®s->mtdr); + } + + return result; +} + +static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + lpi2c_status_t result = LPI2C_SUCESS; + u32 val; + ulong start_time = get_timer(0); + + /* empty read */ + if (!len) + return result; + + result = bus_i2c_wait_for_tx_ready(bus); + if (result) { + debug("i2c: receive wait fot tx ready: %d\n", result); + return result; + } + + /* clear all status flags */ + writel(0x7f00, ®s->msr); + /* send receive command */ + val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1); + writel(val, ®s->mtdr); + + while (len--) { + do { + result = imx_lpci2c_check_clear_error(bus); + if (result) { + debug("i2c: receive check clear error: %d\n", result); + return result; + } + if (get_timer(start_time) > LPI2C_TIMEOUT_MS) { + debug("i2c: receive mrdr: timeout\n"); + return -1; + } + val = readl(®s->mrdr); + } while (val & LPI2C_MRDR_RXEMPTY_MASK); + *rxbuf++ = LPI2C_MRDR_DATA(val); + } + + return result; +} + +static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + lpi2c_status_t result = LPI2C_SUCESS; + u32 val; + + result = imx_lpci2c_check_busy_bus(bus); + if (result) { + debug("i2c: start check busy bus: 0x%x\n", result); + return result; + } + /* clear all status flags */ + writel(0x7f00, ®s->msr); + /* turn off auto-stop condition */ + val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK; + writel(val, ®s->mcfgr1); + /* wait tx fifo ready */ + result = bus_i2c_wait_for_tx_ready(bus); + if (result) { + debug("i2c: start wait for tx ready: 0x%x\n", result); + return result; + } + /* issue start command */ + val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir; + writel(val, ®s->mtdr); + + return result; +} +static int bus_i2c_stop(struct udevice *bus) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + lpi2c_status_t result = LPI2C_SUCESS; + u32 status; + + result = bus_i2c_wait_for_tx_ready(bus); + if (result) { + debug("i2c: stop wait for tx ready: 0x%x\n", result); + return result; + } + + /* send stop command */ + writel(LPI2C_MTDR_CMD(0x2), ®s->mtdr); + + while (result == LPI2C_SUCESS) { + status = readl(®s->msr); + result = imx_lpci2c_check_clear_error(bus); + /* stop detect flag */ + if (status & LPI2C_MSR_SDF_MASK) { + /* clear stop flag */ + status &= LPI2C_MSR_SDF_MASK; + writel(status, ®s->msr); + break; + } + } + + return result; +} + +static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len) +{ + lpi2c_status_t result = LPI2C_SUCESS; + + result = bus_i2c_start(bus, chip, 1); + if (result) + return result; + result = bus_i2c_receive(bus, buf, len); + if (result) + return result; + result = bus_i2c_stop(bus); + if (result) + return result; + + return result; +} + +static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len) +{ + lpi2c_status_t result = LPI2C_SUCESS; + + result = bus_i2c_start(bus, chip, 0); + if (result) + return result; + result = bus_i2c_send(bus, buf, len); + if (result) + return result; + result = bus_i2c_stop(bus); + if (result) + return result; + + return result; +} + + +static int bus_i2c_set_bus_speed(struct udevice *bus, int speed) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + u32 val; + u32 preescale = 0, best_pre = 0, clkhi = 0; + u32 best_clkhi = 0, abs_error = 0, rate; + u32 error = 0xffffffff; + u32 clock_rate; + bool mode; + int i; + + clock_rate = imx_get_i2cclk(bus->seq + 4); + if (!clock_rate) + return -EPERM; + + mode = (readl(®s->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT; + /* disable master mode */ + val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK; + writel(val | LPI2C_MCR_MEN(0), ®s->mcr); + + for (preescale = 1; (preescale <= 128) && + (error != 0); preescale = 2 * preescale) { + for (clkhi = 1; clkhi < 32; clkhi++) { + if (clkhi == 1) + rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale); + else + rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale)); + + abs_error = speed > rate ? speed - rate : rate - speed; + + if (abs_error < error) { + best_pre = preescale; + best_clkhi = clkhi; + error = abs_error; + if (abs_error == 0) + break; + } + } + } + + /* Standard, fast, fast mode plus and ultra-fast transfers. */ + val = LPI2C_MCCR0_CLKHI(best_clkhi); + if (best_clkhi < 2) + val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1); + else + val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) | + LPI2C_MCCR0_DATAVD(best_clkhi / 2); + writel(val, ®s->mccr0); + + for (i = 0; i < 8; i++) { + if (best_pre == (1 << i)) { + best_pre = i; + break; + } + } + + val = readl(®s->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK; + writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), ®s->mcfgr1); + + if (mode) { + val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK; + writel(val | LPI2C_MCR_MEN(1), ®s->mcr); + } + + return 0; +} + +static int bus_i2c_init(struct udevice *bus, int speed) +{ + struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)dev_get_addr(bus); + u32 val; + int ret; + + /* reset peripheral */ + writel(LPI2C_MCR_RST_MASK, ®s->mcr); + writel(0x0, ®s->mcr); + /* Disable Dozen mode */ + writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), ®s->mcr); + /* host request disable, active high, external pin */ + val = readl(®s->mcfgr0); + val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK | + LPI2C_MCFGR0_HRSEL_MASK)); + val |= LPI2C_MCFGR0_HRPOL(0x1); + writel(val, ®s->mcfgr0); + /* pincfg and ignore ack */ + val = readl(®s->mcfgr1); + val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK); + val |= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */ + val |= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */ + writel(val, ®s->mcfgr1); + + ret = bus_i2c_set_bus_speed(bus, speed); + + /* enable lpi2c in master mode */ + val = readl(®s->mcr) & ~LPI2C_MCR_MEN_MASK; + writel(val | LPI2C_MCR_MEN(1), ®s->mcr); + + debug("i2c : controller bus %d, speed %d:\n", bus->seq, speed); + + return ret; +} + +static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip, + u32 chip_flags) +{ + lpi2c_status_t result = LPI2C_SUCESS; + + result = bus_i2c_start(bus, chip, 0); + if (result) { + bus_i2c_stop(bus); + bus_i2c_init(bus, 100000); + return result; + } + + result = bus_i2c_stop(bus); + if (result) { + bus_i2c_init(bus, 100000); + return -result; + } + + return result; +} + +static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + int ret = 0; + + for (; nmsgs > 0; nmsgs--, msg++) { + debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); + if (msg->flags & I2C_M_RD) + ret = bus_i2c_read(bus, msg->addr, msg->buf, + msg->len); + else { + ret = bus_i2c_write(bus, msg->addr, msg->buf, + msg->len); + if (ret) + break; + } + } + + if (ret) + debug("i2c_write: error sending\n"); + + return ret; +} + +static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + return bus_i2c_set_bus_speed(bus, speed); +} + +static int imx_lpi2c_probe(struct udevice *bus) +{ + struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus); + fdt_addr_t addr; + int ret; + + i2c_bus->driver_data = dev_get_driver_data(bus); + + addr = dev_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -ENODEV; + + i2c_bus->base = addr; + i2c_bus->index = bus->seq; + i2c_bus->bus = bus; + + /* power up i2c resource */ + ret = init_i2c_power(bus->seq + 4); + if (ret) { + debug("init_i2c_power err = %d\n", ret); + return ret; + } + + /* Enable clk, only i2c4-7 can be handled by A7 core */ + ret = enable_i2c_clk(1, bus->seq + 4); + if (ret < 0) + return ret; + + ret = bus_i2c_init(bus, 100000); + if (ret < 0) + return ret; + + debug("i2c : controller bus %d@%lu , speed %d: ", + bus->seq, i2c_bus->base, + i2c_bus->speed); + + return 0; +} + +static const struct dm_i2c_ops imx_lpi2c_ops = { + .xfer = imx_lpi2c_xfer, + .probe_chip = imx_lpi2c_probe_chip, + .set_bus_speed = imx_lpi2c_set_bus_speed, +}; + +static const struct udevice_id imx_lpi2c_ids[] = { + { .compatible = "fsl,imx7ulp-lpi2c", }, + {} +}; + +U_BOOT_DRIVER(imx_lpi2c) = { + .name = "imx_lpi2c", + .id = UCLASS_I2C, + .of_match = imx_lpi2c_ids, + .probe = imx_lpi2c_probe, + .priv_auto_alloc_size = sizeof(struct imx_lpi2c_bus), + .ops = &imx_lpi2c_ops, +}; -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 14/20] serial: lpuart: restructure lpuart driver 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (12 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 13/20] i2c: lpi2c: add lpi2c driver for i.MX7ULP Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2016-12-29 9:28 ` Bhuvanchandra DV 2017-02-12 9:27 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 15/20] serial: lpuart: add i.MX7ULP support Peng Fan ` (6 subsequent siblings) 20 siblings, 2 replies; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Drop CONFIG_LPUART_32B_REG. Move the register structure to a common file include/fsl_lpuart.h Define lpuart_serial_platdata structure which includes the reg base and flags. For 32Bit register access, use lpuart_read32/lpuart_write32 which handles big/little endian. For 8Bit register access, still use the orignal code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: York Sun <york.sun@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@nxp.com> Cc: Alison Wang <b18965@freescale.com> --- V2: New. I do not have vf610 and LSx board, please help test if you have the board. arch/arm/cpu/armv7/vf610/generic.c | 5 + .../arm/include/asm/arch-fsl-layerscape/imx-regs.h | 42 ---- arch/arm/include/asm/arch-ls102xa/imx-regs.h | 40 --- arch/arm/include/asm/arch-vf610/clock.h | 1 + arch/arm/include/asm/arch-vf610/imx-regs.h | 28 --- drivers/serial/serial_lpuart.c | 267 +++++++++++---------- 6 files changed, 148 insertions(+), 235 deletions(-) diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index 50eb0c6..0328096 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -204,6 +204,11 @@ static u32 get_dspi_clk(void) return get_ipg_clk(); } +u32 get_lpuart_clk(void) +{ + return get_uart_clk(); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { diff --git a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h index 57e417b..b0e58ca 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h @@ -10,46 +10,4 @@ #define I2C_QUIRK_REG /* enable 8-bit driver */ -#ifdef CONFIG_FSL_LPUART -#ifdef CONFIG_LPUART_32B_REG -struct lpuart_fsl { - u32 baud; - u32 stat; - u32 ctrl; - u32 data; - u32 match; - u32 modir; - u32 fifo; - u32 water; -}; -#else -struct lpuart_fsl { - u8 ubdh; - u8 ubdl; - u8 uc1; - u8 uc2; - u8 us1; - u8 us2; - u8 uc3; - u8 ud; - u8 uma1; - u8 uma2; - u8 uc4; - u8 uc5; - u8 ued; - u8 umodem; - u8 uir; - u8 reserved; - u8 upfifo; - u8 ucfifo; - u8 usfifo; - u8 utwfifo; - u8 utcfifo; - u8 urwfifo; - u8 urcfifo; - u8 rsvd[28]; -}; -#endif -#endif /* CONFIG_FSL_LPUART */ - #endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-ls102xa/imx-regs.h b/arch/arm/include/asm/arch-ls102xa/imx-regs.h index f9cd75b..7190f3d 100644 --- a/arch/arm/include/asm/arch-ls102xa/imx-regs.h +++ b/arch/arm/include/asm/arch-ls102xa/imx-regs.h @@ -10,44 +10,4 @@ #define I2C_QUIRK_REG /* enable 8-bit driver */ -#ifdef CONFIG_LPUART_32B_REG -struct lpuart_fsl { - u32 baud; - u32 stat; - u32 ctrl; - u32 data; - u32 match; - u32 modir; - u32 fifo; - u32 water; -}; -#else -struct lpuart_fsl { - u8 ubdh; - u8 ubdl; - u8 uc1; - u8 uc2; - u8 us1; - u8 us2; - u8 uc3; - u8 ud; - u8 uma1; - u8 uma2; - u8 uc4; - u8 uc5; - u8 ued; - u8 umodem; - u8 uir; - u8 reserved; - u8 upfifo; - u8 ucfifo; - u8 usfifo; - u8 utwfifo; - u8 utcfifo; - u8 urwfifo; - u8 urcfifo; - u8 rsvd[28]; -}; -#endif - #endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h index e5a5c6d..c5ba240 100644 --- a/arch/arm/include/asm/arch-vf610/clock.h +++ b/arch/arm/include/asm/arch-vf610/clock.h @@ -22,6 +22,7 @@ enum mxc_clock { void enable_ocotp_clk(unsigned char enable); unsigned int mxc_get_clock(enum mxc_clock clk); +u32 get_lpuart_clk(void); #define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 9758323..cac68ef 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -429,34 +429,6 @@ struct fuse_bank4_regs { u32 rsvd7[3]; }; -/* UART */ -struct lpuart_fsl { - u8 ubdh; - u8 ubdl; - u8 uc1; - u8 uc2; - u8 us1; - u8 us2; - u8 uc3; - u8 ud; - u8 uma1; - u8 uma2; - u8 uc4; - u8 uc5; - u8 ued; - u8 umodem; - u8 uir; - u8 reserved; - u8 upfifo; - u8 ucfifo; - u8 usfifo; - u8 utwfifo; - u8 utcfifo; - u8 urwfifo; - u8 urcfifo; - u8 rsvd[28]; -}; - /* MSCM Interrupt Router */ struct mscm_ir { u32 ircp0ir; diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index beb4243..3f030a6 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -6,6 +6,7 @@ #include <common.h> #include <dm.h> +#include <fsl_lpuart.h> #include <watchdog.h> #include <asm/io.h> #include <serial.h> @@ -48,14 +49,56 @@ DECLARE_GLOBAL_DATA_PTR; +#define LPUART_FLAG_REGMAP_32BIT_REG BIT(0) +#define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1) + struct lpuart_serial_platdata { - struct lpuart_fsl *reg; + void *reg; + ulong flags; }; -#ifndef CONFIG_LPUART_32B_REG -static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate) +static void lpuart_read32(u32 flags, u32 *addr, u32 *val) +{ + if (flags & LPUART_FLAG_REGMAP_32BIT_REG) { + if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG) + *(u32 *)val = in_be32(addr); + else + *(u32 *)val = in_le32(addr); + } +} + +static void lpuart_write32(u32 flags, u32 *addr, u32 val) +{ + if (flags & LPUART_FLAG_REGMAP_32BIT_REG) { + if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG) + out_be32(addr, val); + else + out_le32(addr, val); + } +} + + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 0 +#endif + +u32 __weak get_lpuart_clk(void) { - u32 clk = mxc_get_clock(MXC_UART_CLK); + return CONFIG_SYS_CLK_FREQ; +} + +static bool is_lpuart32(struct udevice *dev) +{ + struct lpuart_serial_platdata *plat = dev->platdata; + + return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG; +} + +static void _lpuart_serial_setbrg(struct lpuart_serial_platdata *plat, + int baudrate) +{ + struct lpuart_fsl *base = plat->reg; + u32 clk = get_lpuart_clk(); u16 sbr; sbr = (u16)(clk / (16 * baudrate)); @@ -65,8 +108,9 @@ static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate) __raw_writeb(sbr & 0xff, &base->ubdl); } -static int _lpuart_serial_getc(struct lpuart_fsl *base) +static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat) { + struct lpuart_fsl *base = plat->reg; while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR))) WATCHDOG_RESET(); @@ -75,8 +119,11 @@ static int _lpuart_serial_getc(struct lpuart_fsl *base) return __raw_readb(&base->ud); } -static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c) +static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat, + const char c) { + struct lpuart_fsl *base = plat->reg; + while (!(__raw_readb(&base->us1) & US1_TDRE)) WATCHDOG_RESET(); @@ -84,8 +131,10 @@ static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c) } /* Test whether a character is in the RX buffer */ -static int _lpuart_serial_tstc(struct lpuart_fsl *base) +static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat) { + struct lpuart_fsl *base = plat->reg; + if (__raw_readb(&base->urcfifo) == 0) return 0; @@ -96,8 +145,9 @@ static int _lpuart_serial_tstc(struct lpuart_fsl *base) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static int _lpuart_serial_init(struct lpuart_fsl *base) +static int _lpuart_serial_init(struct lpuart_serial_platdata *plat) { + struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg; u8 ctrl; ctrl = __raw_readb(&base->uc2); @@ -115,101 +165,71 @@ static int _lpuart_serial_init(struct lpuart_fsl *base) __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo); /* provide data bits, parity, stop bit, etc */ - _lpuart_serial_setbrg(base, gd->baudrate); + _lpuart_serial_setbrg(plat, gd->baudrate); __raw_writeb(UC2_RE | UC2_TE, &base->uc2); return 0; } -static int lpuart_serial_setbrg(struct udevice *dev, int baudrate) -{ - struct lpuart_serial_platdata *plat = dev->platdata; - struct lpuart_fsl *reg = plat->reg; - - _lpuart_serial_setbrg(reg, baudrate); - - return 0; -} - -static int lpuart_serial_getc(struct udevice *dev) -{ - struct lpuart_serial_platdata *plat = dev->platdata; - struct lpuart_fsl *reg = plat->reg; - - return _lpuart_serial_getc(reg); -} - -static int lpuart_serial_putc(struct udevice *dev, const char c) -{ - struct lpuart_serial_platdata *plat = dev->platdata; - struct lpuart_fsl *reg = plat->reg; - - _lpuart_serial_putc(reg, c); - - return 0; -} - -static int lpuart_serial_pending(struct udevice *dev, bool input) -{ - struct lpuart_serial_platdata *plat = dev->platdata; - struct lpuart_fsl *reg = plat->reg; - - if (input) - return _lpuart_serial_tstc(reg); - else - return __raw_readb(®->us1) & US1_TDRE ? 0 : 1; -} - -static int lpuart_serial_probe(struct udevice *dev) -{ - struct lpuart_serial_platdata *plat = dev->platdata; - struct lpuart_fsl *reg = plat->reg; - - return _lpuart_serial_init(reg); -} -#else - -u32 __weak get_lpuart_clk(void) -{ - return CONFIG_SYS_CLK_FREQ; -} - -static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate) +static void _lpuart32_serial_setbrg(struct lpuart_serial_platdata *plat, + int baudrate) { + struct lpuart_fsl_reg32 *base = plat->reg; u32 clk = get_lpuart_clk(); u32 sbr; sbr = (clk / (16 * baudrate)); /* place adjustment later - n/32 BRFA */ - out_be32(&base->baud, sbr); + lpuart_write32(plat->flags, &base->baud, sbr); } -static int _lpuart32_serial_getc(struct lpuart_fsl *base) +static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat) { + struct lpuart_fsl_reg32 *base = plat->reg; u32 stat; - while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) { - out_be32(&base->stat, STAT_FLAGS); + lpuart_read32(plat->flags, &base->stat, &stat); + while ((stat & STAT_RDRF) == 0) { + lpuart_write32(plat->flags, &base->stat, STAT_FLAGS); WATCHDOG_RESET(); + lpuart_read32(plat->flags, &base->stat, &stat); } - return in_be32(&base->data) & 0x3ff; + /* Reuse stat */ + lpuart_read32(plat->flags, &base->data, &stat); + + return stat & 0x3ff; } -static void _lpuart32_serial_putc(struct lpuart_fsl *base, const char c) +static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat, + const char c) { - while (!(in_be32(&base->stat) & STAT_TDRE)) + struct lpuart_fsl_reg32 *base = plat->reg; + u32 stat; + + while (true) { + lpuart_read32(plat->flags, &base->stat, &stat); + + if ((stat & STAT_TDRE)) + break; + WATCHDOG_RESET(); + } - out_be32(&base->data, c); + lpuart_write32(plat->flags, &base->data, c); } /* Test whether a character is in the RX buffer */ -static int _lpuart32_serial_tstc(struct lpuart_fsl *base) +static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat) { - if ((in_be32(&base->water) >> 24) == 0) + struct lpuart_fsl_reg32 *base = plat->reg; + u32 water; + + lpuart_read32(plat->flags, &base->water, &water); + + if ((water >> 24) == 0) return 0; return 1; @@ -219,75 +239,94 @@ static int _lpuart32_serial_tstc(struct lpuart_fsl *base) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static int _lpuart32_serial_init(struct lpuart_fsl *base) +static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat) { - u8 ctrl; + struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg; + u32 ctrl; - ctrl = in_be32(&base->ctrl); + lpuart_read32(plat->flags, &base->ctrl, &ctrl); ctrl &= ~CTRL_RE; ctrl &= ~CTRL_TE; - out_be32(&base->ctrl, ctrl); + lpuart_write32(plat->flags, &base->ctrl, ctrl); - out_be32(&base->modir, 0); - out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE)); + lpuart_write32(plat->flags, &base->modir, 0); + lpuart_write32(plat->flags, &base->fifo, ~(FIFO_TXFE | FIFO_RXFE)); - out_be32(&base->match, 0); + lpuart_write32(plat->flags, &base->match, 0); /* provide data bits, parity, stop bit, etc */ - _lpuart32_serial_setbrg(base, gd->baudrate); + _lpuart32_serial_setbrg(plat, gd->baudrate); - out_be32(&base->ctrl, CTRL_RE | CTRL_TE); + lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE); return 0; } -static int lpuart32_serial_setbrg(struct udevice *dev, int baudrate) +static int lpuart_serial_setbrg(struct udevice *dev, int baudrate) { struct lpuart_serial_platdata *plat = dev->platdata; - struct lpuart_fsl *reg = plat->reg; - _lpuart32_serial_setbrg(reg, baudrate); + if (is_lpuart32(dev)) + _lpuart32_serial_setbrg(plat, baudrate); + else + _lpuart_serial_setbrg(plat, baudrate); return 0; } -static int lpuart32_serial_getc(struct udevice *dev) +static int lpuart_serial_getc(struct udevice *dev) { struct lpuart_serial_platdata *plat = dev->platdata; - struct lpuart_fsl *reg = plat->reg; - return _lpuart32_serial_getc(reg); + if (is_lpuart32(dev)) + return _lpuart32_serial_getc(plat); + + return _lpuart_serial_getc(plat); } -static int lpuart32_serial_putc(struct udevice *dev, const char c) +static int lpuart_serial_putc(struct udevice *dev, const char c) { struct lpuart_serial_platdata *plat = dev->platdata; - struct lpuart_fsl *reg = plat->reg; - _lpuart32_serial_putc(reg, c); + if (is_lpuart32(dev)) + _lpuart32_serial_putc(plat, c); + else + _lpuart_serial_putc(plat, c); return 0; } -static int lpuart32_serial_pending(struct udevice *dev, bool input) +static int lpuart_serial_pending(struct udevice *dev, bool input) { struct lpuart_serial_platdata *plat = dev->platdata; struct lpuart_fsl *reg = plat->reg; + struct lpuart_fsl_reg32 *reg32 = plat->reg; + u32 stat; + + if (is_lpuart32(dev)) { + if (input) { + return _lpuart32_serial_tstc(plat); + } else { + lpuart_read32(plat->flags, ®32->stat, &stat); + return stat & STAT_TDRE ? 0 : 1; + } + } if (input) - return _lpuart32_serial_tstc(reg); + return _lpuart_serial_tstc(plat); else - return in_be32(®->stat) & STAT_TDRE ? 0 : 1; + return __raw_readb(®->us1) & US1_TDRE ? 0 : 1; } -static int lpuart32_serial_probe(struct udevice *dev) +static int lpuart_serial_probe(struct udevice *dev) { struct lpuart_serial_platdata *plat = dev->platdata; - struct lpuart_fsl *reg = plat->reg; - return _lpuart32_serial_init(reg); + if (is_lpuart32(dev)) + return _lpuart32_serial_init(plat); + else + return _lpuart_serial_init(plat); } -#endif /* CONFIG_LPUART_32B_REG */ static int lpuart_serial_ofdata_to_platdata(struct udevice *dev) { @@ -298,12 +337,12 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; - plat->reg = (struct lpuart_fsl *)addr; + plat->reg = (void *)addr; + plat->flags = dev_get_driver_data(dev); return 0; } -#ifndef CONFIG_LPUART_32B_REG static const struct dm_serial_ops lpuart_serial_ops = { .putc = lpuart_serial_putc, .pending = lpuart_serial_pending, @@ -312,7 +351,9 @@ static const struct dm_serial_ops lpuart_serial_ops = { }; static const struct udevice_id lpuart_serial_ids[] = { - { .compatible = "fsl,vf610-lpuart" }, + { .compatible = "fsl,ls1021a-lpuart", .data = + LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG }, + { .compatible = "fsl,vf610-lpuart"}, { } }; @@ -326,27 +367,3 @@ U_BOOT_DRIVER(serial_lpuart) = { .ops = &lpuart_serial_ops, .flags = DM_FLAG_PRE_RELOC, }; -#else /* CONFIG_LPUART_32B_REG */ -static const struct dm_serial_ops lpuart32_serial_ops = { - .putc = lpuart32_serial_putc, - .pending = lpuart32_serial_pending, - .getc = lpuart32_serial_getc, - .setbrg = lpuart32_serial_setbrg, -}; - -static const struct udevice_id lpuart32_serial_ids[] = { - { .compatible = "fsl,ls1021a-lpuart" }, - { } -}; - -U_BOOT_DRIVER(serial_lpuart32) = { - .name = "serial_lpuart32", - .id = UCLASS_SERIAL, - .of_match = lpuart32_serial_ids, - .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata), - .probe = lpuart32_serial_probe, - .ops = &lpuart32_serial_ops, - .flags = DM_FLAG_PRE_RELOC, -}; -#endif /* CONFIG_LPUART_32B_REG */ -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 14/20] serial: lpuart: restructure lpuart driver 2016-12-27 10:04 ` [U-Boot] [PATCH V2 14/20] serial: lpuart: restructure lpuart driver Peng Fan @ 2016-12-29 9:28 ` Bhuvanchandra DV 2017-02-12 9:27 ` Stefano Babic 1 sibling, 0 replies; 48+ messages in thread From: Bhuvanchandra DV @ 2016-12-29 9:28 UTC (permalink / raw) To: u-boot On 12/27/2016 03:34 PM, Peng Fan wrote: > Drop CONFIG_LPUART_32B_REG. > Move the register structure to a common file include/fsl_lpuart.h > Define lpuart_serial_platdata structure which includes the reg base and flags. > For 32Bit register access, use lpuart_read32/lpuart_write32 which handles > big/little endian. > For 8Bit register access, still use the orignal code. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> > Cc: York Sun <york.sun@nxp.com> > Cc: Shaohui Xie <Shaohui.Xie@nxp.com> > Cc: Alison Wang <b18965@freescale.com> > --- > > V2: > New. I do not have vf610 and LSx board, please help test if you have the board. Tested on Toradex Colibri VF50 and Colibri VF61, works fine. Tested-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> -- Bhuvan > > arch/arm/cpu/armv7/vf610/generic.c | 5 + > .../arm/include/asm/arch-fsl-layerscape/imx-regs.h | 42 ---- > arch/arm/include/asm/arch-ls102xa/imx-regs.h | 40 --- > arch/arm/include/asm/arch-vf610/clock.h | 1 + > arch/arm/include/asm/arch-vf610/imx-regs.h | 28 --- > drivers/serial/serial_lpuart.c | 267 +++++++++++---------- > 6 files changed, 148 insertions(+), 235 deletions(-) > > diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c > index 50eb0c6..0328096 100644 > --- a/arch/arm/cpu/armv7/vf610/generic.c > +++ b/arch/arm/cpu/armv7/vf610/generic.c > @@ -204,6 +204,11 @@ static u32 get_dspi_clk(void) > return get_ipg_clk(); > } > > +u32 get_lpuart_clk(void) > +{ > + return get_uart_clk(); > +} > + > unsigned int mxc_get_clock(enum mxc_clock clk) > { > switch (clk) { > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h > index 57e417b..b0e58ca 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h > @@ -10,46 +10,4 @@ > > #define I2C_QUIRK_REG /* enable 8-bit driver */ > > -#ifdef CONFIG_FSL_LPUART > -#ifdef CONFIG_LPUART_32B_REG > -struct lpuart_fsl { > - u32 baud; > - u32 stat; > - u32 ctrl; > - u32 data; > - u32 match; > - u32 modir; > - u32 fifo; > - u32 water; > -}; > -#else > -struct lpuart_fsl { > - u8 ubdh; > - u8 ubdl; > - u8 uc1; > - u8 uc2; > - u8 us1; > - u8 us2; > - u8 uc3; > - u8 ud; > - u8 uma1; > - u8 uma2; > - u8 uc4; > - u8 uc5; > - u8 ued; > - u8 umodem; > - u8 uir; > - u8 reserved; > - u8 upfifo; > - u8 ucfifo; > - u8 usfifo; > - u8 utwfifo; > - u8 utcfifo; > - u8 urwfifo; > - u8 urcfifo; > - u8 rsvd[28]; > -}; > -#endif > -#endif /* CONFIG_FSL_LPUART */ > - > #endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */ > diff --git a/arch/arm/include/asm/arch-ls102xa/imx-regs.h b/arch/arm/include/asm/arch-ls102xa/imx-regs.h > index f9cd75b..7190f3d 100644 > --- a/arch/arm/include/asm/arch-ls102xa/imx-regs.h > +++ b/arch/arm/include/asm/arch-ls102xa/imx-regs.h > @@ -10,44 +10,4 @@ > > #define I2C_QUIRK_REG /* enable 8-bit driver */ > > -#ifdef CONFIG_LPUART_32B_REG > -struct lpuart_fsl { > - u32 baud; > - u32 stat; > - u32 ctrl; > - u32 data; > - u32 match; > - u32 modir; > - u32 fifo; > - u32 water; > -}; > -#else > -struct lpuart_fsl { > - u8 ubdh; > - u8 ubdl; > - u8 uc1; > - u8 uc2; > - u8 us1; > - u8 us2; > - u8 uc3; > - u8 ud; > - u8 uma1; > - u8 uma2; > - u8 uc4; > - u8 uc5; > - u8 ued; > - u8 umodem; > - u8 uir; > - u8 reserved; > - u8 upfifo; > - u8 ucfifo; > - u8 usfifo; > - u8 utwfifo; > - u8 utcfifo; > - u8 urwfifo; > - u8 urcfifo; > - u8 rsvd[28]; > -}; > -#endif > - > #endif /* __ASM_ARCH_IMX_REGS_H__ */ > diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h > index e5a5c6d..c5ba240 100644 > --- a/arch/arm/include/asm/arch-vf610/clock.h > +++ b/arch/arm/include/asm/arch-vf610/clock.h > @@ -22,6 +22,7 @@ enum mxc_clock { > > void enable_ocotp_clk(unsigned char enable); > unsigned int mxc_get_clock(enum mxc_clock clk); > +u32 get_lpuart_clk(void); > > #define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) > > diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h > index 9758323..cac68ef 100644 > --- a/arch/arm/include/asm/arch-vf610/imx-regs.h > +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h > @@ -429,34 +429,6 @@ struct fuse_bank4_regs { > u32 rsvd7[3]; > }; > > -/* UART */ > -struct lpuart_fsl { > - u8 ubdh; > - u8 ubdl; > - u8 uc1; > - u8 uc2; > - u8 us1; > - u8 us2; > - u8 uc3; > - u8 ud; > - u8 uma1; > - u8 uma2; > - u8 uc4; > - u8 uc5; > - u8 ued; > - u8 umodem; > - u8 uir; > - u8 reserved; > - u8 upfifo; > - u8 ucfifo; > - u8 usfifo; > - u8 utwfifo; > - u8 utcfifo; > - u8 urwfifo; > - u8 urcfifo; > - u8 rsvd[28]; > -}; > - > /* MSCM Interrupt Router */ > struct mscm_ir { > u32 ircp0ir; > diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c > index beb4243..3f030a6 100644 > --- a/drivers/serial/serial_lpuart.c > +++ b/drivers/serial/serial_lpuart.c > @@ -6,6 +6,7 @@ > > #include <common.h> > #include <dm.h> > +#include <fsl_lpuart.h> > #include <watchdog.h> > #include <asm/io.h> > #include <serial.h> > @@ -48,14 +49,56 @@ > > DECLARE_GLOBAL_DATA_PTR; > > +#define LPUART_FLAG_REGMAP_32BIT_REG BIT(0) > +#define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1) > + > struct lpuart_serial_platdata { > - struct lpuart_fsl *reg; > + void *reg; > + ulong flags; > }; > > -#ifndef CONFIG_LPUART_32B_REG > -static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate) > +static void lpuart_read32(u32 flags, u32 *addr, u32 *val) > +{ > + if (flags & LPUART_FLAG_REGMAP_32BIT_REG) { > + if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG) > + *(u32 *)val = in_be32(addr); > + else > + *(u32 *)val = in_le32(addr); > + } > +} > + > +static void lpuart_write32(u32 flags, u32 *addr, u32 val) > +{ > + if (flags & LPUART_FLAG_REGMAP_32BIT_REG) { > + if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG) > + out_be32(addr, val); > + else > + out_le32(addr, val); > + } > +} > + > + > +#ifndef CONFIG_SYS_CLK_FREQ > +#define CONFIG_SYS_CLK_FREQ 0 > +#endif > + > +u32 __weak get_lpuart_clk(void) > { > - u32 clk = mxc_get_clock(MXC_UART_CLK); > + return CONFIG_SYS_CLK_FREQ; > +} > + > +static bool is_lpuart32(struct udevice *dev) > +{ > + struct lpuart_serial_platdata *plat = dev->platdata; > + > + return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG; > +} > + > +static void _lpuart_serial_setbrg(struct lpuart_serial_platdata *plat, > + int baudrate) > +{ > + struct lpuart_fsl *base = plat->reg; > + u32 clk = get_lpuart_clk(); > u16 sbr; > > sbr = (u16)(clk / (16 * baudrate)); > @@ -65,8 +108,9 @@ static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate) > __raw_writeb(sbr & 0xff, &base->ubdl); > } > > -static int _lpuart_serial_getc(struct lpuart_fsl *base) > +static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat) > { > + struct lpuart_fsl *base = plat->reg; > while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR))) > WATCHDOG_RESET(); > > @@ -75,8 +119,11 @@ static int _lpuart_serial_getc(struct lpuart_fsl *base) > return __raw_readb(&base->ud); > } > > -static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c) > +static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat, > + const char c) > { > + struct lpuart_fsl *base = plat->reg; > + > while (!(__raw_readb(&base->us1) & US1_TDRE)) > WATCHDOG_RESET(); > > @@ -84,8 +131,10 @@ static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c) > } > > /* Test whether a character is in the RX buffer */ > -static int _lpuart_serial_tstc(struct lpuart_fsl *base) > +static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat) > { > + struct lpuart_fsl *base = plat->reg; > + > if (__raw_readb(&base->urcfifo) == 0) > return 0; > > @@ -96,8 +145,9 @@ static int _lpuart_serial_tstc(struct lpuart_fsl *base) > * Initialise the serial port with the given baudrate. The settings > * are always 8 data bits, no parity, 1 stop bit, no start bits. > */ > -static int _lpuart_serial_init(struct lpuart_fsl *base) > +static int _lpuart_serial_init(struct lpuart_serial_platdata *plat) > { > + struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg; > u8 ctrl; > > ctrl = __raw_readb(&base->uc2); > @@ -115,101 +165,71 @@ static int _lpuart_serial_init(struct lpuart_fsl *base) > __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo); > > /* provide data bits, parity, stop bit, etc */ > - _lpuart_serial_setbrg(base, gd->baudrate); > + _lpuart_serial_setbrg(plat, gd->baudrate); > > __raw_writeb(UC2_RE | UC2_TE, &base->uc2); > > return 0; > } > > -static int lpuart_serial_setbrg(struct udevice *dev, int baudrate) > -{ > - struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > - > - _lpuart_serial_setbrg(reg, baudrate); > - > - return 0; > -} > - > -static int lpuart_serial_getc(struct udevice *dev) > -{ > - struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > - > - return _lpuart_serial_getc(reg); > -} > - > -static int lpuart_serial_putc(struct udevice *dev, const char c) > -{ > - struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > - > - _lpuart_serial_putc(reg, c); > - > - return 0; > -} > - > -static int lpuart_serial_pending(struct udevice *dev, bool input) > -{ > - struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > - > - if (input) > - return _lpuart_serial_tstc(reg); > - else > - return __raw_readb(®->us1) & US1_TDRE ? 0 : 1; > -} > - > -static int lpuart_serial_probe(struct udevice *dev) > -{ > - struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > - > - return _lpuart_serial_init(reg); > -} > -#else > - > -u32 __weak get_lpuart_clk(void) > -{ > - return CONFIG_SYS_CLK_FREQ; > -} > - > -static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate) > +static void _lpuart32_serial_setbrg(struct lpuart_serial_platdata *plat, > + int baudrate) > { > + struct lpuart_fsl_reg32 *base = plat->reg; > u32 clk = get_lpuart_clk(); > u32 sbr; > > sbr = (clk / (16 * baudrate)); > > /* place adjustment later - n/32 BRFA */ > - out_be32(&base->baud, sbr); > + lpuart_write32(plat->flags, &base->baud, sbr); > } > > -static int _lpuart32_serial_getc(struct lpuart_fsl *base) > +static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat) > { > + struct lpuart_fsl_reg32 *base = plat->reg; > u32 stat; > > - while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) { > - out_be32(&base->stat, STAT_FLAGS); > + lpuart_read32(plat->flags, &base->stat, &stat); > + while ((stat & STAT_RDRF) == 0) { > + lpuart_write32(plat->flags, &base->stat, STAT_FLAGS); > WATCHDOG_RESET(); > + lpuart_read32(plat->flags, &base->stat, &stat); > } > > - return in_be32(&base->data) & 0x3ff; > + /* Reuse stat */ > + lpuart_read32(plat->flags, &base->data, &stat); > + > + return stat & 0x3ff; > } > > -static void _lpuart32_serial_putc(struct lpuart_fsl *base, const char c) > +static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat, > + const char c) > { > - while (!(in_be32(&base->stat) & STAT_TDRE)) > + struct lpuart_fsl_reg32 *base = plat->reg; > + u32 stat; > + > + while (true) { > + lpuart_read32(plat->flags, &base->stat, &stat); > + > + if ((stat & STAT_TDRE)) > + break; > + > WATCHDOG_RESET(); > + } > > - out_be32(&base->data, c); > + lpuart_write32(plat->flags, &base->data, c); > } > > /* Test whether a character is in the RX buffer */ > -static int _lpuart32_serial_tstc(struct lpuart_fsl *base) > +static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat) > { > - if ((in_be32(&base->water) >> 24) == 0) > + struct lpuart_fsl_reg32 *base = plat->reg; > + u32 water; > + > + lpuart_read32(plat->flags, &base->water, &water); > + > + if ((water >> 24) == 0) > return 0; > > return 1; > @@ -219,75 +239,94 @@ static int _lpuart32_serial_tstc(struct lpuart_fsl *base) > * Initialise the serial port with the given baudrate. The settings > * are always 8 data bits, no parity, 1 stop bit, no start bits. > */ > -static int _lpuart32_serial_init(struct lpuart_fsl *base) > +static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat) > { > - u8 ctrl; > + struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg; > + u32 ctrl; > > - ctrl = in_be32(&base->ctrl); > + lpuart_read32(plat->flags, &base->ctrl, &ctrl); > ctrl &= ~CTRL_RE; > ctrl &= ~CTRL_TE; > - out_be32(&base->ctrl, ctrl); > + lpuart_write32(plat->flags, &base->ctrl, ctrl); > > - out_be32(&base->modir, 0); > - out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE)); > + lpuart_write32(plat->flags, &base->modir, 0); > + lpuart_write32(plat->flags, &base->fifo, ~(FIFO_TXFE | FIFO_RXFE)); > > - out_be32(&base->match, 0); > + lpuart_write32(plat->flags, &base->match, 0); > > /* provide data bits, parity, stop bit, etc */ > - _lpuart32_serial_setbrg(base, gd->baudrate); > + _lpuart32_serial_setbrg(plat, gd->baudrate); > > - out_be32(&base->ctrl, CTRL_RE | CTRL_TE); > + lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE); > > return 0; > } > > -static int lpuart32_serial_setbrg(struct udevice *dev, int baudrate) > +static int lpuart_serial_setbrg(struct udevice *dev, int baudrate) > { > struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > > - _lpuart32_serial_setbrg(reg, baudrate); > + if (is_lpuart32(dev)) > + _lpuart32_serial_setbrg(plat, baudrate); > + else > + _lpuart_serial_setbrg(plat, baudrate); > > return 0; > } > > -static int lpuart32_serial_getc(struct udevice *dev) > +static int lpuart_serial_getc(struct udevice *dev) > { > struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > > - return _lpuart32_serial_getc(reg); > + if (is_lpuart32(dev)) > + return _lpuart32_serial_getc(plat); > + > + return _lpuart_serial_getc(plat); > } > > -static int lpuart32_serial_putc(struct udevice *dev, const char c) > +static int lpuart_serial_putc(struct udevice *dev, const char c) > { > struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > > - _lpuart32_serial_putc(reg, c); > + if (is_lpuart32(dev)) > + _lpuart32_serial_putc(plat, c); > + else > + _lpuart_serial_putc(plat, c); > > return 0; > } > > -static int lpuart32_serial_pending(struct udevice *dev, bool input) > +static int lpuart_serial_pending(struct udevice *dev, bool input) > { > struct lpuart_serial_platdata *plat = dev->platdata; > struct lpuart_fsl *reg = plat->reg; > + struct lpuart_fsl_reg32 *reg32 = plat->reg; > + u32 stat; > + > + if (is_lpuart32(dev)) { > + if (input) { > + return _lpuart32_serial_tstc(plat); > + } else { > + lpuart_read32(plat->flags, ®32->stat, &stat); > + return stat & STAT_TDRE ? 0 : 1; > + } > + } > > if (input) > - return _lpuart32_serial_tstc(reg); > + return _lpuart_serial_tstc(plat); > else > - return in_be32(®->stat) & STAT_TDRE ? 0 : 1; > + return __raw_readb(®->us1) & US1_TDRE ? 0 : 1; > } > > -static int lpuart32_serial_probe(struct udevice *dev) > +static int lpuart_serial_probe(struct udevice *dev) > { > struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > > - return _lpuart32_serial_init(reg); > + if (is_lpuart32(dev)) > + return _lpuart32_serial_init(plat); > + else > + return _lpuart_serial_init(plat); > } > -#endif /* CONFIG_LPUART_32B_REG */ > > static int lpuart_serial_ofdata_to_platdata(struct udevice *dev) > { > @@ -298,12 +337,12 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice *dev) > if (addr == FDT_ADDR_T_NONE) > return -EINVAL; > > - plat->reg = (struct lpuart_fsl *)addr; > + plat->reg = (void *)addr; > + plat->flags = dev_get_driver_data(dev); > > return 0; > } > > -#ifndef CONFIG_LPUART_32B_REG > static const struct dm_serial_ops lpuart_serial_ops = { > .putc = lpuart_serial_putc, > .pending = lpuart_serial_pending, > @@ -312,7 +351,9 @@ static const struct dm_serial_ops lpuart_serial_ops = { > }; > > static const struct udevice_id lpuart_serial_ids[] = { > - { .compatible = "fsl,vf610-lpuart" }, > + { .compatible = "fsl,ls1021a-lpuart", .data = > + LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG }, > + { .compatible = "fsl,vf610-lpuart"}, > { } > }; > > @@ -326,27 +367,3 @@ U_BOOT_DRIVER(serial_lpuart) = { > .ops = &lpuart_serial_ops, > .flags = DM_FLAG_PRE_RELOC, > }; > -#else /* CONFIG_LPUART_32B_REG */ > -static const struct dm_serial_ops lpuart32_serial_ops = { > - .putc = lpuart32_serial_putc, > - .pending = lpuart32_serial_pending, > - .getc = lpuart32_serial_getc, > - .setbrg = lpuart32_serial_setbrg, > -}; > - > -static const struct udevice_id lpuart32_serial_ids[] = { > - { .compatible = "fsl,ls1021a-lpuart" }, > - { } > -}; > - > -U_BOOT_DRIVER(serial_lpuart32) = { > - .name = "serial_lpuart32", > - .id = UCLASS_SERIAL, > - .of_match = lpuart32_serial_ids, > - .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata, > - .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata), > - .probe = lpuart32_serial_probe, > - .ops = &lpuart32_serial_ops, > - .flags = DM_FLAG_PRE_RELOC, > -}; > -#endif /* CONFIG_LPUART_32B_REG */ ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 14/20] serial: lpuart: restructure lpuart driver 2016-12-27 10:04 ` [U-Boot] [PATCH V2 14/20] serial: lpuart: restructure lpuart driver Peng Fan 2016-12-29 9:28 ` Bhuvanchandra DV @ 2017-02-12 9:27 ` Stefano Babic 1 sibling, 0 replies; 48+ messages in thread From: Stefano Babic @ 2017-02-12 9:27 UTC (permalink / raw) To: u-boot On 27/12/2016 11:04, Peng Fan wrote: > Drop CONFIG_LPUART_32B_REG. > Move the register structure to a common file include/fsl_lpuart.h > Define lpuart_serial_platdata structure which includes the reg base and flags. > For 32Bit register access, use lpuart_read32/lpuart_write32 which handles > big/little endian. > For 8Bit register access, still use the orignal code. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> > Cc: York Sun <york.sun@nxp.com> > Cc: Shaohui Xie <Shaohui.Xie@nxp.com> > Cc: Alison Wang <b18965@freescale.com> > --- > > V2: > New. I do not have vf610 and LSx board, please help test if you have the board. > > arch/arm/cpu/armv7/vf610/generic.c | 5 + > .../arm/include/asm/arch-fsl-layerscape/imx-regs.h | 42 ---- > arch/arm/include/asm/arch-ls102xa/imx-regs.h | 40 --- > arch/arm/include/asm/arch-vf610/clock.h | 1 + > arch/arm/include/asm/arch-vf610/imx-regs.h | 28 --- > drivers/serial/serial_lpuart.c | 267 +++++++++++---------- > 6 files changed, 148 insertions(+), 235 deletions(-) > > diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c > index 50eb0c6..0328096 100644 > --- a/arch/arm/cpu/armv7/vf610/generic.c > +++ b/arch/arm/cpu/armv7/vf610/generic.c > @@ -204,6 +204,11 @@ static u32 get_dspi_clk(void) > return get_ipg_clk(); > } > > +u32 get_lpuart_clk(void) > +{ > + return get_uart_clk(); > +} > + > unsigned int mxc_get_clock(enum mxc_clock clk) > { > switch (clk) { > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h > index 57e417b..b0e58ca 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h > @@ -10,46 +10,4 @@ > > #define I2C_QUIRK_REG /* enable 8-bit driver */ > > -#ifdef CONFIG_FSL_LPUART > -#ifdef CONFIG_LPUART_32B_REG > -struct lpuart_fsl { > - u32 baud; > - u32 stat; > - u32 ctrl; > - u32 data; > - u32 match; > - u32 modir; > - u32 fifo; > - u32 water; > -}; > -#else > -struct lpuart_fsl { > - u8 ubdh; > - u8 ubdl; > - u8 uc1; > - u8 uc2; > - u8 us1; > - u8 us2; > - u8 uc3; > - u8 ud; > - u8 uma1; > - u8 uma2; > - u8 uc4; > - u8 uc5; > - u8 ued; > - u8 umodem; > - u8 uir; > - u8 reserved; > - u8 upfifo; > - u8 ucfifo; > - u8 usfifo; > - u8 utwfifo; > - u8 utcfifo; > - u8 urwfifo; > - u8 urcfifo; > - u8 rsvd[28]; > -}; > -#endif > -#endif /* CONFIG_FSL_LPUART */ > - > #endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */ > diff --git a/arch/arm/include/asm/arch-ls102xa/imx-regs.h b/arch/arm/include/asm/arch-ls102xa/imx-regs.h > index f9cd75b..7190f3d 100644 > --- a/arch/arm/include/asm/arch-ls102xa/imx-regs.h > +++ b/arch/arm/include/asm/arch-ls102xa/imx-regs.h > @@ -10,44 +10,4 @@ > > #define I2C_QUIRK_REG /* enable 8-bit driver */ > > -#ifdef CONFIG_LPUART_32B_REG > -struct lpuart_fsl { > - u32 baud; > - u32 stat; > - u32 ctrl; > - u32 data; > - u32 match; > - u32 modir; > - u32 fifo; > - u32 water; > -}; > -#else > -struct lpuart_fsl { > - u8 ubdh; > - u8 ubdl; > - u8 uc1; > - u8 uc2; > - u8 us1; > - u8 us2; > - u8 uc3; > - u8 ud; > - u8 uma1; > - u8 uma2; > - u8 uc4; > - u8 uc5; > - u8 ued; > - u8 umodem; > - u8 uir; > - u8 reserved; > - u8 upfifo; > - u8 ucfifo; > - u8 usfifo; > - u8 utwfifo; > - u8 utcfifo; > - u8 urwfifo; > - u8 urcfifo; > - u8 rsvd[28]; > -}; > -#endif > - > #endif /* __ASM_ARCH_IMX_REGS_H__ */ > diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h > index e5a5c6d..c5ba240 100644 > --- a/arch/arm/include/asm/arch-vf610/clock.h > +++ b/arch/arm/include/asm/arch-vf610/clock.h > @@ -22,6 +22,7 @@ enum mxc_clock { > > void enable_ocotp_clk(unsigned char enable); > unsigned int mxc_get_clock(enum mxc_clock clk); > +u32 get_lpuart_clk(void); > > #define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) > > diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h > index 9758323..cac68ef 100644 > --- a/arch/arm/include/asm/arch-vf610/imx-regs.h > +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h > @@ -429,34 +429,6 @@ struct fuse_bank4_regs { > u32 rsvd7[3]; > }; > > -/* UART */ > -struct lpuart_fsl { > - u8 ubdh; > - u8 ubdl; > - u8 uc1; > - u8 uc2; > - u8 us1; > - u8 us2; > - u8 uc3; > - u8 ud; > - u8 uma1; > - u8 uma2; > - u8 uc4; > - u8 uc5; > - u8 ued; > - u8 umodem; > - u8 uir; > - u8 reserved; > - u8 upfifo; > - u8 ucfifo; > - u8 usfifo; > - u8 utwfifo; > - u8 utcfifo; > - u8 urwfifo; > - u8 urcfifo; > - u8 rsvd[28]; > -}; > - > /* MSCM Interrupt Router */ > struct mscm_ir { > u32 ircp0ir; > diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c > index beb4243..3f030a6 100644 > --- a/drivers/serial/serial_lpuart.c > +++ b/drivers/serial/serial_lpuart.c > @@ -6,6 +6,7 @@ > > #include <common.h> > #include <dm.h> > +#include <fsl_lpuart.h> > #include <watchdog.h> > #include <asm/io.h> > #include <serial.h> > @@ -48,14 +49,56 @@ > > DECLARE_GLOBAL_DATA_PTR; > > +#define LPUART_FLAG_REGMAP_32BIT_REG BIT(0) > +#define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1) > + > struct lpuart_serial_platdata { > - struct lpuart_fsl *reg; > + void *reg; > + ulong flags; > }; > > -#ifndef CONFIG_LPUART_32B_REG > -static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate) > +static void lpuart_read32(u32 flags, u32 *addr, u32 *val) > +{ > + if (flags & LPUART_FLAG_REGMAP_32BIT_REG) { > + if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG) > + *(u32 *)val = in_be32(addr); > + else > + *(u32 *)val = in_le32(addr); > + } > +} > + > +static void lpuart_write32(u32 flags, u32 *addr, u32 val) > +{ > + if (flags & LPUART_FLAG_REGMAP_32BIT_REG) { > + if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG) > + out_be32(addr, val); > + else > + out_le32(addr, val); > + } > +} > + > + > +#ifndef CONFIG_SYS_CLK_FREQ > +#define CONFIG_SYS_CLK_FREQ 0 > +#endif > + > +u32 __weak get_lpuart_clk(void) > { > - u32 clk = mxc_get_clock(MXC_UART_CLK); > + return CONFIG_SYS_CLK_FREQ; > +} > + > +static bool is_lpuart32(struct udevice *dev) > +{ > + struct lpuart_serial_platdata *plat = dev->platdata; > + > + return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG; > +} > + > +static void _lpuart_serial_setbrg(struct lpuart_serial_platdata *plat, > + int baudrate) > +{ > + struct lpuart_fsl *base = plat->reg; > + u32 clk = get_lpuart_clk(); > u16 sbr; > > sbr = (u16)(clk / (16 * baudrate)); > @@ -65,8 +108,9 @@ static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate) > __raw_writeb(sbr & 0xff, &base->ubdl); > } > > -static int _lpuart_serial_getc(struct lpuart_fsl *base) > +static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat) > { > + struct lpuart_fsl *base = plat->reg; > while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR))) > WATCHDOG_RESET(); > > @@ -75,8 +119,11 @@ static int _lpuart_serial_getc(struct lpuart_fsl *base) > return __raw_readb(&base->ud); > } > > -static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c) > +static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat, > + const char c) > { > + struct lpuart_fsl *base = plat->reg; > + > while (!(__raw_readb(&base->us1) & US1_TDRE)) > WATCHDOG_RESET(); > > @@ -84,8 +131,10 @@ static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c) > } > > /* Test whether a character is in the RX buffer */ > -static int _lpuart_serial_tstc(struct lpuart_fsl *base) > +static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat) > { > + struct lpuart_fsl *base = plat->reg; > + > if (__raw_readb(&base->urcfifo) == 0) > return 0; > > @@ -96,8 +145,9 @@ static int _lpuart_serial_tstc(struct lpuart_fsl *base) > * Initialise the serial port with the given baudrate. The settings > * are always 8 data bits, no parity, 1 stop bit, no start bits. > */ > -static int _lpuart_serial_init(struct lpuart_fsl *base) > +static int _lpuart_serial_init(struct lpuart_serial_platdata *plat) > { > + struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg; > u8 ctrl; > > ctrl = __raw_readb(&base->uc2); > @@ -115,101 +165,71 @@ static int _lpuart_serial_init(struct lpuart_fsl *base) > __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo); > > /* provide data bits, parity, stop bit, etc */ > - _lpuart_serial_setbrg(base, gd->baudrate); > + _lpuart_serial_setbrg(plat, gd->baudrate); > > __raw_writeb(UC2_RE | UC2_TE, &base->uc2); > > return 0; > } > > -static int lpuart_serial_setbrg(struct udevice *dev, int baudrate) > -{ > - struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > - > - _lpuart_serial_setbrg(reg, baudrate); > - > - return 0; > -} > - > -static int lpuart_serial_getc(struct udevice *dev) > -{ > - struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > - > - return _lpuart_serial_getc(reg); > -} > - > -static int lpuart_serial_putc(struct udevice *dev, const char c) > -{ > - struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > - > - _lpuart_serial_putc(reg, c); > - > - return 0; > -} > - > -static int lpuart_serial_pending(struct udevice *dev, bool input) > -{ > - struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > - > - if (input) > - return _lpuart_serial_tstc(reg); > - else > - return __raw_readb(®->us1) & US1_TDRE ? 0 : 1; > -} > - > -static int lpuart_serial_probe(struct udevice *dev) > -{ > - struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > - > - return _lpuart_serial_init(reg); > -} > -#else > - > -u32 __weak get_lpuart_clk(void) > -{ > - return CONFIG_SYS_CLK_FREQ; > -} > - > -static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate) > +static void _lpuart32_serial_setbrg(struct lpuart_serial_platdata *plat, > + int baudrate) > { > + struct lpuart_fsl_reg32 *base = plat->reg; > u32 clk = get_lpuart_clk(); > u32 sbr; > > sbr = (clk / (16 * baudrate)); > > /* place adjustment later - n/32 BRFA */ > - out_be32(&base->baud, sbr); > + lpuart_write32(plat->flags, &base->baud, sbr); > } > > -static int _lpuart32_serial_getc(struct lpuart_fsl *base) > +static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat) > { > + struct lpuart_fsl_reg32 *base = plat->reg; > u32 stat; > > - while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) { > - out_be32(&base->stat, STAT_FLAGS); > + lpuart_read32(plat->flags, &base->stat, &stat); > + while ((stat & STAT_RDRF) == 0) { > + lpuart_write32(plat->flags, &base->stat, STAT_FLAGS); > WATCHDOG_RESET(); > + lpuart_read32(plat->flags, &base->stat, &stat); > } > > - return in_be32(&base->data) & 0x3ff; > + /* Reuse stat */ > + lpuart_read32(plat->flags, &base->data, &stat); > + > + return stat & 0x3ff; > } > > -static void _lpuart32_serial_putc(struct lpuart_fsl *base, const char c) > +static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat, > + const char c) > { > - while (!(in_be32(&base->stat) & STAT_TDRE)) > + struct lpuart_fsl_reg32 *base = plat->reg; > + u32 stat; > + > + while (true) { > + lpuart_read32(plat->flags, &base->stat, &stat); > + > + if ((stat & STAT_TDRE)) > + break; > + > WATCHDOG_RESET(); > + } > > - out_be32(&base->data, c); > + lpuart_write32(plat->flags, &base->data, c); > } > > /* Test whether a character is in the RX buffer */ > -static int _lpuart32_serial_tstc(struct lpuart_fsl *base) > +static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat) > { > - if ((in_be32(&base->water) >> 24) == 0) > + struct lpuart_fsl_reg32 *base = plat->reg; > + u32 water; > + > + lpuart_read32(plat->flags, &base->water, &water); > + > + if ((water >> 24) == 0) > return 0; > > return 1; > @@ -219,75 +239,94 @@ static int _lpuart32_serial_tstc(struct lpuart_fsl *base) > * Initialise the serial port with the given baudrate. The settings > * are always 8 data bits, no parity, 1 stop bit, no start bits. > */ > -static int _lpuart32_serial_init(struct lpuart_fsl *base) > +static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat) > { > - u8 ctrl; > + struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg; > + u32 ctrl; > > - ctrl = in_be32(&base->ctrl); > + lpuart_read32(plat->flags, &base->ctrl, &ctrl); > ctrl &= ~CTRL_RE; > ctrl &= ~CTRL_TE; > - out_be32(&base->ctrl, ctrl); > + lpuart_write32(plat->flags, &base->ctrl, ctrl); > > - out_be32(&base->modir, 0); > - out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE)); > + lpuart_write32(plat->flags, &base->modir, 0); > + lpuart_write32(plat->flags, &base->fifo, ~(FIFO_TXFE | FIFO_RXFE)); > > - out_be32(&base->match, 0); > + lpuart_write32(plat->flags, &base->match, 0); > > /* provide data bits, parity, stop bit, etc */ > - _lpuart32_serial_setbrg(base, gd->baudrate); > + _lpuart32_serial_setbrg(plat, gd->baudrate); > > - out_be32(&base->ctrl, CTRL_RE | CTRL_TE); > + lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE); > > return 0; > } > > -static int lpuart32_serial_setbrg(struct udevice *dev, int baudrate) > +static int lpuart_serial_setbrg(struct udevice *dev, int baudrate) > { > struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > > - _lpuart32_serial_setbrg(reg, baudrate); > + if (is_lpuart32(dev)) > + _lpuart32_serial_setbrg(plat, baudrate); > + else > + _lpuart_serial_setbrg(plat, baudrate); > > return 0; > } > > -static int lpuart32_serial_getc(struct udevice *dev) > +static int lpuart_serial_getc(struct udevice *dev) > { > struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > > - return _lpuart32_serial_getc(reg); > + if (is_lpuart32(dev)) > + return _lpuart32_serial_getc(plat); > + > + return _lpuart_serial_getc(plat); > } > > -static int lpuart32_serial_putc(struct udevice *dev, const char c) > +static int lpuart_serial_putc(struct udevice *dev, const char c) > { > struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > > - _lpuart32_serial_putc(reg, c); > + if (is_lpuart32(dev)) > + _lpuart32_serial_putc(plat, c); > + else > + _lpuart_serial_putc(plat, c); > > return 0; > } > > -static int lpuart32_serial_pending(struct udevice *dev, bool input) > +static int lpuart_serial_pending(struct udevice *dev, bool input) > { > struct lpuart_serial_platdata *plat = dev->platdata; > struct lpuart_fsl *reg = plat->reg; > + struct lpuart_fsl_reg32 *reg32 = plat->reg; > + u32 stat; > + > + if (is_lpuart32(dev)) { > + if (input) { > + return _lpuart32_serial_tstc(plat); > + } else { > + lpuart_read32(plat->flags, ®32->stat, &stat); > + return stat & STAT_TDRE ? 0 : 1; > + } > + } > > if (input) > - return _lpuart32_serial_tstc(reg); > + return _lpuart_serial_tstc(plat); > else > - return in_be32(®->stat) & STAT_TDRE ? 0 : 1; > + return __raw_readb(®->us1) & US1_TDRE ? 0 : 1; > } > > -static int lpuart32_serial_probe(struct udevice *dev) > +static int lpuart_serial_probe(struct udevice *dev) > { > struct lpuart_serial_platdata *plat = dev->platdata; > - struct lpuart_fsl *reg = plat->reg; > > - return _lpuart32_serial_init(reg); > + if (is_lpuart32(dev)) > + return _lpuart32_serial_init(plat); > + else > + return _lpuart_serial_init(plat); > } > -#endif /* CONFIG_LPUART_32B_REG */ > > static int lpuart_serial_ofdata_to_platdata(struct udevice *dev) > { > @@ -298,12 +337,12 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice *dev) > if (addr == FDT_ADDR_T_NONE) > return -EINVAL; > > - plat->reg = (struct lpuart_fsl *)addr; > + plat->reg = (void *)addr; > + plat->flags = dev_get_driver_data(dev); > > return 0; > } > > -#ifndef CONFIG_LPUART_32B_REG > static const struct dm_serial_ops lpuart_serial_ops = { > .putc = lpuart_serial_putc, > .pending = lpuart_serial_pending, > @@ -312,7 +351,9 @@ static const struct dm_serial_ops lpuart_serial_ops = { > }; > > static const struct udevice_id lpuart_serial_ids[] = { > - { .compatible = "fsl,vf610-lpuart" }, > + { .compatible = "fsl,ls1021a-lpuart", .data = > + LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG }, > + { .compatible = "fsl,vf610-lpuart"}, > { } > }; > > @@ -326,27 +367,3 @@ U_BOOT_DRIVER(serial_lpuart) = { > .ops = &lpuart_serial_ops, > .flags = DM_FLAG_PRE_RELOC, > }; > -#else /* CONFIG_LPUART_32B_REG */ > -static const struct dm_serial_ops lpuart32_serial_ops = { > - .putc = lpuart32_serial_putc, > - .pending = lpuart32_serial_pending, > - .getc = lpuart32_serial_getc, > - .setbrg = lpuart32_serial_setbrg, > -}; > - > -static const struct udevice_id lpuart32_serial_ids[] = { > - { .compatible = "fsl,ls1021a-lpuart" }, > - { } > -}; > - > -U_BOOT_DRIVER(serial_lpuart32) = { > - .name = "serial_lpuart32", > - .id = UCLASS_SERIAL, > - .of_match = lpuart32_serial_ids, > - .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata, > - .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata), > - .probe = lpuart32_serial_probe, > - .ops = &lpuart32_serial_ops, > - .flags = DM_FLAG_PRE_RELOC, > -}; > -#endif /* CONFIG_LPUART_32B_REG */ > Reviewed-by : Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 15/20] serial: lpuart: add i.MX7ULP support 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (13 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 14/20] serial: lpuart: restructure lpuart driver Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2016-12-27 10:04 ` [U-Boot] [PATCH V2 16/20] mx7ulp: Add HAB boot support Peng Fan ` (5 subsequent siblings) 20 siblings, 0 replies; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Add i.MX7ULP support. The buadrate calculation on i.MX7ULP is different,so add a new setbrg function for i.MX7ULP. Add a enum lpuart_devtype for runtime check for different platforms. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: York Sun <york.sun@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@nxp.com> Cc: Alison Wang <b18965@freescale.com> --- V2: New drivers/serial/serial_lpuart.c | 113 +++++++++++++++++++++++++++++++++++++---- include/fsl_lpuart.h | 72 ++++++++++++++++++++++++++ 2 files changed, 176 insertions(+), 9 deletions(-) create mode 100644 include/fsl_lpuart.h diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 3f030a6..95e002e 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -52,8 +52,15 @@ DECLARE_GLOBAL_DATA_PTR; #define LPUART_FLAG_REGMAP_32BIT_REG BIT(0) #define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1) +enum lpuart_devtype { + DEV_VF610 = 1, + DEV_LS1021A, + DEV_MX7ULP +}; + struct lpuart_serial_platdata { void *reg; + enum lpuart_devtype devtype; ulong flags; }; @@ -172,6 +179,65 @@ static int _lpuart_serial_init(struct lpuart_serial_platdata *plat) return 0; } +static void _lpuart32_serial_setbrg_7ulp(struct lpuart_serial_platdata *plat, + int baudrate) +{ + struct lpuart_fsl_reg32 *base = plat->reg; + u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; + u32 clk = get_lpuart_clk(); + + baud_diff = baudrate; + osr = 0; + sbr = 0; + + for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { + tmp_sbr = (clk / (baudrate * tmp_osr)); + + if (tmp_sbr == 0) + tmp_sbr = 1; + + /*calculate difference in actual buad w/ current values */ + tmp_diff = (clk / (tmp_osr * tmp_sbr)); + tmp_diff = tmp_diff - baudrate; + + /* select best values between sbr and sbr+1 */ + if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) { + tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1))); + tmp_sbr++; + } + + if (tmp_diff <= baud_diff) { + baud_diff = tmp_diff; + osr = tmp_osr; + sbr = tmp_sbr; + } + } + + /* + * TODO: handle buadrate outside acceptable rate + * if (baudDiff > ((config->baudRate_Bps / 100) * 3)) + * { + * Unacceptable baud rate difference of more than 3% + * return kStatus_LPUART_BaudrateNotSupport; + * } + */ + tmp = in_le32(&base->baud); + + if ((osr > 3) && (osr < 8)) + tmp |= LPUART_BAUD_BOTHEDGE_MASK; + + tmp &= ~LPUART_BAUD_OSR_MASK; + tmp |= LPUART_BAUD_OSR(osr-1); + + tmp &= ~LPUART_BAUD_SBR_MASK; + tmp |= LPUART_BAUD_SBR(sbr); + + /* explicitly disable 10 bit mode & set 1 stop bit */ + tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK); + + out_le32(&base->baud, tmp); +} + static void _lpuart32_serial_setbrg(struct lpuart_serial_platdata *plat, int baudrate) { @@ -188,7 +254,7 @@ static void _lpuart32_serial_setbrg(struct lpuart_serial_platdata *plat, static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat) { struct lpuart_fsl_reg32 *base = plat->reg; - u32 stat; + u32 stat, val; lpuart_read32(plat->flags, &base->stat, &stat); while ((stat & STAT_RDRF) == 0) { @@ -197,10 +263,15 @@ static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat) lpuart_read32(plat->flags, &base->stat, &stat); } - /* Reuse stat */ - lpuart_read32(plat->flags, &base->data, &stat); + lpuart_read32(plat->flags, &base->data, &val); - return stat & 0x3ff; + if (plat->devtype & DEV_MX7ULP) { + lpuart_read32(plat->flags, &base->stat, &stat); + if (stat & STAT_OR) + lpuart_write32(plat->flags, &base->stat, STAT_OR); + } + + return val & 0x3ff; } static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat, @@ -209,6 +280,11 @@ static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat, struct lpuart_fsl_reg32 *base = plat->reg; u32 stat; + if (plat->devtype & DEV_MX7ULP) { + if (c == '\n') + serial_putc('\r'); + } + while (true) { lpuart_read32(plat->flags, &base->stat, &stat); @@ -254,8 +330,12 @@ static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat) lpuart_write32(plat->flags, &base->match, 0); - /* provide data bits, parity, stop bit, etc */ - _lpuart32_serial_setbrg(plat, gd->baudrate); + if (plat->devtype & DEV_MX7ULP) { + _lpuart32_serial_setbrg_7ulp(plat, gd->baudrate); + } else { + /* provide data bits, parity, stop bit, etc */ + _lpuart32_serial_setbrg(plat, gd->baudrate); + } lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE); @@ -266,10 +346,14 @@ static int lpuart_serial_setbrg(struct udevice *dev, int baudrate) { struct lpuart_serial_platdata *plat = dev->platdata; - if (is_lpuart32(dev)) - _lpuart32_serial_setbrg(plat, baudrate); - else + if (is_lpuart32(dev)) { + if (plat->devtype & DEV_MX7ULP) + _lpuart32_serial_setbrg_7ulp(plat, baudrate); + else + _lpuart32_serial_setbrg(plat, baudrate); + } else { _lpuart_serial_setbrg(plat, baudrate); + } return 0; } @@ -331,6 +415,8 @@ static int lpuart_serial_probe(struct udevice *dev) static int lpuart_serial_ofdata_to_platdata(struct udevice *dev) { struct lpuart_serial_platdata *plat = dev->platdata; + const void *blob = gd->fdt_blob; + int node = dev->of_offset; fdt_addr_t addr; addr = dev_get_addr(dev); @@ -340,6 +426,13 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice *dev) plat->reg = (void *)addr; plat->flags = dev_get_driver_data(dev); + if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart")) + plat->devtype = DEV_LS1021A; + else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart")) + plat->devtype = DEV_MX7ULP; + else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart")) + plat->devtype = DEV_VF610; + return 0; } @@ -353,6 +446,8 @@ static const struct dm_serial_ops lpuart_serial_ops = { static const struct udevice_id lpuart_serial_ids[] = { { .compatible = "fsl,ls1021a-lpuart", .data = LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG }, + { .compatible = "fsl,imx7ulp-lpuart", + .data = LPUART_FLAG_REGMAP_32BIT_REG }, { .compatible = "fsl,vf610-lpuart"}, { } }; diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h new file mode 100644 index 0000000..4643ee7 --- /dev/null +++ b/include/fsl_lpuart.h @@ -0,0 +1,72 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifdef CONFIG_ARCH_MX7ULP +struct lpuart_fsl_reg32 { + u32 verid; + u32 param; + u32 global; + u32 pincfg; + u32 baud; + u32 stat; + u32 ctrl; + u32 data; + u32 match; + u32 modir; + u32 fifo; + u32 water; +}; +#else +struct lpuart_fsl_reg32 { + u32 baud; + u32 stat; + u32 ctrl; + u32 data; + u32 match; + u32 modir; + u32 fifo; + u32 water; +}; +#endif + +struct lpuart_fsl { + u8 ubdh; + u8 ubdl; + u8 uc1; + u8 uc2; + u8 us1; + u8 us2; + u8 uc3; + u8 ud; + u8 uma1; + u8 uma2; + u8 uc4; + u8 uc5; + u8 ued; + u8 umodem; + u8 uir; + u8 reserved; + u8 upfifo; + u8 ucfifo; + u8 usfifo; + u8 utwfifo; + u8 utcfifo; + u8 urwfifo; + u8 urcfifo; + u8 rsvd[28]; +}; + +/* Used on i.MX7ULP */ +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000) +#define LPUART_BAUD_OSR_MASK (0x1F000000) +#define LPUART_BAUD_OSR_SHIFT (24) +#define LPUART_BAUD_OSR(x) ((((uint32_t)(x)) << 24) & 0x1F000000) +#define LPUART_BAUD_SBR_MASK (0x1FFF) +#define LPUART_BAUD_SBR_SHIFT (0U) +#define LPUART_BAUD_SBR(x) (((uint32_t)(x)) & 0x1FFF) +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_SBNS_MASK (0x2000U) -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 16/20] mx7ulp: Add HAB boot support 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (14 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 15/20] serial: lpuart: add i.MX7ULP support Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2017-02-12 9:28 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 17/20] arm: dts: add i.MX7ULP dtsi file Peng Fan ` (4 subsequent siblings) 20 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Add CAAM clock functions, SEC_CONFIG[1] fuse checking, and default CSF size for HAB support boot on mx7ulp. Users need to uncomment the CONFIG_SECURE_BOOT in mx7ulp_evk.h to build secure uboot. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: New arch/arm/cpu/armv7/mx7ulp/clock.c | 10 ++++++++++ arch/arm/cpu/armv7/mx7ulp/soc.c | 8 ++++++++ arch/arm/imx-common/hab.c | 3 ++- arch/arm/include/asm/arch-mx7ulp/clock.h | 1 + 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/mx7ulp/clock.c b/arch/arm/cpu/armv7/mx7ulp/clock.c index 30db67d..f7eaa4b 100644 --- a/arch/arm/cpu/armv7/mx7ulp/clock.c +++ b/arch/arm/cpu/armv7/mx7ulp/clock.c @@ -312,6 +312,16 @@ void clock_init(void) enable_usboh3_clk(1); } +#ifdef CONFIG_SECURE_BOOT +void hab_caam_clock_enable(unsigned char enable) +{ + if (enable) + pcc_clock_enable(PER_CLK_CAAM, true); + else + pcc_clock_enable(PER_CLK_CAAM, false); +} +#endif + /* * Dump some core clockes. */ diff --git a/arch/arm/cpu/armv7/mx7ulp/soc.c b/arch/arm/cpu/armv7/mx7ulp/soc.c index d04edc5..6fa97bb 100644 --- a/arch/arm/cpu/armv7/mx7ulp/soc.c +++ b/arch/arm/cpu/armv7/mx7ulp/soc.c @@ -7,9 +7,17 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> +#include <asm/imx-common/hab.h> static char *get_reset_cause(char *); +#if defined(CONFIG_SECURE_BOOT) +struct imx_sec_config_fuse_t const imx_sec_config_fuse = { + .bank = 29, + .word = 6, +}; +#endif + u32 get_cpu_rev(void) { /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */ diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c index 6731825..74bb3ff 100644 --- a/arch/arm/imx-common/hab.c +++ b/arch/arm/imx-common/hab.c @@ -77,7 +77,8 @@ #define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0 #define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18 #define IS_HAB_ENABLED_BIT \ - (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2) + (is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \ + (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)) /* * +------------+ 0x0 (DDR_UIMAGE_START) - diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h index ebf32c6..170a9b3 100644 --- a/arch/arm/include/asm/arch-mx7ulp/clock.h +++ b/arch/arm/include/asm/arch-mx7ulp/clock.h @@ -39,4 +39,5 @@ void enable_usboh3_clk(unsigned char enable); #endif void init_clk_usdhc(u32 index); void clock_init(void); +void hab_caam_clock_enable(unsigned char enable); #endif -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 16/20] mx7ulp: Add HAB boot support 2016-12-27 10:04 ` [U-Boot] [PATCH V2 16/20] mx7ulp: Add HAB boot support Peng Fan @ 2017-02-12 9:28 ` Stefano Babic 0 siblings, 0 replies; 48+ messages in thread From: Stefano Babic @ 2017-02-12 9:28 UTC (permalink / raw) To: u-boot On 27/12/2016 11:04, Peng Fan wrote: > Add CAAM clock functions, SEC_CONFIG[1] fuse checking, and default CSF > size for HAB support boot on mx7ulp. > > Users need to uncomment the CONFIG_SECURE_BOOT in mx7ulp_evk.h to build > secure uboot. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Signed-off-by: Ye Li <ye.li@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > New > > arch/arm/cpu/armv7/mx7ulp/clock.c | 10 ++++++++++ > arch/arm/cpu/armv7/mx7ulp/soc.c | 8 ++++++++ > arch/arm/imx-common/hab.c | 3 ++- > arch/arm/include/asm/arch-mx7ulp/clock.h | 1 + > 4 files changed, 21 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/cpu/armv7/mx7ulp/clock.c b/arch/arm/cpu/armv7/mx7ulp/clock.c > index 30db67d..f7eaa4b 100644 > --- a/arch/arm/cpu/armv7/mx7ulp/clock.c > +++ b/arch/arm/cpu/armv7/mx7ulp/clock.c > @@ -312,6 +312,16 @@ void clock_init(void) > enable_usboh3_clk(1); > } > > +#ifdef CONFIG_SECURE_BOOT > +void hab_caam_clock_enable(unsigned char enable) > +{ > + if (enable) > + pcc_clock_enable(PER_CLK_CAAM, true); > + else > + pcc_clock_enable(PER_CLK_CAAM, false); > +} > +#endif > + > /* > * Dump some core clockes. > */ > diff --git a/arch/arm/cpu/armv7/mx7ulp/soc.c b/arch/arm/cpu/armv7/mx7ulp/soc.c > index d04edc5..6fa97bb 100644 > --- a/arch/arm/cpu/armv7/mx7ulp/soc.c > +++ b/arch/arm/cpu/armv7/mx7ulp/soc.c > @@ -7,9 +7,17 @@ > #include <asm/arch/clock.h> > #include <asm/arch/imx-regs.h> > #include <asm/arch/sys_proto.h> > +#include <asm/imx-common/hab.h> > > static char *get_reset_cause(char *); > > +#if defined(CONFIG_SECURE_BOOT) > +struct imx_sec_config_fuse_t const imx_sec_config_fuse = { > + .bank = 29, > + .word = 6, > +}; > +#endif > + > u32 get_cpu_rev(void) > { > /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */ > diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c > index 6731825..74bb3ff 100644 > --- a/arch/arm/imx-common/hab.c > +++ b/arch/arm/imx-common/hab.c > @@ -77,7 +77,8 @@ > #define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0 > #define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18 > #define IS_HAB_ENABLED_BIT \ > - (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2) > + (is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \ > + (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)) > > /* > * +------------+ 0x0 (DDR_UIMAGE_START) - > diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h > index ebf32c6..170a9b3 100644 > --- a/arch/arm/include/asm/arch-mx7ulp/clock.h > +++ b/arch/arm/include/asm/arch-mx7ulp/clock.h > @@ -39,4 +39,5 @@ void enable_usboh3_clk(unsigned char enable); > #endif > void init_clk_usdhc(u32 index); > void clock_init(void); > +void hab_caam_clock_enable(unsigned char enable); > #endif > Reviewed-by : Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 17/20] arm: dts: add i.MX7ULP dtsi file 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (15 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 16/20] mx7ulp: Add HAB boot support Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2016-12-27 10:04 ` [U-Boot] [PATCH V2 18/20] mmc: fsl_esdhc: support i.MX7ULP Peng Fan ` (3 subsequent siblings) 20 siblings, 0 replies; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Add i.MX7ULP dtsi file. Add clock and pinfun header files. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: None arch/arm/dts/imx7ulp-pinfunc.h | 882 ++++++++++++++++++++++++++++++ arch/arm/dts/imx7ulp.dtsi | 598 ++++++++++++++++++++ include/dt-bindings/clock/imx7ulp-clock.h | 161 ++++++ 3 files changed, 1641 insertions(+) create mode 100644 arch/arm/dts/imx7ulp-pinfunc.h create mode 100644 arch/arm/dts/imx7ulp.dtsi create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h diff --git a/arch/arm/dts/imx7ulp-pinfunc.h b/arch/arm/dts/imx7ulp-pinfunc.h new file mode 100644 index 0000000..b1b6a71 --- /dev/null +++ b/arch/arm/dts/imx7ulp-pinfunc.h @@ -0,0 +1,882 @@ +/* + * Copyright 2014 - 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_ULP1_PINFUNC_H +#define __DTS_ULP1_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_conf_reg mux2_reg mux_mode mux2_val> + * + * !!! IMPORTANT NOTE !!! + * + * There's common mux_reg & conf_reg register for each pad on ULP1 device, so the first + * two values are defined as same value. Extra non-zero mux2_reg value within the tuple + * means that there's additional mux2 control register that must be configured to + * mux2_val accordingly to fetch desired pin functionality on ULP1 device. + * + */ + +#define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0 +#define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0 +#define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0 +#define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2 +#define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2 +#define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2 +#define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2 +#define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2 +#define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0 +#define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0 +#define ULP1_PAD_PTA1__LPSPI0_PCS2 0x0004 0xd108 0x3 0x1 +#define ULP1_PAD_PTA1__LPUART0_RTS_B 0x0004 0x0000 0x4 0x0 +#define ULP1_PAD_PTA1__LPI2C0_SDA 0x0004 0xd180 0x5 0x1 +#define ULP1_PAD_PTA1__TPM0_CH0 0x0004 0xd138 0x6 0x1 +#define ULP1_PAD_PTA1__I2S0_RX_FS 0x0004 0x01bc 0x7 0x1 +#define ULP1_PAD_PTA2__CMP1_IN2A 0x0008 0x0000 0x0 0x0 +#define ULP1_PAD_PTA2__PTA2 0x0008 0x0000 0x1 0x0 +#define ULP1_PAD_PTA2__LPSPI0_PCS3 0x0008 0xd10c 0x3 0x1 +#define ULP1_PAD_PTA2__LPUART0_TX 0x0008 0xd200 0x4 0x1 +#define ULP1_PAD_PTA2__LPI2C0_HREQ 0x0008 0xd178 0x5 0x1 +#define ULP1_PAD_PTA2__TPM0_CH1 0x0008 0xd13c 0x6 0x1 +#define ULP1_PAD_PTA2__I2S0_RXD0 0x0008 0x01dc 0x7 0x1 +#define ULP1_PAD_PTA3_LLWU0_P1__CMP1_IN2B 0x000c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA3_LLWU0_P1__PTA3 0x000c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA3_LLWU0_P1__CMP0_OUT 0x000c 0x0000 0xb 0x0 +#define ULP1_PAD_PTA3_LLWU0_P1__LLWU0_P1 0x000c 0x0000 0xd 0x0 +#define ULP1_PAD_PTA3_LLWU0_P1__LPUART0_RX 0x000c 0xd1fc 0x4 0x1 +#define ULP1_PAD_PTA3_LLWU0_P1__TPM0_CH2 0x000c 0xd140 0x6 0x1 +#define ULP1_PAD_PTA3_LLWU0_P1__I2S0_RXD1 0x000c 0x01e0 0x7 0x1 +#define ULP1_PAD_PTA4__ADC1_CH2A 0x0010 0x0000 0x0 0x0 +#define ULP1_PAD_PTA4__PTA4 0x0010 0x0000 0x1 0x0 +#define ULP1_PAD_PTA4__LPSPI0_SIN 0x0010 0xd114 0x3 0x1 +#define ULP1_PAD_PTA4__LPUART1_CTS_B 0x0010 0xd204 0x4 0x1 +#define ULP1_PAD_PTA4__LPI2C1_SCL 0x0010 0xd188 0x5 0x1 +#define ULP1_PAD_PTA4__TPM0_CH3 0x0010 0xd144 0x6 0x1 +#define ULP1_PAD_PTA4__I2S0_MCLK 0x0010 0x01b4 0x7 0x1 +#define ULP1_PAD_PTA5__ADC1_CH2B 0x0014 0x0000 0x0 0x0 +#define ULP1_PAD_PTA5__PTA5 0x0014 0x0000 0x1 0x0 +#define ULP1_PAD_PTA5__LPSPI0_SOUT 0x0014 0xd118 0x3 0x1 +#define ULP1_PAD_PTA5__LPUART1_RTS_B 0x0014 0x0000 0x4 0x0 +#define ULP1_PAD_PTA5__LPI2C1_SDA 0x0014 0xd18c 0x5 0x1 +#define ULP1_PAD_PTA5__TPM0_CH4 0x0014 0xd148 0x6 0x1 +#define ULP1_PAD_PTA5__I2S0_TX_BCLK 0x0014 0x01c0 0x7 0x1 +#define ULP1_PAD_PTA6__ADC1_CH3A 0x0018 0x0000 0x0 0x0 +#define ULP1_PAD_PTA6__PTA6 0x0018 0x0000 0x1 0x0 +#define ULP1_PAD_PTA6__LPSPI0_SCK 0x0018 0xd110 0x3 0x1 +#define ULP1_PAD_PTA6__LPUART1_TX 0x0018 0xd20c 0x4 0x1 +#define ULP1_PAD_PTA6__LPI2C1_HREQ 0x0018 0xd184 0x5 0x1 +#define ULP1_PAD_PTA6__TPM0_CH5 0x0018 0xd14c 0x6 0x1 +#define ULP1_PAD_PTA6__I2S0_TX_FS 0x0018 0x01c4 0x7 0x1 +#define ULP1_PAD_PTA7__ADC1_CH3B 0x001c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA7__PTA7 0x001c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA7__LPSPI0_PCS0 0x001c 0xd100 0x3 0x1 +#define ULP1_PAD_PTA7__LPUART1_RX 0x001c 0xd208 0x4 0x1 +#define ULP1_PAD_PTA7__TPM1_CH1 0x001c 0xd154 0x6 0x1 +#define ULP1_PAD_PTA7__I2S0_TXD0 0x001c 0x0000 0x7 0x0 +#define ULP1_PAD_PTA8__ADC1_CH7A 0x0020 0x0000 0x0 0x0 +#define ULP1_PAD_PTA8__PTA8 0x0020 0x0000 0x1 0x0 +#define ULP1_PAD_PTA8__LPSPI1_PCS1 0x0020 0xd120 0x3 0x1 +#define ULP1_PAD_PTA8__LPUART2_CTS_B 0x0020 0xd210 0x4 0x1 +#define ULP1_PAD_PTA8__LPI2C2_SCL 0x0020 0xd194 0x5 0x1 +#define ULP1_PAD_PTA8__TPM1_CLKIN 0x0020 0xd1ac 0x6 0x1 +#define ULP1_PAD_PTA8__I2S0_TXD1 0x0020 0x0000 0x7 0x0 +#define ULP1_PAD_PTA9__ADC1_CH7B 0x0024 0x0000 0x0 0x0 +#define ULP1_PAD_PTA9__PTA9 0x0024 0x0000 0x1 0x0 +#define ULP1_PAD_PTA9__NMI0_B 0x0024 0x0000 0xb 0x0 +#define ULP1_PAD_PTA9__LPSPI1_PCS2 0x0024 0xd124 0x3 0x1 +#define ULP1_PAD_PTA9__LPUART2_RTS_B 0x0024 0x0000 0x4 0x0 +#define ULP1_PAD_PTA9__LPI2C2_SDA 0x0024 0xd198 0x5 0x1 +#define ULP1_PAD_PTA9__TPM1_CH0 0x0024 0xd150 0x6 0x1 +#define ULP1_PAD_PTA10__ADC1_CH6A 0x0028 0x0000 0x0 0x0 +#define ULP1_PAD_PTA10__PTA10 0x0028 0x0000 0x1 0x0 +#define ULP1_PAD_PTA10__LPSPI1_PCS3 0x0028 0xd128 0x3 0x1 +#define ULP1_PAD_PTA10__LPUART2_TX 0x0028 0xd218 0x4 0x1 +#define ULP1_PAD_PTA10__LPI2C2_HREQ 0x0028 0xd190 0x5 0x1 +#define ULP1_PAD_PTA10__TPM2_CLKIN 0x0028 0xd1f4 0x6 0x1 +#define ULP1_PAD_PTA10__I2S0_RX_BCLK 0x0028 0x01b8 0x7 0x1 +#define ULP1_PAD_PTA11__ADC1_CH6B 0x002c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA11__PTA11 0x002c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA11__LPUART2_RX 0x002c 0xd214 0x4 0x1 +#define ULP1_PAD_PTA11__TPM2_CH0 0x002c 0xd158 0x6 0x1 +#define ULP1_PAD_PTA11__I2S0_RX_FS 0x002c 0x01bc 0x7 0x2 +#define ULP1_PAD_PTA12__ADC1_CH5A 0x0030 0x0000 0x0 0x0 +#define ULP1_PAD_PTA12__PTA12 0x0030 0x0000 0x1 0x0 +#define ULP1_PAD_PTA12__LPSPI1_SIN 0x0030 0xd130 0x3 0x1 +#define ULP1_PAD_PTA12__LPUART3_CTS_B 0x0030 0xd21c 0x4 0x1 +#define ULP1_PAD_PTA12__LPI2C3_SCL 0x0030 0xd1a0 0x5 0x1 +#define ULP1_PAD_PTA12__TPM2_CH1 0x0030 0xd15c 0x6 0x1 +#define ULP1_PAD_PTA12__I2S0_RXD0 0x0030 0x01dc 0x7 0x2 +#define ULP1_PAD_PTA13_LLWU0_P2__ADC1_CH5B 0x0034 0x0000 0x0 0x0 +#define ULP1_PAD_PTA13_LLWU0_P2__PTA13 0x0034 0x0000 0x1 0x0 +#define ULP1_PAD_PTA13_LLWU0_P2__CMP0_OUT 0x0034 0x0000 0xb 0x0 +#define ULP1_PAD_PTA13_LLWU0_P2__LLWU0_P2 0x0034 0x0000 0xd 0x0 +#define ULP1_PAD_PTA13_LLWU0_P2__LPSPI1_SOUT 0x0034 0xd134 0x3 0x2 +#define ULP1_PAD_PTA13_LLWU0_P2__LPUART3_RTS_B 0x0034 0x0000 0x4 0x0 +#define ULP1_PAD_PTA13_LLWU0_P2__LPI2C3_SDA 0x0034 0xd1a4 0x5 0x2 +#define ULP1_PAD_PTA13_LLWU0_P2__TPM3_CLKIN 0x0034 0xd1b0 0x6 0x1 +#define ULP1_PAD_PTA13_LLWU0_P2__I2S0_RXD1 0x0034 0x01e0 0x7 0x2 +#define ULP1_PAD_PTA14_LLWU0_P3__ADC1_CH4A 0x0038 0x0000 0x0 0x0 +#define ULP1_PAD_PTA14_LLWU0_P3__PTA14 0x0038 0x0000 0x1 0x0 +#define ULP1_PAD_PTA14_LLWU0_P3__LLWU0_P3 0x0038 0x0000 0xd 0x0 +#define ULP1_PAD_PTA14_LLWU0_P3__LPSPI1_SCK 0x0038 0xd12c 0x3 0x2 +#define ULP1_PAD_PTA14_LLWU0_P3__LPUART3_TX 0x0038 0xd224 0x4 0x2 +#define ULP1_PAD_PTA14_LLWU0_P3__LPI2C3_HREQ 0x0038 0xd19c 0x5 0x2 +#define ULP1_PAD_PTA14_LLWU0_P3__TPM3_CH0 0x0038 0xd160 0x6 0x1 +#define ULP1_PAD_PTA14_LLWU0_P3__I2S0_MCLK 0x0038 0x01b4 0x7 0x2 +#define ULP1_PAD_PTA15__ADC1_CH4B 0x003c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA15__PTA15 0x003c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA15__LPSPI1_PCS0 0x003c 0xd11c 0x3 0x1 +#define ULP1_PAD_PTA15__LPUART3_RX 0x003c 0xd220 0x4 0x1 +#define ULP1_PAD_PTA15__TPM3_CH1 0x003c 0xd164 0x6 0x1 +#define ULP1_PAD_PTA15__I2S0_TX_BCLK 0x003c 0x01c0 0x7 0x2 +#define ULP1_PAD_PTA16__CMP1_IN0A 0x0040 0x0000 0x0 0x0 +#define ULP1_PAD_PTA16__PTA16 0x0040 0x0000 0x1 0x0 +#define ULP1_PAD_PTA16__FXIO0_D0 0x0040 0x0000 0x2 0x0 +#define ULP1_PAD_PTA16__LPSPI0_PCS1 0x0040 0xd104 0x3 0x1 +#define ULP1_PAD_PTA16__LPUART0_CTS_B 0x0040 0xd1f8 0x4 0x1 +#define ULP1_PAD_PTA16__LPI2C0_SCL 0x0040 0xd17c 0x5 0x1 +#define ULP1_PAD_PTA16__TPM3_CH2 0x0040 0xd168 0x6 0x1 +#define ULP1_PAD_PTA16__I2S0_TX_FS 0x0040 0x01c4 0x7 0x2 +#define ULP1_PAD_PTA17__CMP1_IN0B 0x0044 0x0000 0x0 0x0 +#define ULP1_PAD_PTA17__PTA17 0x0044 0x0000 0x1 0x0 +#define ULP1_PAD_PTA17__FXIO0_D1 0x0044 0x0000 0x2 0x0 +#define ULP1_PAD_PTA17__LPSPI0_PCS2 0x0044 0xd108 0x3 0x2 +#define ULP1_PAD_PTA17__LPUART0_RTS_B 0x0044 0x0000 0x4 0x0 +#define ULP1_PAD_PTA17__LPI2C0_SDA 0x0044 0xd180 0x5 0x2 +#define ULP1_PAD_PTA17__TPM3_CH3 0x0044 0xd16c 0x6 0x1 +#define ULP1_PAD_PTA17__I2S0_TXD0 0x0044 0x0000 0x7 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__CMP1_IN1A 0x0048 0x0000 0x0 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__PTA18 0x0048 0x0000 0x1 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__NMI1_B 0x0048 0x0000 0xb 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__LLWU0_P4 0x0048 0x0000 0xd 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__FXIO0_D2 0x0048 0x0000 0x2 0x0 +#define ULP1_PAD_PTA18_LLWU0_P4__LPSPI0_PCS3 0x0048 0xd10c 0x3 0x2 +#define ULP1_PAD_PTA18_LLWU0_P4__LPUART0_TX 0x0048 0xd200 0x4 0x2 +#define ULP1_PAD_PTA18_LLWU0_P4__LPI2C0_HREQ 0x0048 0xd178 0x5 0x2 +#define ULP1_PAD_PTA18_LLWU0_P4__TPM3_CH4 0x0048 0xd170 0x6 0x1 +#define ULP1_PAD_PTA18_LLWU0_P4__I2S0_TXD1 0x0048 0x0000 0x7 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__CMP1_IN1B 0x004c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__PTA19 0x004c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__LPTMR0_ALT3 0x004c 0x0000 0xb 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__LLWU0_P5 0x004c 0x0000 0xd 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__FXIO0_D3 0x004c 0x0000 0x2 0x0 +#define ULP1_PAD_PTA19_LLWU0_P5__LPUART0_RX 0x004c 0xd1fc 0x4 0x2 +#define ULP1_PAD_PTA19_LLWU0_P5__TPM3_CH5 0x004c 0xd174 0x6 0x1 +#define ULP1_PAD_PTA19_LLWU0_P5__I2S1_RX_BCLK 0x004c 0xd1cc 0x7 0x1 +#define ULP1_PAD_PTA20__ADC0_CH7A 0x0050 0x0000 0x0 0x0 +#define ULP1_PAD_PTA20__PTA20 0x0050 0x0000 0x1 0x0 +#define ULP1_PAD_PTA20__FXIO0_D4 0x0050 0x0000 0x2 0x0 +#define ULP1_PAD_PTA20__LPSPI0_SIN 0x0050 0xd114 0x3 0x2 +#define ULP1_PAD_PTA20__LPUART1_CTS_B 0x0050 0xd204 0x4 0x2 +#define ULP1_PAD_PTA20__LPI2C1_SCL 0x0050 0xd188 0x5 0x2 +#define ULP1_PAD_PTA20__TPM0_CLKIN 0x0050 0xd1a8 0x6 0x1 +#define ULP1_PAD_PTA20__I2S1_RX_FS 0x0050 0xd1d0 0x7 0x1 +#define ULP1_PAD_PTA21__ADC0_CH7B 0x0054 0x0000 0x0 0x0 +#define ULP1_PAD_PTA21__PTA21 0x0054 0x0000 0x1 0x0 +#define ULP1_PAD_PTA21__FXIO0_D5 0x0054 0x0000 0x2 0x0 +#define ULP1_PAD_PTA21__LPSPI0_SOUT 0x0054 0xd118 0x3 0x2 +#define ULP1_PAD_PTA21__LPUART1_RTS_B 0x0054 0x0000 0x4 0x0 +#define ULP1_PAD_PTA21__LPI2C1_SDA 0x0054 0xd18c 0x5 0x2 +#define ULP1_PAD_PTA21__TPM0_CH0 0x0054 0xd138 0x6 0x2 +#define ULP1_PAD_PTA21__I2S1_RXD0 0x0054 0xd1e4 0x7 0x1 +#define ULP1_PAD_PTA22__ADC0_CH6A 0x0058 0x0000 0x0 0x0 +#define ULP1_PAD_PTA22__PTA22 0x0058 0x0000 0x1 0x0 +#define ULP1_PAD_PTA22__LPTMR0_ALT2 0x0058 0x0000 0xb 0x0 +#define ULP1_PAD_PTA22__EWM_OUT_B 0x0058 0x0000 0xc 0x0 +#define ULP1_PAD_PTA22__FXIO0_D6 0x0058 0x0000 0x2 0x0 +#define ULP1_PAD_PTA22__LPSPI0_SCK 0x0058 0xd110 0x3 0x2 +#define ULP1_PAD_PTA22__LPUART1_TX 0x0058 0xd20c 0x4 0x2 +#define ULP1_PAD_PTA22__LPI2C1_HREQ 0x0058 0xd184 0x5 0x2 +#define ULP1_PAD_PTA22__TPM0_CH1 0x0058 0xd13c 0x6 0x2 +#define ULP1_PAD_PTA22__I2S1_RXD1 0x0058 0xd1e8 0x7 0x1 +#define ULP1_PAD_PTA23_LLWU0_P6__ADC0_CH6B 0x005c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA23_LLWU0_P6__PTA23 0x005c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA23_LLWU0_P6__LLWU0_P6 0x005c 0x0000 0xd 0x0 +#define ULP1_PAD_PTA23_LLWU0_P6__FXIO0_D7 0x005c 0x0000 0x2 0x0 +#define ULP1_PAD_PTA23_LLWU0_P6__LPSPI0_PCS0 0x005c 0xd100 0x3 0x2 +#define ULP1_PAD_PTA23_LLWU0_P6__LPUART1_RX 0x005c 0xd208 0x4 0x2 +#define ULP1_PAD_PTA23_LLWU0_P6__TPM0_CH2 0x005c 0xd140 0x6 0x2 +#define ULP1_PAD_PTA23_LLWU0_P6__I2S1_MCLK 0x005c 0xd1c8 0x7 0x1 +#define ULP1_PAD_PTA24__ADC0_CH5A 0x0060 0x0000 0x0 0x0 +#define ULP1_PAD_PTA24__PTA24 0x0060 0x0000 0x1 0x0 +#define ULP1_PAD_PTA24__FXIO0_D8 0x0060 0x0000 0x2 0x0 +#define ULP1_PAD_PTA24__LPSPI1_PCS1 0x0060 0xd120 0x3 0x2 +#define ULP1_PAD_PTA24__LPUART2_CTS_B 0x0060 0xd210 0x4 0x2 +#define ULP1_PAD_PTA24__LPI2C2_SCL 0x0060 0xd194 0x5 0x2 +#define ULP1_PAD_PTA24__TPM0_CH3 0x0060 0xd144 0x6 0x2 +#define ULP1_PAD_PTA24__I2S1_TX_BCLK 0x0060 0xd1d4 0x7 0x1 +#define ULP1_PAD_PTA25__ADC0_CH5B 0x0064 0x0000 0x0 0x0 +#define ULP1_PAD_PTA25__PTA25 0x0064 0x0000 0x1 0x0 +#define ULP1_PAD_PTA25__FXIO0_D9 0x0064 0x0000 0x2 0x0 +#define ULP1_PAD_PTA25__LPSPI1_PCS2 0x0064 0xd124 0x3 0x2 +#define ULP1_PAD_PTA25__LPUART2_RTS_B 0x0064 0x0000 0x4 0x0 +#define ULP1_PAD_PTA25__LPI2C2_SDA 0x0064 0xd198 0x5 0x2 +#define ULP1_PAD_PTA25__TPM0_CH4 0x0064 0xd148 0x6 0x2 +#define ULP1_PAD_PTA25__I2S1_TX_FS 0x0064 0xd1d8 0x7 0x1 +#define ULP1_PAD_PTA26__PTA26 0x0068 0x0000 0x1 0x0 +#define ULP1_PAD_PTA26__JTAG_TMS_SWD_DIO 0x0068 0x0000 0xa 0x0 +#define ULP1_PAD_PTA26__FXIO0_D10 0x0068 0x0000 0x2 0x0 +#define ULP1_PAD_PTA26__LPSPI1_PCS3 0x0068 0xd128 0x3 0x2 +#define ULP1_PAD_PTA26__LPUART2_TX 0x0068 0xd218 0x4 0x2 +#define ULP1_PAD_PTA26__LPI2C2_HREQ 0x0068 0xd190 0x5 0x2 +#define ULP1_PAD_PTA26__TPM0_CH5 0x0068 0xd14c 0x6 0x2 +#define ULP1_PAD_PTA26__I2S1_RXD2 0x0068 0xd1ec 0x7 0x1 +#define ULP1_PAD_PTA27__PTA27 0x006c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA27__JTAG_TDO 0x006c 0x0000 0xa 0x0 +#define ULP1_PAD_PTA27__FXIO0_D11 0x006c 0x0000 0x2 0x0 +#define ULP1_PAD_PTA27__LPUART2_RX 0x006c 0xd214 0x4 0x2 +#define ULP1_PAD_PTA27__TPM1_CH1 0x006c 0xd154 0x6 0x2 +#define ULP1_PAD_PTA27__I2S1_RXD3 0x006c 0xd1f0 0x7 0x1 +#define ULP1_PAD_PTA28__PTA28 0x0070 0x0000 0x1 0x0 +#define ULP1_PAD_PTA28__JTAG_TDI 0x0070 0x0000 0xa 0x0 +#define ULP1_PAD_PTA28__FXIO0_D12 0x0070 0x0000 0x2 0x0 +#define ULP1_PAD_PTA28__LPSPI1_SIN 0x0070 0xd130 0x3 0x2 +#define ULP1_PAD_PTA28__LPUART3_CTS_B 0x0070 0xd21c 0x4 0x2 +#define ULP1_PAD_PTA28__LPI2C3_SCL 0x0070 0xd1a0 0x5 0x2 +#define ULP1_PAD_PTA28__TPM1_CLKIN 0x0070 0xd1ac 0x6 0x2 +#define ULP1_PAD_PTA28__I2S1_TXD2 0x0070 0x0000 0x7 0x0 +#define ULP1_PAD_PTA29__PTA29 0x0074 0x0000 0x1 0x0 +#define ULP1_PAD_PTA29__JTAG_TCLK_SWD_CLK 0x0074 0x0000 0xa 0x0 +#define ULP1_PAD_PTA29__FXIO0_D13 0x0074 0x0000 0x2 0x0 +#define ULP1_PAD_PTA29__LPSPI1_SOUT 0x0074 0xd134 0x3 0x1 +#define ULP1_PAD_PTA29__LPUART3_RTS_B 0x0074 0x0000 0x4 0x0 +#define ULP1_PAD_PTA29__LPI2C3_SDA 0x0074 0xd1a4 0x5 0x1 +#define ULP1_PAD_PTA29__TPM1_CH0 0x0074 0xd150 0x6 0x2 +#define ULP1_PAD_PTA29__I2S1_TXD3 0x0074 0x0000 0x7 0x0 +#define ULP1_PAD_PTA30__ADC0_CH4A 0x0078 0x0000 0x0 0x0 +#define ULP1_PAD_PTA30__PTA30 0x0078 0x0000 0x1 0x0 +#define ULP1_PAD_PTA30__JTAG_TRST_B 0x0078 0x0000 0xa 0x0 +#define ULP1_PAD_PTA30__FXIO0_D14 0x0078 0x0000 0x2 0x0 +#define ULP1_PAD_PTA30__LPSPI1_SCK 0x0078 0xd12c 0x3 0x1 +#define ULP1_PAD_PTA30__LPUART3_TX 0x0078 0xd224 0x4 0x1 +#define ULP1_PAD_PTA30__LPI2C3_HREQ 0x0078 0xd19c 0x5 0x1 +#define ULP1_PAD_PTA30__TPM2_CLKIN 0x0078 0xd1f4 0x6 0x2 +#define ULP1_PAD_PTA30__I2S1_TXD0 0x0078 0x0000 0x7 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__ADC0_CH4B 0x007c 0x0000 0x0 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__PTA31 0x007c 0x0000 0x1 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__LPTMR0_ALT1 0x007c 0x0000 0xb 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__EWM_IN 0x007c 0xd228 0xc 0x1 +#define ULP1_PAD_PTA31_LLWU0_P7__LLWU0_P7 0x007c 0x0000 0xd 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__FXIO0_D15 0x007c 0x0000 0x2 0x0 +#define ULP1_PAD_PTA31_LLWU0_P7__LPSPI1_PCS0 0x007c 0xd11c 0x3 0x2 +#define ULP1_PAD_PTA31_LLWU0_P7__LPUART3_RX 0x007c 0xd220 0x4 0x2 +#define ULP1_PAD_PTA31_LLWU0_P7__TPM2_CH0 0x007c 0xd158 0x6 0x2 +#define ULP1_PAD_PTA31_LLWU0_P7__I2S1_TXD1 0x007c 0x0000 0x7 0x0 +#define ULP1_PAD_PTB0__ADC0_CH0A 0x0080 0x0000 0x0 0x0 +#define ULP1_PAD_PTB0__PTB0 0x0080 0x0000 0x1 0x0 +#define ULP1_PAD_PTB0__CMP1_OUT 0x0080 0x0000 0xb 0x0 +#define ULP1_PAD_PTB0__EWM_OUT_B 0x0080 0x0000 0xc 0x0 +#define ULP1_PAD_PTB0__FXIO0_D16 0x0080 0x0000 0x2 0x0 +#define ULP1_PAD_PTB0__LPSPI0_SIN 0x0080 0xd114 0x3 0x3 +#define ULP1_PAD_PTB0__LPUART0_TX 0x0080 0xd200 0x4 0x3 +#define ULP1_PAD_PTB0__TPM2_CH1 0x0080 0xd15c 0x6 0x2 +#define ULP1_PAD_PTB0__CLKOUT 0x0080 0x0000 0x9 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__ADC0_CH0B 0x0084 0x0000 0x0 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__PTB1 0x0084 0x0000 0x1 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__RTC_CLKOUT 0x0084 0x0000 0xb 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__EWM_IN 0x0084 0xd228 0xc 0x2 +#define ULP1_PAD_PTB1_LLWU0_P8__LLWU0_P8 0x0084 0x0000 0xd 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__FXIO0_D17 0x0084 0x0000 0x2 0x0 +#define ULP1_PAD_PTB1_LLWU0_P8__LPSPI0_SOUT 0x0084 0xd118 0x3 0x3 +#define ULP1_PAD_PTB1_LLWU0_P8__LPUART0_RX 0x0084 0xd1fc 0x4 0x3 +#define ULP1_PAD_PTB1_LLWU0_P8__TPM3_CLKIN 0x0084 0xd1b0 0x6 0x3 +#define ULP1_PAD_PTB1_LLWU0_P8__I2S1_TX_BCLK 0x0084 0xd1d4 0x7 0x2 +#define ULP1_PAD_PTB2__ADC0_CH1A 0x0088 0x0000 0x0 0x0 +#define ULP1_PAD_PTB2__PTB2 0x0088 0x0000 0x1 0x0 +#define ULP1_PAD_PTB2__TRACE_CLKOUT 0x0088 0x0000 0xa 0x0 +#define ULP1_PAD_PTB2__FXIO0_D18 0x0088 0x0000 0x2 0x0 +#define ULP1_PAD_PTB2__LPSPI0_SCK 0x0088 0xd110 0x3 0x3 +#define ULP1_PAD_PTB2__LPUART1_TX 0x0088 0xd20c 0x4 0x3 +#define ULP1_PAD_PTB2__TPM3_CH0 0x0088 0xd160 0x6 0x2 +#define ULP1_PAD_PTB2__I2S1_TX_FS 0x0088 0xd1d8 0x7 0x2 +#define ULP1_PAD_PTB3_LLWU0_P9__ADC0_CH1B 0x008c 0x0000 0x0 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__PTB3 0x008c 0x0000 0x1 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__TRACE_D0 0x008c 0x0000 0xa 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__LPTMR1_ALT2 0x008c 0x0000 0xb 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__LLWU0_P9 0x008c 0x0000 0xd 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__FXIO0_D19 0x008c 0x0000 0x2 0x0 +#define ULP1_PAD_PTB3_LLWU0_P9__LPSPI0_PCS0 0x008c 0xd100 0x3 0x3 +#define ULP1_PAD_PTB3_LLWU0_P9__LPUART1_RX 0x008c 0xd208 0x4 0x3 +#define ULP1_PAD_PTB3_LLWU0_P9__TPM3_CH1 0x008c 0xd164 0x6 0x2 +#define ULP1_PAD_PTB3_LLWU0_P9__I2S1_TXD0 0x008c 0x0000 0x7 0x0 +#define ULP1_PAD_PTB4__PTB4 0x0090 0x0000 0x1 0x0 +#define ULP1_PAD_PTB4__TRACE_D1 0x0090 0x0000 0xa 0x0 +#define ULP1_PAD_PTB4__BOOTCFG0 0x0090 0x0000 0xd 0x0 +#define ULP1_PAD_PTB4__FXIO0_D20 0x0090 0x0000 0x2 0x0 +#define ULP1_PAD_PTB4__LPSPI0_PCS1 0x0090 0xd104 0x3 0x3 +#define ULP1_PAD_PTB4__LPUART2_TX 0x0090 0xd218 0x4 0x3 +#define ULP1_PAD_PTB4__LPI2C0_HREQ 0x0090 0xd178 0x5 0x3 +#define ULP1_PAD_PTB4__TPM3_CH2 0x0090 0xd168 0x6 0x2 +#define ULP1_PAD_PTB4__I2S1_TXD1 0x0090 0x0000 0x7 0x0 +#define ULP1_PAD_PTB5__PTB5 0x0094 0x0000 0x1 0x0 +#define ULP1_PAD_PTB5__TRACE_D2 0x0094 0x0000 0xa 0x0 +#define ULP1_PAD_PTB5__BOOTCFG1 0x0094 0x0000 0xd 0x0 +#define ULP1_PAD_PTB5__FXIO0_D21 0x0094 0x0000 0x2 0x0 +#define ULP1_PAD_PTB5__LPSPI0_PCS2 0x0094 0xd108 0x3 0x3 +#define ULP1_PAD_PTB5__LPUART2_RX 0x0094 0xd214 0x4 0x3 +#define ULP1_PAD_PTB5__LPI2C1_HREQ 0x0094 0xd184 0x5 0x3 +#define ULP1_PAD_PTB5__TPM3_CH3 0x0094 0xd16c 0x6 0x2 +#define ULP1_PAD_PTB5__I2S1_TXD2 0x0094 0x0000 0x7 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__PTB6 0x0098 0x0000 0x1 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__TRACE_D3 0x0098 0x0000 0xa 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__LPTMR1_ALT3 0x0098 0x0000 0xb 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__LLWU0_P10 0x0098 0x0000 0xd 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__FXIO0_D22 0x0098 0x0000 0x2 0x0 +#define ULP1_PAD_PTB6_LLWU0_P10__LPSPI0_PCS3 0x0098 0xd10c 0x3 0x3 +#define ULP1_PAD_PTB6_LLWU0_P10__LPUART3_TX 0x0098 0xd224 0x4 0x3 +#define ULP1_PAD_PTB6_LLWU0_P10__LPI2C0_SCL 0x0098 0xd17c 0x5 0x3 +#define ULP1_PAD_PTB6_LLWU0_P10__TPM3_CH4 0x0098 0xd170 0x6 0x2 +#define ULP1_PAD_PTB6_LLWU0_P10__I2S1_TXD3 0x0098 0x0000 0x7 0x0 +#define ULP1_PAD_PTB7_LLWU0_P11__PTB7 0x009c 0x0000 0x1 0x0 +#define ULP1_PAD_PTB7_LLWU0_P11__CMP1_OUT 0x009c 0x0000 0xb 0x0 +#define ULP1_PAD_PTB7_LLWU0_P11__LLWU0_P11 0x009c 0x0000 0xd 0x0 +#define ULP1_PAD_PTB7_LLWU0_P11__FXIO0_D23 0x009c 0x0000 0x2 0x0 +#define ULP1_PAD_PTB7_LLWU0_P11__LPSPI1_SIN 0x009c 0xd130 0x3 0x3 +#define ULP1_PAD_PTB7_LLWU0_P11__LPUART3_RX 0x009c 0xd220 0x4 0x3 +#define ULP1_PAD_PTB7_LLWU0_P11__LPI2C0_SDA 0x009c 0xd180 0x5 0x3 +#define ULP1_PAD_PTB7_LLWU0_P11__TPM3_CH5 0x009c 0xd174 0x6 0x2 +#define ULP1_PAD_PTB7_LLWU0_P11__I2S1_MCLK 0x009c 0xd1c8 0x7 0x2 +#define ULP1_PAD_PTB7_LLWU0_P11__QSPIA_SS1_B 0x009c 0x0000 0x8 0x0 +#define ULP1_PAD_PTB8__CMP0_IN0A 0x00a0 0x0000 0x0 0x0 +#define ULP1_PAD_PTB8__PTB8 0x00a0 0x0000 0x1 0x0 +#define ULP1_PAD_PTB8__RTC_CLKOUT 0x00a0 0x0000 0xb 0x0 +#define ULP1_PAD_PTB8__FXIO0_D24 0x00a0 0x0000 0x2 0x0 +#define ULP1_PAD_PTB8__LPSPI1_SOUT 0x00a0 0xd134 0x3 0x3 +#define ULP1_PAD_PTB8__LPI2C1_SCL 0x00a0 0xd188 0x5 0x3 +#define ULP1_PAD_PTB8__TPM0_CLKIN 0x00a0 0xd1a8 0x6 0x3 +#define ULP1_PAD_PTB8__I2S1_RX_BCLK 0x00a0 0xd1cc 0x7 0x2 +#define ULP1_PAD_PTB8__QSPIA_SS0_B 0x00a0 0x0000 0x8 0x0 +#define ULP1_PAD_PTB9_LLWU0_P12__CMP0_IN0B 0x00a4 0x0000 0x0 0x0 +#define ULP1_PAD_PTB9_LLWU0_P12__PTB9 0x00a4 0x0000 0x1 0x0 +#define ULP1_PAD_PTB9_LLWU0_P12__LLWU0_P12 0x00a4 0x0000 0xd 0x0 +#define ULP1_PAD_PTB9_LLWU0_P12__FXIO0_D25 0x00a4 0x0000 0x2 0x0 +#define ULP1_PAD_PTB9_LLWU0_P12__LPSPI1_SCK 0x00a4 0xd12c 0x3 0x3 +#define ULP1_PAD_PTB9_LLWU0_P12__LPI2C1_SDA 0x00a4 0xd18c 0x5 0x3 +#define ULP1_PAD_PTB9_LLWU0_P12__TPM0_CH0 0x00a4 0xd138 0x6 0x3 +#define ULP1_PAD_PTB9_LLWU0_P12__I2S1_RX_FS 0x00a4 0xd1d0 0x7 0x2 +#define ULP1_PAD_PTB9_LLWU0_P12__QSPIA_DQS 0x00a4 0x0000 0x8 0x0 +#define ULP1_PAD_PTB10__CMP0_IN1A 0x00a8 0x0000 0x0 0x0 +#define ULP1_PAD_PTB10__PTB10 0x00a8 0x0000 0x1 0x0 +#define ULP1_PAD_PTB10__TRACE_D4 0x00a8 0x0000 0xa 0x0 +#define ULP1_PAD_PTB10__FXIO0_D26 0x00a8 0x0000 0x2 0x0 +#define ULP1_PAD_PTB10__LPSPI1_PCS0 0x00a8 0xd11c 0x3 0x3 +#define ULP1_PAD_PTB10__LPI2C2_SCL 0x00a8 0xd194 0x5 0x3 +#define ULP1_PAD_PTB10__TPM0_CH1 0x00a8 0xd13c 0x6 0x3 +#define ULP1_PAD_PTB10__I2S1_RXD0 0x00a8 0xd1e4 0x7 0x2 +#define ULP1_PAD_PTB10__QSPIA_DATA7 0x00a8 0x0000 0x8 0x0 +#define ULP1_PAD_PTB11__CMP0_IN1B 0x00ac 0x0000 0x0 0x0 +#define ULP1_PAD_PTB11__PTB11 0x00ac 0x0000 0x1 0x0 +#define ULP1_PAD_PTB11__TRACE_D5 0x00ac 0x0000 0xa 0x0 +#define ULP1_PAD_PTB11__FXIO0_D27 0x00ac 0x0000 0x2 0x0 +#define ULP1_PAD_PTB11__LPSPI1_PCS1 0x00ac 0xd120 0x3 0x3 +#define ULP1_PAD_PTB11__LPI2C2_SDA 0x00ac 0xd198 0x5 0x3 +#define ULP1_PAD_PTB11__TPM1_CLKIN 0x00ac 0xd1ac 0x6 0x3 +#define ULP1_PAD_PTB11__I2S1_RXD1 0x00ac 0xd1e8 0x7 0x2 +#define ULP1_PAD_PTB11__QSPIA_DATA6 0x00ac 0x0000 0x8 0x0 +#define ULP1_PAD_PTB12__ADC1_CH0A 0x00b0 0x0000 0x0 0x0 +#define ULP1_PAD_PTB12__PTB12 0x00b0 0x0000 0x1 0x0 +#define ULP1_PAD_PTB12__TRACE_D6 0x00b0 0x0000 0xa 0x0 +#define ULP1_PAD_PTB12__FXIO0_D28 0x00b0 0x0000 0x2 0x0 +#define ULP1_PAD_PTB12__LPSPI1_PCS2 0x00b0 0xd124 0x3 0x3 +#define ULP1_PAD_PTB12__LPI2C3_SCL 0x00b0 0xd1a0 0x5 0x3 +#define ULP1_PAD_PTB12__TPM1_CH0 0x00b0 0xd150 0x6 0x3 +#define ULP1_PAD_PTB12__I2S1_RXD2 0x00b0 0xd1ec 0x7 0x2 +#define ULP1_PAD_PTB12__QSPIA_DATA5 0x00b0 0x0000 0x8 0x0 +#define ULP1_PAD_PTB13__ADC1_CH0B 0x00b4 0x0000 0x0 0x0 +#define ULP1_PAD_PTB13__PTB13 0x00b4 0x0000 0x1 0x0 +#define ULP1_PAD_PTB13__TRACE_D7 0x00b4 0x0000 0xa 0x0 +#define ULP1_PAD_PTB13__FXIO0_D29 0x00b4 0x0000 0x2 0x0 +#define ULP1_PAD_PTB13__LPSPI1_PCS3 0x00b4 0xd128 0x3 0x3 +#define ULP1_PAD_PTB13__LPI2C3_SDA 0x00b4 0xd1a4 0x5 0x3 +#define ULP1_PAD_PTB13__TPM1_CH1 0x00b4 0xd154 0x6 0x3 +#define ULP1_PAD_PTB13__I2S1_RXD3 0x00b4 0xd1f0 0x7 0x2 +#define ULP1_PAD_PTB13__QSPIA_DATA4 0x00b4 0x0000 0x8 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__ADC1_CH1A 0x00b8 0x0000 0x0 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__PTB14 0x00b8 0x0000 0x1 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__LLWU0_P13 0x00b8 0x0000 0xd 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__FXIO0_D30 0x00b8 0x0000 0x2 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__LPI2C2_HREQ 0x00b8 0xd190 0x5 0x3 +#define ULP1_PAD_PTB14_LLWU0_P13__TPM2_CLKIN 0x00b8 0xd1f4 0x6 0x3 +#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SS0_B 0x00b8 0x0000 0x8 0x0 +#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SCLK_B 0x00b8 0x0000 0x9 0x0 +#define ULP1_PAD_PTB15__ADC1_CH1B 0x00bc 0x0000 0x0 0x0 +#define ULP1_PAD_PTB15__PTB15 0x00bc 0x0000 0x1 0x0 +#define ULP1_PAD_PTB15__FXIO0_D31 0x00bc 0x0000 0x2 0x0 +#define ULP1_PAD_PTB15__LPI2C3_HREQ 0x00bc 0xd19c 0x5 0x3 +#define ULP1_PAD_PTB15__TPM2_CH0 0x00bc 0xd158 0x6 0x3 +#define ULP1_PAD_PTB15__QSPIA_SCLK 0x00bc 0x0000 0x8 0x0 +#define ULP1_PAD_PTB16_LLWU0_P14__ADC0_CH2A 0x00c0 0x0000 0x0 0x0 +#define ULP1_PAD_PTB16_LLWU0_P14__PTB16 0x00c0 0x0000 0x1 0x0 +#define ULP1_PAD_PTB16_LLWU0_P14__LLWU0_P14 0x00c0 0x0000 0xd 0x0 +#define ULP1_PAD_PTB16_LLWU0_P14__TPM2_CH1 0x00c0 0xd15c 0x6 0x3 +#define ULP1_PAD_PTB16_LLWU0_P14__QSPIA_DATA3 0x00c0 0x0000 0x8 0x0 +#define ULP1_PAD_PTB17__ADC0_CH2B 0x00c4 0x0000 0x0 0x0 +#define ULP1_PAD_PTB17__PTB17 0x00c4 0x0000 0x1 0x0 +#define ULP1_PAD_PTB17__TPM3_CLKIN 0x00c4 0xd1b0 0x6 0x2 +#define ULP1_PAD_PTB17__QSPIA_DATA2 0x00c4 0x0000 0x8 0x0 +#define ULP1_PAD_PTB18__ADC0_CH3A 0x00c8 0x0000 0x0 0x0 +#define ULP1_PAD_PTB18__PTB18 0x00c8 0x0000 0x1 0x0 +#define ULP1_PAD_PTB18__TPM3_CH0 0x00c8 0xd160 0x6 0x3 +#define ULP1_PAD_PTB18__QSPIA_DATA1 0x00c8 0x0000 0x8 0x0 +#define ULP1_PAD_PTB19_LLWU0_P15__ADC0_CH3B 0x00cc 0x0000 0x0 0x0 +#define ULP1_PAD_PTB19_LLWU0_P15__PTB19 0x00cc 0x0000 0x1 0x0 +#define ULP1_PAD_PTB19_LLWU0_P15__USB0_ID 0x00cc 0x0000 0xa 0x0 +#define ULP1_PAD_PTB19_LLWU0_P15__LLWU0_P15 0x00cc 0x0000 0xd 0x0 +#define ULP1_PAD_PTB19_LLWU0_P15__TPM3_CH1 0x00cc 0xd164 0x6 0x3 +#define ULP1_PAD_PTB19_LLWU0_P15__QSPIA_DATA0 0x00cc 0x0000 0x8 0x0 +#define ULP1_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 +#define ULP1_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 +#define ULP1_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 +#define ULP1_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 +#define ULP1_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 +#define ULP1_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 +#define ULP1_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 +#define ULP1_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 +#define ULP1_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 +#define ULP1_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1 +#define ULP1_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1 +#define ULP1_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0 +#define ULP1_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0 +#define ULP1_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 +#define ULP1_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1 +#define ULP1_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1 +#define ULP1_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1 +#define ULP1_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0 +#define ULP1_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0 +#define ULP1_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0 +#define ULP1_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1 +#define ULP1_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1 +#define ULP1_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0 +#define ULP1_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0 +#define ULP1_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 +#define ULP1_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1 +#define ULP1_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1 +#define ULP1_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1 +#define ULP1_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1 +#define ULP1_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1 +#define ULP1_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0 +#define ULP1_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0 +#define ULP1_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 +#define ULP1_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1 +#define ULP1_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1 +#define ULP1_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0 +#define ULP1_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1 +#define ULP1_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1 +#define ULP1_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0 +#define ULP1_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0 +#define ULP1_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 +#define ULP1_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1 +#define ULP1_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1 +#define ULP1_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1 +#define ULP1_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1 +#define ULP1_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1 +#define ULP1_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0 +#define ULP1_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0 +#define ULP1_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0 +#define ULP1_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1 +#define ULP1_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1 +#define ULP1_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1 +#define ULP1_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0 +#define ULP1_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0 +#define ULP1_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 +#define ULP1_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1 +#define ULP1_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1 +#define ULP1_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1 +#define ULP1_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1 +#define ULP1_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1 +#define ULP1_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0 +#define ULP1_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0 +#define ULP1_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 +#define ULP1_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1 +#define ULP1_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1 +#define ULP1_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0 +#define ULP1_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1 +#define ULP1_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1 +#define ULP1_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0 +#define ULP1_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0 +#define ULP1_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 +#define ULP1_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1 +#define ULP1_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1 +#define ULP1_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1 +#define ULP1_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1 +#define ULP1_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1 +#define ULP1_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0 +#define ULP1_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0 +#define ULP1_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0 +#define ULP1_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1 +#define ULP1_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1 +#define ULP1_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1 +#define ULP1_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1 +#define ULP1_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0 +#define ULP1_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0 +#define ULP1_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 +#define ULP1_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1 +#define ULP1_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 +#define ULP1_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1 +#define ULP1_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1 +#define ULP1_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1 +#define ULP1_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0 +#define ULP1_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0 +#define ULP1_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 +#define ULP1_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1 +#define ULP1_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 +#define ULP1_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0 +#define ULP1_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1 +#define ULP1_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1 +#define ULP1_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 +#define ULP1_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 +#define ULP1_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 +#define ULP1_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1 +#define ULP1_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1 +#define ULP1_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1 +#define ULP1_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1 +#define ULP1_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1 +#define ULP1_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0 +#define ULP1_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0 +#define ULP1_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0 +#define ULP1_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1 +#define ULP1_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1 +#define ULP1_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1 +#define ULP1_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0 +#define ULP1_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0 +#define ULP1_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 +#define ULP1_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1 +#define ULP1_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 +#define ULP1_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1 +#define ULP1_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 +#define ULP1_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 +#define ULP1_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 +#define ULP1_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 +#define ULP1_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1 +#define ULP1_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0 +#define ULP1_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0 +#define ULP1_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1 +#define ULP1_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 +#define ULP1_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1 +#define ULP1_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 +#define ULP1_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0 +#define ULP1_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1 +#define ULP1_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1 +#define ULP1_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1 +#define ULP1_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0 +#define ULP1_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 +#define ULP1_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 +#define ULP1_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 +#define ULP1_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0 +#define ULP1_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0 +#define ULP1_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0 +#define ULP1_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0 +#define ULP1_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0 +#define ULP1_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0 +#define ULP1_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0 +#define ULP1_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0 +#define ULP1_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0 +#define ULP1_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0 +#define ULP1_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0 +#define ULP1_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0 +#define ULP1_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0 +#define ULP1_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0 +#define ULP1_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2 +#define ULP1_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0 +#define ULP1_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0 +#define ULP1_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2 +#define ULP1_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0 +#define ULP1_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0 +#define ULP1_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2 +#define ULP1_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0 +#define ULP1_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0 +#define ULP1_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2 +#define ULP1_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0 +#define ULP1_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0 +#define ULP1_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0 +#define ULP1_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2 +#define ULP1_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2 +#define ULP1_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2 +#define ULP1_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0 +#define ULP1_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0 +#define ULP1_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0 +#define ULP1_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0 +#define ULP1_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2 +#define ULP1_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0 +#define ULP1_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2 +#define ULP1_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0 +#define ULP1_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0 +#define ULP1_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0 +#define ULP1_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0 +#define ULP1_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2 +#define ULP1_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2 +#define ULP1_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2 +#define ULP1_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0 +#define ULP1_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0 +#define ULP1_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0 +#define ULP1_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2 +#define ULP1_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2 +#define ULP1_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0 +#define ULP1_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0 +#define ULP1_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0 +#define ULP1_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2 +#define ULP1_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2 +#define ULP1_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2 +#define ULP1_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2 +#define ULP1_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0 +#define ULP1_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0 +#define ULP1_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0 +#define ULP1_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2 +#define ULP1_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0 +#define ULP1_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2 +#define ULP1_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2 +#define ULP1_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 +#define ULP1_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 +#define ULP1_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 +#define ULP1_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2 +#define ULP1_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2 +#define ULP1_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2 +#define ULP1_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2 +#define ULP1_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 +#define ULP1_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 +#define ULP1_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0 +#define ULP1_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0 +#define ULP1_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0 +#define ULP1_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0 +#define ULP1_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2 +#define ULP1_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2 +#define ULP1_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2 +#define ULP1_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0 +#define ULP1_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0 +#define ULP1_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0 +#define ULP1_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0 +#define ULP1_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0 +#define ULP1_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0 +#define ULP1_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2 +#define ULP1_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2 +#define ULP1_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2 +#define ULP1_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2 +#define ULP1_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1 +#define ULP1_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0 +#define ULP1_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0 +#define ULP1_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0 +#define ULP1_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0 +#define ULP1_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0 +#define ULP1_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0 +#define ULP1_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2 +#define ULP1_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0 +#define ULP1_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2 +#define ULP1_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2 +#define ULP1_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1 +#define ULP1_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0 +#define ULP1_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0 +#define ULP1_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0 +#define ULP1_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0 +#define ULP1_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0 +#define ULP1_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0 +#define ULP1_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2 +#define ULP1_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2 +#define ULP1_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2 +#define ULP1_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2 +#define ULP1_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0 +#define ULP1_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0 +#define ULP1_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0 +#define ULP1_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0 +#define ULP1_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0 +#define ULP1_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0 +#define ULP1_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0 +#define ULP1_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2 +#define ULP1_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2 +#define ULP1_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0 +#define ULP1_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0 +#define ULP1_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 +#define ULP1_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 +#define ULP1_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 +#define ULP1_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 +#define ULP1_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 +#define ULP1_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2 +#define ULP1_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2 +#define ULP1_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2 +#define ULP1_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2 +#define ULP1_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 +#define ULP1_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 +#define ULP1_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 +#define ULP1_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 +#define ULP1_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 +#define ULP1_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 +#define ULP1_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0 +#define ULP1_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2 +#define ULP1_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2 +#define ULP1_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2 +#define ULP1_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 +#define ULP1_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 +#define ULP1_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 +#define ULP1_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 +#define ULP1_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 +#define ULP1_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 +#define ULP1_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2 +#define ULP1_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2 +#define ULP1_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2 +#define ULP1_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0 +#define ULP1_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 +#define ULP1_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0 +#define ULP1_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0 +#define ULP1_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0 +#define ULP1_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0 +#define ULP1_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2 +#define ULP1_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2 +#define ULP1_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2 +#define ULP1_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0 +#define ULP1_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 +#define ULP1_PAD_PTF0__VIU_DE 0x0180 0x0000 0xc 0x0 +#define ULP1_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 +#define ULP1_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 +#define ULP1_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 +#define ULP1_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0 +#define ULP1_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0 +#define ULP1_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 +#define ULP1_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0 +#define ULP1_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3 +#define ULP1_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3 +#define ULP1_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0 +#define ULP1_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0 +#define ULP1_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 +#define ULP1_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3 +#define ULP1_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3 +#define ULP1_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3 +#define ULP1_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0 +#define ULP1_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0 +#define ULP1_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0 +#define ULP1_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3 +#define ULP1_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3 +#define ULP1_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0 +#define ULP1_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0 +#define ULP1_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 +#define ULP1_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2 +#define ULP1_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3 +#define ULP1_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3 +#define ULP1_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3 +#define ULP1_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2 +#define ULP1_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0 +#define ULP1_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0 +#define ULP1_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 +#define ULP1_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2 +#define ULP1_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3 +#define ULP1_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0 +#define ULP1_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3 +#define ULP1_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2 +#define ULP1_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0 +#define ULP1_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0 +#define ULP1_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 +#define ULP1_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2 +#define ULP1_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3 +#define ULP1_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3 +#define ULP1_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3 +#define ULP1_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2 +#define ULP1_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0 +#define ULP1_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0 +#define ULP1_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0 +#define ULP1_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2 +#define ULP1_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3 +#define ULP1_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3 +#define ULP1_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0 +#define ULP1_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0 +#define ULP1_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0 +#define ULP1_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0 +#define ULP1_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2 +#define ULP1_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3 +#define ULP1_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3 +#define ULP1_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3 +#define ULP1_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3 +#define ULP1_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0 +#define ULP1_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0 +#define ULP1_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0 +#define ULP1_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0 +#define ULP1_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2 +#define ULP1_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3 +#define ULP1_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0 +#define ULP1_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3 +#define ULP1_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3 +#define ULP1_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0 +#define ULP1_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0 +#define ULP1_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0 +#define ULP1_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0 +#define ULP1_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2 +#define ULP1_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3 +#define ULP1_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3 +#define ULP1_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3 +#define ULP1_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3 +#define ULP1_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0 +#define ULP1_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0 +#define ULP1_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0 +#define ULP1_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0 +#define ULP1_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2 +#define ULP1_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3 +#define ULP1_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3 +#define ULP1_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3 +#define ULP1_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0 +#define ULP1_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0 +#define ULP1_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0 +#define ULP1_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0 +#define ULP1_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2 +#define ULP1_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3 +#define ULP1_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3 +#define ULP1_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3 +#define ULP1_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3 +#define ULP1_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0 +#define ULP1_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0 +#define ULP1_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0 +#define ULP1_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0 +#define ULP1_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2 +#define ULP1_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3 +#define ULP1_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0 +#define ULP1_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3 +#define ULP1_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3 +#define ULP1_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0 +#define ULP1_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0 +#define ULP1_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0 +#define ULP1_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0 +#define ULP1_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2 +#define ULP1_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3 +#define ULP1_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3 +#define ULP1_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3 +#define ULP1_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3 +#define ULP1_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0 +#define ULP1_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0 +#define ULP1_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0 +#define ULP1_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0 +#define ULP1_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2 +#define ULP1_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3 +#define ULP1_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3 +#define ULP1_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0 +#define ULP1_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0 +#define ULP1_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0 +#define ULP1_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0 +#define ULP1_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2 +#define ULP1_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3 +#define ULP1_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3 +#define ULP1_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0 +#define ULP1_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0 +#define ULP1_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0 +#define ULP1_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0 +#define ULP1_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2 +#define ULP1_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3 +#define ULP1_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3 +#define ULP1_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0 +#define ULP1_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0 +#define ULP1_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0 +#define ULP1_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0 +#define ULP1_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2 +#define ULP1_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3 +#define ULP1_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3 +#define ULP1_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0 +#define ULP1_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0 +#define ULP1_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0 +#define ULP1_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0 +#define ULP1_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2 +#define ULP1_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3 +#define ULP1_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3 +#define ULP1_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0 + +#endif /* __DTS_ULP1_PINFUNC_H */ diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi new file mode 100644 index 0000000..5497734 --- /dev/null +++ b/arch/arm/dts/imx7ulp.dtsi @@ -0,0 +1,598 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/clock/imx7ulp-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/gpio/gpio.h> +#include "skeleton.dtsi" +#include "imx7ulp-pinfunc.h" + +/ { + interrupt-parent = <&intc>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + mmc0 = &usdhc0; + mmc1 = &usdhc1; + serial0 = &lpuart4; + serial1 = &lpuart5; + serial2 = &lpuart6; + serial3 = &lpuart7; + usbphy0 = &usbphy1; + i2c0 = &lpi2c4; + i2c1 = &lpi2c5; + i2c2 = &lpi2c6; + i2c3 = &lpi2c7; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu at 0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0xC000000>; + alignment = <0x2000>; + linux,cma-default; + }; + + rpmsg_reserved: rpmsg at 9FFF0000 { + no-map; + reg = <0x9FF00000 0x100000>; + }; + + }; + + intc: interrupt-controller at 40021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x40021000 0x1000>, + <0x40022000 0x100>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil: clock at 0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock at 1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + sirc: clock at 2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "sirc"; + }; + + firc: clock at 3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "firc"; + }; + + upll: clock at 4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <480000000>; + clock-output-names = "upll"; + }; + + mpll: clock at 5 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <480000000>; + clock-output-names = "mpll"; + }; + }; + + sram: sram at 20000000 { + compatible = "fsl,lpm-sram"; + reg = <0x1fffc000 0x4000>; + }; + + ahbbridge0: ahb-bridge0 at 40000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x800000>; + ranges; + + edma0: dma-controller at 40080000 { + #dma-cells = <2>; + compatible = "nxp,imx7ulp-edma"; + reg = <0x40080000 0x2000>, + <0x40210000 0x1000>; + dma-channels = <32>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dma", "dmamux0"; + clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>; + }; + + mu: mu at 40220000 { + compatible = "fsl,imx7ulp-mu", "fsl,imx6sx-mu"; + reg = <0x40220000 0x1000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + }; + + nmi: nmi at 40220000 { + compatible = "fsl,imx7ulp-nmi"; + reg = <0x40220000 0x1000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx7ulp-rpmsg"; + memory-region = <&rpmsg_reserved>; + status = "disabled"; + }; + + snvs: snvs at 40230000 { + compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; + reg = <0x40230000 0x10000>; + + snvs_rtc: snvs-rtc-lp{ + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap =<&snvs>; + offset = <0x34>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "snvs-rtc"; + clocks = <&clks IMX7ULP_CLK_SNVS>; + }; + }; + + tpm5: tpm at 40260000 { + compatible = "fsl,imx7ulp-tpm"; + reg = <0x40260000 0x1000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_LPTPM5>; + }; + + lpit: 1 at 40270000 { + compatible = "fsl,imx-lpit"; + reg = <0x40270000 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + /* clocks = <&lpclk>;*/ + clocks = <&clks IMX7ULP_CLK_LPIT1>; + assigned-clock-rates = <48000000>; + assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + }; + + lpi2c4: lpi2c4 at 402B0000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x402B0000 0x10000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_LPI2C4>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c5: lpi2c4 at 402C0000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x402C0000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_LPI2C5>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpspi2: lpspi at 40290000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x40290000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_LPSPI2>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpspi3: lpspi at 402A0000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x402A0000 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_LPSPI3>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart4: serial at 402D0000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x402D0000 0x1000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_LPUART4>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>; + assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>; + assigned-clock-rates = <24000000>; + status = "disabled"; + }; + + lpuart5: serial at 402E0000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x402E0000 0x1000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_LPUART5>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + dmas = <&edma0 0 20>, <&edma0 0 19>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + usbotg1: usb at 40330000 { + compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", + "fsl,imx27-usb"; + reg = <0x40330000 0x200>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_USB0>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x8>; + rx-burst-size-dword = <0x8>; + status = "disabled"; + }; + + usbmisc1: usbmisc at 40330200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x40330200 0x200>; + }; + + usbphy1: usbphy at 0x40350000 { + compatible = "fsl,imx7ulp-usbphy", + "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x40350000 0x1000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_USB_PHY>; + nxp,sim = <&sim>; + }; + + usdhc0: usdhc at 40370000 { + compatible = "fsl,imx7ulp-usdhc"; + reg = <0x40370000 0x10000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, + <&clks IMX7ULP_CLK_NIC1_DIV>, + <&clks IMX7ULP_CLK_USDHC0>; + clock-names ="ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc1: usdhc at 40380000 { + compatible = "fsl,imx7ulp-usdhc"; + reg = <0x40380000 0x10000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, + <&clks IMX7ULP_CLK_NIC1_DIV>, + <&clks IMX7ULP_CLK_USDHC1>; + clock-names ="ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + wdog1: wdog at 403D0000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x403D0000 0x10000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_WDG1>; + assigned-clocks = <&clks IMX7ULP_CLK_WDG1>; + assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>; + /* + * As the 1KHz LPO clock rate is not trimed,the actually clock + * is about 667Hz, so the init timeout 60s should set 40*1000 + * in the TOVAL register. + */ + timeout-sec = <40>; + }; + + wdog2: wdog at 40430000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x40430000 0x10000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_WDG2>; + assigned-clocks = <&clks IMX7ULP_CLK_WDG2>; + assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>; + timeout-sec = <40>; + }; + + clks: scg1 at 403E0000 { + compatible = "fsl,imx7ulp-scg1"; + reg = <0x403E0000 0x10000>; + clocks = <&ckil>, <&osc>, <&sirc>, + <&firc>, <&upll>, <&mpll>; + clock-names = "ckil", "osc", "sirc", + "firc", "upll", "mpll"; + #clock-cells = <1>; + assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>, + <&clks IMX7ULP_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>, + <&clks IMX7ULP_CLK_NIC1_DIV>; + }; + + pcc2: pcc2 at 403F0000 { + compatible = "fsl,imx7ulp-pcc2"; + reg = <0x403F0000 0x10000>; + }; + + pmc1: pmc1 at 40400000 { + compatible = "fsl,imx7ulp-pmc1"; + reg = <0x40400000 0x1000>; + }; + + smc1: smc1 at 40410000 { + compatible = "fsl,imx7ulp-smc1"; + reg = <0x40410000 0x1000>; + }; + + }; + + ahbbridge1: ahb-bridge1 at 40800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40800000 0x800000>; + ranges; + + lpi2c6: lpi2c6 at 40A40000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x40A40000 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_LPI2C6>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c7: lpi2c7 at 40A50000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x40A50000 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_LPI2C7>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart6: serial at 40A60000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x40A60000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_LPUART6>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + dmas = <&edma0 0 22>, <&edma0 0 21>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lpuart7: serial at 40A70000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x40A70000 0x1000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_LPUART7>; + clock-names = "ipg"; + assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>; + assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <50000000>; + dmas = <&edma0 0 24>, <&edma0 0 23>; + dma-names = "tx","rx"; + status = "disabled"; + }; + + lcdif: lcdif at 40AA0000 { + compatible = "fsl,imx7ulp-lcdif"; + reg = <0x40aa0000 0x10000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_DUMMY>, + <&clks IMX7ULP_CLK_LCDIF>, + <&clks IMX7ULP_CLK_DUMMY>; + clock-names = "axi", "pix", "disp_axi"; + status = "disabled"; + }; + + mipi_dsi: mipi_dsi at 40A90000 { + compatible = "fsl,imx7ulp-mipi-dsi"; + reg = <0x40A90000 0x10000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_DSI>; + clock-names = "mipi_dsi_clk"; + sim = <&sim>; + status = "disabled"; + }; + + mmdc: mmdc at 40ab0000 { + compatible = "fsl,imx7ulp-mmdc"; + reg = <0x40ab0000 0x4000>; + }; + + pcc3: pcc3 at 40B30000 { + compatible = "fsl,imx7ulp-pcc3"; + reg = <0x40B30000 0x10000>; + }; + + iomuxc: iomuxc at 4103D000 { + compatible = "fsl,imx7ulp-iomuxc-0"; + reg = <0x4103D000 0x1000>; + fsl,mux_mask = <0xf00>; + status = "disabled"; + }; + + iomuxc1: iomuxc1 at 40ac0000 { + compatible = "fsl,imx7ulp-iomuxc-1"; + reg = <0x40ac0000 0x1000>; + fsl,mux_mask = <0xf00>; + }; + + gpio0: gpio at 40ae0000 { + compatible = "fsl,imx7ulp-gpio"; + reg = <0x40ae0000 0x1000 0x400F0000 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 0 32>; + }; + + gpio1: gpio at 40af0000 { + compatible = "fsl,imx7ulp-gpio"; + reg = <0x40af0000 0x1000 0x400F0040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 32 32>; + }; + + gpio2: gpio at 40b00000 { + compatible = "fsl,imx7ulp-gpio"; + reg = <0x40b00000 0x1000 0x400F0080 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 64 32>; + }; + + gpio3: gpio at 40b10000 { + compatible = "fsl,imx7ulp-gpio"; + reg = <0x40b10000 0x1000 0x400F00c0 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc1 0 96 32>; + }; + + pmc0: pmc0 at 410a1000 { + compatible = "fsl,imx7ulp-pmc0"; + reg = <0x410a1000 0x1000>; + }; + + sim: sim at 410a3000 { + compatible = "fsl,imx7ulp-sim", "syscon"; + reg = <0x410a3000 0x1000>; + }; + + qspi1: qspi at 410A5000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7ulp-qspi"; + reg = <0x410A5000 0x10000>, <0xC0000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_DUMMY>, + <&clks IMX7ULP_CLK_DUMMY>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + gpu: gpu at 41800000 { + compatible = "fsl,imx6q-gpu"; + reg = <0x41800000 0x80000>, <0x41880000 0x80000>, + <0x60000000 0x40000000>, <0x0 0x4000000>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr", "contiguous_mem"; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&clks IMX7ULP_CLK_GPU3D>, + <&clks IMX7ULP_CLK_NIC1_DIV>, + <&clks IMX7ULP_CLK_GPU_DIV>, + <&clks IMX7ULP_CLK_GPU2D>, + <&clks IMX7ULP_CLK_NIC1_DIV>, + <&clks IMX7ULP_CLK_NIC1_DIV>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", + "gpu3d_axi_clk", "gpu2d_clk", + "gpu2d_shader_clk", "gpu2d_axi_clk"; + }; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; +}; diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h new file mode 100644 index 0000000..0a955df --- /dev/null +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H +#define __DT_BINDINGS_CLOCK_IMX7ULP_H + +#define IMX7ULP_CLK_DUMMY 0 +#define IMX7ULP_CLK_CKIL 1 +#define IMX7ULP_CLK_OSC 2 +#define IMX7ULP_CLK_FIRC 3 + +/* SCG1 */ +#define IMX7ULP_CLK_SPLL_PRE_SEL 4 +#define IMX7ULP_CLK_SPLL_PRE_DIV 5 +#define IMX7ULP_CLK_SPLL 6 +#define IMX7ULP_CLK_SPLL_POST_DIV1 7 +#define IMX7ULP_CLK_SPLL_POST_DIV2 8 +#define IMX7ULP_CLK_SPLL_PFD0 9 +#define IMX7ULP_CLK_SPLL_PFD1 10 +#define IMX7ULP_CLK_SPLL_PFD2 11 +#define IMX7ULP_CLK_SPLL_PFD3 12 +#define IMX7ULP_CLK_SPLL_PFD_SEL 13 +#define IMX7ULP_CLK_SPLL_SEL 14 +#define IMX7ULP_CLK_APLL_PRE_SEL 15 +#define IMX7ULP_CLK_APLL_PRE_DIV 16 +#define IMX7ULP_CLK_APLL 17 +#define IMX7ULP_CLK_APLL_POST_DIV1 18 +#define IMX7ULP_CLK_APLL_POST_DIV2 19 +#define IMX7ULP_CLK_APLL_PFD0 20 +#define IMX7ULP_CLK_APLL_PFD1 21 +#define IMX7ULP_CLK_APLL_PFD2 22 +#define IMX7ULP_CLK_APLL_PFD3 23 +#define IMX7ULP_CLK_APLL_PFD_SEL 24 +#define IMX7ULP_CLK_APLL_SEL 25 +#define IMX7ULP_CLK_UPLL 26 +#define IMX7ULP_CLK_SYS_SEL 27 +#define IMX7ULP_CLK_CORE_DIV 28 +#define IMX7ULP_CLK_BUS_DIV 29 +#define IMX7ULP_CLK_PLAT_DIV 30 +#define IMX7ULP_CLK_DDR_SEL 31 +#define IMX7ULP_CLK_DDR_DIV 32 +#define IMX7ULP_CLK_NIC_SEL 33 +#define IMX7ULP_CLK_NIC0_DIV 34 +#define IMX7ULP_CLK_GPU_DIV 35 +#define IMX7ULP_CLK_NIC1_DIV 36 +#define IMX7ULP_CLK_NIC1_BUS_DIV 37 +#define IMX7ULP_CLK_NIC1_EXT_DIV 38 + +/* PCG2 */ +#define IMX7ULP_CLK_DMA1 39 +#define IMX7ULP_CLK_RGPIO2P1 40 +#define IMX7ULP_CLK_FLEXBUS 41 +#define IMX7ULP_CLK_SEMA42_1 42 +#define IMX7ULP_CLK_DMA_MUX1 43 +#define IMX7ULP_CLK_SNVS 44 +#define IMX7ULP_CLK_CAAM 45 +#define IMX7ULP_CLK_LPTPM4 46 +#define IMX7ULP_CLK_LPTPM5 47 +#define IMX7ULP_CLK_LPIT1 48 +#define IMX7ULP_CLK_LPSPI2 49 +#define IMX7ULP_CLK_LPSPI3 50 +#define IMX7ULP_CLK_LPI2C4 51 +#define IMX7ULP_CLK_LPI2C5 52 +#define IMX7ULP_CLK_LPUART4 53 +#define IMX7ULP_CLK_LPUART5 54 +#define IMX7ULP_CLK_FLEXIO1 55 +#define IMX7ULP_CLK_USB0 56 +#define IMX7ULP_CLK_USB1 57 +#define IMX7ULP_CLK_USB_PHY 58 +#define IMX7ULP_CLK_USB_PL301 59 +#define IMX7ULP_CLK_USDHC0 60 +#define IMX7ULP_CLK_USDHC1 61 +#define IMX7ULP_CLK_WDG1 62 +#define IMX7ULP_CLK_WDG2 63 + +/* PCG3 */ +#define IMX7ULP_CLK_LPTPM6 64 +#define IMX7ULP_CLK_LPTPM7 65 +#define IMX7ULP_CLK_LPI2C6 66 +#define IMX7ULP_CLK_LPI2C7 67 +#define IMX7ULP_CLK_LPUART6 68 +#define IMX7ULP_CLK_LPUART7 69 +#define IMX7ULP_CLK_VIU 70 +#define IMX7ULP_CLK_DSI 71 +#define IMX7ULP_CLK_LCDIF 72 +#define IMX7ULP_CLK_MMDC 73 +#define IMX7ULP_CLK_PCTLC 74 +#define IMX7ULP_CLK_PCTLD 75 +#define IMX7ULP_CLK_PCTLE 76 +#define IMX7ULP_CLK_PCTLF 77 +#define IMX7ULP_CLK_GPU3D 78 +#define IMX7ULP_CLK_GPU2D 79 + +#define IMX7ULP_CLK_MIPI_PLL 80 +#define IMX7ULP_CLK_SIRC 81 + +#define IMX7ULP_CLK_SCG1_CLKOUT 82 + +#define IMX7ULP_CLK_END 83 + +/*cm4 clocks*/ +#define IMX7ULP_CM4_CLK_DUMMY 0 +#define IMX7ULP_CM4_CLK_CKIL 1 +#define IMX7ULP_CM4_CLK_OSC 2 +#define IMX7ULP_CM4_CLK_FIRC 3 +#define IMX7ULP_CM4_CLK_SIRC 4 + +/* SCG0 */ +#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL 5 +#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV 6 +#define IMX7ULP_CM4_CLK_SPLL 7 +#define IMX7ULP_CM4_CLK_SPLL_VCO 8 +#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1 9 +#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2 10 +#define IMX7ULP_CM4_CLK_SPLL_PFD0 11 +#define IMX7ULP_CM4_CLK_SPLL_PFD1 12 +#define IMX7ULP_CM4_CLK_SPLL_PFD2 13 +#define IMX7ULP_CM4_CLK_SPLL_PFD3 14 +#define IMX7ULP_CM4_CLK_SPLL_PFD_SEL 15 +#define IMX7ULP_CM4_CLK_SPLL_PFD 16 +#define IMX7ULP_CM4_CLK_SPLL_SEL 17 +#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL 18 +#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV 19 +#define IMX7ULP_CM4_CLK_APLL 20 +#define IMX7ULP_CM4_CLK_APLL_VCO 21 +#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1 22 +#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2 23 +#define IMX7ULP_CM4_CLK_APLL_PFD0 24 +#define IMX7ULP_CM4_CLK_APLL_PFD1 25 +#define IMX7ULP_CM4_CLK_APLL_PFD2 26 +#define IMX7ULP_CM4_CLK_APLL_PFD3 27 +#define IMX7ULP_CM4_CLK_APLL_PFD_SEL 28 +#define IMX7ULP_CM4_CLK_APLL_PFD 29 +#define IMX7ULP_CM4_CLK_APLL_SEL 30 +#define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV 31 +#define IMX7ULP_CM4_CLK_SYS_SEL 32 +#define IMX7ULP_CM4_CLK_CORE_DIV 33 +#define IMX7ULP_CM4_CLK_BUS_DIV 34 +#define IMX7ULP_CM4_CLK_PLAT_DIV 35 +#define IMX7ULP_CM4_CLK_SLOW_DIV 36 + +#define IMX7ULP_CM4_CLK_SAI0_SEL 37 +#define IMX7ULP_CM4_CLK_SAI0_DIV 38 +#define IMX7ULP_CM4_CLK_SAI0_ROOT 39 +#define IMX7ULP_CM4_CLK_SAI0_IPG 40 +#define IMX7ULP_CM4_CLK_SAI1_SEL 41 +#define IMX7ULP_CM4_CLK_SAI1_DIV 42 +#define IMX7ULP_CM4_CLK_SAI1_ROOT 43 +#define IMX7ULP_CM4_CLK_SAI1_IPG 44 + +#define IMX7ULP_CLK_SCG0_CLKOUT 45 + +#define IMX7ULP_CM4_CLK_END 46 + +#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */ -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 18/20] mmc: fsl_esdhc: support i.MX7ULP 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (16 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 17/20] arm: dts: add i.MX7ULP dtsi file Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2016-12-27 22:17 ` Jaehoon Chung 2017-02-12 9:29 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 19/20] imx: imx7ulp: add EVK board support Peng Fan ` (2 subsequent siblings) 20 siblings, 2 replies; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Add compatible property for i.MX7ULP. Add a weak init_usdhc_clk function, i.MX7ULP use this to init the clock. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> --- V2: None drivers/mmc/fsl_esdhc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 9796d39..c6b1ec9 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -938,6 +938,10 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd) #ifdef CONFIG_DM_MMC #include <asm/arch/clock.h> +__weak void init_clk_usdhc(u32 index) +{ +} + static int fsl_esdhc_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); @@ -997,6 +1001,9 @@ static int fsl_esdhc_probe(struct udevice *dev) * correctly get the seq as 2 and 3, then let mxc_get_clock * work as expected. */ + + init_clk_usdhc(dev->seq); + priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); if (priv->sdhc_clk <= 0) { dev_err(dev, "Unable to get clk for %s\n", dev->name); @@ -1021,6 +1028,7 @@ static const struct udevice_id fsl_esdhc_ids[] = { { .compatible = "fsl,imx6sl-usdhc", }, { .compatible = "fsl,imx6q-usdhc", }, { .compatible = "fsl,imx7d-usdhc", }, + { .compatible = "fsl,imx7ulp-usdhc", }, { /* sentinel */ } }; -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 18/20] mmc: fsl_esdhc: support i.MX7ULP 2016-12-27 10:04 ` [U-Boot] [PATCH V2 18/20] mmc: fsl_esdhc: support i.MX7ULP Peng Fan @ 2016-12-27 22:17 ` Jaehoon Chung 2017-02-12 9:29 ` Stefano Babic 1 sibling, 0 replies; 48+ messages in thread From: Jaehoon Chung @ 2016-12-27 22:17 UTC (permalink / raw) To: u-boot Hi Peng, On 12/27/2016 07:04 PM, Peng Fan wrote: > Add compatible property for i.MX7ULP. > Add a weak init_usdhc_clk function, i.MX7ULP use this to init the clock. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > Cc: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Best Regards, Jaehoon Chung > --- > > V2: > None > > drivers/mmc/fsl_esdhc.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c > index 9796d39..c6b1ec9 100644 > --- a/drivers/mmc/fsl_esdhc.c > +++ b/drivers/mmc/fsl_esdhc.c > @@ -938,6 +938,10 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd) > > #ifdef CONFIG_DM_MMC > #include <asm/arch/clock.h> > +__weak void init_clk_usdhc(u32 index) > +{ > +} > + > static int fsl_esdhc_probe(struct udevice *dev) > { > struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); > @@ -997,6 +1001,9 @@ static int fsl_esdhc_probe(struct udevice *dev) > * correctly get the seq as 2 and 3, then let mxc_get_clock > * work as expected. > */ > + > + init_clk_usdhc(dev->seq); > + > priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); > if (priv->sdhc_clk <= 0) { > dev_err(dev, "Unable to get clk for %s\n", dev->name); > @@ -1021,6 +1028,7 @@ static const struct udevice_id fsl_esdhc_ids[] = { > { .compatible = "fsl,imx6sl-usdhc", }, > { .compatible = "fsl,imx6q-usdhc", }, > { .compatible = "fsl,imx7d-usdhc", }, > + { .compatible = "fsl,imx7ulp-usdhc", }, > { /* sentinel */ } > }; > > ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 18/20] mmc: fsl_esdhc: support i.MX7ULP 2016-12-27 10:04 ` [U-Boot] [PATCH V2 18/20] mmc: fsl_esdhc: support i.MX7ULP Peng Fan 2016-12-27 22:17 ` Jaehoon Chung @ 2017-02-12 9:29 ` Stefano Babic 1 sibling, 0 replies; 48+ messages in thread From: Stefano Babic @ 2017-02-12 9:29 UTC (permalink / raw) To: u-boot On 27/12/2016 11:04, Peng Fan wrote: > Add compatible property for i.MX7ULP. > Add a weak init_usdhc_clk function, i.MX7ULP use this to init the clock. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > Cc: Jaehoon Chung <jh80.chung@samsung.com> > --- > > V2: > None > > drivers/mmc/fsl_esdhc.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c > index 9796d39..c6b1ec9 100644 > --- a/drivers/mmc/fsl_esdhc.c > +++ b/drivers/mmc/fsl_esdhc.c > @@ -938,6 +938,10 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd) > > #ifdef CONFIG_DM_MMC > #include <asm/arch/clock.h> > +__weak void init_clk_usdhc(u32 index) > +{ > +} > + > static int fsl_esdhc_probe(struct udevice *dev) > { > struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); > @@ -997,6 +1001,9 @@ static int fsl_esdhc_probe(struct udevice *dev) > * correctly get the seq as 2 and 3, then let mxc_get_clock > * work as expected. > */ > + > + init_clk_usdhc(dev->seq); > + > priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); > if (priv->sdhc_clk <= 0) { > dev_err(dev, "Unable to get clk for %s\n", dev->name); > @@ -1021,6 +1028,7 @@ static const struct udevice_id fsl_esdhc_ids[] = { > { .compatible = "fsl,imx6sl-usdhc", }, > { .compatible = "fsl,imx6q-usdhc", }, > { .compatible = "fsl,imx7d-usdhc", }, > + { .compatible = "fsl,imx7ulp-usdhc", }, > { /* sentinel */ } > }; > > Reviewed-by : Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 19/20] imx: imx7ulp: add EVK board support 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (17 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 18/20] mmc: fsl_esdhc: support i.MX7ULP Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2016-12-27 10:04 ` [U-Boot] [PATCH V2 20/20] imx: mx7ulp_evk: enable mmc/regulator support Peng Fan 2017-02-08 8:36 ` [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan 20 siblings, 0 replies; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Add EVK board support. Add the evk dts file. LOG: U-Boot 2017.01-rc2-00054-gdc3b609 (Dec 27 2016 - 16:25:47 +0800) CPU: Freescale i.MX7ULP rev1.0 at 500 MHz Reset cause: POR Boot mode: Dual boot Model: NXP i.MX7ULP EVK DRAM: 1 GiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial at 402D0000 Out: serial at 402D0000 Err: serial at 402D0000 Net: Net Initialization Skipped No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: Add maintainer file Drop board rev Drop check board function Add plugin support arch/arm/cpu/armv7/mx7ulp/Kconfig | 11 + arch/arm/dts/Makefile | 2 + arch/arm/dts/imx7ulp-evk.dts | 426 ++++++++++++++++++++++++++++++++ arch/arm/dts/imx7ulp-uboot.dtsi | 43 ++++ board/freescale/mx7ulp_evk/Kconfig | 12 + board/freescale/mx7ulp_evk/MAINTAINERS | 7 + board/freescale/mx7ulp_evk/Makefile | 6 + board/freescale/mx7ulp_evk/imximage.cfg | 137 ++++++++++ board/freescale/mx7ulp_evk/mx7ulp_evk.c | 48 ++++ board/freescale/mx7ulp_evk/plugin.S | 224 +++++++++++++++++ configs/mx7ulp_evk_defconfig | 17 ++ configs/mx7ulp_evk_plugin_defconfig | 18 ++ include/configs/mx7ulp_evk.h | 112 +++++++++ 13 files changed, 1063 insertions(+) create mode 100644 arch/arm/dts/imx7ulp-evk.dts create mode 100644 arch/arm/dts/imx7ulp-uboot.dtsi create mode 100644 board/freescale/mx7ulp_evk/Kconfig create mode 100644 board/freescale/mx7ulp_evk/MAINTAINERS create mode 100644 board/freescale/mx7ulp_evk/Makefile create mode 100644 board/freescale/mx7ulp_evk/imximage.cfg create mode 100644 board/freescale/mx7ulp_evk/mx7ulp_evk.c create mode 100644 board/freescale/mx7ulp_evk/plugin.S create mode 100644 configs/mx7ulp_evk_defconfig create mode 100644 configs/mx7ulp_evk_plugin_defconfig create mode 100644 include/configs/mx7ulp_evk.h diff --git a/arch/arm/cpu/armv7/mx7ulp/Kconfig b/arch/arm/cpu/armv7/mx7ulp/Kconfig index 85efd6d..1bdc85a 100644 --- a/arch/arm/cpu/armv7/mx7ulp/Kconfig +++ b/arch/arm/cpu/armv7/mx7ulp/Kconfig @@ -3,4 +3,15 @@ if ARCH_MX7ULP config SYS_SOC default "mx7ulp" +choice + prompt "MX7ULP board select" + optional + +config TARGET_MX7ULP_EVK + bool "Support mx7ulp EVK board" + +endchoice + +source "board/freescale/mx7ulp_evk/Kconfig" + endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3ee608b..b88f02c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -305,6 +305,8 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ dtb-$(CONFIG_MX7) += imx7-colibri.dtb +dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb + dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2l-evm.dtb \ k2e-evm.dtb \ diff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts new file mode 100644 index 0000000..e56b722 --- /dev/null +++ b/arch/arm/dts/imx7ulp-evk.dts @@ -0,0 +1,426 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx7ulp.dtsi" + +/ { + model = "NXP i.MX7ULP EVK"; + compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200"; + stdout-path = &lpuart4; + }; + + bcmdhd_wlan_0: bcmdhd_wlan at 0 { + compatible = "android,bcmdhd_wlan"; + wlreg_on-supply = <&wlreg_on>; + bcmdhd_fw = "/lib/firmware/bcm/1DX_BCM4343W/fw_bcmdhd.bin"; + bcmdhd_nv = "/lib/firmware/bcm/1DX_BCM4343W/bcmdhd.1DX.SDIO.cal"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + backlight { + compatible = "gpio-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; + default-on; + status = "okay"; + }; + + mipi_dsi_reset: mipi-dsi-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + wlreg_on: fixedregulator at 100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "wlreg_on"; + gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator at 0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vsd_3v3: regulator at 1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vsd_3v3b: regulator at 2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "VSD_3V3B"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_extcon_usb1>; + }; + + pf1550-rpmsg { + compatible = "fsl,pf1550-rpmsg"; + sw1_reg: SW1 { + regulator-name = "SW1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: SW2 { + regulator-name = "SW2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: SW3 { + regulator-name = "SW3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: VREFDDR { + regulator-name = "VREFDDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&iomuxc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7ulp-evk { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + ULP1_PAD_PTC10__PTC10 0x30100 /* USDHC0 CD */ + ULP1_PAD_PTC1__PTC1 0x20100 + ULP1_PAD_PTD0__PTD0 0x30100 /* USDHC0 RST */ + ULP1_PAD_PTE13__PTE13 0x30103 /* USDHC1 CD */ + ULP1_PAD_PTE12__PTE12 0x30103 /* USDHC1 WP */ + ULP1_PAD_PTE14__SDHC1_VS 0x843 /* USDHC1 VSEL */ + >; + }; + + pinctrl_backlight: backlight_grp { + fsl,pins = < + ULP1_PAD_PTF2__PTF2 0x20100 + >; + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = < + ULP1_PAD_PTC4__LPI2C5_SCL 0x527 + ULP1_PAD_PTC5__LPI2C5_SDA 0x527 + >; + }; + + pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { + fsl,pins = < + ULP1_PAD_PTC19__PTC19 0x20103 + >; + }; + + pinctrl_lpuart4: lpuart4grp { + fsl,pins = < + ULP1_PAD_PTC3__LPUART4_RX 0x400 + ULP1_PAD_PTC2__LPUART4_TX 0x400 + >; + }; + + pinctrl_lpuart6: lpuart6grp { + fsl,pins = < + ULP1_PAD_PTE10__LPUART6_TX 0x400 + ULP1_PAD_PTE11__LPUART6_RX 0x400 + ULP1_PAD_PTE9__LPUART6_RTS_B 0x400 + ULP1_PAD_PTE8__LPUART6_CTS_B 0x400 + ULP1_PAD_PTE7__PTE7 0x00 /* BT_REG_ON */ + >; + }; + + pinctrl_lpuart7: lpuart7grp { + fsl,pins = < + ULP1_PAD_PTF14__LPUART7_TX 0x400 + ULP1_PAD_PTF15__LPUART7_RX 0x400 + ULP1_PAD_PTF13__LPUART7_RTS_B 0x400 + ULP1_PAD_PTF12__LPUART7_CTS_B 0x400 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + ULP1_PAD_PTD1__SDHC0_CMD 0x843 + ULP1_PAD_PTD2__SDHC0_CLK 0x10843 + ULP1_PAD_PTD7__SDHC0_D3 0x843 + ULP1_PAD_PTD8__SDHC0_D2 0x843 + ULP1_PAD_PTD9__SDHC0_D1 0x843 + ULP1_PAD_PTD10__SDHC0_D0 0x843 + >; + }; + + pinctrl_usdhc0_8bit: usdhc0grp_8bit { + fsl,pins = < + ULP1_PAD_PTD1__SDHC0_CMD 0x843 + ULP1_PAD_PTD2__SDHC0_CLK 0x843 + ULP1_PAD_PTD3__SDHC0_D7 0x843 + ULP1_PAD_PTD4__SDHC0_D6 0x843 + ULP1_PAD_PTD5__SDHC0_D5 0x843 + ULP1_PAD_PTD6__SDHC0_D4 0x843 + ULP1_PAD_PTD7__SDHC0_D3 0x843 + ULP1_PAD_PTD8__SDHC0_D2 0x843 + ULP1_PAD_PTD9__SDHC0_D1 0x843 + ULP1_PAD_PTD10__SDHC0_D0 0x843 + >; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = < + ULP1_PAD_PTF12__LPI2C7_SCL 0x527 + ULP1_PAD_PTF13__LPI2C7_SDA 0x527 + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + ULP1_PAD_PTF16__LPSPI3_SIN 0x300 + ULP1_PAD_PTF17__LPSPI3_SOUT 0x300 + ULP1_PAD_PTF18__LPSPI3_SCK 0x300 + ULP1_PAD_PTF19__LPSPI3_PCS0 0x300 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + ULP1_PAD_PTC0__PTC0 0x30100 + >; + }; + + pinctrl_extcon_usb1: extcon1grp { + fsl,pins = < + ULP1_PAD_PTC8__PTC8 0x30103 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + ULP1_PAD_PTE3__SDHC1_CMD 0x843 + ULP1_PAD_PTE2__SDHC1_CLK 0x843 + ULP1_PAD_PTE1__SDHC1_D0 0x843 + ULP1_PAD_PTE0__SDHC1_D1 0x843 + ULP1_PAD_PTE5__SDHC1_D2 0x843 + ULP1_PAD_PTE4__SDHC1_D3 0x843 + >; + }; + + pinctrl_usdhc1_rst: usdhc1grp_rst { + fsl,pins = < + ULP1_PAD_PTE11__PTE11 0x30100 /* USDHC1 RST */ + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + ULP1_PAD_PTE6__PTE6 0x43 /* WL_REG_ON */ + >; + }; + }; +}; + +&lcdif { + status = "okay"; + disp-dev = "mipi_dsi_northwest"; + display = <&display0>; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&lpi2c7 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c7>; +}; + +&lpi2c5 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c5>; + status = "okay"; + + fxas2100x at 20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700 at 1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + }; + + mpl3115 at 60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&lpspi3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + status = "okay"; + + spidev0: spi at 0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <1000000>; + }; +}; + +&mipi_dsi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_dsi_reset>; + lcd_panel = "TRULY-WVGA-TFT3P5581E"; + resets = <&mipi_dsi_reset>; + status = "okay"; +}; + +&lpuart4 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart4>; + status = "okay"; +}; + +&lpuart6 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart6>; + status = "okay"; +}; + +&lpuart7 { /* Uart test */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart7>; + status = "disabled"; +}; + +&rpmsg{ + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + extcon = <0>, <&extcon_usb1>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + cd-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_vsd_3v3>; + vqmmc-supply = <&vldo2_reg>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx7ulp-uboot.dtsi b/arch/arm/dts/imx7ulp-uboot.dtsi new file mode 100644 index 0000000..712cec4 --- /dev/null +++ b/arch/arm/dts/imx7ulp-uboot.dtsi @@ -0,0 +1,43 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&soc { + u-boot,dm-pre-reloc; +}; + +&ahbbridge0 { + u-boot,dm-pre-reloc; +}; + +&ahbbridge1 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + u-boot,dm-pre-reloc; +}; + +&iomuxc1 { + u-boot,dm-pre-reloc; +}; + +&lpuart4 { + u-boot,dm-pre-reloc; +}; + +&lpuart5 { + u-boot,dm-pre-reloc; +}; + +&lpuart6 { + u-boot,dm-pre-reloc; +}; + +&lpuart7 { + u-boot,dm-pre-reloc; +}; diff --git a/board/freescale/mx7ulp_evk/Kconfig b/board/freescale/mx7ulp_evk/Kconfig new file mode 100644 index 0000000..ff44831 --- /dev/null +++ b/board/freescale/mx7ulp_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX7ULP_EVK + +config SYS_BOARD + default "mx7ulp_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx7ulp_evk" + +endif diff --git a/board/freescale/mx7ulp_evk/MAINTAINERS b/board/freescale/mx7ulp_evk/MAINTAINERS new file mode 100644 index 0000000..1aa2644 --- /dev/null +++ b/board/freescale/mx7ulp_evk/MAINTAINERS @@ -0,0 +1,7 @@ +MX7ULPEVK BOARD +M: Peng Fan <peng.fan@nxp.com> +S: Maintained +F: board/freescale/mx7ulp_evk/ +F: include/configs/mx7ulp_evk.h +F: configs/mx7ulp_evk_defconfig +F: configs/mx7ulp_evk_plugin_defconfig diff --git a/board/freescale/mx7ulp_evk/Makefile b/board/freescale/mx7ulp_evk/Makefile new file mode 100644 index 0000000..5e19eb4 --- /dev/null +++ b/board/freescale/mx7ulp_evk/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7ulp_evk.o diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg new file mode 100644 index 0000000..e4e4cb3 --- /dev/null +++ b/board/freescale/mx7ulp_evk/imximage.cfg @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x403f00dc 0x00000000 +DATA 4 0x403e0040 0x01000020 +DATA 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x80808080 +DATA 4 0x403e0508 0x00140000 +DATA 4 0x403E0510 0x00000004 +DATA 4 0x403E0514 0x00000002 +DATA 4 0x403e0500 0x00000001 +CHECK_BITS_SET 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x8080801E +CHECK_BITS_SET 4 0x403e050c 0x00000040 +DATA 4 0x403E0030 0x00000001 +DATA 4 0x403e0040 0x11000020 +DATA 4 0x403f00dc 0x42000000 + +DATA 4 0x40B300AC 0x40000000 + +DATA 4 0x40AD0128 0x00040000 +DATA 4 0x40AD00F8 0x00000000 +DATA 4 0x40AD00D8 0x00000180 +DATA 4 0x40AD0108 0x00000180 +DATA 4 0x40AD0104 0x00000180 +DATA 4 0x40AD0124 0x00010000 +DATA 4 0x40AD0080 0x0000018C +DATA 4 0x40AD0084 0x0000018C +DATA 4 0x40AD0088 0x0000018C +DATA 4 0x40AD008C 0x0000018C + +DATA 4 0x40AD0120 0x00010000 +DATA 4 0x40AD010C 0x00000180 +DATA 4 0x40AD0110 0x00000180 +DATA 4 0x40AD0114 0x00000180 +DATA 4 0x40AD0118 0x00000180 +DATA 4 0x40AD0090 0x00000180 +DATA 4 0x40AD0094 0x00000180 +DATA 4 0x40AD0098 0x00000180 +DATA 4 0x40AD009C 0x00000180 + +DATA 4 0x40AD00E0 0x00040000 +DATA 4 0x40AD00E4 0x00040000 + +DATA 4 0x40AB001C 0x00008000 +DATA 4 0x40AB0800 0xA1390003 +DATA 4 0x40AB085C 0x0D3900A0 +DATA 4 0x40AB0890 0x00400000 + +DATA 4 0x40AB0848 0x40404040 +DATA 4 0x40AB0850 0x40404040 +DATA 4 0x40AB081C 0x33333333 +DATA 4 0x40AB0820 0x33333333 +DATA 4 0x40AB0824 0x33333333 +DATA 4 0x40AB0828 0x33333333 + +DATA 4 0x40AB082C 0xf3333333 +DATA 4 0x40AB0830 0xf3333333 +DATA 4 0x40AB0834 0xf3333333 +DATA 4 0x40AB0838 0xf3333333 + +DATA 4 0x40AB08C0 0x24922492 +DATA 4 0x40AB08B8 0x00000800 + +DATA 4 0x40AB0004 0x00020052 +DATA 4 0x40AB000C 0x292C42F3 +DATA 4 0x40AB0010 0x00100A22 +DATA 4 0x40AB0038 0x00120556 +DATA 4 0x40AB0014 0x00C700DB +DATA 4 0x40AB0018 0x00211718 +DATA 4 0x40AB002C 0x0F9F26D2 +DATA 4 0x40AB0030 0x009F0E10 +DATA 4 0x40AB0040 0x0000003F +DATA 4 0x40AB0000 0xC3190000 + +DATA 4 0x40AB001C 0x00008050 +DATA 4 0x40AB001C 0x00008058 +DATA 4 0x40AB001C 0x003F8030 +DATA 4 0x40AB001C 0x003F8038 +DATA 4 0x40AB001C 0xFF0A8030 +DATA 4 0x40AB001C 0xFF0A8038 +DATA 4 0x40AB001C 0x04028030 +DATA 4 0x40AB001C 0x04028038 +DATA 4 0x40AB001C 0x83018030 +DATA 4 0x40AB001C 0x83018038 +DATA 4 0x40AB001C 0x01038030 +DATA 4 0x40AB001C 0x01038038 + +DATA 4 0x40AB083C 0x20000000 + +DATA 4 0x40AB0020 0x00001800 +DATA 4 0x40AB0800 0xA1310000 +DATA 4 0x40AB0004 0x00020052 +DATA 4 0x40AB0404 0x00011006 +DATA 4 0x40AB001C 0x00000000 +#endif diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c new file mode 100644 index 0000000..3618715 --- /dev/null +++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mx7ulp-pins.h> +#include <asm/arch/iomux.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_UP) + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_cfg_t const lpuart4_pads[] = { + MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + mx7ulp_iomux_setup_multiple_pads(lpuart4_pads, + ARRAY_SIZE(lpuart4_pads)); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S new file mode 100644 index 0000000..9eab365 --- /dev/null +++ b/board/freescale/mx7ulp_evk/plugin.S @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> + +.macro imx7ulp_ddr_freq_decrease + ldr r2, =0x403f0000 + ldr r3, =0x00000000 + str r3, [r2, #0xdc] + + ldr r2, =0x403e0000 + ldr r3, =0x01000020 + str r3, [r2, #0x40] + ldr r3, =0x01000000 + str r3, [r2, #0x500] + ldr r3, =0x80808080 + str r3, [r2, #0x50c] + ldr r3, =0x00140000 + str r3, [r2, #0x508] + ldr r3, =0x00000004 + str r3, [r2, #0x510] + ldr r3, =0x00000002 + str r3, [r2, #0x514] + ldr r3, =0x00000001 + str r3, [r2, #0x500] + + ldr r3, =0x01000000 +wait1: + ldr r4, [r2, #0x500] + and r4, r3 + cmp r4, r3 + bne wait1 + + ldr r3, =0x8080801E + str r3, [r2, #0x50c] + + ldr r3, =0x00000040 +wait2: + ldr r4, [r2, #0x50c] + and r4, r3 + cmp r4, r3 + bne wait2 + + ldr r3, =0x00000001 + str r3, [r2, #0x30] + ldr r3, =0x11000020 + str r3, [r2, #0x40] + + ldr r2, =0x403f0000 + ldr r3, =0x42000000 + str r3, [r2, #0xdc] + +.endm + +.macro imx7ulp_evk_ddr_setting + + imx7ulp_ddr_freq_decrease + + /* Enable MMDC PCC clock */ + ldr r2, =0x40b30000 + ldr r3, =0x40000000 + str r3, [r2, #0xac] + + /* Configure DDR pad */ + ldr r0, =0x40ad0000 + ldr r1, =0x00040000 + str r1, [r0, #0x128] + ldr r1, =0x0 + str r1, [r0, #0xf8] + ldr r1, =0x00000180 + str r1, [r0, #0xd8] + ldr r1, =0x00000180 + str r1, [r0, #0x108] + ldr r1, =0x00000180 + str r1, [r0, #0x104] + ldr r1, =0x00010000 + str r1, [r0, #0x124] + ldr r1, =0x0000018C + str r1, [r0, #0x80] + ldr r1, =0x0000018C + str r1, [r0, #0x84] + ldr r1, =0x0000018C + str r1, [r0, #0x88] + ldr r1, =0x0000018C + str r1, [r0, #0x8c] + + ldr r1, =0x00010000 + str r1, [r0, #0x120] + ldr r1, =0x00000180 + str r1, [r0, #0x10c] + ldr r1, =0x00000180 + str r1, [r0, #0x110] + ldr r1, =0x00000180 + str r1, [r0, #0x114] + ldr r1, =0x00000180 + str r1, [r0, #0x118] + ldr r1, =0x00000180 + str r1, [r0, #0x90] + ldr r1, =0x00000180 + str r1, [r0, #0x94] + ldr r1, =0x00000180 + str r1, [r0, #0x98] + ldr r1, =0x00000180 + str r1, [r0, #0x9c] + ldr r1, =0x00040000 + str r1, [r0, #0xe0] + ldr r1, =0x00040000 + str r1, [r0, #0xe4] + + ldr r0, =0x40ab0000 + ldr r1, =0x00008000 + str r1, [r0, #0x1c] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x0D3900A0 + str r1, [r0, #0x85c] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + + ldr r1, =0x40404040 + str r1, [r0, #0x848] + ldr r1, =0x40404040 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81c] + ldr r1, =0x33333333 + str r1, [r0, #0x820] + ldr r1, =0x33333333 + str r1, [r0, #0x824] + ldr r1, =0x33333333 + str r1, [r0, #0x828] + + ldr r1, =0xf3333333 + str r1, [r0, #0x82c] + ldr r1, =0xf3333333 + str r1, [r0, #0x830] + ldr r1, =0xf3333333 + str r1, [r0, #0x834] + ldr r1, =0xf3333333 + str r1, [r0, #0x838] + + ldr r1, =0x24922492 + str r1, [r0, #0x8c0] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + + ldr r1, =0x00020052 + str r1, [r0, #0x4] + ldr r1, =0x292C42F3 + str r1, [r0, #0xc] + ldr r1, =0x00100A22 + str r1, [r0, #0x10] + ldr r1, =0x00120556 + str r1, [r0, #0x38] + ldr r1, =0x00C700DB + str r1, [r0, #0x14] + ldr r1, =0x00211718 + str r1, [r0, #0x18] + + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x2c] + ldr r1, =0x009F0E10 + str r1, [r0, #0x30] + ldr r1, =0x0000003F + str r1, [r0, #0x40] + ldr r1, =0xC3190000 + str r1, [r0, #0x0] + + ldr r1, =0x00008050 + str r1, [r0, #0x1c] + ldr r1, =0x00008058 + str r1, [r0, #0x1c] + ldr r1, =0x003F8030 + str r1, [r0, #0x1c] + ldr r1, =0x003F8038 + str r1, [r0, #0x1c] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x1c] + ldr r1, =0xFF0A8038 + str r1, [r0, #0x1c] + ldr r1, =0x04028030 + str r1, [r0, #0x1c] + ldr r1, =0x04028038 + str r1, [r0, #0x1c] + ldr r1, =0x83018030 + str r1, [r0, #0x1c] + ldr r1, =0x83018038 + str r1, [r0, #0x1c] + ldr r1, =0x01038030 + str r1, [r0, #0x1c] + ldr r1, =0x01038038 + str r1, [r0, #0x1c] + + ldr r1, =0x20000000 + str r1, [r0, #0x83c] + + ldr r1, =0x00001800 + str r1, [r0, #0x20] + ldr r1, =0xA1310000 + str r1, [r0, #0x800] + ldr r1, =0x00020052 + str r1, [r0, #0x4] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x1c] + +.endm + +.macro imx7ulp_clock_gating +.endm + +.macro imx7ulp_qos_setting +.endm + +.macro imx7ulp_ddr_setting + imx7ulp_evk_ddr_setting +.endm + +/* include the common plugin code here */ +#include <asm/arch/mx7ulp_plugin.S> diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig new file mode 100644 index 0000000..8c7446b --- /dev/null +++ b/configs/mx7ulp_evk_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_TARGET_MX7ULP_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_I2C=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_I2C=y +CONFIG_SYS_LPI2C_IMX=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig new file mode 100644 index 0000000..87a9324 --- /dev/null +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_TARGET_MX7ULP_EVK=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_I2C=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_I2C=y +CONFIG_SYS_LPI2C_IMX=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h new file mode 100644 index 0000000..4787fec --- /dev/null +++ b/include/configs/mx7ulp_evk.h @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7ULP EVK board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7ULP_EVK_CONFIG_H +#define __MX7ULP_EVK_CONFIG_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +/*Uncomment it to use secure boot*/ +/*#define CONFIG_SECURE_BOOT*/ + +#ifdef CONFIG_SECURE_BOOT +#ifndef CONFIG_CSF_SIZE +#define CONFIG_CSF_SIZE 0x4000 +#endif +#endif + +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + +#define SRC_BASE_ADDR CMC1_RBASE +#define IRAM_BASE_ADDR OCRAM_0_BASE +#define IOMUXC_BASE_ADDR IOMUXC1_RBASE + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE SZ_8K + +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG1_RBASE + +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ + +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +/*#define CONFIG_REVISION_TAG*/ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F + +/* UART */ +#define LPUART_BASE LPUART4_RBASE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +#undef CONFIG_CMD_IMLS +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE SZ_8K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_TEXT_BASE 0x67800000 +#define PHYS_SDRAM 0x60000000 +#define PHYS_SDRAM_SIZE SZ_1G +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_CMD_BOOTZ + +#define CONFIG_LOADADDR 0x60800000 + +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_END 0x9E000000 + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H */ -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 20/20] imx: mx7ulp_evk: enable mmc/regulator support 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (18 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 19/20] imx: imx7ulp: add EVK board support Peng Fan @ 2016-12-27 10:04 ` Peng Fan 2016-12-27 11:22 ` Fabio Estevam 2017-02-08 8:36 ` [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan 20 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2016-12-27 10:04 UTC (permalink / raw) To: u-boot Enable MMC support. The fsl sdhc driver needs regulator to enable power, so enable regulator support. And bootcmd and more env. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: Add bootcmd and more env. configs/mx7ulp_evk_defconfig | 8 ++++ configs/mx7ulp_evk_plugin_defconfig | 8 ++++ include/configs/mx7ulp_evk.h | 93 ++++++++++++++++++++++++++++++++++++- 3 files changed, 108 insertions(+), 1 deletion(-) diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index 8c7446b..ea2a0cf 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -15,3 +15,11 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7ULP=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +# CONFIG_BLK is not set +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_CMD_GPIO=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index 87a9324..d4c36d9 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -16,3 +16,11 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7ULP=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +# CONFIG_BLK is not set +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_CMD_GPIO=y diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 4787fec..1f6c81f 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -28,7 +28,23 @@ #define IRAM_BASE_ADDR OCRAM_0_BASE #define IOMUXC_BASE_ADDR IOMUXC1_RBASE -#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_ENV_OFFSET (12 * SZ_64K) +#define CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_CMD_FAT @@ -91,6 +107,81 @@ #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_END 0x9E000000 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttyLP0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx7ulp-evk.dtb\0" \ + "fdt_addr=0x63000000\0" \ + "boot_fdt=try\0" \ + "earlycon=lpuart32,0x402D0010\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "usb start; "\ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi" + #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- 2.6.2 ^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 20/20] imx: mx7ulp_evk: enable mmc/regulator support 2016-12-27 10:04 ` [U-Boot] [PATCH V2 20/20] imx: mx7ulp_evk: enable mmc/regulator support Peng Fan @ 2016-12-27 11:22 ` Fabio Estevam 2016-12-27 12:07 ` Peng Fan 0 siblings, 1 reply; 48+ messages in thread From: Fabio Estevam @ 2016-12-27 11:22 UTC (permalink / raw) To: u-boot On Tue, Dec 27, 2016 at 8:04 AM, Peng Fan <peng.fan@nxp.com> wrote: > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "script=boot.scr\0" \ > + "image=zImage\0" \ > + "console=ttyLP0\0" \ > + "fdt_high=0xffffffff\0" \ > + "initrd_high=0xffffffff\0" \ > + "fdt_file=imx7ulp-evk.dtb\0" \ > + "fdt_addr=0x63000000\0" \ > + "boot_fdt=try\0" \ On this platform we will always boot from dt, so we can remove this variable... > + "earlycon=lpuart32,0x402D0010\0" \ > + "ip_dyn=yes\0" \ > + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ > + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ > + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ > + "mmcautodetect=yes\0" \ > + "mmcargs=setenv bootargs console=${console},${baudrate} " \ > + "root=${mmcroot}\0" \ > + "loadbootscript=" \ > + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ > + "bootscript=echo Running bootscript from mmc ...; " \ > + "source\0" \ > + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ > + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ > + "mmcboot=echo Booting from mmc ...; " \ > + "run mmcargs; " \ > + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ ,which will also simplify things here. ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 20/20] imx: mx7ulp_evk: enable mmc/regulator support 2016-12-27 11:22 ` Fabio Estevam @ 2016-12-27 12:07 ` Peng Fan 2017-01-03 9:05 ` Peng Fan 0 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2016-12-27 12:07 UTC (permalink / raw) To: u-boot > -----Original Message----- > From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Fabio > Estevam > Sent: Tuesday, December 27, 2016 7:23 PM > To: Peng Fan <peng.fan@nxp.com> > Cc: U-Boot-Denx <u-boot@lists.denx.de> > Subject: Re: [U-Boot] [PATCH V2 20/20] imx: mx7ulp_evk: enable > mmc/regulator support > > On Tue, Dec 27, 2016 at 8:04 AM, Peng Fan <peng.fan@nxp.com> wrote: > > > +#define CONFIG_EXTRA_ENV_SETTINGS \ > > + "script=boot.scr\0" \ > > + "image=zImage\0" \ > > + "console=ttyLP0\0" \ > > + "fdt_high=0xffffffff\0" \ > > + "initrd_high=0xffffffff\0" \ > > + "fdt_file=imx7ulp-evk.dtb\0" \ > > + "fdt_addr=0x63000000\0" \ > > + "boot_fdt=try\0" \ > > On this platform we will always boot from dt, so we can remove this variable... Fix in v3. > > > + "earlycon=lpuart32,0x402D0010\0" \ > > + "ip_dyn=yes\0" \ > > + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ > > + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ > > + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ > > + "mmcautodetect=yes\0" \ > > + "mmcargs=setenv bootargs console=${console},${baudrate} " \ > > + "root=${mmcroot}\0" \ > > + "loadbootscript=" \ > > + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ > > + "bootscript=echo Running bootscript from mmc ...; " \ > > + "source\0" \ > > + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} > ${image}\0" \ > > + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" > \ > > + "mmcboot=echo Booting from mmc ...; " \ > > + "run mmcargs; " \ > > + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ > > ,which will also simplify things here. Agree. Thanks, Peng. > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 20/20] imx: mx7ulp_evk: enable mmc/regulator support 2016-12-27 12:07 ` Peng Fan @ 2017-01-03 9:05 ` Peng Fan 2017-01-12 2:23 ` Peng Fan 0 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2017-01-03 9:05 UTC (permalink / raw) To: u-boot Hi Stefano, On Tue, Dec 27, 2016 at 12:07:40PM +0000, Peng Fan wrote: > > >> -----Original Message----- >> From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Fabio >> Estevam >> Sent: Tuesday, December 27, 2016 7:23 PM >> To: Peng Fan <peng.fan@nxp.com> >> Cc: U-Boot-Denx <u-boot@lists.denx.de> >> Subject: Re: [U-Boot] [PATCH V2 20/20] imx: mx7ulp_evk: enable >> mmc/regulator support >> >> On Tue, Dec 27, 2016 at 8:04 AM, Peng Fan <peng.fan@nxp.com> wrote: >> >> > +#define CONFIG_EXTRA_ENV_SETTINGS \ >> > + "script=boot.scr\0" \ >> > + "image=zImage\0" \ >> > + "console=ttyLP0\0" \ >> > + "fdt_high=0xffffffff\0" \ >> > + "initrd_high=0xffffffff\0" \ >> > + "fdt_file=imx7ulp-evk.dtb\0" \ >> > + "fdt_addr=0x63000000\0" \ >> > + "boot_fdt=try\0" \ >> >> On this platform we will always boot from dt, so we can remove this variable... > > >Fix in v3. I do not see more comments on the patch set. Can I post a follow up patch to fix this, but not send out a whole V3 patch set? Thanks, Peng. ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 20/20] imx: mx7ulp_evk: enable mmc/regulator support 2017-01-03 9:05 ` Peng Fan @ 2017-01-12 2:23 ` Peng Fan 2017-01-12 2:24 ` Peng Fan 0 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2017-01-12 2:23 UTC (permalink / raw) To: u-boot On Tue, Jan 03, 2017 at 05:05:02PM +0800, Peng Fan wrote: >Hi Stefano, > >On Tue, Dec 27, 2016 at 12:07:40PM +0000, Peng Fan wrote: >>> > + "boot_fdt=try\0" \ >>> >>> On this platform we will always boot from dt, so we can remove this variable... >> >> >>Fix in v3. > >I do not see more comments on the patch set. >Can I post a follow up patch to fix this, but not send out a whole V3 patch set? Ping.. Thanks, Peng. ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 20/20] imx: mx7ulp_evk: enable mmc/regulator support 2017-01-12 2:23 ` Peng Fan @ 2017-01-12 2:24 ` Peng Fan 0 siblings, 0 replies; 48+ messages in thread From: Peng Fan @ 2017-01-12 2:24 UTC (permalink / raw) To: u-boot +Stefano On Thu, Jan 12, 2017 at 10:23:03AM +0800, Peng Fan wrote: >On Tue, Jan 03, 2017 at 05:05:02PM +0800, Peng Fan wrote: >>Hi Stefano, >> >>On Tue, Dec 27, 2016 at 12:07:40PM +0000, Peng Fan wrote: >>>> > + "boot_fdt=try\0" \ >>>> >>>> On this platform we will always boot from dt, so we can remove this variable... >>> >>> >>>Fix in v3. >> >>I do not see more comments on the patch set. >>Can I post a follow up patch to fix this, but not send out a whole V3 patch set? > >Ping.. > >Thanks, >Peng. ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan ` (19 preceding siblings ...) 2016-12-27 10:04 ` [U-Boot] [PATCH V2 20/20] imx: mx7ulp_evk: enable mmc/regulator support Peng Fan @ 2017-02-08 8:36 ` Peng Fan 2017-02-08 12:16 ` Stefano Babic 20 siblings, 1 reply; 48+ messages in thread From: Peng Fan @ 2017-02-08 8:36 UTC (permalink / raw) To: u-boot Hi Stefano, On Tue, Dec 27, 2016 at 06:04:06PM +0800, Peng Fan wrote: >This patchset is to add i.MX7 ULP support default enabling OF_CONTROL. >Also there are some new IPs, such lpi2c/lpuart/rapid gpio2p and etc. Do you have plan to pick this patchset? or any comments? We plan to choose 2017.03 to as our base. So I hope this patchset could be merged to 2017.03. Thanks, Peng. ^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support 2017-02-08 8:36 ` [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan @ 2017-02-08 12:16 ` Stefano Babic 0 siblings, 0 replies; 48+ messages in thread From: Stefano Babic @ 2017-02-08 12:16 UTC (permalink / raw) To: u-boot Hi Peng, On 08/02/2017 09:36, Peng Fan wrote: > > Hi Stefano, > > On Tue, Dec 27, 2016 at 06:04:06PM +0800, Peng Fan wrote: >> This patchset is to add i.MX7 ULP support default enabling OF_CONTROL. >> Also there are some new IPs, such lpi2c/lpuart/rapid gpio2p and etc. > > Do you have plan to pick this patchset? or any comments? > > We plan to choose 2017.03 to as our base. So I hope this patchset > could be merged to 2017.03. > Me too. I am on business trip this week, but I plan to check you patches when I will back in the next week-end. Regards, Stefano -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 48+ messages in thread
end of thread, other threads:[~2017-02-22 8:18 UTC | newest] Thread overview: 48+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-12-27 10:04 [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan 2016-12-27 10:04 ` [U-Boot] [PATCH V2 01/20] imx: mx7ulp: Add mx7ulp to Kconfig Peng Fan 2017-02-12 8:39 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 02/20] imx: mx7ulp: add registers header file Peng Fan 2017-02-12 8:40 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 03/20] imx: mx7ulp: add iomux driver to support IOMUXC0 and IOMUXC1 Peng Fan 2017-02-12 8:45 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 04/20] imx: mx7ulp: Add clock framework and functions Peng Fan 2017-02-12 9:12 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 05/20] imx: mx7ulp: Add soc level initialization codes " Peng Fan 2017-02-12 9:19 ` Stefano Babic 2017-02-22 6:48 ` Peng Fan 2016-12-27 10:04 ` [U-Boot] [PATCH V2 06/20] imx: mx7ulp: handle all the lpuarts in get_lpuart_clk Peng Fan 2017-02-12 9:20 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 07/20] imx: mx7ulp: Implement the clock functions for i2c driver Peng Fan 2017-02-12 9:20 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 08/20] gpio: Add Rapid GPIO2P driver for i.MX7ULP Peng Fan 2017-02-12 9:21 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 09/20] mxc_ocotp: Update driver to support OCOTP controller on i.MX7ULP Peng Fan 2017-02-12 9:22 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 10/20] mx7ulp: Add iomux pins header file Peng Fan 2016-12-27 10:04 ` [U-Boot] [PATCH V2 11/20] wdog: Add the watchdog driver for MX7ULP Peng Fan 2017-02-12 9:25 ` Stefano Babic 2017-02-22 6:59 ` Peng Fan 2017-02-22 8:18 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 12/20] pinctrl: Add i.MX7ULP pinctrl driver Peng Fan 2017-01-12 5:07 ` Simon Glass 2017-02-12 9:25 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 13/20] i2c: lpi2c: add lpi2c driver for i.MX7ULP Peng Fan 2016-12-27 10:04 ` [U-Boot] [PATCH V2 14/20] serial: lpuart: restructure lpuart driver Peng Fan 2016-12-29 9:28 ` Bhuvanchandra DV 2017-02-12 9:27 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 15/20] serial: lpuart: add i.MX7ULP support Peng Fan 2016-12-27 10:04 ` [U-Boot] [PATCH V2 16/20] mx7ulp: Add HAB boot support Peng Fan 2017-02-12 9:28 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 17/20] arm: dts: add i.MX7ULP dtsi file Peng Fan 2016-12-27 10:04 ` [U-Boot] [PATCH V2 18/20] mmc: fsl_esdhc: support i.MX7ULP Peng Fan 2016-12-27 22:17 ` Jaehoon Chung 2017-02-12 9:29 ` Stefano Babic 2016-12-27 10:04 ` [U-Boot] [PATCH V2 19/20] imx: imx7ulp: add EVK board support Peng Fan 2016-12-27 10:04 ` [U-Boot] [PATCH V2 20/20] imx: mx7ulp_evk: enable mmc/regulator support Peng Fan 2016-12-27 11:22 ` Fabio Estevam 2016-12-27 12:07 ` Peng Fan 2017-01-03 9:05 ` Peng Fan 2017-01-12 2:23 ` Peng Fan 2017-01-12 2:24 ` Peng Fan 2017-02-08 8:36 ` [U-Boot] [PATCH V2 00/20] imx: add i.MX7ULP support Peng Fan 2017-02-08 12:16 ` Stefano Babic
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