From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> To: netdev@vger.kernel.org, "David S. Miller" <davem@davemloft.net>, devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>, Ian Campbell <ijc+devicetree@hellion.org.uk>, Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>, Kumar Gala <galak@codeaurora.org> Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement <gregory.clement@free-electrons.com>, Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>, Yehuda Yitschak <yehuday@marvell.com>, linux-arm-kernel@lists.infradead.org, Stefan Chulski <stefanc@marvell.com>, Marcin Wojtas <mw@semihalf.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Subject: [PATCHv2 net-next 12/16] net: mvpp2: add AXI bridge initialization for PPv2.2 Date: Wed, 28 Dec 2016 17:46:28 +0100 [thread overview] Message-ID: <1482943592-12556-13-git-send-email-thomas.petazzoni@free-electrons.com> (raw) In-Reply-To: <1482943592-12556-1-git-send-email-thomas.petazzoni@free-electrons.com> The PPv2.2 unit is connected to an AXI bus on Armada 7K/8K, so this commit adds the necessary initialization of the AXI bridge. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- drivers/net/ethernet/marvell/mvpp2.c | 85 ++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index eb55576..d5b197d 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -157,6 +157,34 @@ #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2)) #define MVPP2_BASE_ADDR_ENABLE 0x4060 +/* AXI Bridge Registers */ +#define MVPP22_AXI_BM_WR_ATTR_REG 0x4100 +#define MVPP22_AXI_BM_RD_ATTR_REG 0x4104 +#define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110 +#define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114 +#define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118 +#define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c +#define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120 +#define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130 +#define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150 +#define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154 +#define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160 +#define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164 + +/* Values for AXI Bridge registers */ +#define MVPP22_AXI_ATTR_CACHE_OFFS 0 +#define MVPP22_AXI_ATTR_DOMAIN_OFFS 12 + +#define MVPP22_AXI_CODE_CACHE_OFFS 0 +#define MVPP22_AXI_CODE_DOMAIN_OFFS 4 + +#define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3 +#define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7 +#define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb + +#define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2 +#define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3 + /* Interrupt Cause and Mask registers */ #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0 @@ -6640,6 +6668,60 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv) mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); } +static void mvpp2_axi_init(struct mvpp2 *priv) +{ + u32 val, rdval, wrval; + + mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); + + /* AXI Bridge Configuration */ + + rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE + << MVPP22_AXI_ATTR_CACHE_OFFS; + rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM + << MVPP22_AXI_ATTR_DOMAIN_OFFS; + + wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE + << MVPP22_AXI_ATTR_CACHE_OFFS; + wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM + << MVPP22_AXI_ATTR_DOMAIN_OFFS; + + /* BM */ + mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); + mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); + + /* Descriptors */ + mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); + mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); + mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); + mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); + + /* Buffer Data */ + mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); + mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); + + val = MVPP22_AXI_CODE_CACHE_NON_CACHE + << MVPP22_AXI_CODE_CACHE_OFFS; + val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM + << MVPP22_AXI_CODE_DOMAIN_OFFS; + mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); + mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); + + val = MVPP22_AXI_CODE_CACHE_RD_CACHE + << MVPP22_AXI_CODE_CACHE_OFFS; + val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM + << MVPP22_AXI_CODE_DOMAIN_OFFS; + + mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); + + val = MVPP22_AXI_CODE_CACHE_WR_CACHE + << MVPP22_AXI_CODE_CACHE_OFFS; + val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM + << MVPP22_AXI_CODE_DOMAIN_OFFS; + + mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); +} + /* Initialize network controller common part HW */ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) { @@ -6659,6 +6741,9 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) if (dram_target_info) mvpp2_conf_mbus_windows(dram_target_info, priv); + if (priv->hw_version == MVPP22) + mvpp2_axi_init(priv); + /* Disable HW PHY polling */ if (priv->hw_version == MVPP21) { val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: thomas.petazzoni@free-electrons.com (Thomas Petazzoni) To: linux-arm-kernel@lists.infradead.org Subject: [PATCHv2 net-next 12/16] net: mvpp2: add AXI bridge initialization for PPv2.2 Date: Wed, 28 Dec 2016 17:46:28 +0100 [thread overview] Message-ID: <1482943592-12556-13-git-send-email-thomas.petazzoni@free-electrons.com> (raw) In-Reply-To: <1482943592-12556-1-git-send-email-thomas.petazzoni@free-electrons.com> The PPv2.2 unit is connected to an AXI bus on Armada 7K/8K, so this commit adds the necessary initialization of the AXI bridge. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- drivers/net/ethernet/marvell/mvpp2.c | 85 ++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index eb55576..d5b197d 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -157,6 +157,34 @@ #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2)) #define MVPP2_BASE_ADDR_ENABLE 0x4060 +/* AXI Bridge Registers */ +#define MVPP22_AXI_BM_WR_ATTR_REG 0x4100 +#define MVPP22_AXI_BM_RD_ATTR_REG 0x4104 +#define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110 +#define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114 +#define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118 +#define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c +#define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120 +#define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130 +#define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150 +#define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154 +#define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160 +#define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164 + +/* Values for AXI Bridge registers */ +#define MVPP22_AXI_ATTR_CACHE_OFFS 0 +#define MVPP22_AXI_ATTR_DOMAIN_OFFS 12 + +#define MVPP22_AXI_CODE_CACHE_OFFS 0 +#define MVPP22_AXI_CODE_DOMAIN_OFFS 4 + +#define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3 +#define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7 +#define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb + +#define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2 +#define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3 + /* Interrupt Cause and Mask registers */ #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0 @@ -6640,6 +6668,60 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv) mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); } +static void mvpp2_axi_init(struct mvpp2 *priv) +{ + u32 val, rdval, wrval; + + mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); + + /* AXI Bridge Configuration */ + + rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE + << MVPP22_AXI_ATTR_CACHE_OFFS; + rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM + << MVPP22_AXI_ATTR_DOMAIN_OFFS; + + wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE + << MVPP22_AXI_ATTR_CACHE_OFFS; + wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM + << MVPP22_AXI_ATTR_DOMAIN_OFFS; + + /* BM */ + mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); + mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); + + /* Descriptors */ + mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); + mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); + mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); + mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); + + /* Buffer Data */ + mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); + mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); + + val = MVPP22_AXI_CODE_CACHE_NON_CACHE + << MVPP22_AXI_CODE_CACHE_OFFS; + val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM + << MVPP22_AXI_CODE_DOMAIN_OFFS; + mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); + mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); + + val = MVPP22_AXI_CODE_CACHE_RD_CACHE + << MVPP22_AXI_CODE_CACHE_OFFS; + val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM + << MVPP22_AXI_CODE_DOMAIN_OFFS; + + mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); + + val = MVPP22_AXI_CODE_CACHE_WR_CACHE + << MVPP22_AXI_CODE_CACHE_OFFS; + val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM + << MVPP22_AXI_CODE_DOMAIN_OFFS; + + mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); +} + /* Initialize network controller common part HW */ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) { @@ -6659,6 +6741,9 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) if (dram_target_info) mvpp2_conf_mbus_windows(dram_target_info, priv); + if (priv->hw_version == MVPP22) + mvpp2_axi_init(priv); + /* Disable HW PHY polling */ if (priv->hw_version == MVPP21) { val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); -- 2.7.4
next prev parent reply other threads:[~2016-12-28 16:48 UTC|newest] Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-12-28 16:46 [PATCHv2 net-next 00/16] net: mvpp2: add basic support for PPv2.2 Thomas Petazzoni 2016-12-28 16:46 ` Thomas Petazzoni [not found] ` <1482943592-12556-1-git-send-email-thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> 2016-12-28 16:46 ` [PATCHv2 net-next 01/16] dt-bindings: net: update Marvell PPv2 binding for PPv2.2 support Thomas Petazzoni 2016-12-28 16:46 ` Thomas Petazzoni [not found] ` <1482943592-12556-2-git-send-email-thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> 2017-01-03 20:18 ` Rob Herring 2017-01-03 20:18 ` Rob Herring 2017-02-02 16:56 ` Thomas Petazzoni 2017-02-02 16:56 ` Thomas Petazzoni 2017-02-03 16:48 ` Russell King - ARM Linux 2017-02-03 16:48 ` Russell King - ARM Linux 2017-02-14 14:25 ` Thomas Petazzoni 2017-02-14 14:25 ` Thomas Petazzoni [not found] ` <20170214152503.602878cb-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> 2017-02-21 10:12 ` Thomas Petazzoni 2017-02-21 10:12 ` Thomas Petazzoni 2017-01-07 9:32 ` Russell King - ARM Linux 2017-01-07 9:32 ` Russell King - ARM Linux 2017-02-02 16:44 ` Thomas Petazzoni 2017-02-02 16:44 ` Thomas Petazzoni 2016-12-28 16:46 ` [PATCHv2 net-next 02/16] net: mvpp2: add and use accessors for TX/RX descriptors Thomas Petazzoni 2016-12-28 16:46 ` Thomas Petazzoni 2016-12-28 16:46 ` [PATCHv2 net-next 03/16] net: mvpp2: add hw_version field in "struct mvpp2" Thomas Petazzoni 2016-12-28 16:46 ` Thomas Petazzoni 2016-12-28 16:46 ` [PATCHv2 net-next 07/16] net: mvpp2: adapt the mvpp2_rxq_*_pool_set functions to PPv2.2 Thomas Petazzoni 2016-12-28 16:46 ` Thomas Petazzoni 2016-12-28 16:46 ` [PATCHv2 net-next 14/16] net: mvpp2: adapt rxq distribution " Thomas Petazzoni 2016-12-28 16:46 ` Thomas Petazzoni 2016-12-28 16:46 ` [PATCHv2 net-next 16/16] net: mvpp2: finally add the PPv2.2 compatible string Thomas Petazzoni 2016-12-28 16:46 ` Thomas Petazzoni 2016-12-28 17:06 ` [PATCHv2 net-next 00/16] net: mvpp2: add basic support for PPv2.2 David Miller 2016-12-28 17:06 ` David Miller [not found] ` <20161228.120644.1166014191192724301.davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org> 2016-12-28 21:08 ` Thomas Petazzoni 2016-12-28 21:08 ` Thomas Petazzoni 2016-12-28 16:46 ` [PATCHv2 net-next 04/16] net: mvpp2: introduce an intermediate union for the TX/RX descriptors Thomas Petazzoni 2016-12-28 16:46 ` Thomas Petazzoni 2016-12-28 16:46 ` [PATCHv2 net-next 05/16] net: mvpp2: introduce PPv2.2 HW descriptors and adapt accessors Thomas Petazzoni 2016-12-28 16:46 ` Thomas Petazzoni 2017-01-06 14:29 ` Russell King - ARM Linux 2017-01-06 14:29 ` Russell King - ARM Linux 2017-01-06 14:44 ` Robin Murphy 2017-01-06 14:44 ` Robin Murphy [not found] ` <113811b6-79a4-9c66-d302-add9fb0c5b1a-5wv7dgnIgG8@public.gmane.org> 2017-02-03 13:24 ` Thomas Petazzoni 2017-02-03 13:24 ` Thomas Petazzoni 2017-02-03 14:05 ` Robin Murphy 2017-02-03 14:05 ` Robin Murphy [not found] ` <231514f4-2e35-8bde-4469-aada833635aa-5wv7dgnIgG8@public.gmane.org> 2017-02-03 15:02 ` Thomas Petazzoni 2017-02-03 15:02 ` Thomas Petazzoni [not found] ` <20170203160227.08b40c58-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> 2017-02-03 16:31 ` Robin Murphy 2017-02-03 16:31 ` Robin Murphy 2017-02-03 15:54 ` Russell King - ARM Linux 2017-02-03 15:54 ` Russell King - ARM Linux 2017-02-04 13:59 ` Thomas Petazzoni 2017-02-04 13:59 ` Thomas Petazzoni 2017-02-06 12:43 ` David Laight 2017-02-06 12:43 ` David Laight 2017-02-06 12:43 ` David Laight 2016-12-28 16:46 ` [PATCHv2 net-next 06/16] net: mvpp2: adjust the allocation/free of BM pools for PPv2.2 Thomas Petazzoni 2016-12-28 16:46 ` Thomas Petazzoni 2017-01-06 14:32 ` Russell King - ARM Linux 2017-01-06 14:32 ` Russell King - ARM Linux 2016-12-28 16:46 ` [PATCHv2 net-next 08/16] net: mvpp2: adapt mvpp2_defaults_set() to PPv2.2 Thomas Petazzoni 2016-12-28 16:46 ` Thomas Petazzoni 2016-12-28 16:46 ` [PATCHv2 net-next 09/16] net: mvpp2: adjust mvpp2_{rxq,txq}_init for PPv2.2 Thomas Petazzoni 2016-12-28 16:46 ` [PATCHv2 net-next 09/16] net: mvpp2: adjust mvpp2_{rxq, txq}_init " Thomas Petazzoni 2016-12-28 16:46 ` [PATCHv2 net-next 10/16] net: mvpp2: handle register mapping and access " Thomas Petazzoni 2016-12-28 16:46 ` Thomas Petazzoni 2017-01-06 14:46 ` Russell King - ARM Linux 2017-01-06 14:46 ` Russell King - ARM Linux [not found] ` <20170106144648.GE14217-l+eeeJia6m9URfEZ8mYm6t73F7V6hmMc@public.gmane.org> 2017-03-02 8:45 ` Thomas Petazzoni 2017-03-02 8:45 ` Thomas Petazzoni 2016-12-28 16:46 ` [PATCHv2 net-next 11/16] net: mvpp2: handle misc PPv2.1/PPv2.2 differences Thomas Petazzoni 2016-12-28 16:46 ` Thomas Petazzoni 2017-01-07 9:38 ` Russell King - ARM Linux 2017-01-07 9:38 ` Russell King - ARM Linux [not found] ` <20170107093834.GJ14217-l+eeeJia6m9URfEZ8mYm6t73F7V6hmMc@public.gmane.org> 2017-01-07 20:10 ` Russell King - ARM Linux 2017-01-07 20:10 ` Russell King - ARM Linux 2017-02-14 14:53 ` Thomas Petazzoni 2017-02-14 14:53 ` Thomas Petazzoni 2017-01-07 11:03 ` Russell King - ARM Linux 2017-01-07 11:03 ` Russell King - ARM Linux 2017-01-07 12:12 ` Marcin Wojtas 2017-01-07 12:12 ` Marcin Wojtas [not found] ` <CAPv3WKeQ=fj2cKPyJ2NqCaAv55cOyWodujKwj3-v5iCrDYNcmA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2017-01-07 13:50 ` Russell King - ARM Linux 2017-01-07 13:50 ` Russell King - ARM Linux 2017-01-07 13:50 ` Russell King - ARM Linux 2016-12-28 16:46 ` Thomas Petazzoni [this message] 2016-12-28 16:46 ` [PATCHv2 net-next 12/16] net: mvpp2: add AXI bridge initialization for PPv2.2 Thomas Petazzoni 2016-12-28 16:46 ` [PATCHv2 net-next 13/16] net: mvpp2: rework RXQ interrupt group " Thomas Petazzoni 2016-12-28 16:46 ` Thomas Petazzoni 2016-12-28 16:46 ` [PATCHv2 net-next 15/16] net: mvpp2: add support for an additional clock needed " Thomas Petazzoni 2016-12-28 16:46 ` Thomas Petazzoni [not found] ` <1482943592-12556-16-git-send-email-thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> 2017-01-07 9:29 ` Russell King - ARM Linux 2017-01-07 9:29 ` Russell King - ARM Linux
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