[PATCH v2 0/8] Pad retentions support for Exynos5433

[PATCH v2 0/8] Pad retentions support for Exynos5433

[Marek Szyprowski]

Hello,

This patchset is a first step to add support for all power domains on
Exynos5433 SoCs. This patchset contains patches for Exynos pin control
driver and Exynos LPASS MFD driver, which are needed to make the
platform ready for adding power domains support.

Patches in this patchset depends on each other. They are order in such a
way to make the changes bisectable.

Patch #3 has runtime dependency on #1.
Patch #5 has runtime dependency on #3.
Patch #6 has runtime dependency on #4.

This patchset also directly depends on the "Move pad retention control to
Exynos pin controller driver" patchset:
https://www.spinics.net/lists/arm-kernel/msg556074.html

Patches have been generated on top of linux-next from 25th January 2017.

This is a part of a larger task, which goal is to add support for power
domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it
working have been pushed to the following git repo:
https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd

Best regards
Marek Szyprowski
Samsung R&D Institute Poland


Changelog:
v2:
- fixed issues pointed by Krzysztof Kozlowski:
  1. added more checks to Exynos PMU driver for NULL drvdata
  2. reused EXYNOS_WAKEUP_FROM_LOWPWR in retention data for Exynos5433
  3. converted lpass driver to devm_clk_get
  4. added missing ->remove callback to lpass driver

v1: https://lkml.org/lkml/2017/1/25/214
- initial version


Patch summary:

Marek Szyprowski (8):
  soc: samsung: pmu: Add dummy support for Exynos5433 SoC
  pinctrl: samsung: Ensure that pad retention is disabled on driver init
  pinctrl: samsung: Add support for pad retention control for Exynos5433
    SoCs
  arm64: dts: exynos: Add clocks to Exynos5433 LPASS module
  mfd: exynos-lpass: Remove pad retention control
  mfd: exynos-lpass: Add support for clocks
  mfd: exynos-lpass: Add missing remove() function
  mfd: exynos-lpass: Add runtime PM support

 .../bindings/mfd/samsung,exynos5433-lpass.txt      |  8 ++-
 arch/arm64/boot/dts/exynos/exynos5433.dtsi         |  2 +
 drivers/mfd/exynos-lpass.c                         | 48 ++++++++++-------
 drivers/pinctrl/samsung/pinctrl-exynos.c           | 63 ++++++++++++++++++++++
 drivers/soc/samsung/exynos-pmu.c                   |  6 ++-
 include/linux/mfd/syscon/exynos5-pmu.h             |  3 --
 include/linux/soc/samsung/exynos-regs-pmu.h        | 16 ++++++
 7 files changed, 121 insertions(+), 25 deletions(-)

-- 
1.9.1

[PATCH v2 0/8] Pad retentions support for Exynos5433

[Marek Szyprowski]

Hello,

This patchset is a first step to add support for all power domains on
Exynos5433 SoCs. This patchset contains patches for Exynos pin control
driver and Exynos LPASS MFD driver, which are needed to make the
platform ready for adding power domains support.

Patches in this patchset depends on each other. They are order in such a
way to make the changes bisectable.

Patch #3 has runtime dependency on #1.
Patch #5 has runtime dependency on #3.
Patch #6 has runtime dependency on #4.

This patchset also directly depends on the "Move pad retention control to
Exynos pin controller driver" patchset:
https://www.spinics.net/lists/arm-kernel/msg556074.html

Patches have been generated on top of linux-next from 25th January 2017.

This is a part of a larger task, which goal is to add support for power
domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it
working have been pushed to the following git repo:
https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd

Best regards
Marek Szyprowski
Samsung R&D Institute Poland


Changelog:
v2:
- fixed issues pointed by Krzysztof Kozlowski:
  1. added more checks to Exynos PMU driver for NULL drvdata
  2. reused EXYNOS_WAKEUP_FROM_LOWPWR in retention data for Exynos5433
  3. converted lpass driver to devm_clk_get
  4. added missing ->remove callback to lpass driver

v1: https://lkml.org/lkml/2017/1/25/214
- initial version


Patch summary:

Marek Szyprowski (8):
  soc: samsung: pmu: Add dummy support for Exynos5433 SoC
  pinctrl: samsung: Ensure that pad retention is disabled on driver init
  pinctrl: samsung: Add support for pad retention control for Exynos5433
    SoCs
  arm64: dts: exynos: Add clocks to Exynos5433 LPASS module
  mfd: exynos-lpass: Remove pad retention control
  mfd: exynos-lpass: Add support for clocks
  mfd: exynos-lpass: Add missing remove() function
  mfd: exynos-lpass: Add runtime PM support

 .../bindings/mfd/samsung,exynos5433-lpass.txt      |  8 ++-
 arch/arm64/boot/dts/exynos/exynos5433.dtsi         |  2 +
 drivers/mfd/exynos-lpass.c                         | 48 ++++++++++-------
 drivers/pinctrl/samsung/pinctrl-exynos.c           | 63 ++++++++++++++++++++++
 drivers/soc/samsung/exynos-pmu.c                   |  6 ++-
 include/linux/mfd/syscon/exynos5-pmu.h             |  3 --
 include/linux/soc/samsung/exynos-regs-pmu.h        | 16 ++++++
 7 files changed, 121 insertions(+), 25 deletions(-)

-- 
1.9.1

[PATCH v2 1/8] soc: samsung: pmu: Add dummy support for Exynos5433 SoC

[Marek Szyprowski]

Add compatible for Exynos5433 SoC, so the driver will bind and let other
drivers to use PMU regmap.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/soc/samsung/exynos-pmu.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
index 813df6e7292d..56d9244ff981 100644
--- a/drivers/soc/samsung/exynos-pmu.c
+++ b/drivers/soc/samsung/exynos-pmu.c
@@ -44,7 +44,7 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
 	unsigned int i;
 	const struct exynos_pmu_data *pmu_data;
 
-	if (!pmu_context)
+	if (!pmu_context || !pmu_context->pmu_data)
 		return;
 
 	pmu_data = pmu_context->pmu_data;
@@ -90,6 +90,8 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
 	}, {
 		.compatible = "samsung,exynos5420-pmu",
 		.data = &exynos5420_pmu_data,
+	}, {
+		.compatible = "samsung,exynos5433-pmu",
 	},
 	{ /*sentinel*/ },
 };
@@ -122,7 +124,7 @@ static int exynos_pmu_probe(struct platform_device *pdev)
 	pmu_context->dev = dev;
 	pmu_context->pmu_data = of_device_get_match_data(dev);
 
-	if (pmu_context->pmu_data->pmu_init)
+	if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_init)
 		pmu_context->pmu_data->pmu_init();
 
 	platform_set_drvdata(pdev, pmu_context);
-- 
1.9.1

[PATCH v2 1/8] soc: samsung: pmu: Add dummy support for Exynos5433 SoC

[Marek Szyprowski]

Add compatible for Exynos5433 SoC, so the driver will bind and let other
drivers to use PMU regmap.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/soc/samsung/exynos-pmu.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
index 813df6e7292d..56d9244ff981 100644
--- a/drivers/soc/samsung/exynos-pmu.c
+++ b/drivers/soc/samsung/exynos-pmu.c
@@ -44,7 +44,7 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
 	unsigned int i;
 	const struct exynos_pmu_data *pmu_data;
 
-	if (!pmu_context)
+	if (!pmu_context || !pmu_context->pmu_data)
 		return;
 
 	pmu_data = pmu_context->pmu_data;
@@ -90,6 +90,8 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
 	}, {
 		.compatible = "samsung,exynos5420-pmu",
 		.data = &exynos5420_pmu_data,
+	}, {
+		.compatible = "samsung,exynos5433-pmu",
 	},
 	{ /*sentinel*/ },
 };
@@ -122,7 +124,7 @@ static int exynos_pmu_probe(struct platform_device *pdev)
 	pmu_context->dev = dev;
 	pmu_context->pmu_data = of_device_get_match_data(dev);
 
-	if (pmu_context->pmu_data->pmu_init)
+	if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_init)
 		pmu_context->pmu_data->pmu_init();
 
 	platform_set_drvdata(pdev, pmu_context);
-- 
1.9.1

Re: [PATCH v2 1/8] soc: samsung: pmu: Add dummy support for Exynos5433 SoC

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:33:47AM +0100, Marek Szyprowski wrote:
> Add compatible for Exynos5433 SoC, so the driver will bind and let other
> drivers to use PMU regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/soc/samsung/exynos-pmu.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 

Thanks, applied.

I already have some PMU patches on separate branch (and tag), so this
lands on top of it.

Best regards,
Krzysztof

[PATCH v2 1/8] soc: samsung: pmu: Add dummy support for Exynos5433 SoC

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:33:47AM +0100, Marek Szyprowski wrote:
> Add compatible for Exynos5433 SoC, so the driver will bind and let other
> drivers to use PMU regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/soc/samsung/exynos-pmu.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 

Thanks, applied.

I already have some PMU patches on separate branch (and tag), so this
lands on top of it.

Best regards,
Krzysztof

[PATCH v2 2/8] pinctrl: samsung: Ensure that pad retention is disabled on driver init

[Marek Szyprowski]

When pin controller device is a part of power domain, there is no guarantee
that the power domain was not turned off and then on during boot process
before probing of the pin control driver. If it happened, then pin control
driver should ensure that pad retention is turned off during its probe call.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 drivers/pinctrl/samsung/pinctrl-exynos.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 63e51b56a22a..fa3802970570 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -777,6 +777,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 {
 	struct samsung_retention_ctrl *ctrl;
 	struct regmap *pmu_regs;
+	int i;
 
 	ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
 	if (!ctrl)
@@ -794,6 +795,10 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 	ctrl->enable = exynos_retention_enable;
 	ctrl->disable = exynos_retention_disable;
 
+	/* Ensure that retention is disabled on driver init */
+	for (i = 0; i < ctrl->nr_regs; i++)
+		regmap_write(pmu_regs, ctrl->regs[i], ctrl->value);
+
 	return ctrl;
 }
 
-- 
1.9.1

[PATCH v2 2/8] pinctrl: samsung: Ensure that pad retention is disabled on driver init

[Marek Szyprowski]

When pin controller device is a part of power domain, there is no guarantee
that the power domain was not turned off and then on during boot process
before probing of the pin control driver. If it happened, then pin control
driver should ensure that pad retention is turned off during its probe call.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 drivers/pinctrl/samsung/pinctrl-exynos.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 63e51b56a22a..fa3802970570 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -777,6 +777,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 {
 	struct samsung_retention_ctrl *ctrl;
 	struct regmap *pmu_regs;
+	int i;
 
 	ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
 	if (!ctrl)
@@ -794,6 +795,10 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 	ctrl->enable = exynos_retention_enable;
 	ctrl->disable = exynos_retention_disable;
 
+	/* Ensure that retention is disabled on driver init */
+	for (i = 0; i < ctrl->nr_regs; i++)
+		regmap_write(pmu_regs, ctrl->regs[i], ctrl->value);
+
 	return ctrl;
 }
 
-- 
1.9.1

[PATCH v2 3/8] pinctrl: samsung: Add support for pad retention control for Exynos5433 SoCs

[Marek Szyprowski]

This patch adds support for retention control for Exynos5433 SoCs. Three
groups of pins has been defined for retention control: common shared group
for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and
separate control for FSYS and AUD pin banks, for which PMU retention
registers match whole banks.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/pinctrl/samsung/pinctrl-exynos.c    | 58 +++++++++++++++++++++++++++++
 include/linux/soc/samsung/exynos-regs-pmu.h | 16 ++++++++
 2 files changed, 74 insertions(+)

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index fa3802970570..7b0e6cc35e04 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1551,6 +1551,54 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 	EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
 };
 
+/* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */
+static const u32 exynos5433_retention_regs[] = {
+	EXYNOS5433_PAD_RETENTION_TOP_OPTION,
+	EXYNOS5433_PAD_RETENTION_UART_OPTION,
+	EXYNOS5433_PAD_RETENTION_EBIA_OPTION,
+	EXYNOS5433_PAD_RETENTION_EBIB_OPTION,
+	EXYNOS5433_PAD_RETENTION_SPI_OPTION,
+	EXYNOS5433_PAD_RETENTION_MIF_OPTION,
+	EXYNOS5433_PAD_RETENTION_USBXTI_OPTION,
+	EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION,
+	EXYNOS5433_PAD_RETENTION_UFS_OPTION,
+	EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION,
+};
+
+static const struct samsung_retention_data exynos5433_retention_data __initconst = {
+	.regs	 = exynos5433_retention_regs,
+	.nr_regs = ARRAY_SIZE(exynos5433_retention_regs),
+	.value	 = EXYNOS_WAKEUP_FROM_LOWPWR,
+	.refcnt	 = &exynos_shared_retention_refcnt,
+	.init	 = exynos_retention_init,
+};
+
+/* PMU retention control for audio pins can be tied to audio pin bank */
+static const u32 exynos5433_audio_retention_regs[] = {
+	EXYNOS5433_PAD_RETENTION_AUD_OPTION,
+};
+
+static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = {
+	.regs	 = exynos5433_audio_retention_regs,
+	.nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs),
+	.value	 = EXYNOS_WAKEUP_FROM_LOWPWR,
+	.init	 = exynos_retention_init,
+};
+
+/* PMU retention control for mmc pins can be tied to fsys pin bank */
+static const u32 exynos5433_fsys_retention_regs[] = {
+	EXYNOS5433_PAD_RETENTION_MMC0_OPTION,
+	EXYNOS5433_PAD_RETENTION_MMC1_OPTION,
+	EXYNOS5433_PAD_RETENTION_MMC2_OPTION,
+};
+
+static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = {
+	.regs	 = exynos5433_fsys_retention_regs,
+	.nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs),
+	.value	 = EXYNOS_WAKEUP_FROM_LOWPWR,
+	.init	 = exynos_retention_init,
+};
+
 /*
  * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
  * ten gpio/pin-mux/pinconfig controllers.
@@ -1564,6 +1612,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
 		.nr_ext_resources = 1,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 1 data */
 		.pin_banks	= exynos5433_pin_banks1,
@@ -1571,6 +1620,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_audio_retention_data,
 	}, {
 		/* pin-controller instance 2 data */
 		.pin_banks	= exynos5433_pin_banks2,
@@ -1578,6 +1628,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 3 data */
 		.pin_banks	= exynos5433_pin_banks3,
@@ -1585,6 +1636,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 4 data */
 		.pin_banks	= exynos5433_pin_banks4,
@@ -1592,6 +1644,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 5 data */
 		.pin_banks	= exynos5433_pin_banks5,
@@ -1599,6 +1652,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_fsys_retention_data,
 	}, {
 		/* pin-controller instance 6 data */
 		.pin_banks	= exynos5433_pin_banks6,
@@ -1606,6 +1660,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 7 data */
 		.pin_banks	= exynos5433_pin_banks7,
@@ -1613,6 +1668,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 8 data */
 		.pin_banks	= exynos5433_pin_banks8,
@@ -1620,6 +1676,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 9 data */
 		.pin_banks	= exynos5433_pin_banks9,
@@ -1627,6 +1684,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	},
 };
 
diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h
index d30186e2b609..86f24b633e11 100644
--- a/include/linux/soc/samsung/exynos-regs-pmu.h
+++ b/include/linux/soc/samsung/exynos-regs-pmu.h
@@ -690,4 +690,20 @@
 					 | EXYNOS5420_KFC_USE_STANDBY_WFI2  \
 					 | EXYNOS5420_KFC_USE_STANDBY_WFI3)
 
+/* For EXYNOS5433 */
+#define EXYNOS5433_PAD_RETENTION_AUD_OPTION			(0x3028)
+#define EXYNOS5433_PAD_RETENTION_MMC2_OPTION			(0x30C8)
+#define EXYNOS5433_PAD_RETENTION_TOP_OPTION			(0x3108)
+#define EXYNOS5433_PAD_RETENTION_UART_OPTION			(0x3128)
+#define EXYNOS5433_PAD_RETENTION_MMC0_OPTION			(0x3148)
+#define EXYNOS5433_PAD_RETENTION_MMC1_OPTION			(0x3168)
+#define EXYNOS5433_PAD_RETENTION_EBIA_OPTION			(0x3188)
+#define EXYNOS5433_PAD_RETENTION_EBIB_OPTION			(0x31A8)
+#define EXYNOS5433_PAD_RETENTION_SPI_OPTION			(0x31C8)
+#define EXYNOS5433_PAD_RETENTION_MIF_OPTION			(0x31E8)
+#define EXYNOS5433_PAD_RETENTION_USBXTI_OPTION			(0x3228)
+#define EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION			(0x3248)
+#define EXYNOS5433_PAD_RETENTION_UFS_OPTION			(0x3268)
+#define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION		(0x32A8)
+
 #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */
-- 
1.9.1

[PATCH v2 3/8] pinctrl: samsung: Add support for pad retention control for Exynos5433 SoCs

[Marek Szyprowski]

This patch adds support for retention control for Exynos5433 SoCs. Three
groups of pins has been defined for retention control: common shared group
for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and
separate control for FSYS and AUD pin banks, for which PMU retention
registers match whole banks.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/pinctrl/samsung/pinctrl-exynos.c    | 58 +++++++++++++++++++++++++++++
 include/linux/soc/samsung/exynos-regs-pmu.h | 16 ++++++++
 2 files changed, 74 insertions(+)

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index fa3802970570..7b0e6cc35e04 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1551,6 +1551,54 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 	EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
 };
 
+/* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */
+static const u32 exynos5433_retention_regs[] = {
+	EXYNOS5433_PAD_RETENTION_TOP_OPTION,
+	EXYNOS5433_PAD_RETENTION_UART_OPTION,
+	EXYNOS5433_PAD_RETENTION_EBIA_OPTION,
+	EXYNOS5433_PAD_RETENTION_EBIB_OPTION,
+	EXYNOS5433_PAD_RETENTION_SPI_OPTION,
+	EXYNOS5433_PAD_RETENTION_MIF_OPTION,
+	EXYNOS5433_PAD_RETENTION_USBXTI_OPTION,
+	EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION,
+	EXYNOS5433_PAD_RETENTION_UFS_OPTION,
+	EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION,
+};
+
+static const struct samsung_retention_data exynos5433_retention_data __initconst = {
+	.regs	 = exynos5433_retention_regs,
+	.nr_regs = ARRAY_SIZE(exynos5433_retention_regs),
+	.value	 = EXYNOS_WAKEUP_FROM_LOWPWR,
+	.refcnt	 = &exynos_shared_retention_refcnt,
+	.init	 = exynos_retention_init,
+};
+
+/* PMU retention control for audio pins can be tied to audio pin bank */
+static const u32 exynos5433_audio_retention_regs[] = {
+	EXYNOS5433_PAD_RETENTION_AUD_OPTION,
+};
+
+static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = {
+	.regs	 = exynos5433_audio_retention_regs,
+	.nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs),
+	.value	 = EXYNOS_WAKEUP_FROM_LOWPWR,
+	.init	 = exynos_retention_init,
+};
+
+/* PMU retention control for mmc pins can be tied to fsys pin bank */
+static const u32 exynos5433_fsys_retention_regs[] = {
+	EXYNOS5433_PAD_RETENTION_MMC0_OPTION,
+	EXYNOS5433_PAD_RETENTION_MMC1_OPTION,
+	EXYNOS5433_PAD_RETENTION_MMC2_OPTION,
+};
+
+static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = {
+	.regs	 = exynos5433_fsys_retention_regs,
+	.nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs),
+	.value	 = EXYNOS_WAKEUP_FROM_LOWPWR,
+	.init	 = exynos_retention_init,
+};
+
 /*
  * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
  * ten gpio/pin-mux/pinconfig controllers.
@@ -1564,6 +1612,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
 		.nr_ext_resources = 1,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 1 data */
 		.pin_banks	= exynos5433_pin_banks1,
@@ -1571,6 +1620,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_audio_retention_data,
 	}, {
 		/* pin-controller instance 2 data */
 		.pin_banks	= exynos5433_pin_banks2,
@@ -1578,6 +1628,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 3 data */
 		.pin_banks	= exynos5433_pin_banks3,
@@ -1585,6 +1636,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 4 data */
 		.pin_banks	= exynos5433_pin_banks4,
@@ -1592,6 +1644,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 5 data */
 		.pin_banks	= exynos5433_pin_banks5,
@@ -1599,6 +1652,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_fsys_retention_data,
 	}, {
 		/* pin-controller instance 6 data */
 		.pin_banks	= exynos5433_pin_banks6,
@@ -1606,6 +1660,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 7 data */
 		.pin_banks	= exynos5433_pin_banks7,
@@ -1613,6 +1668,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 8 data */
 		.pin_banks	= exynos5433_pin_banks8,
@@ -1620,6 +1676,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 9 data */
 		.pin_banks	= exynos5433_pin_banks9,
@@ -1627,6 +1684,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	},
 };
 
diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h
index d30186e2b609..86f24b633e11 100644
--- a/include/linux/soc/samsung/exynos-regs-pmu.h
+++ b/include/linux/soc/samsung/exynos-regs-pmu.h
@@ -690,4 +690,20 @@
 					 | EXYNOS5420_KFC_USE_STANDBY_WFI2  \
 					 | EXYNOS5420_KFC_USE_STANDBY_WFI3)
 
+/* For EXYNOS5433 */
+#define EXYNOS5433_PAD_RETENTION_AUD_OPTION			(0x3028)
+#define EXYNOS5433_PAD_RETENTION_MMC2_OPTION			(0x30C8)
+#define EXYNOS5433_PAD_RETENTION_TOP_OPTION			(0x3108)
+#define EXYNOS5433_PAD_RETENTION_UART_OPTION			(0x3128)
+#define EXYNOS5433_PAD_RETENTION_MMC0_OPTION			(0x3148)
+#define EXYNOS5433_PAD_RETENTION_MMC1_OPTION			(0x3168)
+#define EXYNOS5433_PAD_RETENTION_EBIA_OPTION			(0x3188)
+#define EXYNOS5433_PAD_RETENTION_EBIB_OPTION			(0x31A8)
+#define EXYNOS5433_PAD_RETENTION_SPI_OPTION			(0x31C8)
+#define EXYNOS5433_PAD_RETENTION_MIF_OPTION			(0x31E8)
+#define EXYNOS5433_PAD_RETENTION_USBXTI_OPTION			(0x3228)
+#define EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION			(0x3248)
+#define EXYNOS5433_PAD_RETENTION_UFS_OPTION			(0x3268)
+#define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION		(0x32A8)
+
 #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */
-- 
1.9.1

Re: [PATCH v2 3/8] pinctrl: samsung: Add support for pad retention control for Exynos5433 SoCs

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:33:49AM +0100, Marek Szyprowski wrote:
> This patch adds support for retention control for Exynos5433 SoCs. Three
> groups of pins has been defined for retention control: common shared group
> for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and
> separate control for FSYS and AUD pin banks, for which PMU retention
> registers match whole banks.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/pinctrl/samsung/pinctrl-exynos.c    | 58 +++++++++++++++++++++++++++++
>  include/linux/soc/samsung/exynos-regs-pmu.h | 16 ++++++++
>  2 files changed, 74 insertions(+)
>  		.eint_gpio_init = exynos_eint_gpio_init,

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

[PATCH v2 3/8] pinctrl: samsung: Add support for pad retention control for Exynos5433 SoCs

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:33:49AM +0100, Marek Szyprowski wrote:
> This patch adds support for retention control for Exynos5433 SoCs. Three
> groups of pins has been defined for retention control: common shared group
> for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and
> separate control for FSYS and AUD pin banks, for which PMU retention
> registers match whole banks.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/pinctrl/samsung/pinctrl-exynos.c    | 58 +++++++++++++++++++++++++++++
>  include/linux/soc/samsung/exynos-regs-pmu.h | 16 ++++++++
>  2 files changed, 74 insertions(+)
>  		.eint_gpio_init = exynos_eint_gpio_init,

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

Re: [PATCH v2 3/8] pinctrl: samsung: Add support for pad retention control for Exynos5433 SoCs

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:48:11PM +0200, Krzysztof Kozlowski wrote:
> On Thu, Jan 26, 2017 at 09:33:49AM +0100, Marek Szyprowski wrote:
> > This patch adds support for retention control for Exynos5433 SoCs. Three
> > groups of pins has been defined for retention control: common shared group
> > for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and
> > separate control for FSYS and AUD pin banks, for which PMU retention
> > registers match whole banks.
> > 
> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> > ---
> >  drivers/pinctrl/samsung/pinctrl-exynos.c    | 58 +++++++++++++++++++++++++++++
> >  include/linux/soc/samsung/exynos-regs-pmu.h | 16 ++++++++

I already have some non-conflicting changes to exynos-regs-pmu.h in my
branch. Now I want to add some more which will create conflicts.

How about splitting the header to separate patch, so I will take it to
my exynos-pmu branch?

Best regards,
Krzysztof

[PATCH v2 3/8] pinctrl: samsung: Add support for pad retention control for Exynos5433 SoCs

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:48:11PM +0200, Krzysztof Kozlowski wrote:
> On Thu, Jan 26, 2017 at 09:33:49AM +0100, Marek Szyprowski wrote:
> > This patch adds support for retention control for Exynos5433 SoCs. Three
> > groups of pins has been defined for retention control: common shared group
> > for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and
> > separate control for FSYS and AUD pin banks, for which PMU retention
> > registers match whole banks.
> > 
> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> > ---
> >  drivers/pinctrl/samsung/pinctrl-exynos.c    | 58 +++++++++++++++++++++++++++++
> >  include/linux/soc/samsung/exynos-regs-pmu.h | 16 ++++++++

I already have some non-conflicting changes to exynos-regs-pmu.h in my
branch. Now I want to add some more which will create conflicts.

How about splitting the header to separate patch, so I will take it to
my exynos-pmu branch?

Best regards,
Krzysztof

Re: [PATCH v2 3/8] pinctrl: samsung: Add support for pad retention control for Exynos5433 SoCs

[Marek Szyprowski]

Hi Krzysztof,

On 2017-01-27 19:02, Krzysztof Kozlowski wrote:
> On Thu, Jan 26, 2017 at 09:48:11PM +0200, Krzysztof Kozlowski wrote:
>> On Thu, Jan 26, 2017 at 09:33:49AM +0100, Marek Szyprowski wrote:
>>> This patch adds support for retention control for Exynos5433 SoCs. Three
>>> groups of pins has been defined for retention control: common shared group
>>> for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and
>>> separate control for FSYS and AUD pin banks, for which PMU retention
>>> registers match whole banks.
>>>
>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>> ---
>>>   drivers/pinctrl/samsung/pinctrl-exynos.c    | 58 +++++++++++++++++++++++++++++
>>>   include/linux/soc/samsung/exynos-regs-pmu.h | 16 ++++++++
> I already have some non-conflicting changes to exynos-regs-pmu.h in my
> branch. Now I want to add some more which will create conflicts.
>
> How about splitting the header to separate patch, so I will take it to
> my exynos-pmu branch?

Okay, I will split this into 2 patches.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

[PATCH v2 3/8] pinctrl: samsung: Add support for pad retention control for Exynos5433 SoCs

[Marek Szyprowski]

Hi Krzysztof,

On 2017-01-27 19:02, Krzysztof Kozlowski wrote:
> On Thu, Jan 26, 2017 at 09:48:11PM +0200, Krzysztof Kozlowski wrote:
>> On Thu, Jan 26, 2017 at 09:33:49AM +0100, Marek Szyprowski wrote:
>>> This patch adds support for retention control for Exynos5433 SoCs. Three
>>> groups of pins has been defined for retention control: common shared group
>>> for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and
>>> separate control for FSYS and AUD pin banks, for which PMU retention
>>> registers match whole banks.
>>>
>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>> ---
>>>   drivers/pinctrl/samsung/pinctrl-exynos.c    | 58 +++++++++++++++++++++++++++++
>>>   include/linux/soc/samsung/exynos-regs-pmu.h | 16 ++++++++
> I already have some non-conflicting changes to exynos-regs-pmu.h in my
> branch. Now I want to add some more which will create conflicts.
>
> How about splitting the header to separate patch, so I will take it to
> my exynos-pmu branch?

Okay, I will split this into 2 patches.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH v2 3/8] pinctrl: samsung: Add support for pad retention control for Exynos5433 SoCs

[Marek Szyprowski]

Hi Krzysztof,

On 2017-01-27 19:02, Krzysztof Kozlowski wrote:
> On Thu, Jan 26, 2017 at 09:48:11PM +0200, Krzysztof Kozlowski wrote:
>> On Thu, Jan 26, 2017 at 09:33:49AM +0100, Marek Szyprowski wrote:
>>> This patch adds support for retention control for Exynos5433 SoCs. Three
>>> groups of pins has been defined for retention control: common shared group
>>> for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and
>>> separate control for FSYS and AUD pin banks, for which PMU retention
>>> registers match whole banks.
>>>
>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>> ---
>>>   drivers/pinctrl/samsung/pinctrl-exynos.c    | 58 +++++++++++++++++++++++++++++
>>>   include/linux/soc/samsung/exynos-regs-pmu.h | 16 ++++++++
> I already have some non-conflicting changes to exynos-regs-pmu.h in my
> branch. Now I want to add some more which will create conflicts.
>
> How about splitting the header to separate patch, so I will take it to
> my exynos-pmu branch?

Okay, I will split this into 2 patches.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH v2 3/8] pinctrl: samsung: Add support for pad retention control for Exynos5433 SoCs

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:33:49AM +0100, Marek Szyprowski wrote:
> This patch adds support for retention control for Exynos5433 SoCs. Three
> groups of pins has been defined for retention control: common shared group
> for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and
> separate control for FSYS and AUD pin banks, for which PMU retention
> registers match whole banks.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/pinctrl/samsung/pinctrl-exynos.c    | 58 +++++++++++++++++++++++++++++
>  include/linux/soc/samsung/exynos-regs-pmu.h | 16 ++++++++
>  2 files changed, 74 insertions(+)
> 

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

[PATCH v2 3/8] pinctrl: samsung: Add support for pad retention control for Exynos5433 SoCs

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:33:49AM +0100, Marek Szyprowski wrote:
> This patch adds support for retention control for Exynos5433 SoCs. Three
> groups of pins has been defined for retention control: common shared group
> for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and
> separate control for FSYS and AUD pin banks, for which PMU retention
> registers match whole banks.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/pinctrl/samsung/pinctrl-exynos.c    | 58 +++++++++++++++++++++++++++++
>  include/linux/soc/samsung/exynos-regs-pmu.h | 16 ++++++++
>  2 files changed, 74 insertions(+)
> 

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

[PATCH v2 4/8] arm64: dts: exynos: Add clocks to Exynos5433 LPASS module

[Marek Szyprowski]

Exynos5433 LPASS module requires some clocks for proper operation with
power domain.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 57c7bbeb65a7..16072c1c3ed3 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -1494,6 +1494,8 @@
 		audio-subsystem@11400000 {
 			compatible = "samsung,exynos5433-lpass";
 			reg = <0x11400000 0x100>, <0x11500000 0x08>;
+			clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
+			clock-names = "sfr0_ctrl";
 			samsung,pmu-syscon = <&pmu_system_controller>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-- 
1.9.1

[PATCH v2 4/8] arm64: dts: exynos: Add clocks to Exynos5433 LPASS module

[Marek Szyprowski]

Exynos5433 LPASS module requires some clocks for proper operation with
power domain.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 57c7bbeb65a7..16072c1c3ed3 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -1494,6 +1494,8 @@
 		audio-subsystem at 11400000 {
 			compatible = "samsung,exynos5433-lpass";
 			reg = <0x11400000 0x100>, <0x11500000 0x08>;
+			clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
+			clock-names = "sfr0_ctrl";
 			samsung,pmu-syscon = <&pmu_system_controller>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-- 
1.9.1

Re: [PATCH v2 4/8] arm64: dts: exynos: Add clocks to Exynos5433 LPASS module

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:33:50AM +0100, Marek Szyprowski wrote:
> Exynos5433 LPASS module requires some clocks for proper operation with
> power domain.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
> 

Thanks, applied to the same branch as other Exynos5433 changes. I can
provide a tag with it, just give me a couple of days. Anyway it will be
good if dependencies like this enter v4.11.

Best regards,
Krzysztof

[PATCH v2 4/8] arm64: dts: exynos: Add clocks to Exynos5433 LPASS module

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:33:50AM +0100, Marek Szyprowski wrote:
> Exynos5433 LPASS module requires some clocks for proper operation with
> power domain.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
> 

Thanks, applied to the same branch as other Exynos5433 changes. I can
provide a tag with it, just give me a couple of days. Anyway it will be
good if dependencies like this enter v4.11.

Best regards,
Krzysztof

[PATCH v2 5/8] mfd: exynos-lpass: Remove pad retention control

[Marek Szyprowski]

Pad retention should be controlled from pin control driver, so remove it
from Exynos LPASS driver. After this change, no more access to PMU regmap
is needed, so remove also the code for handling PMU regmap.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 .../bindings/mfd/samsung,exynos5433-lpass.txt           |  2 --
 drivers/mfd/exynos-lpass.c                              | 17 -----------------
 include/linux/mfd/syscon/exynos5-pmu.h                  |  3 ---
 3 files changed, 22 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
index c110e118b79f..a8deaee82c44 100644
--- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
+++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
@@ -5,7 +5,6 @@ Required properties:
  - compatible		: "samsung,exynos5433-lpass"
  - reg			: should contain the LPASS top SFR region location
 			  and size
- - samsung,pmu-syscon	: the phandle to the Power Management Unit node
  - #address-cells	: should be 1
  - #size-cells		: should be 1
  - ranges		: must be present
@@ -25,7 +24,6 @@ Example:
 audio-subsystem {
 	compatible = "samsung,exynos5433-lpass";
 	reg = <0x11400000 0x100>, <0x11500000 0x08>;
-	samsung,pmu-syscon = <&pmu_system_controller>;
 	#address-cells = <1>;
 	#size-cells = <1>;
 	ranges;
diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
index 2e064fb8826f..17915daa2e80 100644
--- a/drivers/mfd/exynos-lpass.c
+++ b/drivers/mfd/exynos-lpass.c
@@ -18,7 +18,6 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/mfd/syscon.h>
-#include <linux/mfd/syscon/exynos5-pmu.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
@@ -51,8 +50,6 @@
 #define  LPASS_INTR_SFR			BIT(0)
 
 struct exynos_lpass {
-	/* pointer to the Power Management Unit regmap */
-	struct regmap *pmu;
 	/* pointer to the LPASS TOP regmap */
 	struct regmap *top;
 };
@@ -81,10 +78,6 @@ static void exynos_lpass_enable(struct exynos_lpass *lpass)
 	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
 		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
 
-	/* Activate related PADs from retention state */
-	regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION,
-		     EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR);
-
 	exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
 	exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
 	exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
@@ -95,9 +88,6 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass)
 	/* Mask any unmasked IP interrupt sources */
 	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
 	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
-
-	/* Deactivate related PADs from retention state */
-	regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION, 0);
 }
 
 static const struct regmap_config exynos_lpass_reg_conf = {
@@ -131,13 +121,6 @@ static int exynos_lpass_probe(struct platform_device *pdev)
 		return PTR_ERR(lpass->top);
 	}
 
-	lpass->pmu = syscon_regmap_lookup_by_phandle(dev->of_node,
-						"samsung,pmu-syscon");
-	if (IS_ERR(lpass->pmu)) {
-		dev_err(dev, "Failed to lookup PMU regmap\n");
-		return PTR_ERR(lpass->pmu);
-	}
-
 	platform_set_drvdata(pdev, lpass);
 	exynos_lpass_enable(lpass);
 
diff --git a/include/linux/mfd/syscon/exynos5-pmu.h b/include/linux/mfd/syscon/exynos5-pmu.h
index c28ff21ca4d2..0622ae86f9db 100644
--- a/include/linux/mfd/syscon/exynos5-pmu.h
+++ b/include/linux/mfd/syscon/exynos5-pmu.h
@@ -46,7 +46,4 @@
 #define EXYNOS5_MIPI_PHY_S_RESETN		BIT(1)
 #define EXYNOS5_MIPI_PHY_M_RESETN		BIT(2)
 
-#define EXYNOS5433_PAD_RETENTION_AUD_OPTION		(0x3028)
-#define EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR	BIT(28)
-
 #endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */
-- 
1.9.1

[PATCH v2 5/8] mfd: exynos-lpass: Remove pad retention control

[Marek Szyprowski]

Pad retention should be controlled from pin control driver, so remove it
from Exynos LPASS driver. After this change, no more access to PMU regmap
is needed, so remove also the code for handling PMU regmap.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 .../bindings/mfd/samsung,exynos5433-lpass.txt           |  2 --
 drivers/mfd/exynos-lpass.c                              | 17 -----------------
 include/linux/mfd/syscon/exynos5-pmu.h                  |  3 ---
 3 files changed, 22 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
index c110e118b79f..a8deaee82c44 100644
--- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
+++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
@@ -5,7 +5,6 @@ Required properties:
  - compatible		: "samsung,exynos5433-lpass"
  - reg			: should contain the LPASS top SFR region location
 			  and size
- - samsung,pmu-syscon	: the phandle to the Power Management Unit node
  - #address-cells	: should be 1
  - #size-cells		: should be 1
  - ranges		: must be present
@@ -25,7 +24,6 @@ Example:
 audio-subsystem {
 	compatible = "samsung,exynos5433-lpass";
 	reg = <0x11400000 0x100>, <0x11500000 0x08>;
-	samsung,pmu-syscon = <&pmu_system_controller>;
 	#address-cells = <1>;
 	#size-cells = <1>;
 	ranges;
diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
index 2e064fb8826f..17915daa2e80 100644
--- a/drivers/mfd/exynos-lpass.c
+++ b/drivers/mfd/exynos-lpass.c
@@ -18,7 +18,6 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/mfd/syscon.h>
-#include <linux/mfd/syscon/exynos5-pmu.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
@@ -51,8 +50,6 @@
 #define  LPASS_INTR_SFR			BIT(0)
 
 struct exynos_lpass {
-	/* pointer to the Power Management Unit regmap */
-	struct regmap *pmu;
 	/* pointer to the LPASS TOP regmap */
 	struct regmap *top;
 };
@@ -81,10 +78,6 @@ static void exynos_lpass_enable(struct exynos_lpass *lpass)
 	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
 		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
 
-	/* Activate related PADs from retention state */
-	regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION,
-		     EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR);
-
 	exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
 	exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
 	exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
@@ -95,9 +88,6 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass)
 	/* Mask any unmasked IP interrupt sources */
 	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
 	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
-
-	/* Deactivate related PADs from retention state */
-	regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION, 0);
 }
 
 static const struct regmap_config exynos_lpass_reg_conf = {
@@ -131,13 +121,6 @@ static int exynos_lpass_probe(struct platform_device *pdev)
 		return PTR_ERR(lpass->top);
 	}
 
-	lpass->pmu = syscon_regmap_lookup_by_phandle(dev->of_node,
-						"samsung,pmu-syscon");
-	if (IS_ERR(lpass->pmu)) {
-		dev_err(dev, "Failed to lookup PMU regmap\n");
-		return PTR_ERR(lpass->pmu);
-	}
-
 	platform_set_drvdata(pdev, lpass);
 	exynos_lpass_enable(lpass);
 
diff --git a/include/linux/mfd/syscon/exynos5-pmu.h b/include/linux/mfd/syscon/exynos5-pmu.h
index c28ff21ca4d2..0622ae86f9db 100644
--- a/include/linux/mfd/syscon/exynos5-pmu.h
+++ b/include/linux/mfd/syscon/exynos5-pmu.h
@@ -46,7 +46,4 @@
 #define EXYNOS5_MIPI_PHY_S_RESETN		BIT(1)
 #define EXYNOS5_MIPI_PHY_M_RESETN		BIT(2)
 
-#define EXYNOS5433_PAD_RETENTION_AUD_OPTION		(0x3028)
-#define EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR	BIT(28)
-
 #endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */
-- 
1.9.1

Re: [PATCH v2 5/8] mfd: exynos-lpass: Remove pad retention control

[Sylwester Nawrocki]

On 01/26/2017 09:33 AM, Marek Szyprowski wrote:
> Pad retention should be controlled from pin control driver, so remove it
> from Exynos LPASS driver. After this change, no more access to PMU regmap
> is needed, so remove also the code for handling PMU regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Patches 5/8...8/8:

Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

[PATCH v2 5/8] mfd: exynos-lpass: Remove pad retention control

[Sylwester Nawrocki]

On 01/26/2017 09:33 AM, Marek Szyprowski wrote:
> Pad retention should be controlled from pin control driver, so remove it
> from Exynos LPASS driver. After this change, no more access to PMU regmap
> is needed, so remove also the code for handling PMU regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Patches 5/8...8/8:

Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

Re: [PATCH v2 5/8] mfd: exynos-lpass: Remove pad retention control

[Rob Herring]

On Thu, Jan 26, 2017 at 09:33:51AM +0100, Marek Szyprowski wrote:
> Pad retention should be controlled from pin control driver, so remove it
> from Exynos LPASS driver. After this change, no more access to PMU regmap
> is needed, so remove also the code for handling PMU regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  .../bindings/mfd/samsung,exynos5433-lpass.txt           |  2 --

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/mfd/exynos-lpass.c                              | 17 -----------------
>  include/linux/mfd/syscon/exynos5-pmu.h                  |  3 ---
>  3 files changed, 22 deletions(-)

[PATCH v2 5/8] mfd: exynos-lpass: Remove pad retention control

[Rob Herring]

On Thu, Jan 26, 2017 at 09:33:51AM +0100, Marek Szyprowski wrote:
> Pad retention should be controlled from pin control driver, so remove it
> from Exynos LPASS driver. After this change, no more access to PMU regmap
> is needed, so remove also the code for handling PMU regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  .../bindings/mfd/samsung,exynos5433-lpass.txt           |  2 --

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/mfd/exynos-lpass.c                              | 17 -----------------
>  include/linux/mfd/syscon/exynos5-pmu.h                  |  3 ---
>  3 files changed, 22 deletions(-)

Re: [PATCH v2 5/8] mfd: exynos-lpass: Remove pad retention control

[Lee Jones]

On Thu, 26 Jan 2017, Marek Szyprowski wrote:

> Pad retention should be controlled from pin control driver, so remove it
> from Exynos LPASS driver. After this change, no more access to PMU regmap
> is needed, so remove also the code for handling PMU regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  .../bindings/mfd/samsung,exynos5433-lpass.txt           |  2 --
>  drivers/mfd/exynos-lpass.c                              | 17 -----------------
>  include/linux/mfd/syscon/exynos5-pmu.h                  |  3 ---
>  3 files changed, 22 deletions(-)

Love the diff! :)

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
  
> diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> index c110e118b79f..a8deaee82c44 100644
> --- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> +++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> @@ -5,7 +5,6 @@ Required properties:
>   - compatible		: "samsung,exynos5433-lpass"
>   - reg			: should contain the LPASS top SFR region location
>  			  and size
> - - samsung,pmu-syscon	: the phandle to the Power Management Unit node
>   - #address-cells	: should be 1
>   - #size-cells		: should be 1
>   - ranges		: must be present
> @@ -25,7 +24,6 @@ Example:
>  audio-subsystem {
>  	compatible = "samsung,exynos5433-lpass";
>  	reg = <0x11400000 0x100>, <0x11500000 0x08>;
> -	samsung,pmu-syscon = <&pmu_system_controller>;
>  	#address-cells = <1>;
>  	#size-cells = <1>;
>  	ranges;
> diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
> index 2e064fb8826f..17915daa2e80 100644
> --- a/drivers/mfd/exynos-lpass.c
> +++ b/drivers/mfd/exynos-lpass.c
> @@ -18,7 +18,6 @@
>  #include <linux/io.h>
>  #include <linux/module.h>
>  #include <linux/mfd/syscon.h>
> -#include <linux/mfd/syscon/exynos5-pmu.h>
>  #include <linux/of.h>
>  #include <linux/of_platform.h>
>  #include <linux/platform_device.h>
> @@ -51,8 +50,6 @@
>  #define  LPASS_INTR_SFR			BIT(0)
>  
>  struct exynos_lpass {
> -	/* pointer to the Power Management Unit regmap */
> -	struct regmap *pmu;
>  	/* pointer to the LPASS TOP regmap */
>  	struct regmap *top;
>  };
> @@ -81,10 +78,6 @@ static void exynos_lpass_enable(struct exynos_lpass *lpass)
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
>  		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
>  
> -	/* Activate related PADs from retention state */
> -	regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION,
> -		     EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR);
> -
>  	exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
>  	exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
>  	exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
> @@ -95,9 +88,6 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass)
>  	/* Mask any unmasked IP interrupt sources */
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
> -
> -	/* Deactivate related PADs from retention state */
> -	regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION, 0);
>  }
>  
>  static const struct regmap_config exynos_lpass_reg_conf = {
> @@ -131,13 +121,6 @@ static int exynos_lpass_probe(struct platform_device *pdev)
>  		return PTR_ERR(lpass->top);
>  	}
>  
> -	lpass->pmu = syscon_regmap_lookup_by_phandle(dev->of_node,
> -						"samsung,pmu-syscon");
> -	if (IS_ERR(lpass->pmu)) {
> -		dev_err(dev, "Failed to lookup PMU regmap\n");
> -		return PTR_ERR(lpass->pmu);
> -	}
> -
>  	platform_set_drvdata(pdev, lpass);
>  	exynos_lpass_enable(lpass);
>  
> diff --git a/include/linux/mfd/syscon/exynos5-pmu.h b/include/linux/mfd/syscon/exynos5-pmu.h
> index c28ff21ca4d2..0622ae86f9db 100644
> --- a/include/linux/mfd/syscon/exynos5-pmu.h
> +++ b/include/linux/mfd/syscon/exynos5-pmu.h
> @@ -46,7 +46,4 @@
>  #define EXYNOS5_MIPI_PHY_S_RESETN		BIT(1)
>  #define EXYNOS5_MIPI_PHY_M_RESETN		BIT(2)
>  
> -#define EXYNOS5433_PAD_RETENTION_AUD_OPTION		(0x3028)
> -#define EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR	BIT(28)
> -
>  #endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

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[PATCH v2 5/8] mfd: exynos-lpass: Remove pad retention control

[Lee Jones]

On Thu, 26 Jan 2017, Marek Szyprowski wrote:

> Pad retention should be controlled from pin control driver, so remove it
> from Exynos LPASS driver. After this change, no more access to PMU regmap
> is needed, so remove also the code for handling PMU regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  .../bindings/mfd/samsung,exynos5433-lpass.txt           |  2 --
>  drivers/mfd/exynos-lpass.c                              | 17 -----------------
>  include/linux/mfd/syscon/exynos5-pmu.h                  |  3 ---
>  3 files changed, 22 deletions(-)

Love the diff! :)

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
  
> diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> index c110e118b79f..a8deaee82c44 100644
> --- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> +++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> @@ -5,7 +5,6 @@ Required properties:
>   - compatible		: "samsung,exynos5433-lpass"
>   - reg			: should contain the LPASS top SFR region location
>  			  and size
> - - samsung,pmu-syscon	: the phandle to the Power Management Unit node
>   - #address-cells	: should be 1
>   - #size-cells		: should be 1
>   - ranges		: must be present
> @@ -25,7 +24,6 @@ Example:
>  audio-subsystem {
>  	compatible = "samsung,exynos5433-lpass";
>  	reg = <0x11400000 0x100>, <0x11500000 0x08>;
> -	samsung,pmu-syscon = <&pmu_system_controller>;
>  	#address-cells = <1>;
>  	#size-cells = <1>;
>  	ranges;
> diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
> index 2e064fb8826f..17915daa2e80 100644
> --- a/drivers/mfd/exynos-lpass.c
> +++ b/drivers/mfd/exynos-lpass.c
> @@ -18,7 +18,6 @@
>  #include <linux/io.h>
>  #include <linux/module.h>
>  #include <linux/mfd/syscon.h>
> -#include <linux/mfd/syscon/exynos5-pmu.h>
>  #include <linux/of.h>
>  #include <linux/of_platform.h>
>  #include <linux/platform_device.h>
> @@ -51,8 +50,6 @@
>  #define  LPASS_INTR_SFR			BIT(0)
>  
>  struct exynos_lpass {
> -	/* pointer to the Power Management Unit regmap */
> -	struct regmap *pmu;
>  	/* pointer to the LPASS TOP regmap */
>  	struct regmap *top;
>  };
> @@ -81,10 +78,6 @@ static void exynos_lpass_enable(struct exynos_lpass *lpass)
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
>  		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
>  
> -	/* Activate related PADs from retention state */
> -	regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION,
> -		     EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR);
> -
>  	exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
>  	exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
>  	exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
> @@ -95,9 +88,6 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass)
>  	/* Mask any unmasked IP interrupt sources */
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
> -
> -	/* Deactivate related PADs from retention state */
> -	regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION, 0);
>  }
>  
>  static const struct regmap_config exynos_lpass_reg_conf = {
> @@ -131,13 +121,6 @@ static int exynos_lpass_probe(struct platform_device *pdev)
>  		return PTR_ERR(lpass->top);
>  	}
>  
> -	lpass->pmu = syscon_regmap_lookup_by_phandle(dev->of_node,
> -						"samsung,pmu-syscon");
> -	if (IS_ERR(lpass->pmu)) {
> -		dev_err(dev, "Failed to lookup PMU regmap\n");
> -		return PTR_ERR(lpass->pmu);
> -	}
> -
>  	platform_set_drvdata(pdev, lpass);
>  	exynos_lpass_enable(lpass);
>  
> diff --git a/include/linux/mfd/syscon/exynos5-pmu.h b/include/linux/mfd/syscon/exynos5-pmu.h
> index c28ff21ca4d2..0622ae86f9db 100644
> --- a/include/linux/mfd/syscon/exynos5-pmu.h
> +++ b/include/linux/mfd/syscon/exynos5-pmu.h
> @@ -46,7 +46,4 @@
>  #define EXYNOS5_MIPI_PHY_S_RESETN		BIT(1)
>  #define EXYNOS5_MIPI_PHY_M_RESETN		BIT(2)
>  
> -#define EXYNOS5433_PAD_RETENTION_AUD_OPTION		(0x3028)
> -#define EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR	BIT(28)
> -
>  #endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v2 5/8] mfd: exynos-lpass: Remove pad retention control

[Lee Jones]

On Thu, 26 Jan 2017, Marek Szyprowski wrote:

> Pad retention should be controlled from pin control driver, so remove it
> from Exynos LPASS driver. After this change, no more access to PMU regmap
> is needed, so remove also the code for handling PMU regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  .../bindings/mfd/samsung,exynos5433-lpass.txt           |  2 --
>  drivers/mfd/exynos-lpass.c                              | 17 -----------------
>  include/linux/mfd/syscon/exynos5-pmu.h                  |  3 ---
>  3 files changed, 22 deletions(-)

Love the diff! :)

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
  
> diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> index c110e118b79f..a8deaee82c44 100644
> --- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> +++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> @@ -5,7 +5,6 @@ Required properties:
>   - compatible		: "samsung,exynos5433-lpass"
>   - reg			: should contain the LPASS top SFR region location
>  			  and size
> - - samsung,pmu-syscon	: the phandle to the Power Management Unit node
>   - #address-cells	: should be 1
>   - #size-cells		: should be 1
>   - ranges		: must be present
> @@ -25,7 +24,6 @@ Example:
>  audio-subsystem {
>  	compatible = "samsung,exynos5433-lpass";
>  	reg = <0x11400000 0x100>, <0x11500000 0x08>;
> -	samsung,pmu-syscon = <&pmu_system_controller>;
>  	#address-cells = <1>;
>  	#size-cells = <1>;
>  	ranges;
> diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
> index 2e064fb8826f..17915daa2e80 100644
> --- a/drivers/mfd/exynos-lpass.c
> +++ b/drivers/mfd/exynos-lpass.c
> @@ -18,7 +18,6 @@
>  #include <linux/io.h>
>  #include <linux/module.h>
>  #include <linux/mfd/syscon.h>
> -#include <linux/mfd/syscon/exynos5-pmu.h>
>  #include <linux/of.h>
>  #include <linux/of_platform.h>
>  #include <linux/platform_device.h>
> @@ -51,8 +50,6 @@
>  #define  LPASS_INTR_SFR			BIT(0)
>  
>  struct exynos_lpass {
> -	/* pointer to the Power Management Unit regmap */
> -	struct regmap *pmu;
>  	/* pointer to the LPASS TOP regmap */
>  	struct regmap *top;
>  };
> @@ -81,10 +78,6 @@ static void exynos_lpass_enable(struct exynos_lpass *lpass)
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
>  		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
>  
> -	/* Activate related PADs from retention state */
> -	regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION,
> -		     EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR);
> -
>  	exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
>  	exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
>  	exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
> @@ -95,9 +88,6 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass)
>  	/* Mask any unmasked IP interrupt sources */
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
> -
> -	/* Deactivate related PADs from retention state */
> -	regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION, 0);
>  }
>  
>  static const struct regmap_config exynos_lpass_reg_conf = {
> @@ -131,13 +121,6 @@ static int exynos_lpass_probe(struct platform_device *pdev)
>  		return PTR_ERR(lpass->top);
>  	}
>  
> -	lpass->pmu = syscon_regmap_lookup_by_phandle(dev->of_node,
> -						"samsung,pmu-syscon");
> -	if (IS_ERR(lpass->pmu)) {
> -		dev_err(dev, "Failed to lookup PMU regmap\n");
> -		return PTR_ERR(lpass->pmu);
> -	}
> -
>  	platform_set_drvdata(pdev, lpass);
>  	exynos_lpass_enable(lpass);
>  
> diff --git a/include/linux/mfd/syscon/exynos5-pmu.h b/include/linux/mfd/syscon/exynos5-pmu.h
> index c28ff21ca4d2..0622ae86f9db 100644
> --- a/include/linux/mfd/syscon/exynos5-pmu.h
> +++ b/include/linux/mfd/syscon/exynos5-pmu.h
> @@ -46,7 +46,4 @@
>  #define EXYNOS5_MIPI_PHY_S_RESETN		BIT(1)
>  #define EXYNOS5_MIPI_PHY_M_RESETN		BIT(2)
>  
> -#define EXYNOS5433_PAD_RETENTION_AUD_OPTION		(0x3028)
> -#define EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR	BIT(28)
> -
>  #endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

[PATCH v2 6/8] mfd: exynos-lpass: Add support for clocks

[Marek Szyprowski]

Exynos LPASS requires some clocks to be enabled to make any access to its
registers. This patch adds code for handling such clocks. For current set
of registers it is enough to keep sfr0_ctrl clock enabled. Till now it
worked only because those clocks were enabled by bootloader and driver
probe() happened before they were disabled by clock core because of lack
of users. Handling those clocks is also needed to make it possible to
enable support for audio power domain.

This patch requires adding sfr0_ctrl clock to device tree.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 .../devicetree/bindings/mfd/samsung,exynos5433-lpass.txt       |  6 ++++++
 drivers/mfd/exynos-lpass.c                                     | 10 ++++++++++
 2 files changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
index a8deaee82c44..df664018c148 100644
--- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
+++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
@@ -5,6 +5,10 @@ Required properties:
  - compatible		: "samsung,exynos5433-lpass"
  - reg			: should contain the LPASS top SFR region location
 			  and size
+ - clock-names		: should contain following required clocks: "sfr0_ctrl"
+ - clocks		: should contain clock specifiers of all clocks, which
+			  input names have been specified in clock-names
+			  property, in same order.
  - #address-cells	: should be 1
  - #size-cells		: should be 1
  - ranges		: must be present
@@ -24,6 +28,8 @@ Example:
 audio-subsystem {
 	compatible = "samsung,exynos5433-lpass";
 	reg = <0x11400000 0x100>, <0x11500000 0x08>;
+	clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
+	clock-names = "sfr0_ctrl";
 	#address-cells = <1>;
 	#size-cells = <1>;
 	ranges;
diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
index 17915daa2e80..be264988bdc9 100644
--- a/drivers/mfd/exynos-lpass.c
+++ b/drivers/mfd/exynos-lpass.c
@@ -14,6 +14,7 @@
  * only version 2 as published by the Free Software Foundation.
  */
 
+#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/module.h>
@@ -52,6 +53,7 @@
 struct exynos_lpass {
 	/* pointer to the LPASS TOP regmap */
 	struct regmap *top;
+	struct clk *sfr0_clk;
 };
 
 static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
@@ -71,6 +73,8 @@ static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
 
 static void exynos_lpass_enable(struct exynos_lpass *lpass)
 {
+	clk_prepare_enable(lpass->sfr0_clk);
+
 	/* Unmask SFR, DMA and I2S interrupt */
 	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
 		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
@@ -88,6 +92,8 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass)
 	/* Mask any unmasked IP interrupt sources */
 	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
 	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
+
+	clk_disable_unprepare(lpass->sfr0_clk);
 }
 
 static const struct regmap_config exynos_lpass_reg_conf = {
@@ -114,6 +120,10 @@ static int exynos_lpass_probe(struct platform_device *pdev)
 	if (IS_ERR(base_top))
 		return PTR_ERR(base_top);
 
+	lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl");
+	if (IS_ERR(lpass->sfr0_clk))
+		return PTR_ERR(lpass->sfr0_clk);
+
 	lpass->top = regmap_init_mmio(dev, base_top,
 					&exynos_lpass_reg_conf);
 	if (IS_ERR(lpass->top)) {
-- 
1.9.1

[PATCH v2 6/8] mfd: exynos-lpass: Add support for clocks

[Marek Szyprowski]

Exynos LPASS requires some clocks to be enabled to make any access to its
registers. This patch adds code for handling such clocks. For current set
of registers it is enough to keep sfr0_ctrl clock enabled. Till now it
worked only because those clocks were enabled by bootloader and driver
probe() happened before they were disabled by clock core because of lack
of users. Handling those clocks is also needed to make it possible to
enable support for audio power domain.

This patch requires adding sfr0_ctrl clock to device tree.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 .../devicetree/bindings/mfd/samsung,exynos5433-lpass.txt       |  6 ++++++
 drivers/mfd/exynos-lpass.c                                     | 10 ++++++++++
 2 files changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
index a8deaee82c44..df664018c148 100644
--- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
+++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
@@ -5,6 +5,10 @@ Required properties:
  - compatible		: "samsung,exynos5433-lpass"
  - reg			: should contain the LPASS top SFR region location
 			  and size
+ - clock-names		: should contain following required clocks: "sfr0_ctrl"
+ - clocks		: should contain clock specifiers of all clocks, which
+			  input names have been specified in clock-names
+			  property, in same order.
  - #address-cells	: should be 1
  - #size-cells		: should be 1
  - ranges		: must be present
@@ -24,6 +28,8 @@ Example:
 audio-subsystem {
 	compatible = "samsung,exynos5433-lpass";
 	reg = <0x11400000 0x100>, <0x11500000 0x08>;
+	clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
+	clock-names = "sfr0_ctrl";
 	#address-cells = <1>;
 	#size-cells = <1>;
 	ranges;
diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
index 17915daa2e80..be264988bdc9 100644
--- a/drivers/mfd/exynos-lpass.c
+++ b/drivers/mfd/exynos-lpass.c
@@ -14,6 +14,7 @@
  * only version 2 as published by the Free Software Foundation.
  */
 
+#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/module.h>
@@ -52,6 +53,7 @@
 struct exynos_lpass {
 	/* pointer to the LPASS TOP regmap */
 	struct regmap *top;
+	struct clk *sfr0_clk;
 };
 
 static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
@@ -71,6 +73,8 @@ static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
 
 static void exynos_lpass_enable(struct exynos_lpass *lpass)
 {
+	clk_prepare_enable(lpass->sfr0_clk);
+
 	/* Unmask SFR, DMA and I2S interrupt */
 	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
 		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
@@ -88,6 +92,8 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass)
 	/* Mask any unmasked IP interrupt sources */
 	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
 	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
+
+	clk_disable_unprepare(lpass->sfr0_clk);
 }
 
 static const struct regmap_config exynos_lpass_reg_conf = {
@@ -114,6 +120,10 @@ static int exynos_lpass_probe(struct platform_device *pdev)
 	if (IS_ERR(base_top))
 		return PTR_ERR(base_top);
 
+	lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl");
+	if (IS_ERR(lpass->sfr0_clk))
+		return PTR_ERR(lpass->sfr0_clk);
+
 	lpass->top = regmap_init_mmio(dev, base_top,
 					&exynos_lpass_reg_conf);
 	if (IS_ERR(lpass->top)) {
-- 
1.9.1

Re: [PATCH v2 6/8] mfd: exynos-lpass: Add support for clocks

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:33:52AM +0100, Marek Szyprowski wrote:
> Exynos LPASS requires some clocks to be enabled to make any access to its
> registers. This patch adds code for handling such clocks. For current set
> of registers it is enough to keep sfr0_ctrl clock enabled. Till now it
> worked only because those clocks were enabled by bootloader and driver
> probe() happened before they were disabled by clock core because of lack
> of users. Handling those clocks is also needed to make it possible to
> enable support for audio power domain.
> 
> This patch requires adding sfr0_ctrl clock to device tree.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  .../devicetree/bindings/mfd/samsung,exynos5433-lpass.txt       |  6 ++++++
>  drivers/mfd/exynos-lpass.c                                     | 10 ++++++++++
>  2 files changed, 16 insertions(+)
>

Thanks for changes. Looks good now.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

[PATCH v2 6/8] mfd: exynos-lpass: Add support for clocks

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:33:52AM +0100, Marek Szyprowski wrote:
> Exynos LPASS requires some clocks to be enabled to make any access to its
> registers. This patch adds code for handling such clocks. For current set
> of registers it is enough to keep sfr0_ctrl clock enabled. Till now it
> worked only because those clocks were enabled by bootloader and driver
> probe() happened before they were disabled by clock core because of lack
> of users. Handling those clocks is also needed to make it possible to
> enable support for audio power domain.
> 
> This patch requires adding sfr0_ctrl clock to device tree.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  .../devicetree/bindings/mfd/samsung,exynos5433-lpass.txt       |  6 ++++++
>  drivers/mfd/exynos-lpass.c                                     | 10 ++++++++++
>  2 files changed, 16 insertions(+)
>

Thanks for changes. Looks good now.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

Re: [PATCH v2 6/8] mfd: exynos-lpass: Add support for clocks

[Rob Herring]

On Thu, Jan 26, 2017 at 09:33:52AM +0100, Marek Szyprowski wrote:
> Exynos LPASS requires some clocks to be enabled to make any access to its
> registers. This patch adds code for handling such clocks. For current set
> of registers it is enough to keep sfr0_ctrl clock enabled. Till now it
> worked only because those clocks were enabled by bootloader and driver
> probe() happened before they were disabled by clock core because of lack
> of users. Handling those clocks is also needed to make it possible to
> enable support for audio power domain.
> 
> This patch requires adding sfr0_ctrl clock to device tree.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  .../devicetree/bindings/mfd/samsung,exynos5433-lpass.txt       |  6 ++++++

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/mfd/exynos-lpass.c                                     | 10 ++++++++++
>  2 files changed, 16 insertions(+)

[PATCH v2 6/8] mfd: exynos-lpass: Add support for clocks

[Rob Herring]

On Thu, Jan 26, 2017 at 09:33:52AM +0100, Marek Szyprowski wrote:
> Exynos LPASS requires some clocks to be enabled to make any access to its
> registers. This patch adds code for handling such clocks. For current set
> of registers it is enough to keep sfr0_ctrl clock enabled. Till now it
> worked only because those clocks were enabled by bootloader and driver
> probe() happened before they were disabled by clock core because of lack
> of users. Handling those clocks is also needed to make it possible to
> enable support for audio power domain.
> 
> This patch requires adding sfr0_ctrl clock to device tree.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  .../devicetree/bindings/mfd/samsung,exynos5433-lpass.txt       |  6 ++++++

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/mfd/exynos-lpass.c                                     | 10 ++++++++++
>  2 files changed, 16 insertions(+)

Re: [PATCH v2 6/8] mfd: exynos-lpass: Add support for clocks

[Lee Jones]

On Thu, 26 Jan 2017, Marek Szyprowski wrote:

> Exynos LPASS requires some clocks to be enabled to make any access to its
> registers. This patch adds code for handling such clocks. For current set
> of registers it is enough to keep sfr0_ctrl clock enabled. Till now it
> worked only because those clocks were enabled by bootloader and driver
> probe() happened before they were disabled by clock core because of lack
> of users. Handling those clocks is also needed to make it possible to
> enable support for audio power domain.
> 
> This patch requires adding sfr0_ctrl clock to device tree.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  .../devicetree/bindings/mfd/samsung,exynos5433-lpass.txt       |  6 ++++++
>  drivers/mfd/exynos-lpass.c                                     | 10 ++++++++++
>  2 files changed, 16 insertions(+)

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
  
> diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> index a8deaee82c44..df664018c148 100644
> --- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> +++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> @@ -5,6 +5,10 @@ Required properties:
>   - compatible		: "samsung,exynos5433-lpass"
>   - reg			: should contain the LPASS top SFR region location
>  			  and size
> + - clock-names		: should contain following required clocks: "sfr0_ctrl"
> + - clocks		: should contain clock specifiers of all clocks, which
> +			  input names have been specified in clock-names
> +			  property, in same order.
>   - #address-cells	: should be 1
>   - #size-cells		: should be 1
>   - ranges		: must be present
> @@ -24,6 +28,8 @@ Example:
>  audio-subsystem {
>  	compatible = "samsung,exynos5433-lpass";
>  	reg = <0x11400000 0x100>, <0x11500000 0x08>;
> +	clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
> +	clock-names = "sfr0_ctrl";
>  	#address-cells = <1>;
>  	#size-cells = <1>;
>  	ranges;
> diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
> index 17915daa2e80..be264988bdc9 100644
> --- a/drivers/mfd/exynos-lpass.c
> +++ b/drivers/mfd/exynos-lpass.c
> @@ -14,6 +14,7 @@
>   * only version 2 as published by the Free Software Foundation.
>   */
>  
> +#include <linux/clk.h>
>  #include <linux/delay.h>
>  #include <linux/io.h>
>  #include <linux/module.h>
> @@ -52,6 +53,7 @@
>  struct exynos_lpass {
>  	/* pointer to the LPASS TOP regmap */
>  	struct regmap *top;
> +	struct clk *sfr0_clk;
>  };
>  
>  static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
> @@ -71,6 +73,8 @@ static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
>  
>  static void exynos_lpass_enable(struct exynos_lpass *lpass)
>  {
> +	clk_prepare_enable(lpass->sfr0_clk);
> +
>  	/* Unmask SFR, DMA and I2S interrupt */
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
>  		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
> @@ -88,6 +92,8 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass)
>  	/* Mask any unmasked IP interrupt sources */
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
> +
> +	clk_disable_unprepare(lpass->sfr0_clk);
>  }
>  
>  static const struct regmap_config exynos_lpass_reg_conf = {
> @@ -114,6 +120,10 @@ static int exynos_lpass_probe(struct platform_device *pdev)
>  	if (IS_ERR(base_top))
>  		return PTR_ERR(base_top);
>  
> +	lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl");
> +	if (IS_ERR(lpass->sfr0_clk))
> +		return PTR_ERR(lpass->sfr0_clk);
> +
>  	lpass->top = regmap_init_mmio(dev, base_top,
>  					&exynos_lpass_reg_conf);
>  	if (IS_ERR(lpass->top)) {

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 6/8] mfd: exynos-lpass: Add support for clocks

[Lee Jones]

On Thu, 26 Jan 2017, Marek Szyprowski wrote:

> Exynos LPASS requires some clocks to be enabled to make any access to its
> registers. This patch adds code for handling such clocks. For current set
> of registers it is enough to keep sfr0_ctrl clock enabled. Till now it
> worked only because those clocks were enabled by bootloader and driver
> probe() happened before they were disabled by clock core because of lack
> of users. Handling those clocks is also needed to make it possible to
> enable support for audio power domain.
> 
> This patch requires adding sfr0_ctrl clock to device tree.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  .../devicetree/bindings/mfd/samsung,exynos5433-lpass.txt       |  6 ++++++
>  drivers/mfd/exynos-lpass.c                                     | 10 ++++++++++
>  2 files changed, 16 insertions(+)

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
  
> diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> index a8deaee82c44..df664018c148 100644
> --- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> +++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> @@ -5,6 +5,10 @@ Required properties:
>   - compatible		: "samsung,exynos5433-lpass"
>   - reg			: should contain the LPASS top SFR region location
>  			  and size
> + - clock-names		: should contain following required clocks: "sfr0_ctrl"
> + - clocks		: should contain clock specifiers of all clocks, which
> +			  input names have been specified in clock-names
> +			  property, in same order.
>   - #address-cells	: should be 1
>   - #size-cells		: should be 1
>   - ranges		: must be present
> @@ -24,6 +28,8 @@ Example:
>  audio-subsystem {
>  	compatible = "samsung,exynos5433-lpass";
>  	reg = <0x11400000 0x100>, <0x11500000 0x08>;
> +	clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
> +	clock-names = "sfr0_ctrl";
>  	#address-cells = <1>;
>  	#size-cells = <1>;
>  	ranges;
> diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
> index 17915daa2e80..be264988bdc9 100644
> --- a/drivers/mfd/exynos-lpass.c
> +++ b/drivers/mfd/exynos-lpass.c
> @@ -14,6 +14,7 @@
>   * only version 2 as published by the Free Software Foundation.
>   */
>  
> +#include <linux/clk.h>
>  #include <linux/delay.h>
>  #include <linux/io.h>
>  #include <linux/module.h>
> @@ -52,6 +53,7 @@
>  struct exynos_lpass {
>  	/* pointer to the LPASS TOP regmap */
>  	struct regmap *top;
> +	struct clk *sfr0_clk;
>  };
>  
>  static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
> @@ -71,6 +73,8 @@ static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
>  
>  static void exynos_lpass_enable(struct exynos_lpass *lpass)
>  {
> +	clk_prepare_enable(lpass->sfr0_clk);
> +
>  	/* Unmask SFR, DMA and I2S interrupt */
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
>  		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
> @@ -88,6 +92,8 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass)
>  	/* Mask any unmasked IP interrupt sources */
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
> +
> +	clk_disable_unprepare(lpass->sfr0_clk);
>  }
>  
>  static const struct regmap_config exynos_lpass_reg_conf = {
> @@ -114,6 +120,10 @@ static int exynos_lpass_probe(struct platform_device *pdev)
>  	if (IS_ERR(base_top))
>  		return PTR_ERR(base_top);
>  
> +	lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl");
> +	if (IS_ERR(lpass->sfr0_clk))
> +		return PTR_ERR(lpass->sfr0_clk);
> +
>  	lpass->top = regmap_init_mmio(dev, base_top,
>  					&exynos_lpass_reg_conf);
>  	if (IS_ERR(lpass->top)) {

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v2 6/8] mfd: exynos-lpass: Add support for clocks

[Lee Jones]

On Thu, 26 Jan 2017, Marek Szyprowski wrote:

> Exynos LPASS requires some clocks to be enabled to make any access to its
> registers. This patch adds code for handling such clocks. For current set
> of registers it is enough to keep sfr0_ctrl clock enabled. Till now it
> worked only because those clocks were enabled by bootloader and driver
> probe() happened before they were disabled by clock core because of lack
> of users. Handling those clocks is also needed to make it possible to
> enable support for audio power domain.
> 
> This patch requires adding sfr0_ctrl clock to device tree.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  .../devicetree/bindings/mfd/samsung,exynos5433-lpass.txt       |  6 ++++++
>  drivers/mfd/exynos-lpass.c                                     | 10 ++++++++++
>  2 files changed, 16 insertions(+)

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
  
> diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> index a8deaee82c44..df664018c148 100644
> --- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> +++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> @@ -5,6 +5,10 @@ Required properties:
>   - compatible		: "samsung,exynos5433-lpass"
>   - reg			: should contain the LPASS top SFR region location
>  			  and size
> + - clock-names		: should contain following required clocks: "sfr0_ctrl"
> + - clocks		: should contain clock specifiers of all clocks, which
> +			  input names have been specified in clock-names
> +			  property, in same order.
>   - #address-cells	: should be 1
>   - #size-cells		: should be 1
>   - ranges		: must be present
> @@ -24,6 +28,8 @@ Example:
>  audio-subsystem {
>  	compatible = "samsung,exynos5433-lpass";
>  	reg = <0x11400000 0x100>, <0x11500000 0x08>;
> +	clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
> +	clock-names = "sfr0_ctrl";
>  	#address-cells = <1>;
>  	#size-cells = <1>;
>  	ranges;
> diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
> index 17915daa2e80..be264988bdc9 100644
> --- a/drivers/mfd/exynos-lpass.c
> +++ b/drivers/mfd/exynos-lpass.c
> @@ -14,6 +14,7 @@
>   * only version 2 as published by the Free Software Foundation.
>   */
>  
> +#include <linux/clk.h>
>  #include <linux/delay.h>
>  #include <linux/io.h>
>  #include <linux/module.h>
> @@ -52,6 +53,7 @@
>  struct exynos_lpass {
>  	/* pointer to the LPASS TOP regmap */
>  	struct regmap *top;
> +	struct clk *sfr0_clk;
>  };
>  
>  static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
> @@ -71,6 +73,8 @@ static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
>  
>  static void exynos_lpass_enable(struct exynos_lpass *lpass)
>  {
> +	clk_prepare_enable(lpass->sfr0_clk);
> +
>  	/* Unmask SFR, DMA and I2S interrupt */
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
>  		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
> @@ -88,6 +92,8 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass)
>  	/* Mask any unmasked IP interrupt sources */
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
> +
> +	clk_disable_unprepare(lpass->sfr0_clk);
>  }
>  
>  static const struct regmap_config exynos_lpass_reg_conf = {
> @@ -114,6 +120,10 @@ static int exynos_lpass_probe(struct platform_device *pdev)
>  	if (IS_ERR(base_top))
>  		return PTR_ERR(base_top);
>  
> +	lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl");
> +	if (IS_ERR(lpass->sfr0_clk))
> +		return PTR_ERR(lpass->sfr0_clk);
> +
>  	lpass->top = regmap_init_mmio(dev, base_top,
>  					&exynos_lpass_reg_conf);
>  	if (IS_ERR(lpass->top)) {

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

[PATCH v2 7/8] mfd: exynos-lpass: Add missing remove() function

[Marek Szyprowski]

Disable device on driver remove and release allocated regmap.

Signed-off-by: Marek Szyprowski <m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 drivers/mfd/exynos-lpass.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
index be264988bdc9..9dbbedad916f 100644
--- a/drivers/mfd/exynos-lpass.c
+++ b/drivers/mfd/exynos-lpass.c
@@ -137,6 +137,16 @@ static int exynos_lpass_probe(struct platform_device *pdev)
 	return of_platform_populate(dev->of_node, NULL, NULL, dev);
 }
 
+static int exynos_lpass_remove(struct platform_device *pdev)
+{
+	struct exynos_lpass *lpass = platform_get_drvdata(pdev);
+
+	exynos_lpass_disable(lpass);
+	regmap_exit(lpass->top);
+
+	return 0;
+}
+
 static int __maybe_unused exynos_lpass_suspend(struct device *dev)
 {
 	struct exynos_lpass *lpass = dev_get_drvdata(dev);
@@ -171,6 +181,7 @@ static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend,
 		.of_match_table	= exynos_lpass_of_match,
 	},
 	.probe	= exynos_lpass_probe,
+	.remove	= exynos_lpass_remove,
 };
 module_platform_driver(exynos_lpass_driver);
 
-- 
1.9.1

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[PATCH v2 7/8] mfd: exynos-lpass: Add missing remove() function

[Marek Szyprowski]

Disable device on driver remove and release allocated regmap.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/mfd/exynos-lpass.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
index be264988bdc9..9dbbedad916f 100644
--- a/drivers/mfd/exynos-lpass.c
+++ b/drivers/mfd/exynos-lpass.c
@@ -137,6 +137,16 @@ static int exynos_lpass_probe(struct platform_device *pdev)
 	return of_platform_populate(dev->of_node, NULL, NULL, dev);
 }
 
+static int exynos_lpass_remove(struct platform_device *pdev)
+{
+	struct exynos_lpass *lpass = platform_get_drvdata(pdev);
+
+	exynos_lpass_disable(lpass);
+	regmap_exit(lpass->top);
+
+	return 0;
+}
+
 static int __maybe_unused exynos_lpass_suspend(struct device *dev)
 {
 	struct exynos_lpass *lpass = dev_get_drvdata(dev);
@@ -171,6 +181,7 @@ static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend,
 		.of_match_table	= exynos_lpass_of_match,
 	},
 	.probe	= exynos_lpass_probe,
+	.remove	= exynos_lpass_remove,
 };
 module_platform_driver(exynos_lpass_driver);
 
-- 
1.9.1

[PATCH v2 7/8] mfd: exynos-lpass: Add missing remove() function

[Marek Szyprowski]

Disable device on driver remove and release allocated regmap.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/mfd/exynos-lpass.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
index be264988bdc9..9dbbedad916f 100644
--- a/drivers/mfd/exynos-lpass.c
+++ b/drivers/mfd/exynos-lpass.c
@@ -137,6 +137,16 @@ static int exynos_lpass_probe(struct platform_device *pdev)
 	return of_platform_populate(dev->of_node, NULL, NULL, dev);
 }
 
+static int exynos_lpass_remove(struct platform_device *pdev)
+{
+	struct exynos_lpass *lpass = platform_get_drvdata(pdev);
+
+	exynos_lpass_disable(lpass);
+	regmap_exit(lpass->top);
+
+	return 0;
+}
+
 static int __maybe_unused exynos_lpass_suspend(struct device *dev)
 {
 	struct exynos_lpass *lpass = dev_get_drvdata(dev);
@@ -171,6 +181,7 @@ static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend,
 		.of_match_table	= exynos_lpass_of_match,
 	},
 	.probe	= exynos_lpass_probe,
+	.remove	= exynos_lpass_remove,
 };
 module_platform_driver(exynos_lpass_driver);
 
-- 
1.9.1

Re: [PATCH v2 7/8] mfd: exynos-lpass: Add missing remove() function

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:33:53AM +0100, Marek Szyprowski wrote:
> Disable device on driver remove and release allocated regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> ---
>  drivers/mfd/exynos-lpass.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 

A Suggested-by would be welcomed but beside that thanks for change:
Reviewed-by: Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

Best regards,
Krzysztof

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[PATCH v2 7/8] mfd: exynos-lpass: Add missing remove() function

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:33:53AM +0100, Marek Szyprowski wrote:
> Disable device on driver remove and release allocated regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/mfd/exynos-lpass.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 

A Suggested-by would be welcomed but beside that thanks for change:
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

Re: [PATCH v2 7/8] mfd: exynos-lpass: Add missing remove() function

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:33:53AM +0100, Marek Szyprowski wrote:
> Disable device on driver remove and release allocated regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/mfd/exynos-lpass.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 

A Suggested-by would be welcomed but beside that thanks for change:
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

Re: [PATCH v2 7/8] mfd: exynos-lpass: Add missing remove() function

[Lee Jones]

On Thu, 26 Jan 2017, Marek Szyprowski wrote:

> Disable device on driver remove and release allocated regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/mfd/exynos-lpass.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
  
> diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
> index be264988bdc9..9dbbedad916f 100644
> --- a/drivers/mfd/exynos-lpass.c
> +++ b/drivers/mfd/exynos-lpass.c
> @@ -137,6 +137,16 @@ static int exynos_lpass_probe(struct platform_device *pdev)
>  	return of_platform_populate(dev->of_node, NULL, NULL, dev);
>  }
>  
> +static int exynos_lpass_remove(struct platform_device *pdev)
> +{
> +	struct exynos_lpass *lpass = platform_get_drvdata(pdev);
> +
> +	exynos_lpass_disable(lpass);
> +	regmap_exit(lpass->top);
> +
> +	return 0;
> +}
> +
>  static int __maybe_unused exynos_lpass_suspend(struct device *dev)
>  {
>  	struct exynos_lpass *lpass = dev_get_drvdata(dev);
> @@ -171,6 +181,7 @@ static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend,
>  		.of_match_table	= exynos_lpass_of_match,
>  	},
>  	.probe	= exynos_lpass_probe,
> +	.remove	= exynos_lpass_remove,
>  };
>  module_platform_driver(exynos_lpass_driver);
>  

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 7/8] mfd: exynos-lpass: Add missing remove() function

[Lee Jones]

On Thu, 26 Jan 2017, Marek Szyprowski wrote:

> Disable device on driver remove and release allocated regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/mfd/exynos-lpass.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
  
> diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
> index be264988bdc9..9dbbedad916f 100644
> --- a/drivers/mfd/exynos-lpass.c
> +++ b/drivers/mfd/exynos-lpass.c
> @@ -137,6 +137,16 @@ static int exynos_lpass_probe(struct platform_device *pdev)
>  	return of_platform_populate(dev->of_node, NULL, NULL, dev);
>  }
>  
> +static int exynos_lpass_remove(struct platform_device *pdev)
> +{
> +	struct exynos_lpass *lpass = platform_get_drvdata(pdev);
> +
> +	exynos_lpass_disable(lpass);
> +	regmap_exit(lpass->top);
> +
> +	return 0;
> +}
> +
>  static int __maybe_unused exynos_lpass_suspend(struct device *dev)
>  {
>  	struct exynos_lpass *lpass = dev_get_drvdata(dev);
> @@ -171,6 +181,7 @@ static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend,
>  		.of_match_table	= exynos_lpass_of_match,
>  	},
>  	.probe	= exynos_lpass_probe,
> +	.remove	= exynos_lpass_remove,
>  };
>  module_platform_driver(exynos_lpass_driver);
>  

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v2 7/8] mfd: exynos-lpass: Add missing remove() function

[Lee Jones]

On Thu, 26 Jan 2017, Marek Szyprowski wrote:

> Disable device on driver remove and release allocated regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/mfd/exynos-lpass.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
  
> diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
> index be264988bdc9..9dbbedad916f 100644
> --- a/drivers/mfd/exynos-lpass.c
> +++ b/drivers/mfd/exynos-lpass.c
> @@ -137,6 +137,16 @@ static int exynos_lpass_probe(struct platform_device *pdev)
>  	return of_platform_populate(dev->of_node, NULL, NULL, dev);
>  }
>  
> +static int exynos_lpass_remove(struct platform_device *pdev)
> +{
> +	struct exynos_lpass *lpass = platform_get_drvdata(pdev);
> +
> +	exynos_lpass_disable(lpass);
> +	regmap_exit(lpass->top);
> +
> +	return 0;
> +}
> +
>  static int __maybe_unused exynos_lpass_suspend(struct device *dev)
>  {
>  	struct exynos_lpass *lpass = dev_get_drvdata(dev);
> @@ -171,6 +181,7 @@ static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend,
>  		.of_match_table	= exynos_lpass_of_match,
>  	},
>  	.probe	= exynos_lpass_probe,
> +	.remove	= exynos_lpass_remove,
>  };
>  module_platform_driver(exynos_lpass_driver);
>  

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

[PATCH v2 8/8] mfd: exynos-lpass: Add runtime PM support

[Marek Szyprowski]

Convert exisitng lpass-suspend/resume callbacks into runtime PM callbacks.
This way Exynos LPASS driver will be ready for use with power domains
enabled. LPASS will be runtime resumed/suspended as a result of its child
devices runtime PM transitions.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 drivers/mfd/exynos-lpass.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
index 9dbbedad916f..6d735e22acda 100644
--- a/drivers/mfd/exynos-lpass.c
+++ b/drivers/mfd/exynos-lpass.c
@@ -22,6 +22,7 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 #include <linux/types.h>
 
@@ -132,6 +133,8 @@ static int exynos_lpass_probe(struct platform_device *pdev)
 	}
 
 	platform_set_drvdata(pdev, lpass);
+	pm_runtime_set_active(dev);
+	pm_runtime_enable(dev);
 	exynos_lpass_enable(lpass);
 
 	return of_platform_populate(dev->of_node, NULL, NULL, dev);
@@ -141,7 +144,9 @@ static int exynos_lpass_remove(struct platform_device *pdev)
 {
 	struct exynos_lpass *lpass = platform_get_drvdata(pdev);
 
-	exynos_lpass_disable(lpass);
+	pm_runtime_disable(&pdev->dev);
+	if (!pm_runtime_status_suspended(&pdev->dev))
+		exynos_lpass_disable(lpass);
 	regmap_exit(lpass->top);
 
 	return 0;
@@ -165,8 +170,11 @@ static int __maybe_unused exynos_lpass_resume(struct device *dev)
 	return 0;
 }
 
-static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend,
-					exynos_lpass_resume);
+static const struct dev_pm_ops lpass_pm_ops = {
+	SET_RUNTIME_PM_OPS(exynos_lpass_suspend, exynos_lpass_resume, NULL)
+	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+				     pm_runtime_force_resume)
+};
 
 static const struct of_device_id exynos_lpass_of_match[] = {
 	{ .compatible = "samsung,exynos5433-lpass" },
-- 
1.9.1

[PATCH v2 8/8] mfd: exynos-lpass: Add runtime PM support

[Marek Szyprowski]

Convert exisitng lpass-suspend/resume callbacks into runtime PM callbacks.
This way Exynos LPASS driver will be ready for use with power domains
enabled. LPASS will be runtime resumed/suspended as a result of its child
devices runtime PM transitions.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 drivers/mfd/exynos-lpass.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
index 9dbbedad916f..6d735e22acda 100644
--- a/drivers/mfd/exynos-lpass.c
+++ b/drivers/mfd/exynos-lpass.c
@@ -22,6 +22,7 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 #include <linux/types.h>
 
@@ -132,6 +133,8 @@ static int exynos_lpass_probe(struct platform_device *pdev)
 	}
 
 	platform_set_drvdata(pdev, lpass);
+	pm_runtime_set_active(dev);
+	pm_runtime_enable(dev);
 	exynos_lpass_enable(lpass);
 
 	return of_platform_populate(dev->of_node, NULL, NULL, dev);
@@ -141,7 +144,9 @@ static int exynos_lpass_remove(struct platform_device *pdev)
 {
 	struct exynos_lpass *lpass = platform_get_drvdata(pdev);
 
-	exynos_lpass_disable(lpass);
+	pm_runtime_disable(&pdev->dev);
+	if (!pm_runtime_status_suspended(&pdev->dev))
+		exynos_lpass_disable(lpass);
 	regmap_exit(lpass->top);
 
 	return 0;
@@ -165,8 +170,11 @@ static int __maybe_unused exynos_lpass_resume(struct device *dev)
 	return 0;
 }
 
-static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend,
-					exynos_lpass_resume);
+static const struct dev_pm_ops lpass_pm_ops = {
+	SET_RUNTIME_PM_OPS(exynos_lpass_suspend, exynos_lpass_resume, NULL)
+	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+				     pm_runtime_force_resume)
+};
 
 static const struct of_device_id exynos_lpass_of_match[] = {
 	{ .compatible = "samsung,exynos5433-lpass" },
-- 
1.9.1

Re: [PATCH v2 8/8] mfd: exynos-lpass: Add runtime PM support

[Lee Jones]

On Thu, 26 Jan 2017, Marek Szyprowski wrote:

> Convert exisitng lpass-suspend/resume callbacks into runtime PM callbacks.
> This way Exynos LPASS driver will be ready for use with power domains
> enabled. LPASS will be runtime resumed/suspended as a result of its child
> devices runtime PM transitions.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Acked-by: Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
>  drivers/mfd/exynos-lpass.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
  
> diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
> index 9dbbedad916f..6d735e22acda 100644
> --- a/drivers/mfd/exynos-lpass.c
> +++ b/drivers/mfd/exynos-lpass.c
> @@ -22,6 +22,7 @@
>  #include <linux/of.h>
>  #include <linux/of_platform.h>
>  #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
>  #include <linux/regmap.h>
>  #include <linux/types.h>
>  
> @@ -132,6 +133,8 @@ static int exynos_lpass_probe(struct platform_device *pdev)
>  	}
>  
>  	platform_set_drvdata(pdev, lpass);
> +	pm_runtime_set_active(dev);
> +	pm_runtime_enable(dev);
>  	exynos_lpass_enable(lpass);
>  
>  	return of_platform_populate(dev->of_node, NULL, NULL, dev);
> @@ -141,7 +144,9 @@ static int exynos_lpass_remove(struct platform_device *pdev)
>  {
>  	struct exynos_lpass *lpass = platform_get_drvdata(pdev);
>  
> -	exynos_lpass_disable(lpass);
> +	pm_runtime_disable(&pdev->dev);
> +	if (!pm_runtime_status_suspended(&pdev->dev))
> +		exynos_lpass_disable(lpass);
>  	regmap_exit(lpass->top);
>  
>  	return 0;
> @@ -165,8 +170,11 @@ static int __maybe_unused exynos_lpass_resume(struct device *dev)
>  	return 0;
>  }
>  
> -static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend,
> -					exynos_lpass_resume);
> +static const struct dev_pm_ops lpass_pm_ops = {
> +	SET_RUNTIME_PM_OPS(exynos_lpass_suspend, exynos_lpass_resume, NULL)
> +	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
> +				     pm_runtime_force_resume)
> +};
>  
>  static const struct of_device_id exynos_lpass_of_match[] = {
>  	{ .compatible = "samsung,exynos5433-lpass" },

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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[PATCH v2 8/8] mfd: exynos-lpass: Add runtime PM support

[Lee Jones]

On Thu, 26 Jan 2017, Marek Szyprowski wrote:

> Convert exisitng lpass-suspend/resume callbacks into runtime PM callbacks.
> This way Exynos LPASS driver will be ready for use with power domains
> enabled. LPASS will be runtime resumed/suspended as a result of its child
> devices runtime PM transitions.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  drivers/mfd/exynos-lpass.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
  
> diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
> index 9dbbedad916f..6d735e22acda 100644
> --- a/drivers/mfd/exynos-lpass.c
> +++ b/drivers/mfd/exynos-lpass.c
> @@ -22,6 +22,7 @@
>  #include <linux/of.h>
>  #include <linux/of_platform.h>
>  #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
>  #include <linux/regmap.h>
>  #include <linux/types.h>
>  
> @@ -132,6 +133,8 @@ static int exynos_lpass_probe(struct platform_device *pdev)
>  	}
>  
>  	platform_set_drvdata(pdev, lpass);
> +	pm_runtime_set_active(dev);
> +	pm_runtime_enable(dev);
>  	exynos_lpass_enable(lpass);
>  
>  	return of_platform_populate(dev->of_node, NULL, NULL, dev);
> @@ -141,7 +144,9 @@ static int exynos_lpass_remove(struct platform_device *pdev)
>  {
>  	struct exynos_lpass *lpass = platform_get_drvdata(pdev);
>  
> -	exynos_lpass_disable(lpass);
> +	pm_runtime_disable(&pdev->dev);
> +	if (!pm_runtime_status_suspended(&pdev->dev))
> +		exynos_lpass_disable(lpass);
>  	regmap_exit(lpass->top);
>  
>  	return 0;
> @@ -165,8 +170,11 @@ static int __maybe_unused exynos_lpass_resume(struct device *dev)
>  	return 0;
>  }
>  
> -static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend,
> -					exynos_lpass_resume);
> +static const struct dev_pm_ops lpass_pm_ops = {
> +	SET_RUNTIME_PM_OPS(exynos_lpass_suspend, exynos_lpass_resume, NULL)
> +	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
> +				     pm_runtime_force_resume)
> +};
>  
>  static const struct of_device_id exynos_lpass_of_match[] = {
>  	{ .compatible = "samsung,exynos5433-lpass" },

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v2 8/8] mfd: exynos-lpass: Add runtime PM support

[Lee Jones]

On Thu, 26 Jan 2017, Marek Szyprowski wrote:

> Convert exisitng lpass-suspend/resume callbacks into runtime PM callbacks.
> This way Exynos LPASS driver will be ready for use with power domains
> enabled. LPASS will be runtime resumed/suspended as a result of its child
> devices runtime PM transitions.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  drivers/mfd/exynos-lpass.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
  
> diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
> index 9dbbedad916f..6d735e22acda 100644
> --- a/drivers/mfd/exynos-lpass.c
> +++ b/drivers/mfd/exynos-lpass.c
> @@ -22,6 +22,7 @@
>  #include <linux/of.h>
>  #include <linux/of_platform.h>
>  #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
>  #include <linux/regmap.h>
>  #include <linux/types.h>
>  
> @@ -132,6 +133,8 @@ static int exynos_lpass_probe(struct platform_device *pdev)
>  	}
>  
>  	platform_set_drvdata(pdev, lpass);
> +	pm_runtime_set_active(dev);
> +	pm_runtime_enable(dev);
>  	exynos_lpass_enable(lpass);
>  
>  	return of_platform_populate(dev->of_node, NULL, NULL, dev);
> @@ -141,7 +144,9 @@ static int exynos_lpass_remove(struct platform_device *pdev)
>  {
>  	struct exynos_lpass *lpass = platform_get_drvdata(pdev);
>  
> -	exynos_lpass_disable(lpass);
> +	pm_runtime_disable(&pdev->dev);
> +	if (!pm_runtime_status_suspended(&pdev->dev))
> +		exynos_lpass_disable(lpass);
>  	regmap_exit(lpass->top);
>  
>  	return 0;
> @@ -165,8 +170,11 @@ static int __maybe_unused exynos_lpass_resume(struct device *dev)
>  	return 0;
>  }
>  
> -static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend,
> -					exynos_lpass_resume);
> +static const struct dev_pm_ops lpass_pm_ops = {
> +	SET_RUNTIME_PM_OPS(exynos_lpass_suspend, exynos_lpass_resume, NULL)
> +	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
> +				     pm_runtime_force_resume)
> +};
>  
>  static const struct of_device_id exynos_lpass_of_match[] = {
>  	{ .compatible = "samsung,exynos5433-lpass" },

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v2 0/8] Pad retentions support for Exynos5433

[Linus Walleij]

On Thu, Jan 26, 2017 at 9:33 AM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:

> Patches in this patchset depends on each other. They are order in such a
> way to make the changes bisectable.
>
> Patch #3 has runtime dependency on #1.
> Patch #5 has runtime dependency on #3.
> Patch #6 has runtime dependency on #4.
>
> This patchset also directly depends on the "Move pad retention control to
> Exynos pin controller driver" patchset:
> https://www.spinics.net/lists/arm-kernel/msg556074.html

Do we *have* to merge it runtime-bisectably?

I'm asking because we need a huge immutable branch
(I guess in the MFD subsystem) to deal with that.

It'd be great if I could just apply the pinctrl patches in
isolation, then Lee applies the MFD patches in isolation,
everything compiles in isolation but maye just work once both
pinctrl and MFD are merged upstream, as in linux-next
or Torvalds' tree.

That is one of the reasons why using a system-agnostic
syscon regmap lookup is so good, BTW.

Yours,
Linus Walleij

[PATCH v2 0/8] Pad retentions support for Exynos5433

[Linus Walleij]

On Thu, Jan 26, 2017 at 9:33 AM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:

> Patches in this patchset depends on each other. They are order in such a
> way to make the changes bisectable.
>
> Patch #3 has runtime dependency on #1.
> Patch #5 has runtime dependency on #3.
> Patch #6 has runtime dependency on #4.
>
> This patchset also directly depends on the "Move pad retention control to
> Exynos pin controller driver" patchset:
> https://www.spinics.net/lists/arm-kernel/msg556074.html

Do we *have* to merge it runtime-bisectably?

I'm asking because we need a huge immutable branch
(I guess in the MFD subsystem) to deal with that.

It'd be great if I could just apply the pinctrl patches in
isolation, then Lee applies the MFD patches in isolation,
everything compiles in isolation but maye just work once both
pinctrl and MFD are merged upstream, as in linux-next
or Torvalds' tree.

That is one of the reasons why using a system-agnostic
syscon regmap lookup is so good, BTW.

Yours,
Linus Walleij

Re: [PATCH v2 0/8] Pad retentions support for Exynos5433

[Linus Walleij]

On Thu, Jan 26, 2017 at 9:33 AM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:

> Patches in this patchset depends on each other. They are order in such a
> way to make the changes bisectable.
>
> Patch #3 has runtime dependency on #1.
> Patch #5 has runtime dependency on #3.
> Patch #6 has runtime dependency on #4.
>
> This patchset also directly depends on the "Move pad retention control to
> Exynos pin controller driver" patchset:
> https://www.spinics.net/lists/arm-kernel/msg556074.html

Do we *have* to merge it runtime-bisectably?

I'm asking because we need a huge immutable branch
(I guess in the MFD subsystem) to deal with that.

It'd be great if I could just apply the pinctrl patches in
isolation, then Lee applies the MFD patches in isolation,
everything compiles in isolation but maye just work once both
pinctrl and MFD are merged upstream, as in linux-next
or Torvalds' tree.

That is one of the reasons why using a system-agnostic
syscon regmap lookup is so good, BTW.

Yours,
Linus Walleij

Re: [PATCH v2 0/8] Pad retentions support for Exynos5433

[Marek Szyprowski]

Hi Linus,

On 2017-01-26 10:50, Linus Walleij wrote:
> On Thu, Jan 26, 2017 at 9:33 AM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
>> Patches in this patchset depends on each other. They are order in such a
>> way to make the changes bisectable.
>>
>> Patch #3 has runtime dependency on #1.
>> Patch #5 has runtime dependency on #3.
>> Patch #6 has runtime dependency on #4.
>>
>> This patchset also directly depends on the "Move pad retention control to
>> Exynos pin controller driver" patchset:
>> https://www.spinics.net/lists/arm-kernel/msg556074.html
> Do we *have* to merge it runtime-bisectably?
>
> I'm asking because we need a huge immutable branch
> (I guess in the MFD subsystem) to deal with that.
>
> It'd be great if I could just apply the pinctrl patches in
> isolation, then Lee applies the MFD patches in isolation,
> everything compiles in isolation but maye just work once both
> pinctrl and MFD are merged upstream, as in linux-next
> or Torvalds' tree.

I always thought that it is good to prepare patches in such a way that they
don't break runtime bisectability, especially if this is just a matter of
applying a few patches via the other tree. In this case it will work fine
if MFD patches gets applied with Lee Jones ack via pinctrl tree (I remember
that MFD changes were often applied via the other trees in the past).

> That is one of the reasons why using a system-agnostic
> syscon regmap lookup is so good, BTW.

I've just explained my rationale about the regmap lookup in the separate
mail.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

[PATCH v2 0/8] Pad retentions support for Exynos5433

[Marek Szyprowski]

Hi Linus,

On 2017-01-26 10:50, Linus Walleij wrote:
> On Thu, Jan 26, 2017 at 9:33 AM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
>> Patches in this patchset depends on each other. They are order in such a
>> way to make the changes bisectable.
>>
>> Patch #3 has runtime dependency on #1.
>> Patch #5 has runtime dependency on #3.
>> Patch #6 has runtime dependency on #4.
>>
>> This patchset also directly depends on the "Move pad retention control to
>> Exynos pin controller driver" patchset:
>> https://www.spinics.net/lists/arm-kernel/msg556074.html
> Do we *have* to merge it runtime-bisectably?
>
> I'm asking because we need a huge immutable branch
> (I guess in the MFD subsystem) to deal with that.
>
> It'd be great if I could just apply the pinctrl patches in
> isolation, then Lee applies the MFD patches in isolation,
> everything compiles in isolation but maye just work once both
> pinctrl and MFD are merged upstream, as in linux-next
> or Torvalds' tree.

I always thought that it is good to prepare patches in such a way that they
don't break runtime bisectability, especially if this is just a matter of
applying a few patches via the other tree. In this case it will work fine
if MFD patches gets applied with Lee Jones ack via pinctrl tree (I remember
that MFD changes were often applied via the other trees in the past).

> That is one of the reasons why using a system-agnostic
> syscon regmap lookup is so good, BTW.

I've just explained my rationale about the regmap lookup in the separate
mail.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH v2 0/8] Pad retentions support for Exynos5433

[Marek Szyprowski]

Hi Linus,

On 2017-01-26 10:50, Linus Walleij wrote:
> On Thu, Jan 26, 2017 at 9:33 AM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
>> Patches in this patchset depends on each other. They are order in such a
>> way to make the changes bisectable.
>>
>> Patch #3 has runtime dependency on #1.
>> Patch #5 has runtime dependency on #3.
>> Patch #6 has runtime dependency on #4.
>>
>> This patchset also directly depends on the "Move pad retention control to
>> Exynos pin controller driver" patchset:
>> https://www.spinics.net/lists/arm-kernel/msg556074.html
> Do we *have* to merge it runtime-bisectably?
>
> I'm asking because we need a huge immutable branch
> (I guess in the MFD subsystem) to deal with that.
>
> It'd be great if I could just apply the pinctrl patches in
> isolation, then Lee applies the MFD patches in isolation,
> everything compiles in isolation but maye just work once both
> pinctrl and MFD are merged upstream, as in linux-next
> or Torvalds' tree.

I always thought that it is good to prepare patches in such a way that they
don't break runtime bisectability, especially if this is just a matter of
applying a few patches via the other tree. In this case it will work fine
if MFD patches gets applied with Lee Jones ack via pinctrl tree (I remember
that MFD changes were often applied via the other trees in the past).

> That is one of the reasons why using a system-agnostic
> syscon regmap lookup is so good, BTW.

I've just explained my rationale about the regmap lookup in the separate
mail.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH v2 0/8] Pad retentions support for Exynos5433

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 11:50 AM, Linus Walleij
<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> On Thu, Jan 26, 2017 at 9:33 AM, Marek Szyprowski
> <m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
>
>> Patches in this patchset depends on each other. They are order in such a
>> way to make the changes bisectable.
>>
>> Patch #3 has runtime dependency on #1.
>> Patch #5 has runtime dependency on #3.
>> Patch #6 has runtime dependency on #4.
>>
>> This patchset also directly depends on the "Move pad retention control to
>> Exynos pin controller driver" patchset:
>> https://www.spinics.net/lists/arm-kernel/msg556074.html
>
> Do we *have* to merge it runtime-bisectably?
>
> I'm asking because we need a huge immutable branch
> (I guess in the MFD subsystem) to deal with that.

It helps a lot with finding introduced issues, so I think yes - we
want it runtime-bisectable. The board has already support in mainline
so it is not theoretical runtime...

Best regards,
Krzysztof
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[PATCH v2 0/8] Pad retentions support for Exynos5433

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 11:50 AM, Linus Walleij
<linus.walleij@linaro.org> wrote:
> On Thu, Jan 26, 2017 at 9:33 AM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
>
>> Patches in this patchset depends on each other. They are order in such a
>> way to make the changes bisectable.
>>
>> Patch #3 has runtime dependency on #1.
>> Patch #5 has runtime dependency on #3.
>> Patch #6 has runtime dependency on #4.
>>
>> This patchset also directly depends on the "Move pad retention control to
>> Exynos pin controller driver" patchset:
>> https://www.spinics.net/lists/arm-kernel/msg556074.html
>
> Do we *have* to merge it runtime-bisectably?
>
> I'm asking because we need a huge immutable branch
> (I guess in the MFD subsystem) to deal with that.

It helps a lot with finding introduced issues, so I think yes - we
want it runtime-bisectable. The board has already support in mainline
so it is not theoretical runtime...

Best regards,
Krzysztof

Re: [PATCH v2 0/8] Pad retentions support for Exynos5433

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 11:50 AM, Linus Walleij
<linus.walleij@linaro.org> wrote:
> On Thu, Jan 26, 2017 at 9:33 AM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
>
>> Patches in this patchset depends on each other. They are order in such a
>> way to make the changes bisectable.
>>
>> Patch #3 has runtime dependency on #1.
>> Patch #5 has runtime dependency on #3.
>> Patch #6 has runtime dependency on #4.
>>
>> This patchset also directly depends on the "Move pad retention control to
>> Exynos pin controller driver" patchset:
>> https://www.spinics.net/lists/arm-kernel/msg556074.html
>
> Do we *have* to merge it runtime-bisectably?
>
> I'm asking because we need a huge immutable branch
> (I guess in the MFD subsystem) to deal with that.

It helps a lot with finding introduced issues, so I think yes - we
want it runtime-bisectable. The board has already support in mainline
so it is not theoretical runtime...

Best regards,
Krzysztof

Re: [PATCH v2 0/8] Pad retentions support for Exynos5433

[Linus Walleij]

On Thu, Jan 26, 2017 at 3:32 PM, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On Thu, Jan 26, 2017 at 11:50 AM, Linus Walleij
> <linus.walleij@linaro.org> wrote:
>> On Thu, Jan 26, 2017 at 9:33 AM, Marek Szyprowski
>> <m.szyprowski@samsung.com> wrote:
>>
>>> Patches in this patchset depends on each other. They are order in such a
>>> way to make the changes bisectable.
>>>
>>> Patch #3 has runtime dependency on #1.
>>> Patch #5 has runtime dependency on #3.
>>> Patch #6 has runtime dependency on #4.
>>>
>>> This patchset also directly depends on the "Move pad retention control to
>>> Exynos pin controller driver" patchset:
>>> https://www.spinics.net/lists/arm-kernel/msg556074.html
>>
>> Do we *have* to merge it runtime-bisectably?
>>
>> I'm asking because we need a huge immutable branch
>> (I guess in the MFD subsystem) to deal with that.
>
> It helps a lot with finding introduced issues, so I think yes - we
> want it runtime-bisectable. The board has already support in mainline
> so it is not theoretical runtime...

OK I just wait for an immutable branch to pull for this to work
out then.

Yours,
Linus Walleij

[PATCH v2 0/8] Pad retentions support for Exynos5433

[Linus Walleij]

On Thu, Jan 26, 2017 at 3:32 PM, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On Thu, Jan 26, 2017 at 11:50 AM, Linus Walleij
> <linus.walleij@linaro.org> wrote:
>> On Thu, Jan 26, 2017 at 9:33 AM, Marek Szyprowski
>> <m.szyprowski@samsung.com> wrote:
>>
>>> Patches in this patchset depends on each other. They are order in such a
>>> way to make the changes bisectable.
>>>
>>> Patch #3 has runtime dependency on #1.
>>> Patch #5 has runtime dependency on #3.
>>> Patch #6 has runtime dependency on #4.
>>>
>>> This patchset also directly depends on the "Move pad retention control to
>>> Exynos pin controller driver" patchset:
>>> https://www.spinics.net/lists/arm-kernel/msg556074.html
>>
>> Do we *have* to merge it runtime-bisectably?
>>
>> I'm asking because we need a huge immutable branch
>> (I guess in the MFD subsystem) to deal with that.
>
> It helps a lot with finding introduced issues, so I think yes - we
> want it runtime-bisectable. The board has already support in mainline
> so it is not theoretical runtime...

OK I just wait for an immutable branch to pull for this to work
out then.

Yours,
Linus Walleij

Re: [PATCH v2 0/8] Pad retentions support for Exynos5433

[Linus Walleij]

On Thu, Jan 26, 2017 at 3:32 PM, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On Thu, Jan 26, 2017 at 11:50 AM, Linus Walleij
> <linus.walleij@linaro.org> wrote:
>> On Thu, Jan 26, 2017 at 9:33 AM, Marek Szyprowski
>> <m.szyprowski@samsung.com> wrote:
>>
>>> Patches in this patchset depends on each other. They are order in such a
>>> way to make the changes bisectable.
>>>
>>> Patch #3 has runtime dependency on #1.
>>> Patch #5 has runtime dependency on #3.
>>> Patch #6 has runtime dependency on #4.
>>>
>>> This patchset also directly depends on the "Move pad retention control to
>>> Exynos pin controller driver" patchset:
>>> https://www.spinics.net/lists/arm-kernel/msg556074.html
>>
>> Do we *have* to merge it runtime-bisectably?
>>
>> I'm asking because we need a huge immutable branch
>> (I guess in the MFD subsystem) to deal with that.
>
> It helps a lot with finding introduced issues, so I think yes - we
> want it runtime-bisectable. The board has already support in mainline
> so it is not theoretical runtime...

OK I just wait for an immutable branch to pull for this to work
out then.

Yours,
Linus Walleij

Re: [PATCH v2 0/8] Pad retentions support for Exynos5433

[Krzysztof Kozlowski]

[-- Attachment #1: Type: text/plain, Size: 1688 bytes --]

On Thu, Jan 26, 2017 at 09:33:46AM +0100, Marek Szyprowski wrote:
> Hello,
> 
> This patchset is a first step to add support for all power domains on
> Exynos5433 SoCs. This patchset contains patches for Exynos pin control
> driver and Exynos LPASS MFD driver, which are needed to make the
> platform ready for adding power domains support.
> 
> Patches in this patchset depends on each other. They are order in such a
> way to make the changes bisectable.
> 
> Patch #3 has runtime dependency on #1.
> Patch #5 has runtime dependency on #3.
> Patch #6 has runtime dependency on #4.
> 
> This patchset also directly depends on the "Move pad retention control to
> Exynos pin controller driver" patchset:
> https://www.spinics.net/lists/arm-kernel/msg556074.html
> 
> Patches have been generated on top of linux-next from 25th January 2017.
> 
> This is a part of a larger task, which goal is to add support for power
> domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it
> working have been pushed to the following git repo:
> https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd
>
I tried your branch above on Odroid U3 and it fails to boot.
next-20170125 works fine. exynos_defconfig, booting from microSD.

Board hangs (silently) on:
[    2.283437] usb 1-3: new high-speed USB device number 3 using exynos-ehci
[    2.473786] usb 1-3: New USB device found, idVendor=0424, idProduct=3503
[    2.474856] usb 1-3: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    2.482656] hub 1-3:1.0: USB hub found
[    2.486017] hub 1-3:1.0: 3 ports detected
[   55.037205] random: crng init done

Full log attached.

Best regards,
Krzysztof


[-- Attachment #2: odroid-log.txt --]
[-- Type: text/plain, Size: 17660 bytes --]

U-Boot 2017.01-rc2-00044-g8653b94a8f5a (Jan 06 2017 - 18:05:55 +0200)

CPU:   Exynos4412 @ 1 GHz
Model: Odroid based on Exynos4412
Board: Odroid based on Exynos4412
Type:  u3
DRAM:  2 GiB
LDO20@VDDQ_EMMC_1.8V: set 1800000 uV; enabling
LDO22@VDDQ_EMMC_2.8V: set 2800000 uV; enabling
LDO21@TFLASH_2.8V: set 2800000 uV; enabling
MMC:   SAMSUNG SDHCI: 0, EXYNOS DWMMC: 1
Net:   No ethernet found.
Hit any key to stop autoboot:  0
Odroid #
Odroid # run nn
reading boot.scr
2051 bytes read in 22 ms (90.8 KiB/s)
## Executing script at 42000000
reading /zImage
4641960 bytes read in 226 ms (19.6 MiB/s)
reading /dtbs/exynos4412-odroidu3.dtb
54779 bytes read in 41 ms (1.3 MiB/s)
reading /initramfs-linux.img
** Unable to read file /initramfs-linux.img **
Kernel image @ 0x40007fc0 [ 0x000000 - 0x46d4a8 ]
## Flattened Device Tree blob at 40800000
   Booting using the fdt blob at 0x40800000
   Loading Device Tree to 4ffef000, end 4ffff5fa ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0xa00
[    0.000000] Linux version 4.10.0-rc5-next-20170125-00050-g0dc3a91a2fba (kozik@kozik-lap) (gcc version 6.2.0 20161005 (Ubuntu 6.2.0-5ubuntu12) ) #368 SMP PREEMPT Fri Jan 27 21:41:22 IST 2017
[    0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] OF: fdt:Machine model: Hardkernel ODROID-U3 board based on Exynos4412
[    0.000000] Reserved memory: created DMA memory pool at 0xbf700000, size 8 MiB
[    0.000000] OF: reserved mem: initialized node region_mfc_right, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0xbe700000, size 16 MiB
[    0.000000] OF: reserved mem: initialized node region_mfc_left, compatible id shared-dma-pool
[    0.000000] cma: Reserved 64 MiB at 0xba400000
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] Samsung CPU ID: 0xe4412220
[    0.000000] Running under secure firmware.
[    0.000000] percpu: Embedded 16 pages/cpu @eefb9000 s34008 r8192 d23336 u65536
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 516352
[    0.000000] Kernel command line: console=tty1 console=ttySAC1,115200n8 root=PARTUUID=82ec0a4a-02 rw rootwait smsc95xx.macaddr=00:1e:06:61:7a:94  no_console_suspend
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Memory: 1976632K/2071552K available (7168K kernel code, 279K rwdata, 2284K rodata, 1024K init, 319K bss, 29384K reserved, 65536K cma-reserved, 1219584K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0800000   (8160 kB)
[    0.000000]       .init : 0xc0b00000 - 0xc0c00000   (1024 kB)
[    0.000000]       .data : 0xc0c00000 - 0xc0c45f00   ( 280 kB)
[    0.000000]        .bss : 0xc0c47000 - 0xc0c96d68   ( 320 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  Build-time adjustment of leaf fanout to 32.
[    0.000000]  RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=4
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] L2C: platform modifies aux control register: 0x02070000 -> 0x3e470001
[    0.000000] L2C: platform provided aux values permit register corruption.
[    0.000000] L2C: DT/platform modifies aux control register: 0x02070000 -> 0x3e470001
[    0.000000] L2C-310 enabling early BRESP for Cortex-A9
[    0.000000] L2C-310: enabling full line of zeros but not enabled in Cortex-A9
[    0.000000] L2C-310 ID prefetch enabled, offset 8 lines
[    0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
[    0.000000] L2C-310 cache controller enabled, 16 ways, 1024 kB
[    0.000000] L2C-310: CACHE_ID 0x4100c4c8, AUX_CTRL 0x7e470001
[    0.000000] Exynos4x12 clocks: sclk_apll = 1000000000, sclk_mpll = 800000000
[    0.000000]  sclk_epll = 96000000, sclk_vpll = 350000000, arm_clk = 1000000000
[    0.000000] Switching to timer-based delay loop, resolution 41ns
[    0.000000] clocksource: mct-frc: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
[    0.000004] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
[    0.000248] Console: colour dummy device 80x30
[    0.000903] console [tty1] enabled
[    0.000928] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000)
[    0.000961] pid_max: default: 32768 minimum: 301
[    0.001046] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001069] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001478] CPU: Testing write buffer coherency: ok
[    0.001790] CPU0: thread -1, cpu 0, socket 10, mpidr 80000a00
[    0.030004] Setting up static identity map for 0x40100000 - 0x40100058
[    0.119992] smp: Bringing up secondary CPUs ...
[    0.200315] CPU1: thread -1, cpu 1, socket 10, mpidr 80000a01
[    0.280298] CPU2: thread -1, cpu 2, socket 10, mpidr 80000a02
[    0.360290] CPU3: thread -1, cpu 3, socket 10, mpidr 80000a03
[    0.360351] smp: Brought up 1 node, 4 CPUs
[    0.360417] SMP: Total of 4 processors activated (192.00 BogoMIPS).
[    0.360435] CPU: All CPU(s) started in SVC mode.
[    0.361227] devtmpfs: initialized
[    0.371920] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
[    0.372168] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.373950] pinctrl core: initialized pinctrl subsystem
[    0.374590] lcd0-power-domain has as child subdomain: tv-power-domain.
[    0.375416] NET: Registered protocol family 16
[    0.377168] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.378419] cpuidle: using governor menu
[    0.409143] SCSI subsystem initialized
[    0.409343] usbcore: registered new interface driver usbfs
[    0.409409] usbcore: registered new interface driver hub
[    0.409490] usbcore: registered new device driver usb
[    0.410050] s3c-i2c 13860000.i2c: slave address 0x00
[    0.410080] s3c-i2c 13860000.i2c: bus frequency set to 390 KHz
[    0.410542] s3c-i2c 13860000.i2c: i2c-0: S3C I2C adapter
[    0.410719] s3c-i2c 13870000.i2c: slave address 0x00
[    0.410747] s3c-i2c 13870000.i2c: bus frequency set to 97 KHz
[    0.411065] s3c-i2c 13870000.i2c: i2c-1: S3C I2C adapter
[    0.411207] s3c-i2c 13880000.i2c: slave address 0x00
[    0.411233] s3c-i2c 13880000.i2c: bus frequency set to 97 KHz
[    0.411429] s3c-i2c 13880000.i2c: i2c-2: S3C I2C adapter
[    0.411538] s3c-i2c 138e0000.i2c: slave address 0x00
[    0.411564] s3c-i2c 138e0000.i2c: bus frequency set to 97 KHz
[    0.411876] s3c-i2c 138e0000.i2c: i2c-8: S3C I2C adapter
[    0.412490] Advanced Linux Sound Architecture Driver Initialized.
[    0.413377] clocksource: Switched to clocksource mct-frc
[    0.421266] NET: Registered protocol family 2
[    0.421722] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[    0.421811] TCP bind hash table entries: 8192 (order: 5, 163840 bytes)
[    0.421964] TCP: Hash tables configured (established 8192 bind 8192)
[    0.422053] UDP hash table entries: 512 (order: 2, 24576 bytes)
[    0.422105] UDP-Lite hash table entries: 512 (order: 2, 24576 bytes)
[    0.422264] NET: Registered protocol family 1
[    0.422620] RPC: Registered named UNIX socket transport module.
[    0.422644] RPC: Registered udp transport module.
[    0.422661] RPC: Registered tcp transport module.
[    0.422678] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.423858] futex hash table entries: 1024 (order: 4, 65536 bytes)
[    0.424208] workingset: timestamp_bits=30 max_order=19 bucket_order=0
[    0.430657] NFS: Registering the id_resolver key type
[    0.430706] Key type id_resolver registered
[    0.430724] Key type id_legacy registered
[    0.430767] romfs: ROMFS MTD (C) 2007 Red Hat, Inc.
[    0.431536] bounce: pool size: 64 pages
[    0.431693] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249)
[    0.431723] io scheduler noop registered
[    0.431740] io scheduler deadline registered
[    0.431877] io scheduler cfq registered (default)
[    0.431897] io scheduler mq-deadline registered
[    0.433431] 125b0000.exynos-usbphy supply vbus not found, using dummy regulator
[    0.439237] dma-pl330 12680000.pdma: Loaded driver for PL330 DMAC-141330
[    0.439270] dma-pl330 12680000.pdma:         DBUFF-32x4bytes Num_Chans-8 Num_Peri-32 Num_Events-32
[    0.441766] dma-pl330 12690000.pdma: Loaded driver for PL330 DMAC-141330
[    0.441798] dma-pl330 12690000.pdma:         DBUFF-32x4bytes Num_Chans-8 Num_Peri-32 Num_Events-32
[    0.442549] dma-pl330 12850000.mdma: Loaded driver for PL330 DMAC-141330
[    0.442579] dma-pl330 12850000.mdma:         DBUFF-64x8bytes Num_Chans-8 Num_Peri-1 Num_Events-32
[    0.494061] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    0.495894] 13800000.serial: ttySAC0 at MMIO 0x13800000 (irq = 53, base_baud = 0) is a S3C6400/10
[    0.496268] 13810000.serial: ttySAC1 at MMIO 0x13810000 (irq = 54, base_baud = 0) is a S3C6400/10
[    1.267780] console [ttySAC1] enabled
[    1.275320] exynos-hdmi 12d00000.hdmi: Failed to get supply 'vdd': -517
[    1.290270] brd: module loaded
[    1.295375] loop: module loaded
[    1.309140] random: fast init done
[    1.318865] s3c64xx-spi 13930000.spi: spi bus clock parent not specified, using clock at index 0 as parent
[    1.322902] s3c64xx-spi 13930000.spi: number of chip select lines not specified, assuming 1 chip select line
[    1.333776] libphy: Fixed MDIO Bus: probed
[    1.336988] usbcore: registered new interface driver r8152
[    1.342292] usbcore: registered new interface driver asix
[    1.347687] usbcore: registered new interface driver ax88179_178a
[    1.353749] usbcore: registered new interface driver cdc_ether
[    1.359557] usbcore: registered new interface driver smsc75xx
[    1.365304] usbcore: registered new interface driver smsc95xx
[    1.371002] usbcore: registered new interface driver net1080
[    1.376690] usbcore: registered new interface driver cdc_subset
[    1.382552] usbcore: registered new interface driver zaurus
[    1.388139] usbcore: registered new interface driver cdc_ncm
[    1.395179] dwc2 12480000.hsotg: Invalid value 1024 for param g-np-tx-fifo-size
[    1.401043] dwc2 12480000.hsotg: EPs: 16, dedicated fifos, 7808 entries in SPRAM
[    1.409298] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    1.414922] ehci-exynos: EHCI EXYNOS driver
[    1.419646] exynos-ehci 12580000.ehci: EHCI Host Controller
[    1.424658] exynos-ehci 12580000.ehci: new USB bus registered, assigned bus number 1
[    1.432518] exynos-ehci 12580000.ehci: irq 51, io mem 0x12580000
[    1.463415] exynos-ehci 12580000.ehci: USB 2.0 started, EHCI 1.00
[    1.464014] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    1.470649] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.477878] usb usb1: Product: EHCI Host Controller
[    1.482710] usb usb1: Manufacturer: Linux 4.10.0-rc5-next-20170125-00050-g0dc3a91a2fba ehci_hcd
[    1.491414] usb usb1: SerialNumber: 12580000.ehci
[    1.496554] hub 1-0:1.0: USB hub found
[    1.499835] hub 1-0:1.0: 3 ports detected
[    1.504425] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    1.510001] ohci-exynos: OHCI EXYNOS driver
[    1.514852] usbcore: registered new interface driver usb-storage
[    1.530924] usb3503 0-0008: switched to HUB mode
[    1.530999] usb3503 0-0008: usb3503_probe: probed in hub mode
[    1.535979] using random self ethernet address
[    1.540062] using random host ethernet address
[    1.544882] usb0: HOST MAC 7a:d4:f7:e7:93:e8
[    1.548792] usb0: MAC 7a:25:6d:db:b1:9e
[    1.552566] using random self ethernet address
[    1.557007] using random host ethernet address
[    1.561441] g_ether gadget: Ethernet Gadget, version: Memorial Day 2008
[    1.568031] g_ether gadget: g_ether ready
[    1.572014] dwc2 12480000.hsotg: bound driver g_ether
[    1.580371] mousedev: PS/2 mouse device common for all mice
[    1.711692] max77686-rtc max77686-rtc: rtc core: registered max77686-rtc as rtc0
[    1.714380] rtc rtc1: invalid alarm value: 1900-1-2 0:0:0
[    1.718981] s3c-rtc 10070000.rtc: rtc core: registered s3c as rtc1
[    1.725512] i2c /dev entries driver
[    1.732753] s3c2410-wdt 10060000.watchdog: watchdog inactive, reset disabled, irq disabled
[    1.737332] device-mapper: ioctl: 4.35.0-ioctl (2016-06-23) initialised: dm-devel@redhat.com
[    1.748201] sdhci: Secure Digital Host Controller Interface driver
[    1.751299] sdhci: Copyright(c) Pierre Ossman
[    1.756052] s3c-sdhci 12530000.sdhci: clock source 2: mmc_busclk.2 (100000000 Hz)
[    1.763186] s3c-sdhci 12530000.sdhci: Got CD GPIO
[    1.823530] mmc0: SDHCI controller on samsung-hsmmc [12530000.sdhci] using ADMA
[    1.825409] Synopsys Designware Multimedia Card Interface Driver
[    1.831817] dwmmc_exynos 12550000.mmc: IDMAC supports 32-bit address mode.
[    1.838133] dwmmc_exynos 12550000.mmc: Using internal DMA controller.
[    1.844493] dwmmc_exynos 12550000.mmc: Version ID is 240a
[    1.849876] dwmmc_exynos 12550000.mmc: DW MMC controller at irq 110,32 bit host data width,128 deep fifo
[    1.859539] dwmmc_exynos 12550000.mmc: allocated mmc-pwrseq
[    1.864902] usb 1-2: new high-speed USB device number 2 using exynos-ehci
[    1.871688] mmc_host mmc1: card is polling.
[    1.903753] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
[    1.933547] dwmmc_exynos 12550000.mmc: 1 slots initialized
[    1.934664] s5p-secss 10830000.sss: s5p-sss driver registered
[    1.942516] usbcore: registered new interface driver usbhid
[    1.944707] usbhid: USB HID core driver
[    1.959692] NET: Registered protocol family 10
[    1.960359] Segment Routing with IPv6
[    1.962179] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    1.968428] NET: Registered protocol family 17
[    1.972486] NET: Registered protocol family 15
[    1.977036] Key type dns_resolver registered
[    1.981461] Registering SWP/SWPB emulation handler
[    1.987135] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
[    2.013136] [drm] Exynos DRM: using 12c10000.mixer device for DMA mapping operations
[    2.015626] exynos-drm exynos-drm: bound 12c10000.mixer (ops mixer_component_ops)
[    2.022899] exynos-drm exynos-drm: bound 12d00000.hdmi (ops hdmi_component_ops)
[    2.030045] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    2.036622] [drm] No driver support for vblank timestamp query.
[    2.042549] [drm] Initialized exynos 1.0.0 20110530 for exynos-drm on minor 0
[    2.050968] exynos-bus: new bus device registered: bus_dmc (100000 KHz ~ 400000 KHz)
[    2.053768] usb 1-2: New USB device found, idVendor=0424, idProduct=9730
[    2.053776] usb 1-2: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    2.056426] smsc95xx v1.0.5
[    2.064078] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
[    2.084445] exynos-bus: new bus device registered: bus_acp (100000 KHz ~ 267000 KHz)
[    2.091742] exynos-bus: new bus device registered: bus_c2c (100000 KHz ~ 400000 KHz)
[    2.093515] mmc0: new high speed SDHC card at address 0007
[    2.094029] mmcblk0: mmc0:0007 SD16G 14.5 GiB
[    2.095502]  mmcblk0: p1 p2 p3
[    2.113868] exynos-bus: new bus device registered: bus_leftbus (100000 KHz ~ 200000 KHz)
[    2.120680] exynos-bus: new bus device registered: bus_rightbus (100000 KHz ~ 200000 KHz)
[    2.129026] exynos-bus: new bus device registered: bus_display (160000 KHz ~ 200000 KHz)
[    2.137031] exynos-bus: new bus device registered: bus_fsys (100000 KHz ~ 134000 KHz)
[    2.144828] exynos-bus: new bus device registered: bus_peri ( 50000 KHz ~ 100000 KHz)
[    2.149095] smsc95xx 1-2:1.0 eth0: register 'smsc95xx' at usb-12580000.ehci-2, smsc95xx USB 2.0 Ethernet, 5a:46:f5:aa:8d:36
[    2.154191] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
[    2.173243] exynos-bus: new bus device registered: bus_mfc (100000 KHz ~ 200000 KHz)
[    2.214263] max98090 1-0010: MAX98090 REVID=0x43
[    2.217699] max98090 1-0010: use default 2.8v micbias
[    2.225755] asoc-simple-card sound: HiFi <-> 3830000.i2s mapping ok
[    2.229872] input: gpio_keys as /devices/platform/gpio_keys/input/input0
[    2.266862] max77686-rtc max77686-rtc: setting system clock to 2017-01-27 19:43:23 UTC (1485546203)
[    2.283437] usb 1-3: new high-speed USB device number 3 using exynos-ehci
[    2.473786] usb 1-3: New USB device found, idVendor=0424, idProduct=3503
[    2.474856] usb 1-3: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    2.482656] hub 1-3:1.0: USB hub found
[    2.486017] hub 1-3:1.0: 3 ports detected
[   55.037205] random: crng init done



[-- Attachment #3: Type: text/plain, Size: 176 bytes --]

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[PATCH v2 0/8] Pad retentions support for Exynos5433

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 09:33:46AM +0100, Marek Szyprowski wrote:
> Hello,
> 
> This patchset is a first step to add support for all power domains on
> Exynos5433 SoCs. This patchset contains patches for Exynos pin control
> driver and Exynos LPASS MFD driver, which are needed to make the
> platform ready for adding power domains support.
> 
> Patches in this patchset depends on each other. They are order in such a
> way to make the changes bisectable.
> 
> Patch #3 has runtime dependency on #1.
> Patch #5 has runtime dependency on #3.
> Patch #6 has runtime dependency on #4.
> 
> This patchset also directly depends on the "Move pad retention control to
> Exynos pin controller driver" patchset:
> https://www.spinics.net/lists/arm-kernel/msg556074.html
> 
> Patches have been generated on top of linux-next from 25th January 2017.
> 
> This is a part of a larger task, which goal is to add support for power
> domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it
> working have been pushed to the following git repo:
> https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd
>
I tried your branch above on Odroid U3 and it fails to boot.
next-20170125 works fine. exynos_defconfig, booting from microSD.

Board hangs (silently) on:
[    2.283437] usb 1-3: new high-speed USB device number 3 using exynos-ehci
[    2.473786] usb 1-3: New USB device found, idVendor=0424, idProduct=3503
[    2.474856] usb 1-3: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    2.482656] hub 1-3:1.0: USB hub found
[    2.486017] hub 1-3:1.0: 3 ports detected
[   55.037205] random: crng init done

Full log attached.

Best regards,
Krzysztof

-------------- next part --------------
U-Boot 2017.01-rc2-00044-g8653b94a8f5a (Jan 06 2017 - 18:05:55 +0200)

CPU:   Exynos4412 @ 1 GHz
Model: Odroid based on Exynos4412
Board: Odroid based on Exynos4412
Type:  u3
DRAM:  2 GiB
LDO20 at VDDQ_EMMC_1.8V: set 1800000 uV; enabling
LDO22 at VDDQ_EMMC_2.8V: set 2800000 uV; enabling
LDO21 at TFLASH_2.8V: set 2800000 uV; enabling
MMC:   SAMSUNG SDHCI: 0, EXYNOS DWMMC: 1
Net:   No ethernet found.
Hit any key to stop autoboot:  0
Odroid #
Odroid # run nn
reading boot.scr
2051 bytes read in 22 ms (90.8 KiB/s)
## Executing script at 42000000
reading /zImage
4641960 bytes read in 226 ms (19.6 MiB/s)
reading /dtbs/exynos4412-odroidu3.dtb
54779 bytes read in 41 ms (1.3 MiB/s)
reading /initramfs-linux.img
** Unable to read file /initramfs-linux.img **
Kernel image @ 0x40007fc0 [ 0x000000 - 0x46d4a8 ]
## Flattened Device Tree blob at 40800000
   Booting using the fdt blob at 0x40800000
   Loading Device Tree to 4ffef000, end 4ffff5fa ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0xa00
[    0.000000] Linux version 4.10.0-rc5-next-20170125-00050-g0dc3a91a2fba (kozik at kozik-lap) (gcc version 6.2.0 20161005 (Ubuntu 6.2.0-5ubuntu12) ) #368 SMP PREEMPT Fri Jan 27 21:41:22 IST 2017
[    0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] OF: fdt:Machine model: Hardkernel ODROID-U3 board based on Exynos4412
[    0.000000] Reserved memory: created DMA memory pool at 0xbf700000, size 8 MiB
[    0.000000] OF: reserved mem: initialized node region_mfc_right, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0xbe700000, size 16 MiB
[    0.000000] OF: reserved mem: initialized node region_mfc_left, compatible id shared-dma-pool
[    0.000000] cma: Reserved 64 MiB at 0xba400000
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] Samsung CPU ID: 0xe4412220
[    0.000000] Running under secure firmware.
[    0.000000] percpu: Embedded 16 pages/cpu @eefb9000 s34008 r8192 d23336 u65536
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 516352
[    0.000000] Kernel command line: console=tty1 console=ttySAC1,115200n8 root=PARTUUID=82ec0a4a-02 rw rootwait smsc95xx.macaddr=00:1e:06:61:7a:94  no_console_suspend
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Memory: 1976632K/2071552K available (7168K kernel code, 279K rwdata, 2284K rodata, 1024K init, 319K bss, 29384K reserved, 65536K cma-reserved, 1219584K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0800000   (8160 kB)
[    0.000000]       .init : 0xc0b00000 - 0xc0c00000   (1024 kB)
[    0.000000]       .data : 0xc0c00000 - 0xc0c45f00   ( 280 kB)
[    0.000000]        .bss : 0xc0c47000 - 0xc0c96d68   ( 320 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  Build-time adjustment of leaf fanout to 32.
[    0.000000]  RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=4
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] L2C: platform modifies aux control register: 0x02070000 -> 0x3e470001
[    0.000000] L2C: platform provided aux values permit register corruption.
[    0.000000] L2C: DT/platform modifies aux control register: 0x02070000 -> 0x3e470001
[    0.000000] L2C-310 enabling early BRESP for Cortex-A9
[    0.000000] L2C-310: enabling full line of zeros but not enabled in Cortex-A9
[    0.000000] L2C-310 ID prefetch enabled, offset 8 lines
[    0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
[    0.000000] L2C-310 cache controller enabled, 16 ways, 1024 kB
[    0.000000] L2C-310: CACHE_ID 0x4100c4c8, AUX_CTRL 0x7e470001
[    0.000000] Exynos4x12 clocks: sclk_apll = 1000000000, sclk_mpll = 800000000
[    0.000000]  sclk_epll = 96000000, sclk_vpll = 350000000, arm_clk = 1000000000
[    0.000000] Switching to timer-based delay loop, resolution 41ns
[    0.000000] clocksource: mct-frc: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
[    0.000004] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
[    0.000248] Console: colour dummy device 80x30
[    0.000903] console [tty1] enabled
[    0.000928] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000)
[    0.000961] pid_max: default: 32768 minimum: 301
[    0.001046] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001069] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001478] CPU: Testing write buffer coherency: ok
[    0.001790] CPU0: thread -1, cpu 0, socket 10, mpidr 80000a00
[    0.030004] Setting up static identity map for 0x40100000 - 0x40100058
[    0.119992] smp: Bringing up secondary CPUs ...
[    0.200315] CPU1: thread -1, cpu 1, socket 10, mpidr 80000a01
[    0.280298] CPU2: thread -1, cpu 2, socket 10, mpidr 80000a02
[    0.360290] CPU3: thread -1, cpu 3, socket 10, mpidr 80000a03
[    0.360351] smp: Brought up 1 node, 4 CPUs
[    0.360417] SMP: Total of 4 processors activated (192.00 BogoMIPS).
[    0.360435] CPU: All CPU(s) started in SVC mode.
[    0.361227] devtmpfs: initialized
[    0.371920] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
[    0.372168] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.373950] pinctrl core: initialized pinctrl subsystem
[    0.374590] lcd0-power-domain has as child subdomain: tv-power-domain.
[    0.375416] NET: Registered protocol family 16
[    0.377168] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.378419] cpuidle: using governor menu
[    0.409143] SCSI subsystem initialized
[    0.409343] usbcore: registered new interface driver usbfs
[    0.409409] usbcore: registered new interface driver hub
[    0.409490] usbcore: registered new device driver usb
[    0.410050] s3c-i2c 13860000.i2c: slave address 0x00
[    0.410080] s3c-i2c 13860000.i2c: bus frequency set to 390 KHz
[    0.410542] s3c-i2c 13860000.i2c: i2c-0: S3C I2C adapter
[    0.410719] s3c-i2c 13870000.i2c: slave address 0x00
[    0.410747] s3c-i2c 13870000.i2c: bus frequency set to 97 KHz
[    0.411065] s3c-i2c 13870000.i2c: i2c-1: S3C I2C adapter
[    0.411207] s3c-i2c 13880000.i2c: slave address 0x00
[    0.411233] s3c-i2c 13880000.i2c: bus frequency set to 97 KHz
[    0.411429] s3c-i2c 13880000.i2c: i2c-2: S3C I2C adapter
[    0.411538] s3c-i2c 138e0000.i2c: slave address 0x00
[    0.411564] s3c-i2c 138e0000.i2c: bus frequency set to 97 KHz
[    0.411876] s3c-i2c 138e0000.i2c: i2c-8: S3C I2C adapter
[    0.412490] Advanced Linux Sound Architecture Driver Initialized.
[    0.413377] clocksource: Switched to clocksource mct-frc
[    0.421266] NET: Registered protocol family 2
[    0.421722] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[    0.421811] TCP bind hash table entries: 8192 (order: 5, 163840 bytes)
[    0.421964] TCP: Hash tables configured (established 8192 bind 8192)
[    0.422053] UDP hash table entries: 512 (order: 2, 24576 bytes)
[    0.422105] UDP-Lite hash table entries: 512 (order: 2, 24576 bytes)
[    0.422264] NET: Registered protocol family 1
[    0.422620] RPC: Registered named UNIX socket transport module.
[    0.422644] RPC: Registered udp transport module.
[    0.422661] RPC: Registered tcp transport module.
[    0.422678] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.423858] futex hash table entries: 1024 (order: 4, 65536 bytes)
[    0.424208] workingset: timestamp_bits=30 max_order=19 bucket_order=0
[    0.430657] NFS: Registering the id_resolver key type
[    0.430706] Key type id_resolver registered
[    0.430724] Key type id_legacy registered
[    0.430767] romfs: ROMFS MTD (C) 2007 Red Hat, Inc.
[    0.431536] bounce: pool size: 64 pages
[    0.431693] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249)
[    0.431723] io scheduler noop registered
[    0.431740] io scheduler deadline registered
[    0.431877] io scheduler cfq registered (default)
[    0.431897] io scheduler mq-deadline registered
[    0.433431] 125b0000.exynos-usbphy supply vbus not found, using dummy regulator
[    0.439237] dma-pl330 12680000.pdma: Loaded driver for PL330 DMAC-141330
[    0.439270] dma-pl330 12680000.pdma:         DBUFF-32x4bytes Num_Chans-8 Num_Peri-32 Num_Events-32
[    0.441766] dma-pl330 12690000.pdma: Loaded driver for PL330 DMAC-141330
[    0.441798] dma-pl330 12690000.pdma:         DBUFF-32x4bytes Num_Chans-8 Num_Peri-32 Num_Events-32
[    0.442549] dma-pl330 12850000.mdma: Loaded driver for PL330 DMAC-141330
[    0.442579] dma-pl330 12850000.mdma:         DBUFF-64x8bytes Num_Chans-8 Num_Peri-1 Num_Events-32
[    0.494061] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    0.495894] 13800000.serial: ttySAC0 at MMIO 0x13800000 (irq = 53, base_baud = 0) is a S3C6400/10
[    0.496268] 13810000.serial: ttySAC1 at MMIO 0x13810000 (irq = 54, base_baud = 0) is a S3C6400/10
[    1.267780] console [ttySAC1] enabled
[    1.275320] exynos-hdmi 12d00000.hdmi: Failed to get supply 'vdd': -517
[    1.290270] brd: module loaded
[    1.295375] loop: module loaded
[    1.309140] random: fast init done
[    1.318865] s3c64xx-spi 13930000.spi: spi bus clock parent not specified, using clock at index 0 as parent
[    1.322902] s3c64xx-spi 13930000.spi: number of chip select lines not specified, assuming 1 chip select line
[    1.333776] libphy: Fixed MDIO Bus: probed
[    1.336988] usbcore: registered new interface driver r8152
[    1.342292] usbcore: registered new interface driver asix
[    1.347687] usbcore: registered new interface driver ax88179_178a
[    1.353749] usbcore: registered new interface driver cdc_ether
[    1.359557] usbcore: registered new interface driver smsc75xx
[    1.365304] usbcore: registered new interface driver smsc95xx
[    1.371002] usbcore: registered new interface driver net1080
[    1.376690] usbcore: registered new interface driver cdc_subset
[    1.382552] usbcore: registered new interface driver zaurus
[    1.388139] usbcore: registered new interface driver cdc_ncm
[    1.395179] dwc2 12480000.hsotg: Invalid value 1024 for param g-np-tx-fifo-size
[    1.401043] dwc2 12480000.hsotg: EPs: 16, dedicated fifos, 7808 entries in SPRAM
[    1.409298] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    1.414922] ehci-exynos: EHCI EXYNOS driver
[    1.419646] exynos-ehci 12580000.ehci: EHCI Host Controller
[    1.424658] exynos-ehci 12580000.ehci: new USB bus registered, assigned bus number 1
[    1.432518] exynos-ehci 12580000.ehci: irq 51, io mem 0x12580000
[    1.463415] exynos-ehci 12580000.ehci: USB 2.0 started, EHCI 1.00
[    1.464014] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    1.470649] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.477878] usb usb1: Product: EHCI Host Controller
[    1.482710] usb usb1: Manufacturer: Linux 4.10.0-rc5-next-20170125-00050-g0dc3a91a2fba ehci_hcd
[    1.491414] usb usb1: SerialNumber: 12580000.ehci
[    1.496554] hub 1-0:1.0: USB hub found
[    1.499835] hub 1-0:1.0: 3 ports detected
[    1.504425] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    1.510001] ohci-exynos: OHCI EXYNOS driver
[    1.514852] usbcore: registered new interface driver usb-storage
[    1.530924] usb3503 0-0008: switched to HUB mode
[    1.530999] usb3503 0-0008: usb3503_probe: probed in hub mode
[    1.535979] using random self ethernet address
[    1.540062] using random host ethernet address
[    1.544882] usb0: HOST MAC 7a:d4:f7:e7:93:e8
[    1.548792] usb0: MAC 7a:25:6d:db:b1:9e
[    1.552566] using random self ethernet address
[    1.557007] using random host ethernet address
[    1.561441] g_ether gadget: Ethernet Gadget, version: Memorial Day 2008
[    1.568031] g_ether gadget: g_ether ready
[    1.572014] dwc2 12480000.hsotg: bound driver g_ether
[    1.580371] mousedev: PS/2 mouse device common for all mice
[    1.711692] max77686-rtc max77686-rtc: rtc core: registered max77686-rtc as rtc0
[    1.714380] rtc rtc1: invalid alarm value: 1900-1-2 0:0:0
[    1.718981] s3c-rtc 10070000.rtc: rtc core: registered s3c as rtc1
[    1.725512] i2c /dev entries driver
[    1.732753] s3c2410-wdt 10060000.watchdog: watchdog inactive, reset disabled, irq disabled
[    1.737332] device-mapper: ioctl: 4.35.0-ioctl (2016-06-23) initialised: dm-devel at redhat.com
[    1.748201] sdhci: Secure Digital Host Controller Interface driver
[    1.751299] sdhci: Copyright(c) Pierre Ossman
[    1.756052] s3c-sdhci 12530000.sdhci: clock source 2: mmc_busclk.2 (100000000 Hz)
[    1.763186] s3c-sdhci 12530000.sdhci: Got CD GPIO
[    1.823530] mmc0: SDHCI controller on samsung-hsmmc [12530000.sdhci] using ADMA
[    1.825409] Synopsys Designware Multimedia Card Interface Driver
[    1.831817] dwmmc_exynos 12550000.mmc: IDMAC supports 32-bit address mode.
[    1.838133] dwmmc_exynos 12550000.mmc: Using internal DMA controller.
[    1.844493] dwmmc_exynos 12550000.mmc: Version ID is 240a
[    1.849876] dwmmc_exynos 12550000.mmc: DW MMC controller at irq 110,32 bit host data width,128 deep fifo
[    1.859539] dwmmc_exynos 12550000.mmc: allocated mmc-pwrseq
[    1.864902] usb 1-2: new high-speed USB device number 2 using exynos-ehci
[    1.871688] mmc_host mmc1: card is polling.
[    1.903753] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
[    1.933547] dwmmc_exynos 12550000.mmc: 1 slots initialized
[    1.934664] s5p-secss 10830000.sss: s5p-sss driver registered
[    1.942516] usbcore: registered new interface driver usbhid
[    1.944707] usbhid: USB HID core driver
[    1.959692] NET: Registered protocol family 10
[    1.960359] Segment Routing with IPv6
[    1.962179] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    1.968428] NET: Registered protocol family 17
[    1.972486] NET: Registered protocol family 15
[    1.977036] Key type dns_resolver registered
[    1.981461] Registering SWP/SWPB emulation handler
[    1.987135] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
[    2.013136] [drm] Exynos DRM: using 12c10000.mixer device for DMA mapping operations
[    2.015626] exynos-drm exynos-drm: bound 12c10000.mixer (ops mixer_component_ops)
[    2.022899] exynos-drm exynos-drm: bound 12d00000.hdmi (ops hdmi_component_ops)
[    2.030045] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    2.036622] [drm] No driver support for vblank timestamp query.
[    2.042549] [drm] Initialized exynos 1.0.0 20110530 for exynos-drm on minor 0
[    2.050968] exynos-bus: new bus device registered: bus_dmc (100000 KHz ~ 400000 KHz)
[    2.053768] usb 1-2: New USB device found, idVendor=0424, idProduct=9730
[    2.053776] usb 1-2: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    2.056426] smsc95xx v1.0.5
[    2.064078] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
[    2.084445] exynos-bus: new bus device registered: bus_acp (100000 KHz ~ 267000 KHz)
[    2.091742] exynos-bus: new bus device registered: bus_c2c (100000 KHz ~ 400000 KHz)
[    2.093515] mmc0: new high speed SDHC card at address 0007
[    2.094029] mmcblk0: mmc0:0007 SD16G 14.5 GiB
[    2.095502]  mmcblk0: p1 p2 p3
[    2.113868] exynos-bus: new bus device registered: bus_leftbus (100000 KHz ~ 200000 KHz)
[    2.120680] exynos-bus: new bus device registered: bus_rightbus (100000 KHz ~ 200000 KHz)
[    2.129026] exynos-bus: new bus device registered: bus_display (160000 KHz ~ 200000 KHz)
[    2.137031] exynos-bus: new bus device registered: bus_fsys (100000 KHz ~ 134000 KHz)
[    2.144828] exynos-bus: new bus device registered: bus_peri ( 50000 KHz ~ 100000 KHz)
[    2.149095] smsc95xx 1-2:1.0 eth0: register 'smsc95xx' at usb-12580000.ehci-2, smsc95xx USB 2.0 Ethernet, 5a:46:f5:aa:8d:36
[    2.154191] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
[    2.173243] exynos-bus: new bus device registered: bus_mfc (100000 KHz ~ 200000 KHz)
[    2.214263] max98090 1-0010: MAX98090 REVID=0x43
[    2.217699] max98090 1-0010: use default 2.8v micbias
[    2.225755] asoc-simple-card sound: HiFi <-> 3830000.i2s mapping ok
[    2.229872] input: gpio_keys as /devices/platform/gpio_keys/input/input0
[    2.266862] max77686-rtc max77686-rtc: setting system clock to 2017-01-27 19:43:23 UTC (1485546203)
[    2.283437] usb 1-3: new high-speed USB device number 3 using exynos-ehci
[    2.473786] usb 1-3: New USB device found, idVendor=0424, idProduct=3503
[    2.474856] usb 1-3: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    2.482656] hub 1-3:1.0: USB hub found
[    2.486017] hub 1-3:1.0: 3 ports detected
[   55.037205] random: crng init done

Re: [PATCH v2 0/8] Pad retentions support for Exynos5433

[Krzysztof Kozlowski]

[-- Attachment #1: Type: text/plain, Size: 1688 bytes --]

On Thu, Jan 26, 2017 at 09:33:46AM +0100, Marek Szyprowski wrote:
> Hello,
> 
> This patchset is a first step to add support for all power domains on
> Exynos5433 SoCs. This patchset contains patches for Exynos pin control
> driver and Exynos LPASS MFD driver, which are needed to make the
> platform ready for adding power domains support.
> 
> Patches in this patchset depends on each other. They are order in such a
> way to make the changes bisectable.
> 
> Patch #3 has runtime dependency on #1.
> Patch #5 has runtime dependency on #3.
> Patch #6 has runtime dependency on #4.
> 
> This patchset also directly depends on the "Move pad retention control to
> Exynos pin controller driver" patchset:
> https://www.spinics.net/lists/arm-kernel/msg556074.html
> 
> Patches have been generated on top of linux-next from 25th January 2017.
> 
> This is a part of a larger task, which goal is to add support for power
> domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it
> working have been pushed to the following git repo:
> https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd
>
I tried your branch above on Odroid U3 and it fails to boot.
next-20170125 works fine. exynos_defconfig, booting from microSD.

Board hangs (silently) on:
[    2.283437] usb 1-3: new high-speed USB device number 3 using exynos-ehci
[    2.473786] usb 1-3: New USB device found, idVendor=0424, idProduct=3503
[    2.474856] usb 1-3: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    2.482656] hub 1-3:1.0: USB hub found
[    2.486017] hub 1-3:1.0: 3 ports detected
[   55.037205] random: crng init done

Full log attached.

Best regards,
Krzysztof


[-- Attachment #2: odroid-log.txt --]
[-- Type: text/plain, Size: 17660 bytes --]

U-Boot 2017.01-rc2-00044-g8653b94a8f5a (Jan 06 2017 - 18:05:55 +0200)

CPU:   Exynos4412 @ 1 GHz
Model: Odroid based on Exynos4412
Board: Odroid based on Exynos4412
Type:  u3
DRAM:  2 GiB
LDO20@VDDQ_EMMC_1.8V: set 1800000 uV; enabling
LDO22@VDDQ_EMMC_2.8V: set 2800000 uV; enabling
LDO21@TFLASH_2.8V: set 2800000 uV; enabling
MMC:   SAMSUNG SDHCI: 0, EXYNOS DWMMC: 1
Net:   No ethernet found.
Hit any key to stop autoboot:  0
Odroid #
Odroid # run nn
reading boot.scr
2051 bytes read in 22 ms (90.8 KiB/s)
## Executing script at 42000000
reading /zImage
4641960 bytes read in 226 ms (19.6 MiB/s)
reading /dtbs/exynos4412-odroidu3.dtb
54779 bytes read in 41 ms (1.3 MiB/s)
reading /initramfs-linux.img
** Unable to read file /initramfs-linux.img **
Kernel image @ 0x40007fc0 [ 0x000000 - 0x46d4a8 ]
## Flattened Device Tree blob at 40800000
   Booting using the fdt blob at 0x40800000
   Loading Device Tree to 4ffef000, end 4ffff5fa ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0xa00
[    0.000000] Linux version 4.10.0-rc5-next-20170125-00050-g0dc3a91a2fba (kozik@kozik-lap) (gcc version 6.2.0 20161005 (Ubuntu 6.2.0-5ubuntu12) ) #368 SMP PREEMPT Fri Jan 27 21:41:22 IST 2017
[    0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] OF: fdt:Machine model: Hardkernel ODROID-U3 board based on Exynos4412
[    0.000000] Reserved memory: created DMA memory pool at 0xbf700000, size 8 MiB
[    0.000000] OF: reserved mem: initialized node region_mfc_right, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0xbe700000, size 16 MiB
[    0.000000] OF: reserved mem: initialized node region_mfc_left, compatible id shared-dma-pool
[    0.000000] cma: Reserved 64 MiB at 0xba400000
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] Samsung CPU ID: 0xe4412220
[    0.000000] Running under secure firmware.
[    0.000000] percpu: Embedded 16 pages/cpu @eefb9000 s34008 r8192 d23336 u65536
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 516352
[    0.000000] Kernel command line: console=tty1 console=ttySAC1,115200n8 root=PARTUUID=82ec0a4a-02 rw rootwait smsc95xx.macaddr=00:1e:06:61:7a:94  no_console_suspend
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Memory: 1976632K/2071552K available (7168K kernel code, 279K rwdata, 2284K rodata, 1024K init, 319K bss, 29384K reserved, 65536K cma-reserved, 1219584K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0800000   (8160 kB)
[    0.000000]       .init : 0xc0b00000 - 0xc0c00000   (1024 kB)
[    0.000000]       .data : 0xc0c00000 - 0xc0c45f00   ( 280 kB)
[    0.000000]        .bss : 0xc0c47000 - 0xc0c96d68   ( 320 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  Build-time adjustment of leaf fanout to 32.
[    0.000000]  RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=4
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] L2C: platform modifies aux control register: 0x02070000 -> 0x3e470001
[    0.000000] L2C: platform provided aux values permit register corruption.
[    0.000000] L2C: DT/platform modifies aux control register: 0x02070000 -> 0x3e470001
[    0.000000] L2C-310 enabling early BRESP for Cortex-A9
[    0.000000] L2C-310: enabling full line of zeros but not enabled in Cortex-A9
[    0.000000] L2C-310 ID prefetch enabled, offset 8 lines
[    0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
[    0.000000] L2C-310 cache controller enabled, 16 ways, 1024 kB
[    0.000000] L2C-310: CACHE_ID 0x4100c4c8, AUX_CTRL 0x7e470001
[    0.000000] Exynos4x12 clocks: sclk_apll = 1000000000, sclk_mpll = 800000000
[    0.000000]  sclk_epll = 96000000, sclk_vpll = 350000000, arm_clk = 1000000000
[    0.000000] Switching to timer-based delay loop, resolution 41ns
[    0.000000] clocksource: mct-frc: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
[    0.000004] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
[    0.000248] Console: colour dummy device 80x30
[    0.000903] console [tty1] enabled
[    0.000928] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000)
[    0.000961] pid_max: default: 32768 minimum: 301
[    0.001046] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001069] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001478] CPU: Testing write buffer coherency: ok
[    0.001790] CPU0: thread -1, cpu 0, socket 10, mpidr 80000a00
[    0.030004] Setting up static identity map for 0x40100000 - 0x40100058
[    0.119992] smp: Bringing up secondary CPUs ...
[    0.200315] CPU1: thread -1, cpu 1, socket 10, mpidr 80000a01
[    0.280298] CPU2: thread -1, cpu 2, socket 10, mpidr 80000a02
[    0.360290] CPU3: thread -1, cpu 3, socket 10, mpidr 80000a03
[    0.360351] smp: Brought up 1 node, 4 CPUs
[    0.360417] SMP: Total of 4 processors activated (192.00 BogoMIPS).
[    0.360435] CPU: All CPU(s) started in SVC mode.
[    0.361227] devtmpfs: initialized
[    0.371920] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
[    0.372168] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.373950] pinctrl core: initialized pinctrl subsystem
[    0.374590] lcd0-power-domain has as child subdomain: tv-power-domain.
[    0.375416] NET: Registered protocol family 16
[    0.377168] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.378419] cpuidle: using governor menu
[    0.409143] SCSI subsystem initialized
[    0.409343] usbcore: registered new interface driver usbfs
[    0.409409] usbcore: registered new interface driver hub
[    0.409490] usbcore: registered new device driver usb
[    0.410050] s3c-i2c 13860000.i2c: slave address 0x00
[    0.410080] s3c-i2c 13860000.i2c: bus frequency set to 390 KHz
[    0.410542] s3c-i2c 13860000.i2c: i2c-0: S3C I2C adapter
[    0.410719] s3c-i2c 13870000.i2c: slave address 0x00
[    0.410747] s3c-i2c 13870000.i2c: bus frequency set to 97 KHz
[    0.411065] s3c-i2c 13870000.i2c: i2c-1: S3C I2C adapter
[    0.411207] s3c-i2c 13880000.i2c: slave address 0x00
[    0.411233] s3c-i2c 13880000.i2c: bus frequency set to 97 KHz
[    0.411429] s3c-i2c 13880000.i2c: i2c-2: S3C I2C adapter
[    0.411538] s3c-i2c 138e0000.i2c: slave address 0x00
[    0.411564] s3c-i2c 138e0000.i2c: bus frequency set to 97 KHz
[    0.411876] s3c-i2c 138e0000.i2c: i2c-8: S3C I2C adapter
[    0.412490] Advanced Linux Sound Architecture Driver Initialized.
[    0.413377] clocksource: Switched to clocksource mct-frc
[    0.421266] NET: Registered protocol family 2
[    0.421722] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[    0.421811] TCP bind hash table entries: 8192 (order: 5, 163840 bytes)
[    0.421964] TCP: Hash tables configured (established 8192 bind 8192)
[    0.422053] UDP hash table entries: 512 (order: 2, 24576 bytes)
[    0.422105] UDP-Lite hash table entries: 512 (order: 2, 24576 bytes)
[    0.422264] NET: Registered protocol family 1
[    0.422620] RPC: Registered named UNIX socket transport module.
[    0.422644] RPC: Registered udp transport module.
[    0.422661] RPC: Registered tcp transport module.
[    0.422678] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.423858] futex hash table entries: 1024 (order: 4, 65536 bytes)
[    0.424208] workingset: timestamp_bits=30 max_order=19 bucket_order=0
[    0.430657] NFS: Registering the id_resolver key type
[    0.430706] Key type id_resolver registered
[    0.430724] Key type id_legacy registered
[    0.430767] romfs: ROMFS MTD (C) 2007 Red Hat, Inc.
[    0.431536] bounce: pool size: 64 pages
[    0.431693] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249)
[    0.431723] io scheduler noop registered
[    0.431740] io scheduler deadline registered
[    0.431877] io scheduler cfq registered (default)
[    0.431897] io scheduler mq-deadline registered
[    0.433431] 125b0000.exynos-usbphy supply vbus not found, using dummy regulator
[    0.439237] dma-pl330 12680000.pdma: Loaded driver for PL330 DMAC-141330
[    0.439270] dma-pl330 12680000.pdma:         DBUFF-32x4bytes Num_Chans-8 Num_Peri-32 Num_Events-32
[    0.441766] dma-pl330 12690000.pdma: Loaded driver for PL330 DMAC-141330
[    0.441798] dma-pl330 12690000.pdma:         DBUFF-32x4bytes Num_Chans-8 Num_Peri-32 Num_Events-32
[    0.442549] dma-pl330 12850000.mdma: Loaded driver for PL330 DMAC-141330
[    0.442579] dma-pl330 12850000.mdma:         DBUFF-64x8bytes Num_Chans-8 Num_Peri-1 Num_Events-32
[    0.494061] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    0.495894] 13800000.serial: ttySAC0 at MMIO 0x13800000 (irq = 53, base_baud = 0) is a S3C6400/10
[    0.496268] 13810000.serial: ttySAC1 at MMIO 0x13810000 (irq = 54, base_baud = 0) is a S3C6400/10
[    1.267780] console [ttySAC1] enabled
[    1.275320] exynos-hdmi 12d00000.hdmi: Failed to get supply 'vdd': -517
[    1.290270] brd: module loaded
[    1.295375] loop: module loaded
[    1.309140] random: fast init done
[    1.318865] s3c64xx-spi 13930000.spi: spi bus clock parent not specified, using clock at index 0 as parent
[    1.322902] s3c64xx-spi 13930000.spi: number of chip select lines not specified, assuming 1 chip select line
[    1.333776] libphy: Fixed MDIO Bus: probed
[    1.336988] usbcore: registered new interface driver r8152
[    1.342292] usbcore: registered new interface driver asix
[    1.347687] usbcore: registered new interface driver ax88179_178a
[    1.353749] usbcore: registered new interface driver cdc_ether
[    1.359557] usbcore: registered new interface driver smsc75xx
[    1.365304] usbcore: registered new interface driver smsc95xx
[    1.371002] usbcore: registered new interface driver net1080
[    1.376690] usbcore: registered new interface driver cdc_subset
[    1.382552] usbcore: registered new interface driver zaurus
[    1.388139] usbcore: registered new interface driver cdc_ncm
[    1.395179] dwc2 12480000.hsotg: Invalid value 1024 for param g-np-tx-fifo-size
[    1.401043] dwc2 12480000.hsotg: EPs: 16, dedicated fifos, 7808 entries in SPRAM
[    1.409298] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    1.414922] ehci-exynos: EHCI EXYNOS driver
[    1.419646] exynos-ehci 12580000.ehci: EHCI Host Controller
[    1.424658] exynos-ehci 12580000.ehci: new USB bus registered, assigned bus number 1
[    1.432518] exynos-ehci 12580000.ehci: irq 51, io mem 0x12580000
[    1.463415] exynos-ehci 12580000.ehci: USB 2.0 started, EHCI 1.00
[    1.464014] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    1.470649] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.477878] usb usb1: Product: EHCI Host Controller
[    1.482710] usb usb1: Manufacturer: Linux 4.10.0-rc5-next-20170125-00050-g0dc3a91a2fba ehci_hcd
[    1.491414] usb usb1: SerialNumber: 12580000.ehci
[    1.496554] hub 1-0:1.0: USB hub found
[    1.499835] hub 1-0:1.0: 3 ports detected
[    1.504425] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    1.510001] ohci-exynos: OHCI EXYNOS driver
[    1.514852] usbcore: registered new interface driver usb-storage
[    1.530924] usb3503 0-0008: switched to HUB mode
[    1.530999] usb3503 0-0008: usb3503_probe: probed in hub mode
[    1.535979] using random self ethernet address
[    1.540062] using random host ethernet address
[    1.544882] usb0: HOST MAC 7a:d4:f7:e7:93:e8
[    1.548792] usb0: MAC 7a:25:6d:db:b1:9e
[    1.552566] using random self ethernet address
[    1.557007] using random host ethernet address
[    1.561441] g_ether gadget: Ethernet Gadget, version: Memorial Day 2008
[    1.568031] g_ether gadget: g_ether ready
[    1.572014] dwc2 12480000.hsotg: bound driver g_ether
[    1.580371] mousedev: PS/2 mouse device common for all mice
[    1.711692] max77686-rtc max77686-rtc: rtc core: registered max77686-rtc as rtc0
[    1.714380] rtc rtc1: invalid alarm value: 1900-1-2 0:0:0
[    1.718981] s3c-rtc 10070000.rtc: rtc core: registered s3c as rtc1
[    1.725512] i2c /dev entries driver
[    1.732753] s3c2410-wdt 10060000.watchdog: watchdog inactive, reset disabled, irq disabled
[    1.737332] device-mapper: ioctl: 4.35.0-ioctl (2016-06-23) initialised: dm-devel@redhat.com
[    1.748201] sdhci: Secure Digital Host Controller Interface driver
[    1.751299] sdhci: Copyright(c) Pierre Ossman
[    1.756052] s3c-sdhci 12530000.sdhci: clock source 2: mmc_busclk.2 (100000000 Hz)
[    1.763186] s3c-sdhci 12530000.sdhci: Got CD GPIO
[    1.823530] mmc0: SDHCI controller on samsung-hsmmc [12530000.sdhci] using ADMA
[    1.825409] Synopsys Designware Multimedia Card Interface Driver
[    1.831817] dwmmc_exynos 12550000.mmc: IDMAC supports 32-bit address mode.
[    1.838133] dwmmc_exynos 12550000.mmc: Using internal DMA controller.
[    1.844493] dwmmc_exynos 12550000.mmc: Version ID is 240a
[    1.849876] dwmmc_exynos 12550000.mmc: DW MMC controller at irq 110,32 bit host data width,128 deep fifo
[    1.859539] dwmmc_exynos 12550000.mmc: allocated mmc-pwrseq
[    1.864902] usb 1-2: new high-speed USB device number 2 using exynos-ehci
[    1.871688] mmc_host mmc1: card is polling.
[    1.903753] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
[    1.933547] dwmmc_exynos 12550000.mmc: 1 slots initialized
[    1.934664] s5p-secss 10830000.sss: s5p-sss driver registered
[    1.942516] usbcore: registered new interface driver usbhid
[    1.944707] usbhid: USB HID core driver
[    1.959692] NET: Registered protocol family 10
[    1.960359] Segment Routing with IPv6
[    1.962179] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    1.968428] NET: Registered protocol family 17
[    1.972486] NET: Registered protocol family 15
[    1.977036] Key type dns_resolver registered
[    1.981461] Registering SWP/SWPB emulation handler
[    1.987135] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
[    2.013136] [drm] Exynos DRM: using 12c10000.mixer device for DMA mapping operations
[    2.015626] exynos-drm exynos-drm: bound 12c10000.mixer (ops mixer_component_ops)
[    2.022899] exynos-drm exynos-drm: bound 12d00000.hdmi (ops hdmi_component_ops)
[    2.030045] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    2.036622] [drm] No driver support for vblank timestamp query.
[    2.042549] [drm] Initialized exynos 1.0.0 20110530 for exynos-drm on minor 0
[    2.050968] exynos-bus: new bus device registered: bus_dmc (100000 KHz ~ 400000 KHz)
[    2.053768] usb 1-2: New USB device found, idVendor=0424, idProduct=9730
[    2.053776] usb 1-2: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    2.056426] smsc95xx v1.0.5
[    2.064078] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
[    2.084445] exynos-bus: new bus device registered: bus_acp (100000 KHz ~ 267000 KHz)
[    2.091742] exynos-bus: new bus device registered: bus_c2c (100000 KHz ~ 400000 KHz)
[    2.093515] mmc0: new high speed SDHC card at address 0007
[    2.094029] mmcblk0: mmc0:0007 SD16G 14.5 GiB
[    2.095502]  mmcblk0: p1 p2 p3
[    2.113868] exynos-bus: new bus device registered: bus_leftbus (100000 KHz ~ 200000 KHz)
[    2.120680] exynos-bus: new bus device registered: bus_rightbus (100000 KHz ~ 200000 KHz)
[    2.129026] exynos-bus: new bus device registered: bus_display (160000 KHz ~ 200000 KHz)
[    2.137031] exynos-bus: new bus device registered: bus_fsys (100000 KHz ~ 134000 KHz)
[    2.144828] exynos-bus: new bus device registered: bus_peri ( 50000 KHz ~ 100000 KHz)
[    2.149095] smsc95xx 1-2:1.0 eth0: register 'smsc95xx' at usb-12580000.ehci-2, smsc95xx USB 2.0 Ethernet, 5a:46:f5:aa:8d:36
[    2.154191] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
[    2.173243] exynos-bus: new bus device registered: bus_mfc (100000 KHz ~ 200000 KHz)
[    2.214263] max98090 1-0010: MAX98090 REVID=0x43
[    2.217699] max98090 1-0010: use default 2.8v micbias
[    2.225755] asoc-simple-card sound: HiFi <-> 3830000.i2s mapping ok
[    2.229872] input: gpio_keys as /devices/platform/gpio_keys/input/input0
[    2.266862] max77686-rtc max77686-rtc: setting system clock to 2017-01-27 19:43:23 UTC (1485546203)
[    2.283437] usb 1-3: new high-speed USB device number 3 using exynos-ehci
[    2.473786] usb 1-3: New USB device found, idVendor=0424, idProduct=3503
[    2.474856] usb 1-3: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    2.482656] hub 1-3:1.0: USB hub found
[    2.486017] hub 1-3:1.0: 3 ports detected
[   55.037205] random: crng init done

Re: [PATCH v2 0/8] Pad retentions support for Exynos5433

[Marek Szyprowski]

Hi Krzysztof,

On 2017-01-27 20:46, Krzysztof Kozlowski wrote:
> On Thu, Jan 26, 2017 at 09:33:46AM +0100, Marek Szyprowski wrote:
>> This patchset is a first step to add support for all power domains on
>> Exynos5433 SoCs. This patchset contains patches for Exynos pin control
>> driver and Exynos LPASS MFD driver, which are needed to make the
>> platform ready for adding power domains support.
>>
>> Patches in this patchset depends on each other. They are order in such a
>> way to make the changes bisectable.
>>
>> Patch #3 has runtime dependency on #1.
>> Patch #5 has runtime dependency on #3.
>> Patch #6 has runtime dependency on #4.
>>
>> This patchset also directly depends on the "Move pad retention control to
>> Exynos pin controller driver" patchset:
>> https://www.spinics.net/lists/arm-kernel/msg556074.html
>>
>> Patches have been generated on top of linux-next from 25th January 2017.
>>
>> This is a part of a larger task, which goal is to add support for power
>> domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it
>> working have been pushed to the following git repo:
>> https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd
>>
> I tried your branch above on Odroid U3 and it fails to boot.
> next-20170125 works fine. exynos_defconfig, booting from microSD.
>
> Board hangs (silently) on:
> [    2.283437] usb 1-3: new high-speed USB device number 3 using exynos-ehci
> [    2.473786] usb 1-3: New USB device found, idVendor=0424, idProduct=3503
> [    2.474856] usb 1-3: New USB device strings: Mfr=0, Product=0, SerialNumber=0
> [    2.482656] hub 1-3:1.0: USB hub found
> [    2.486017] hub 1-3:1.0: 3 ports detected
> [   55.037205] random: crng init done
>
> Full log attached.

Huh... Reproduced. This is another reincarnation of the prepare_mutex in 
clock's
core related deadlock, now caused by Exynos Audio Subsystem clock's 
driver, Exynos
I2S driver and Samsung SDHCI driver.

It looks that this issue becomes even more problematic now and urgently 
needs
a proper fix, because it gets really hard to make more workarounds 
everywhere else.
For now I will probably drop Exynos AudioSS patch from this series and 
send a revert
for commit 9b41da80e09128574f09bed8dc5a5fc6f72a8239 ("ASoC: samsung: 
i2s: Provide
I2S device for registered clocks"), which has to wait until the deadlock 
gets proper
generic fix.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

[PATCH v2 0/8] Pad retentions support for Exynos5433

[Marek Szyprowski]

Hi Krzysztof,

On 2017-01-27 20:46, Krzysztof Kozlowski wrote:
> On Thu, Jan 26, 2017 at 09:33:46AM +0100, Marek Szyprowski wrote:
>> This patchset is a first step to add support for all power domains on
>> Exynos5433 SoCs. This patchset contains patches for Exynos pin control
>> driver and Exynos LPASS MFD driver, which are needed to make the
>> platform ready for adding power domains support.
>>
>> Patches in this patchset depends on each other. They are order in such a
>> way to make the changes bisectable.
>>
>> Patch #3 has runtime dependency on #1.
>> Patch #5 has runtime dependency on #3.
>> Patch #6 has runtime dependency on #4.
>>
>> This patchset also directly depends on the "Move pad retention control to
>> Exynos pin controller driver" patchset:
>> https://www.spinics.net/lists/arm-kernel/msg556074.html
>>
>> Patches have been generated on top of linux-next from 25th January 2017.
>>
>> This is a part of a larger task, which goal is to add support for power
>> domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it
>> working have been pushed to the following git repo:
>> https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd
>>
> I tried your branch above on Odroid U3 and it fails to boot.
> next-20170125 works fine. exynos_defconfig, booting from microSD.
>
> Board hangs (silently) on:
> [    2.283437] usb 1-3: new high-speed USB device number 3 using exynos-ehci
> [    2.473786] usb 1-3: New USB device found, idVendor=0424, idProduct=3503
> [    2.474856] usb 1-3: New USB device strings: Mfr=0, Product=0, SerialNumber=0
> [    2.482656] hub 1-3:1.0: USB hub found
> [    2.486017] hub 1-3:1.0: 3 ports detected
> [   55.037205] random: crng init done
>
> Full log attached.

Huh... Reproduced. This is another reincarnation of the prepare_mutex in 
clock's
core related deadlock, now caused by Exynos Audio Subsystem clock's 
driver, Exynos
I2S driver and Samsung SDHCI driver.

It looks that this issue becomes even more problematic now and urgently 
needs
a proper fix, because it gets really hard to make more workarounds 
everywhere else.
For now I will probably drop Exynos AudioSS patch from this series and 
send a revert
for commit 9b41da80e09128574f09bed8dc5a5fc6f72a8239 ("ASoC: samsung: 
i2s: Provide
I2S device for registered clocks"), which has to wait until the deadlock 
gets proper
generic fix.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH v2 0/8] Pad retentions support for Exynos5433

[Marek Szyprowski]

Hi Krzysztof,

On 2017-01-27 20:46, Krzysztof Kozlowski wrote:
> On Thu, Jan 26, 2017 at 09:33:46AM +0100, Marek Szyprowski wrote:
>> This patchset is a first step to add support for all power domains on
>> Exynos5433 SoCs. This patchset contains patches for Exynos pin control
>> driver and Exynos LPASS MFD driver, which are needed to make the
>> platform ready for adding power domains support.
>>
>> Patches in this patchset depends on each other. They are order in such a
>> way to make the changes bisectable.
>>
>> Patch #3 has runtime dependency on #1.
>> Patch #5 has runtime dependency on #3.
>> Patch #6 has runtime dependency on #4.
>>
>> This patchset also directly depends on the "Move pad retention control to
>> Exynos pin controller driver" patchset:
>> https://www.spinics.net/lists/arm-kernel/msg556074.html
>>
>> Patches have been generated on top of linux-next from 25th January 2017.
>>
>> This is a part of a larger task, which goal is to add support for power
>> domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it
>> working have been pushed to the following git repo:
>> https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd
>>
> I tried your branch above on Odroid U3 and it fails to boot.
> next-20170125 works fine. exynos_defconfig, booting from microSD.
>
> Board hangs (silently) on:
> [    2.283437] usb 1-3: new high-speed USB device number 3 using exynos-ehci
> [    2.473786] usb 1-3: New USB device found, idVendor=0424, idProduct=3503
> [    2.474856] usb 1-3: New USB device strings: Mfr=0, Product=0, SerialNumber=0
> [    2.482656] hub 1-3:1.0: USB hub found
> [    2.486017] hub 1-3:1.0: 3 ports detected
> [   55.037205] random: crng init done
>
> Full log attached.

Huh... Reproduced. This is another reincarnation of the prepare_mutex in 
clock's
core related deadlock, now caused by Exynos Audio Subsystem clock's 
driver, Exynos
I2S driver and Samsung SDHCI driver.

It looks that this issue becomes even more problematic now and urgently 
needs
a proper fix, because it gets really hard to make more workarounds 
everywhere else.
For now I will probably drop Exynos AudioSS patch from this series and 
send a revert
for commit 9b41da80e09128574f09bed8dc5a5fc6f72a8239 ("ASoC: samsung: 
i2s: Provide
I2S device for registered clocks"), which has to wait until the deadlock 
gets proper
generic fix.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland