[PATCH v2 1/2] drm/i915/glk: Apply cdclk workaround for DP audio

[PATCH v2 1/2] drm/i915/glk: Apply cdclk workaround for DP audio

[Dhinakaran Pandiyan]

Implement the DP-Audio cdclk restriction for GLK, similar to what is
implemented for BDW and other GEN9 platforms. The max. pixel clock
adjustment for GLK, however factors in the 2 pixels per clock output that
GLK generates.

Separating min. cdclk and max. pixel_rate would be nicer, but let's
defer that to future and fix the GLK bug for now.

Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index de5ce6b..e8c1181 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1442,16 +1442,21 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
 	if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
 		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
 
-	/* BSpec says "Do not use DisplayPort with CDCLK less than
-	 * 432 MHz, audio enabled, port width x4, and link rate
-	 * HBR2 (5.4 GHz), or else there may be audio corruption or
-	 * screen corruption."
+	/* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
+	 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
+	 * there may be audio corruption or screen corruption." This cdclk
+	 * restriction for GLK is 316.8 MHz and since GLK can output two
+	 * pixels per clock, the pixel rate becomes 2 * 316.8 MHz.
 	 */
 	if (intel_crtc_has_dp_encoder(crtc_state) &&
 	    crtc_state->has_audio &&
 	    crtc_state->port_clock >= 540000 &&
-	    crtc_state->lane_count == 4)
-		pixel_rate = max(432000, pixel_rate);
+	    crtc_state->lane_count == 4) {
+		if (IS_GEMINILAKE(dev_priv))
+			pixel_rate = max(2 * 316800, pixel_rate);
+		else
+			pixel_rate = max(432000, pixel_rate);
+	}
 
 	return pixel_rate;
 }
-- 
2.7.4

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[PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Dhinakaran Pandiyan]

According to BSpec, "The CD clock frequency must be at least twice the
frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
default. This check is needed because BXT and GLK support cdclk
frequencies less than 192 MHz.

Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index e8c1181..7b1ac1d 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
 			pixel_rate = max(432000, pixel_rate);
 	}
 
+	/* According to BSpec, "The CD clock frequency must be at least twice
+	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
+	 * The check for GLK has to be adjusted as the platform can output
+	 * two pixels per clock.
+	 */
+	if (crtc_state->has_audio) {
+		if (IS_GEMINILAKE(dev_priv))
+			pixel_rate = max(2 * 2 * 96000, pixel_rate);
+		if (IS_BROXTON(dev_priv))
+			pixel_rate = max(2 * 96000, pixel_rate);
+	}
+
 	return pixel_rate;
 }
 
-- 
2.7.4

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✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/glk: Apply cdclk workaround for DP audio

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/glk: Apply cdclk workaround for DP audio
URL   : https://patchwork.freedesktop.org/series/20862/
State : success

== Summary ==

Series 20862v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/20862/revisions/1/mbox/

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-uc:
                fail       -> PASS       (fi-snb-2600) fdo#100007
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-c:
                dmesg-warn -> PASS       (fi-bsw-n3050)
Test prime_vgem:
        Subgroup basic-wait-default:
                dmesg-warn -> PASS       (fi-bsw-n3050)

fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 464s
fi-bsw-n3050     total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  time: 615s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 535s
fi-bxt-t5700     total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  time: 630s
fi-byt-j1900     total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  time: 508s
fi-byt-n2820     total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  time: 499s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 437s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 439s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 441s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 491s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 487s
fi-kbl-7500u     total:278  pass:259  dwarn:1   dfail:0   fail:0   skip:18  time: 480s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 527s
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  time: 600s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time: 504s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 549s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 549s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time: 414s

22a3a8313335d0958175580a6212a97fc04b3b69 drm-tip: 2017y-03m-07d-22h-03m-11s UTC integration manifest
79b37ff drm/i915: Implement cdclk restrictions based on Azalia BCLK
8372d33 drm/i915/glk: Apply cdclk workaround for DP audio

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4091/
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Re: [PATCH v2 1/2] drm/i915/glk: Apply cdclk workaround for DP audio

[Paulo Zanoni]

Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan escreveu:
> Implement the DP-Audio cdclk restriction for GLK, similar to what is
> implemented for BDW and other GEN9 platforms. The max. pixel clock
> adjustment for GLK, however factors in the 2 pixels per clock output
> that
> GLK generates.
> 
> Separating min. cdclk and max. pixel_rate would be nicer, but let's
> defer that to future and fix the GLK bug for now.

Looks correct to me.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

No cc:stable seems to be required due to GLK still being alpha_support.

> 
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 17 +++++++++++------
>  1 file changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index de5ce6b..e8c1181 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1442,16 +1442,21 @@ static int
> bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
>  	if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
>  		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
>  
> -	/* BSpec says "Do not use DisplayPort with CDCLK less than
> -	 * 432 MHz, audio enabled, port width x4, and link rate
> -	 * HBR2 (5.4 GHz), or else there may be audio corruption or
> -	 * screen corruption."
> +	/* BSpec says "Do not use DisplayPort with CDCLK less than
> 432 MHz,
> +	 * audio enabled, port width x4, and link rate HBR2 (5.4
> GHz), or else
> +	 * there may be audio corruption or screen corruption." This
> cdclk
> +	 * restriction for GLK is 316.8 MHz and since GLK can output
> two
> +	 * pixels per clock, the pixel rate becomes 2 * 316.8 MHz.
>  	 */
>  	if (intel_crtc_has_dp_encoder(crtc_state) &&
>  	    crtc_state->has_audio &&
>  	    crtc_state->port_clock >= 540000 &&
> -	    crtc_state->lane_count == 4)
> -		pixel_rate = max(432000, pixel_rate);
> +	    crtc_state->lane_count == 4) {
> +		if (IS_GEMINILAKE(dev_priv))
> +			pixel_rate = max(2 * 316800, pixel_rate);
> +		else
> +			pixel_rate = max(432000, pixel_rate);
> +	}
>  
>  	return pixel_rate;
>  }
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Re: [PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Paulo Zanoni]

Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan escreveu:
> According to BSpec, "The CD clock frequency must be at least twice
> the
> frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
> default. This check is needed because BXT and GLK support cdclk
> frequencies less than 192 MHz.
> 
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index e8c1181..7b1ac1d 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1458,6 +1458,18 @@ static int
> bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
>  			pixel_rate = max(432000, pixel_rate);
>  	}
>  
> +	/* According to BSpec, "The CD clock frequency must be at
> least twice
> +	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by
> default.
> +	 * The check for GLK has to be adjusted as the platform can
> output
> +	 * two pixels per clock.
> +	 */
> +	if (crtc_state->has_audio) {
> +		if (IS_GEMINILAKE(dev_priv))
> +			pixel_rate = max(2 * 2 * 96000, pixel_rate);
> +		if (IS_BROXTON(dev_priv))

SKL also documents this in the page that explains the cdclk freq change
sequences. The funny thing is that the minimum CDCLK for SKL seems to
be 308.57, so that's still bigger than 96*2... Anyway, having this for
completeness would probably be good, just in case I'm missing some
detail that's important here.

I'd like to see the SKL addition, but I can live without it in case you
have some better argument, so if you don't send a new version, here's
it:

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>


Perhaps it would also be interesting to have some sort of macro to
identify the platform(s) that need the magic *2 calculation. A more
confusion-proof version of this function would look like this:

if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
	if (HAS_2_PIXELS_PER_CLOCK(dev_priv))
		pixel_rate = max(2 * 2 * 96000, pixel_rate);
	else
		pixel_rate = max(2 * 96000, pixel_rate);

Maybe we'd be able to use the macro in other places too (I haven't
checked). The new macro would definitely be part of a separate patch on
top of these.



> +			pixel_rate = max(2 * 96000, pixel_rate);
> +	}
> +
>  	return pixel_rate;
>  }
>  
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Re: [PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Pandiyan, Dhinakaran]

On Tue, 2017-03-14 at 17:47 -0300, Paulo Zanoni wrote:
> Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan escreveu:
> > According to BSpec, "The CD clock frequency must be at least twice
> > the
> > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
> > default. This check is needed because BXT and GLK support cdclk
> > frequencies less than 192 MHz.
> > 
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > index e8c1181..7b1ac1d 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1458,6 +1458,18 @@ static int
> > bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> >  			pixel_rate = max(432000, pixel_rate);
> >  	}
> >  
> > +	/* According to BSpec, "The CD clock frequency must be at
> > least twice
> > +	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by
> > default.
> > +	 * The check for GLK has to be adjusted as the platform can
> > output
> > +	 * two pixels per clock.
> > +	 */
> > +	if (crtc_state->has_audio) {
> > +		if (IS_GEMINILAKE(dev_priv))
> > +			pixel_rate = max(2 * 2 * 96000, pixel_rate);
> > +		if (IS_BROXTON(dev_priv))
> 
> SKL also documents this in the page that explains the cdclk freq change
> sequences. The funny thing is that the minimum CDCLK for SKL seems to
> be 308.57, so that's still bigger than 96*2... Anyway, having this for
> completeness would probably be good, just in case I'm missing some
> detail that's important here.
> 
> I'd like to see the SKL addition, but I can live without it in case you
> have some better argument, so if you don't send a new version, here's
> it:
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> 

I did not include SKL as the lowest cdclk freq. it supports was higher
than 2 * 96MHz. But, I agree it's good to include it for clarity. I'll
send another version.


> Perhaps it would also be interesting to have some sort of macro to
> identify the platform(s) that need the magic *2 calculation. A more
> confusion-proof version of this function would look like this:
> 
> if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
> 	if (HAS_2_PIXELS_PER_CLOCK(dev_priv))
> 		pixel_rate = max(2 * 2 * 96000, pixel_rate);
> 	else
> 		pixel_rate = max(2 * 96000, pixel_rate);
> 
> Maybe we'd be able to use the macro in other places too (I haven't
> checked). The new macro would definitely be part of a separate patch on
> top of these.
> 
> 
> 

Agreed. Using a macro makes it cleaner, will send a patch for this too.

-DK

> > +			pixel_rate = max(2 * 96000, pixel_rate);
> > +	}
> > +
> >  	return pixel_rate;
> >  }
> >  
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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[PATCH v3 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Dhinakaran Pandiyan]

According to BSpec, "The CD clock frequency must be at least twice the
frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
default. This check is needed because BXT and GLK support cdclk
frequencies less than 192 MHz.

v2: Include other Gen9 platforms too for completeness.(Paulo)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index dd350642..dd3ad52 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
 			pixel_rate = max(432000, pixel_rate);
 	}
 
+	/* According to BSpec, "The CD clock frequency must be at least twice
+	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
+	 * The check for GLK has to be adjusted as the platform can output
+	 * two pixels per clock.
+	 */
+	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
+		if (IS_GEMINILAKE(dev_priv))
+			pixel_rate = max(2 * 2 * 96000, pixel_rate);
+		else
+			pixel_rate = max(2 * 96000, pixel_rate);
+	}
+
 	return pixel_rate;
 }
 
-- 
2.7.4

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✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/glk: Apply cdclk workaround for DP audio (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/glk: Apply cdclk workaround for DP audio (rev2)
URL   : https://patchwork.freedesktop.org/series/20862/
State : failure

== Summary ==

Series 20862v2 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/20862/revisions/2/mbox/

Test gem_exec_flush:
        Subgroup basic-uc-pro-default:
                pass       -> INCOMPLETE (fi-skl-6700hq) fdo#100130
                pass       -> INCOMPLETE (fi-skl-6770hq) fdo#100130
        Subgroup basic-uc-ro-default:
                pass       -> INCOMPLETE (fi-skl-6260u)
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-atomic:
                fail       -> PASS       (fi-snb-2520m)

fdo#100130 https://bugs.freedesktop.org/show_bug.cgi?id=100130

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 459s
fi-bsw-n3050     total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  time: 584s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 533s
fi-bxt-t5700     total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  time: 544s
fi-byt-j1900     total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  time: 499s
fi-byt-n2820     total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  time: 496s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 437s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 502s
fi-skl-6260u     total:55   pass:53   dwarn:0   dfail:0   fail:0   skip:1   time: 0s
fi-skl-6700hq    total:53   pass:45   dwarn:0   dfail:0   fail:0   skip:7   time: 0s
fi-skl-6770hq    total:53   pass:51   dwarn:0   dfail:0   fail:0   skip:1   time: 0s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 556s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time: 424s

c641417b70c6b78efca29ae732d7cbf5716ac6d5 drm-tip: 2017y-03m-14d-16h-04m-56s UTC integration manifest
81b8c78 drm/i915: Implement cdclk restrictions based on Azalia BCLK
0886697 drm/i915/glk: Apply cdclk workaround for DP audio

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4174/
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✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/glk: Apply cdclk workaround for DP audio (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/glk: Apply cdclk workaround for DP audio (rev2)
URL   : https://patchwork.freedesktop.org/series/20862/
State : success

== Summary ==

Series 20862v2 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/20862/revisions/2/mbox/

Test gem_exec_flush:
        Subgroup basic-uc-pro-default:
                pass       -> INCOMPLETE (fi-skl-6700hq) fdo#100130
                pass       -> INCOMPLETE (fi-skl-6770hq) fdo#100130
        Subgroup basic-uc-ro-default:
                pass       -> INCOMPLETE (fi-skl-6260u) fdo#100130
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-atomic:
                fail       -> PASS       (fi-snb-2520m)

fdo#100130 https://bugs.freedesktop.org/show_bug.cgi?id=100130

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 459s
fi-bsw-n3050     total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  time: 584s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 533s
fi-bxt-t5700     total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  time: 544s
fi-byt-j1900     total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  time: 499s
fi-byt-n2820     total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  time: 496s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 437s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 502s
fi-skl-6260u     total:55   pass:53   dwarn:0   dfail:0   fail:0   skip:1   time: 0s
fi-skl-6700hq    total:53   pass:45   dwarn:0   dfail:0   fail:0   skip:7   time: 0s
fi-skl-6770hq    total:53   pass:51   dwarn:0   dfail:0   fail:0   skip:1   time: 0s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 556s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time: 424s

c641417b70c6b78efca29ae732d7cbf5716ac6d5 drm-tip: 2017y-03m-14d-16h-04m-56s UTC integration manifest
81b8c78 drm/i915: Implement cdclk restrictions based on Azalia BCLK
0886697 drm/i915/glk: Apply cdclk workaround for DP audio

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4174/
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Re: [PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Jani Nikula]

On Tue, 14 Mar 2017, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote:
> On Tue, 2017-03-14 at 17:47 -0300, Paulo Zanoni wrote:
>> Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan escreveu:
>> > According to BSpec, "The CD clock frequency must be at least twice
>> > the
>> > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
>> > default. This check is needed because BXT and GLK support cdclk
>> > frequencies less than 192 MHz.
>> > 
>> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
>> >  1 file changed, 12 insertions(+)
>> > 
>> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
>> > b/drivers/gpu/drm/i915/intel_cdclk.c
>> > index e8c1181..7b1ac1d 100644
>> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
>> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>> > @@ -1458,6 +1458,18 @@ static int
>> > bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
>> >  			pixel_rate = max(432000, pixel_rate);
>> >  	}
>> >  
>> > +	/* According to BSpec, "The CD clock frequency must be at
>> > least twice
>> > +	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by
>> > default.
>> > +	 * The check for GLK has to be adjusted as the platform can
>> > output
>> > +	 * two pixels per clock.
>> > +	 */
>> > +	if (crtc_state->has_audio) {
>> > +		if (IS_GEMINILAKE(dev_priv))
>> > +			pixel_rate = max(2 * 2 * 96000, pixel_rate);
>> > +		if (IS_BROXTON(dev_priv))
>> 
>> SKL also documents this in the page that explains the cdclk freq change
>> sequences. The funny thing is that the minimum CDCLK for SKL seems to
>> be 308.57, so that's still bigger than 96*2... Anyway, having this for
>> completeness would probably be good, just in case I'm missing some
>> detail that's important here.
>> 
>> I'd like to see the SKL addition, but I can live without it in case you
>> have some better argument, so if you don't send a new version, here's
>> it:
>> 
>> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> 
>> 
>
> I did not include SKL as the lowest cdclk freq. it supports was higher
> than 2 * 96MHz. But, I agree it's good to include it for clarity. I'll
> send another version.
>
>
>> Perhaps it would also be interesting to have some sort of macro to
>> identify the platform(s) that need the magic *2 calculation. A more
>> confusion-proof version of this function would look like this:
>> 
>> if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
>> 	if (HAS_2_PIXELS_PER_CLOCK(dev_priv))

I didn't check the spec (where's the fun in that?!) about the
terminology it uses, but isn't that just double data rate, or DDR?

BR,
Jani.


>> 		pixel_rate = max(2 * 2 * 96000, pixel_rate);
>> 	else
>> 		pixel_rate = max(2 * 96000, pixel_rate);
>> 
>> Maybe we'd be able to use the macro in other places too (I haven't
>> checked). The new macro would definitely be part of a separate patch on
>> top of these.
>> 
>> 
>> 
>
> Agreed. Using a macro makes it cleaner, will send a patch for this too.
>
> -DK
>
>> > +			pixel_rate = max(2 * 96000, pixel_rate);
>> > +	}
>> > +
>> >  	return pixel_rate;
>> >  }
>> >  
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Pandiyan, Dhinakaran]

On Wed, 2017-03-15 at 11:32 +0200, Jani Nikula wrote:
> On Tue, 14 Mar 2017, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote:
> > On Tue, 2017-03-14 at 17:47 -0300, Paulo Zanoni wrote:
> >> Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan escreveu:
> >> > According to BSpec, "The CD clock frequency must be at least twice
> >> > the
> >> > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
> >> > default. This check is needed because BXT and GLK support cdclk
> >> > frequencies less than 192 MHz.
> >> > 
> >> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
> >> >  1 file changed, 12 insertions(+)
> >> > 
> >> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> >> > b/drivers/gpu/drm/i915/intel_cdclk.c
> >> > index e8c1181..7b1ac1d 100644
> >> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> >> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> >> > @@ -1458,6 +1458,18 @@ static int
> >> > bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> >> >  			pixel_rate = max(432000, pixel_rate);
> >> >  	}
> >> >  
> >> > +	/* According to BSpec, "The CD clock frequency must be at
> >> > least twice
> >> > +	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by
> >> > default.
> >> > +	 * The check for GLK has to be adjusted as the platform can
> >> > output
> >> > +	 * two pixels per clock.
> >> > +	 */
> >> > +	if (crtc_state->has_audio) {
> >> > +		if (IS_GEMINILAKE(dev_priv))
> >> > +			pixel_rate = max(2 * 2 * 96000, pixel_rate);
> >> > +		if (IS_BROXTON(dev_priv))
> >> 
> >> SKL also documents this in the page that explains the cdclk freq change
> >> sequences. The funny thing is that the minimum CDCLK for SKL seems to
> >> be 308.57, so that's still bigger than 96*2... Anyway, having this for
> >> completeness would probably be good, just in case I'm missing some
> >> detail that's important here.
> >> 
> >> I'd like to see the SKL addition, but I can live without it in case you
> >> have some better argument, so if you don't send a new version, here's
> >> it:
> >> 
> >> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >> 
> >> 
> >
> > I did not include SKL as the lowest cdclk freq. it supports was higher
> > than 2 * 96MHz. But, I agree it's good to include it for clarity. I'll
> > send another version.
> >
> >
> >> Perhaps it would also be interesting to have some sort of macro to
> >> identify the platform(s) that need the magic *2 calculation. A more
> >> confusion-proof version of this function would look like this:
> >> 
> >> if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
> >> 	if (HAS_2_PIXELS_PER_CLOCK(dev_priv))
> 
> I didn't check the spec (where's the fun in that?!) about the
> terminology it uses, but isn't that just double data rate, or DDR?
> 
> BR,
> Jani.
> 
> 

I found no reference to "DDR" in the spec., which thankfully avoids
confusing this with the memory technology.

-DK

> >> 		pixel_rate = max(2 * 2 * 96000, pixel_rate);
> >> 	else
> >> 		pixel_rate = max(2 * 96000, pixel_rate);
> >> 
> >> Maybe we'd be able to use the macro in other places too (I haven't
> >> checked). The new macro would definitely be part of a separate patch on
> >> top of these.
> >> 
> >> 
> >> 
> >
> > Agreed. Using a macro makes it cleaner, will send a patch for this too.
> >
> > -DK
> >
> >> > +			pixel_rate = max(2 * 96000, pixel_rate);
> >> > +	}
> >> > +
> >> >  	return pixel_rate;
> >> >  }
> >> >  
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

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Re: [PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Ville Syrjälä]

On Wed, Mar 15, 2017 at 06:03:58PM +0000, Pandiyan, Dhinakaran wrote:
> On Wed, 2017-03-15 at 11:32 +0200, Jani Nikula wrote:
> > On Tue, 14 Mar 2017, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote:
> > > On Tue, 2017-03-14 at 17:47 -0300, Paulo Zanoni wrote:
> > >> Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan escreveu:
> > >> > According to BSpec, "The CD clock frequency must be at least twice
> > >> > the
> > >> > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
> > >> > default. This check is needed because BXT and GLK support cdclk
> > >> > frequencies less than 192 MHz.
> > >> > 
> > >> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > >> > ---
> > >> >  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
> > >> >  1 file changed, 12 insertions(+)
> > >> > 
> > >> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > >> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > >> > index e8c1181..7b1ac1d 100644
> > >> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > >> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > >> > @@ -1458,6 +1458,18 @@ static int
> > >> > bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> > >> >  			pixel_rate = max(432000, pixel_rate);
> > >> >  	}
> > >> >  
> > >> > +	/* According to BSpec, "The CD clock frequency must be at
> > >> > least twice
> > >> > +	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by
> > >> > default.
> > >> > +	 * The check for GLK has to be adjusted as the platform can
> > >> > output
> > >> > +	 * two pixels per clock.
> > >> > +	 */
> > >> > +	if (crtc_state->has_audio) {
> > >> > +		if (IS_GEMINILAKE(dev_priv))
> > >> > +			pixel_rate = max(2 * 2 * 96000, pixel_rate);
> > >> > +		if (IS_BROXTON(dev_priv))
> > >> 
> > >> SKL also documents this in the page that explains the cdclk freq change
> > >> sequences. The funny thing is that the minimum CDCLK for SKL seems to
> > >> be 308.57, so that's still bigger than 96*2... Anyway, having this for
> > >> completeness would probably be good, just in case I'm missing some
> > >> detail that's important here.
> > >> 
> > >> I'd like to see the SKL addition, but I can live without it in case you
> > >> have some better argument, so if you don't send a new version, here's
> > >> it:
> > >> 
> > >> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > >> 
> > >> 
> > >
> > > I did not include SKL as the lowest cdclk freq. it supports was higher
> > > than 2 * 96MHz. But, I agree it's good to include it for clarity. I'll
> > > send another version.
> > >
> > >
> > >> Perhaps it would also be interesting to have some sort of macro to
> > >> identify the platform(s) that need the magic *2 calculation. A more
> > >> confusion-proof version of this function would look like this:
> > >> 
> > >> if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
> > >> 	if (HAS_2_PIXELS_PER_CLOCK(dev_priv))
> > 
> > I didn't check the spec (where's the fun in that?!) about the
> > terminology it uses, but isn't that just double data rate, or DDR?
> > 
> > BR,
> > Jani.
> > 
> > 
> 
> I found no reference to "DDR" in the spec., which thankfully avoids
> confusing this with the memory technology.

What this was called back in the gen2/3 days is "double wide pipe". We
could perhaps just keep using that name. Although the gen2/3 thing was
something you could enable/disable on demand.

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Paulo Zanoni]

Em Qua, 2017-03-15 às 20:16 +0200, Ville Syrjälä escreveu:
> On Wed, Mar 15, 2017 at 06:03:58PM +0000, Pandiyan, Dhinakaran wrote:
> > 
> > On Wed, 2017-03-15 at 11:32 +0200, Jani Nikula wrote:
> > > 
> > > On Tue, 14 Mar 2017, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@
> > > intel.com> wrote:
> > > > 
> > > > On Tue, 2017-03-14 at 17:47 -0300, Paulo Zanoni wrote:
> > > > > 
> > > > > Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan
> > > > > escreveu:
> > > > > > 
> > > > > > According to BSpec, "The CD clock frequency must be at
> > > > > > least twice
> > > > > > the
> > > > > > frequency of the Azalia BCLK." and BCLK is configured to 96
> > > > > > MHz by
> > > > > > default. This check is needed because BXT and GLK support
> > > > > > cdclk
> > > > > > frequencies less than 192 MHz.
> > > > > > 
> > > > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@int
> > > > > > el.com>
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
> > > > > >  1 file changed, 12 insertions(+)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > > > > > b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > > > index e8c1181..7b1ac1d 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > > > @@ -1458,6 +1458,18 @@ static int
> > > > > > bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state
> > > > > > *crtc_state,
> > > > > >  			pixel_rate = max(432000,
> > > > > > pixel_rate);
> > > > > >  	}
> > > > > >  
> > > > > > +	/* According to BSpec, "The CD clock frequency
> > > > > > must be at
> > > > > > least twice
> > > > > > +	 * the frequency of the Azalia BCLK." and BCLK is
> > > > > > 96 MHz by
> > > > > > default.
> > > > > > +	 * The check for GLK has to be adjusted as the
> > > > > > platform can
> > > > > > output
> > > > > > +	 * two pixels per clock.
> > > > > > +	 */
> > > > > > +	if (crtc_state->has_audio) {
> > > > > > +		if (IS_GEMINILAKE(dev_priv))
> > > > > > +			pixel_rate = max(2 * 2 * 96000,
> > > > > > pixel_rate);
> > > > > > +		if (IS_BROXTON(dev_priv))
> > > > > 
> > > > > SKL also documents this in the page that explains the cdclk
> > > > > freq change
> > > > > sequences. The funny thing is that the minimum CDCLK for SKL
> > > > > seems to
> > > > > be 308.57, so that's still bigger than 96*2... Anyway, having
> > > > > this for
> > > > > completeness would probably be good, just in case I'm missing
> > > > > some
> > > > > detail that's important here.
> > > > > 
> > > > > I'd like to see the SKL addition, but I can live without it
> > > > > in case you
> > > > > have some better argument, so if you don't send a new
> > > > > version, here's
> > > > > it:
> > > > > 
> > > > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > > 
> > > > > 
> > > > 
> > > > I did not include SKL as the lowest cdclk freq. it supports was
> > > > higher
> > > > than 2 * 96MHz. But, I agree it's good to include it for
> > > > clarity. I'll
> > > > send another version.
> > > > 
> > > > 
> > > > > 
> > > > > Perhaps it would also be interesting to have some sort of
> > > > > macro to
> > > > > identify the platform(s) that need the magic *2 calculation.
> > > > > A more
> > > > > confusion-proof version of this function would look like
> > > > > this:
> > > > > 
> > > > > if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
> > > > > 	if (HAS_2_PIXELS_PER_CLOCK(dev_priv))
> > > 
> > > I didn't check the spec (where's the fun in that?!) about the
> > > terminology it uses, but isn't that just double data rate, or
> > > DDR?
> > > 
> > > BR,
> > > Jani.
> > > 
> > > 
> > 
> > I found no reference to "DDR" in the spec., which thankfully avoids
> > confusing this with the memory technology.
> 
> What this was called back in the gen2/3 days is "double wide pipe".
> We
> could perhaps just keep using that name. Although the gen2/3 thing
> was
> something you could enable/disable on demand.

At least in the docs I can find, this feature for the new platform is
always referred to as "two pixels per clock". AFAIR the gen 2/3 thing
is indeed "double wide" and I don't think it makes sense to call the
new thing "double wide", even if it were the exact same thing. IMHO
naming a feature of Gen 9 after something that's only present in Gen
2/3, even if it's the same, only adds confusion to the driver: now
you're requiring that people working on new stuff actually have
knowledge about the super old stuff for basically zero reason. You can
just use the new name in the new context...

This is the same reason why I'm not a big fan of using older #defines
for registers that changed name but are still mostly the same on newer
platforms: it requires that people reading the code actually know about
all the different platforms, while having an additional #define
wouldn't really hurt. But, anyway, that's just MHO.

> 
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Re: [PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Ville Syrjälä]

On Wed, Mar 15, 2017 at 03:39:58PM -0300, Paulo Zanoni wrote:
> Em Qua, 2017-03-15 às 20:16 +0200, Ville Syrjälä escreveu:
> > On Wed, Mar 15, 2017 at 06:03:58PM +0000, Pandiyan, Dhinakaran wrote:
> > > 
> > > On Wed, 2017-03-15 at 11:32 +0200, Jani Nikula wrote:
> > > > 
> > > > On Tue, 14 Mar 2017, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@
> > > > intel.com> wrote:
> > > > > 
> > > > > On Tue, 2017-03-14 at 17:47 -0300, Paulo Zanoni wrote:
> > > > > > 
> > > > > > Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan
> > > > > > escreveu:
> > > > > > > 
> > > > > > > According to BSpec, "The CD clock frequency must be at
> > > > > > > least twice
> > > > > > > the
> > > > > > > frequency of the Azalia BCLK." and BCLK is configured to 96
> > > > > > > MHz by
> > > > > > > default. This check is needed because BXT and GLK support
> > > > > > > cdclk
> > > > > > > frequencies less than 192 MHz.
> > > > > > > 
> > > > > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@int
> > > > > > > el.com>
> > > > > > > ---
> > > > > > >  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
> > > > > > >  1 file changed, 12 insertions(+)
> > > > > > > 
> > > > > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > > > > > > b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > > > > index e8c1181..7b1ac1d 100644
> > > > > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > > > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > > > > @@ -1458,6 +1458,18 @@ static int
> > > > > > > bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state
> > > > > > > *crtc_state,
> > > > > > >  			pixel_rate = max(432000,
> > > > > > > pixel_rate);
> > > > > > >  	}
> > > > > > >  
> > > > > > > +	/* According to BSpec, "The CD clock frequency
> > > > > > > must be at
> > > > > > > least twice
> > > > > > > +	 * the frequency of the Azalia BCLK." and BCLK is
> > > > > > > 96 MHz by
> > > > > > > default.
> > > > > > > +	 * The check for GLK has to be adjusted as the
> > > > > > > platform can
> > > > > > > output
> > > > > > > +	 * two pixels per clock.
> > > > > > > +	 */
> > > > > > > +	if (crtc_state->has_audio) {
> > > > > > > +		if (IS_GEMINILAKE(dev_priv))
> > > > > > > +			pixel_rate = max(2 * 2 * 96000,
> > > > > > > pixel_rate);
> > > > > > > +		if (IS_BROXTON(dev_priv))
> > > > > > 
> > > > > > SKL also documents this in the page that explains the cdclk
> > > > > > freq change
> > > > > > sequences. The funny thing is that the minimum CDCLK for SKL
> > > > > > seems to
> > > > > > be 308.57, so that's still bigger than 96*2... Anyway, having
> > > > > > this for
> > > > > > completeness would probably be good, just in case I'm missing
> > > > > > some
> > > > > > detail that's important here.
> > > > > > 
> > > > > > I'd like to see the SKL addition, but I can live without it
> > > > > > in case you
> > > > > > have some better argument, so if you don't send a new
> > > > > > version, here's
> > > > > > it:
> > > > > > 
> > > > > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > > > 
> > > > > > 
> > > > > 
> > > > > I did not include SKL as the lowest cdclk freq. it supports was
> > > > > higher
> > > > > than 2 * 96MHz. But, I agree it's good to include it for
> > > > > clarity. I'll
> > > > > send another version.
> > > > > 
> > > > > 
> > > > > > 
> > > > > > Perhaps it would also be interesting to have some sort of
> > > > > > macro to
> > > > > > identify the platform(s) that need the magic *2 calculation.
> > > > > > A more
> > > > > > confusion-proof version of this function would look like
> > > > > > this:
> > > > > > 
> > > > > > if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
> > > > > > 	if (HAS_2_PIXELS_PER_CLOCK(dev_priv))
> > > > 
> > > > I didn't check the spec (where's the fun in that?!) about the
> > > > terminology it uses, but isn't that just double data rate, or
> > > > DDR?
> > > > 
> > > > BR,
> > > > Jani.
> > > > 
> > > > 
> > > 
> > > I found no reference to "DDR" in the spec., which thankfully avoids
> > > confusing this with the memory technology.
> > 
> > What this was called back in the gen2/3 days is "double wide pipe".
> > We
> > could perhaps just keep using that name. Although the gen2/3 thing
> > was
> > something you could enable/disable on demand.
> 
> At least in the docs I can find, this feature for the new platform is
> always referred to as "two pixels per clock". AFAIR the gen 2/3 thing
> is indeed "double wide" and I don't think it makes sense to call the
> new thing "double wide", even if it were the exact same thing. IMHO
> naming a feature of Gen 9 after something that's only present in Gen
> 2/3, even if it's the same, only adds confusion to the driver: now
> you're requiring that people working on new stuff actually have
> knowledge about the super old stuff for basically zero reason. You can
> just use the new name in the new context...

Dunno. I'll keep calling it double wide most likely. One less name for
me to remember ;)

> 
> This is the same reason why I'm not a big fan of using older #defines
> for registers that changed name but are still mostly the same on newer
> platforms: it requires that people reading the code actually know about
> all the different platforms, while having an additional #define
> wouldn't really hurt. But, anyway, that's just MHO.

We'd have to duplicate boatloads of code if we wanted to match the bspec
register names all the time (+ I have a feeling they keep renaming them
even after the silicon has shipped). And duplicated code just means more
bugs which are also harder to find since it reduces the testing coverage
for each copy of the same code.

Thus we really want to be using the old register names at least when the
code as a whole can be shared. And I think sometimes using the old name
and sometimes the new name would lead to even more confusion. I think
there are a few cases where that is probably happening already, and
people might not even realize because they no longer associate the old
name with the new platform since most other parts of the code are using
the new name.

So I still think trying to follow the latest and greatest naming scheme
of the day would just lead to chaos. IMO the best way to fix this would
be to convinve the hardware folks to stop renaming things all the time.

-- 
Ville Syrjälä
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Re: [PATCH v3 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Paulo Zanoni]

Em Ter, 2017-03-14 às 15:45 -0700, Dhinakaran Pandiyan escreveu:
> According to BSpec, "The CD clock frequency must be at least twice
> the
> frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
> default. This check is needed because BXT and GLK support cdclk
> frequencies less than 192 MHz.
> 
> v2: Include other Gen9 platforms too for completeness.(Paulo)

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index dd350642..dd3ad52 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1458,6 +1458,18 @@ static int
> bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
>  			pixel_rate = max(432000, pixel_rate);
>  	}
>  
> +	/* According to BSpec, "The CD clock frequency must be at
> least twice
> +	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by
> default.
> +	 * The check for GLK has to be adjusted as the platform can
> output
> +	 * two pixels per clock.
> +	 */
> +	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
> +		if (IS_GEMINILAKE(dev_priv))
> +			pixel_rate = max(2 * 2 * 96000, pixel_rate);
> +		else
> +			pixel_rate = max(2 * 96000, pixel_rate);
> +	}
> +
>  	return pixel_rate;
>  }
>  
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Re: [PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Ville Syrjälä]

On Tue, Mar 07, 2017 at 04:12:52PM -0800, Dhinakaran Pandiyan wrote:
> According to BSpec, "The CD clock frequency must be at least twice the
> frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
> default. This check is needed because BXT and GLK support cdclk
> frequencies less than 192 MHz.
> 
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index e8c1181..7b1ac1d 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
>  			pixel_rate = max(432000, pixel_rate);
>  	}
>  
> +	/* According to BSpec, "The CD clock frequency must be at least twice
> +	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> +	 * The check for GLK has to be adjusted as the platform can output
> +	 * two pixels per clock.
> +	 */
> +	if (crtc_state->has_audio) {
> +		if (IS_GEMINILAKE(dev_priv))
> +			pixel_rate = max(2 * 2 * 96000, pixel_rate);

BTW that x2 factor for GLK looks wrong. It should be /2.

https://bugs.freedesktop.org/show_bug.cgi?id=100439

> +		if (IS_BROXTON(dev_priv))
> +			pixel_rate = max(2 * 96000, pixel_rate);
> +	}
> +
>  	return pixel_rate;
>  }
>  
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Pandiyan, Dhinakaran]

On Wed, 2017-03-29 at 11:50 +0300, Ville Syrjälä wrote:
> On Tue, Mar 07, 2017 at 04:12:52PM -0800, Dhinakaran Pandiyan wrote:
> > According to BSpec, "The CD clock frequency must be at least twice the
> > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
> > default. This check is needed because BXT and GLK support cdclk
> > frequencies less than 192 MHz.
> > 
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > index e8c1181..7b1ac1d 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> >  			pixel_rate = max(432000, pixel_rate);
> >  	}
> >  
> > +	/* According to BSpec, "The CD clock frequency must be at least twice
> > +	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> > +	 * The check for GLK has to be adjusted as the platform can output
> > +	 * two pixels per clock.
> > +	 */
> > +	if (crtc_state->has_audio) {
> > +		if (IS_GEMINILAKE(dev_priv))
> > +			pixel_rate = max(2 * 2 * 96000, pixel_rate);
> 
> BTW that x2 factor for GLK looks wrong. It should be /2.
> 
> https://bugs.freedesktop.org/show_bug.cgi?id=100439
> 

BSpec[1] says cdclk needs to be > 2*96 MHz (azalia bclk). To set a cdclk
> 192 MHz on GLK, we need to pass in max_pixclk = 2*192 MHz. But with a
factor of /2, we can end up picking 158.4 MHz or 79.2 MHz for cdclk,
which are lower than 192 MHz.


	static int glk_calc_cdclk(int max_pixclk)
	{
	        if (max_pixclk > 2 * 158400)
        	        return 316800;
	        else if (max_pixclk > 2 * 79200)
        	        return 158400;
        	else
        	        return 79200;
	}

[1] Geminilake Clocks
"158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is
96 MHz)
316.8 MHz CD
79.2 MHz CD (exclusively for resolutions up to 1080p in low power single
pipe eDP/MIPI configurations, no audio support)"



-DK

> > +		if (IS_BROXTON(dev_priv))
> > +			pixel_rate = max(2 * 96000, pixel_rate);
> > +	}
> > +
> >  	return pixel_rate;
> >  }
> >  
> > -- 
> > 2.7.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

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Re: [PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Ville Syrjälä]

On Wed, Mar 29, 2017 at 09:16:36PM +0000, Pandiyan, Dhinakaran wrote:
> On Wed, 2017-03-29 at 11:50 +0300, Ville Syrjälä wrote:
> > On Tue, Mar 07, 2017 at 04:12:52PM -0800, Dhinakaran Pandiyan wrote:
> > > According to BSpec, "The CD clock frequency must be at least twice the
> > > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
> > > default. This check is needed because BXT and GLK support cdclk
> > > frequencies less than 192 MHz.
> > > 
> > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
> > >  1 file changed, 12 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > > index e8c1181..7b1ac1d 100644
> > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > @@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> > >  			pixel_rate = max(432000, pixel_rate);
> > >  	}
> > >  
> > > +	/* According to BSpec, "The CD clock frequency must be at least twice
> > > +	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> > > +	 * The check for GLK has to be adjusted as the platform can output
> > > +	 * two pixels per clock.
> > > +	 */
> > > +	if (crtc_state->has_audio) {
> > > +		if (IS_GEMINILAKE(dev_priv))
> > > +			pixel_rate = max(2 * 2 * 96000, pixel_rate);
> > 
> > BTW that x2 factor for GLK looks wrong. It should be /2.
> > 
> > https://bugs.freedesktop.org/show_bug.cgi?id=100439
> > 
> 
> BSpec[1] says cdclk needs to be > 2*96 MHz (azalia bclk). To set a cdclk
> > 192 MHz on GLK, we need to pass in max_pixclk = 2*192 MHz. But with a
> factor of /2, we can end up picking 158.4 MHz or 79.2 MHz for cdclk,
> which are lower than 192 MHz.
> 
> 
> 	static int glk_calc_cdclk(int max_pixclk)
> 	{
> 	        if (max_pixclk > 2 * 158400)
>         	        return 316800;
> 	        else if (max_pixclk > 2 * 79200)
>         	        return 158400;
>         	else
>         	        return 79200;
> 	}
> 
> [1] Geminilake Clocks
> "158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is
> 96 MHz)
> 316.8 MHz CD
> 79.2 MHz CD (exclusively for resolutions up to 1080p in low power single
> pipe eDP/MIPI configurations, no audio support)"

Argh. So it's really about the cdclk freq vs. bclk. Apparently the fact
that the pipe can output two pixels per clock doesn't extend to the HDA
side. OK, then the code looks correct.

But how do we know the bclk is really 96Mhz? Or are we just making a
worst case estimate here? Base on the hda spec I think bclk should typically
be 24 MHz, but of course the hda spec is so old that it probably has
little to do with today's realities. I guess ideally we'd like the audio
driver to tell us what the frequency is, or we'd dig that up from
somewhere ourselves.

Hmm. AUD_FREQ_CNTRL seems to have something. 96 vs. 48 MHz. But I'm not sure
we could trust that at boot time. Not sure if the audio driver will make
its own choice if BCLK somewhere. Can any alsa folks help us?

> 
> 
> 
> -DK
> 
> > > +		if (IS_BROXTON(dev_priv))
> > > +			pixel_rate = max(2 * 96000, pixel_rate);
> > > +	}
> > > +
> > >  	return pixel_rate;
> > >  }
> > >  
> > > -- 
> > > 2.7.4
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> 

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Takashi Iwai]

On Thu, 30 Mar 2017 13:42:09 +0200,
Ville Syrjälä wrote:
> 
> On Wed, Mar 29, 2017 at 09:16:36PM +0000, Pandiyan, Dhinakaran wrote:
> > On Wed, 2017-03-29 at 11:50 +0300, Ville Syrjälä wrote:
> > > On Tue, Mar 07, 2017 at 04:12:52PM -0800, Dhinakaran Pandiyan wrote:
> > > > According to BSpec, "The CD clock frequency must be at least twice the
> > > > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
> > > > default. This check is needed because BXT and GLK support cdclk
> > > > frequencies less than 192 MHz.
> > > > 
> > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
> > > >  1 file changed, 12 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > index e8c1181..7b1ac1d 100644
> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > @@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> > > >  			pixel_rate = max(432000, pixel_rate);
> > > >  	}
> > > >  
> > > > +	/* According to BSpec, "The CD clock frequency must be at least twice
> > > > +	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> > > > +	 * The check for GLK has to be adjusted as the platform can output
> > > > +	 * two pixels per clock.
> > > > +	 */
> > > > +	if (crtc_state->has_audio) {
> > > > +		if (IS_GEMINILAKE(dev_priv))
> > > > +			pixel_rate = max(2 * 2 * 96000, pixel_rate);
> > > 
> > > BTW that x2 factor for GLK looks wrong. It should be /2.
> > > 
> > > https://bugs.freedesktop.org/show_bug.cgi?id=100439
> > > 
> > 
> > BSpec[1] says cdclk needs to be > 2*96 MHz (azalia bclk). To set a cdclk
> > > 192 MHz on GLK, we need to pass in max_pixclk = 2*192 MHz. But with a
> > factor of /2, we can end up picking 158.4 MHz or 79.2 MHz for cdclk,
> > which are lower than 192 MHz.
> > 
> > 
> > 	static int glk_calc_cdclk(int max_pixclk)
> > 	{
> > 	        if (max_pixclk > 2 * 158400)
> >         	        return 316800;
> > 	        else if (max_pixclk > 2 * 79200)
> >         	        return 158400;
> >         	else
> >         	        return 79200;
> > 	}
> > 
> > [1] Geminilake Clocks
> > "158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is
> > 96 MHz)
> > 316.8 MHz CD
> > 79.2 MHz CD (exclusively for resolutions up to 1080p in low power single
> > pipe eDP/MIPI configurations, no audio support)"
> 
> Argh. So it's really about the cdclk freq vs. bclk. Apparently the fact
> that the pipe can output two pixels per clock doesn't extend to the HDA
> side. OK, then the code looks correct.
> 
> But how do we know the bclk is really 96Mhz? Or are we just making a
> worst case estimate here? Base on the hda spec I think bclk should typically
> be 24 MHz, but of course the hda spec is so old that it probably has
> little to do with today's realities. I guess ideally we'd like the audio
> driver to tell us what the frequency is, or we'd dig that up from
> somewhere ourselves.
> 
> Hmm. AUD_FREQ_CNTRL seems to have something. 96 vs. 48 MHz. But I'm not sure
> we could trust that at boot time. Not sure if the audio driver will make
> its own choice if BCLK somewhere. Can any alsa folks help us?

Well, I'm not sure which BCLK is referred in this context, but if it's
about HD-audio (aka Azalia) BCLK, it's always 24MHz.  It's the
specification, AFAIK.


Takashi
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Re: [PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Ville Syrjälä]

On Thu, Mar 30, 2017 at 02:17:15PM +0200, Takashi Iwai wrote:
> On Thu, 30 Mar 2017 13:42:09 +0200,
> Ville Syrjälä wrote:
> > 
> > On Wed, Mar 29, 2017 at 09:16:36PM +0000, Pandiyan, Dhinakaran wrote:
> > > On Wed, 2017-03-29 at 11:50 +0300, Ville Syrjälä wrote:
> > > > On Tue, Mar 07, 2017 at 04:12:52PM -0800, Dhinakaran Pandiyan wrote:
> > > > > According to BSpec, "The CD clock frequency must be at least twice the
> > > > > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
> > > > > default. This check is needed because BXT and GLK support cdclk
> > > > > frequencies less than 192 MHz.
> > > > > 
> > > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
> > > > >  1 file changed, 12 insertions(+)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > > index e8c1181..7b1ac1d 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > > @@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> > > > >  			pixel_rate = max(432000, pixel_rate);
> > > > >  	}
> > > > >  
> > > > > +	/* According to BSpec, "The CD clock frequency must be at least twice
> > > > > +	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> > > > > +	 * The check for GLK has to be adjusted as the platform can output
> > > > > +	 * two pixels per clock.
> > > > > +	 */
> > > > > +	if (crtc_state->has_audio) {
> > > > > +		if (IS_GEMINILAKE(dev_priv))
> > > > > +			pixel_rate = max(2 * 2 * 96000, pixel_rate);
> > > > 
> > > > BTW that x2 factor for GLK looks wrong. It should be /2.
> > > > 
> > > > https://bugs.freedesktop.org/show_bug.cgi?id=100439
> > > > 
> > > 
> > > BSpec[1] says cdclk needs to be > 2*96 MHz (azalia bclk). To set a cdclk
> > > > 192 MHz on GLK, we need to pass in max_pixclk = 2*192 MHz. But with a
> > > factor of /2, we can end up picking 158.4 MHz or 79.2 MHz for cdclk,
> > > which are lower than 192 MHz.
> > > 
> > > 
> > > 	static int glk_calc_cdclk(int max_pixclk)
> > > 	{
> > > 	        if (max_pixclk > 2 * 158400)
> > >         	        return 316800;
> > > 	        else if (max_pixclk > 2 * 79200)
> > >         	        return 158400;
> > >         	else
> > >         	        return 79200;
> > > 	}
> > > 
> > > [1] Geminilake Clocks
> > > "158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is
> > > 96 MHz)
> > > 316.8 MHz CD
> > > 79.2 MHz CD (exclusively for resolutions up to 1080p in low power single
> > > pipe eDP/MIPI configurations, no audio support)"
> > 
> > Argh. So it's really about the cdclk freq vs. bclk. Apparently the fact
> > that the pipe can output two pixels per clock doesn't extend to the HDA
> > side. OK, then the code looks correct.
> > 
> > But how do we know the bclk is really 96Mhz? Or are we just making a
> > worst case estimate here? Base on the hda spec I think bclk should typically
> > be 24 MHz, but of course the hda spec is so old that it probably has
> > little to do with today's realities. I guess ideally we'd like the audio
> > driver to tell us what the frequency is, or we'd dig that up from
> > somewhere ourselves.
> > 
> > Hmm. AUD_FREQ_CNTRL seems to have something. 96 vs. 48 MHz. But I'm not sure
> > we could trust that at boot time. Not sure if the audio driver will make
> > its own choice if BCLK somewhere. Can any alsa folks help us?
> 
> Well, I'm not sure which BCLK is referred in this context, but if it's
> about HD-audio (aka Azalia) BCLK, it's always 24MHz.  It's the
> specification, AFAIK.

That's what I read also. But considering the HDA spec is so dated
(doesn't even have the MST stuff in it) I can't be sure it matches
any current realities.

The spec quote from DK clearly shows that the CDCLK programming section
of our spec clearly seems to make provisions for a 96MHz Azalia BCLK.

If I look at the AUD_FREQ_CNTRL register I see the following:
"Audio BCLK Frequency Control
...
[4] 96MHz BCLK
Default Value: 	1b
Indicates that iDISPLAY Audio Link will run at 96MHz. This bit is
defaulted to 1. BIOS or System Software must pre-program B96 before the
iDISPLAY Audio Link is brought out from reset.
[3] 48MHz BCLK
Default Value: 	0b
Indicates that iDISPLAY Audio Link will run at 48MHz. This bit is
defaulted to 0. BIOS or System Software must pre-program B96 before the
iDISPLAY Audio Link is brought out from reset."

Whether this iDISPLAY BCLK has anything to do with the Azalia BCLK
I don't know. Maybe they changed it from the standard 24 MHz since it's
all internal now and thus no need to interface with external parts?

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v2 2/2] drm/i915: Implement cdclk restrictions based on Azalia BCLK

[Pandiyan, Dhinakaran]

On Thu, 2017-03-30 at 15:44 +0300, Ville Syrjälä wrote:
> On Thu, Mar 30, 2017 at 02:17:15PM +0200, Takashi Iwai wrote:
> > On Thu, 30 Mar 2017 13:42:09 +0200,
> > Ville Syrjälä wrote:
> > > 
> > > On Wed, Mar 29, 2017 at 09:16:36PM +0000, Pandiyan, Dhinakaran wrote:
> > > > On Wed, 2017-03-29 at 11:50 +0300, Ville Syrjälä wrote:
> > > > > On Tue, Mar 07, 2017 at 04:12:52PM -0800, Dhinakaran Pandiyan wrote:
> > > > > > According to BSpec, "The CD clock frequency must be at least twice the
> > > > > > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
> > > > > > default. This check is needed because BXT and GLK support cdclk
> > > > > > frequencies less than 192 MHz.
> > > > > > 
> > > > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
> > > > > >  1 file changed, 12 insertions(+)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > > > index e8c1181..7b1ac1d 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > > > > @@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> > > > > >  			pixel_rate = max(432000, pixel_rate);
> > > > > >  	}
> > > > > >  
> > > > > > +	/* According to BSpec, "The CD clock frequency must be at least twice
> > > > > > +	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> > > > > > +	 * The check for GLK has to be adjusted as the platform can output
> > > > > > +	 * two pixels per clock.
> > > > > > +	 */
> > > > > > +	if (crtc_state->has_audio) {
> > > > > > +		if (IS_GEMINILAKE(dev_priv))
> > > > > > +			pixel_rate = max(2 * 2 * 96000, pixel_rate);
> > > > > 
> > > > > BTW that x2 factor for GLK looks wrong. It should be /2.
> > > > > 
> > > > > https://bugs.freedesktop.org/show_bug.cgi?id=100439
> > > > > 
> > > > 
> > > > BSpec[1] says cdclk needs to be > 2*96 MHz (azalia bclk). To set a cdclk
> > > > > 192 MHz on GLK, we need to pass in max_pixclk = 2*192 MHz. But with a
> > > > factor of /2, we can end up picking 158.4 MHz or 79.2 MHz for cdclk,
> > > > which are lower than 192 MHz.
> > > > 
> > > > 
> > > > 	static int glk_calc_cdclk(int max_pixclk)
> > > > 	{
> > > > 	        if (max_pixclk > 2 * 158400)
> > > >         	        return 316800;
> > > > 	        else if (max_pixclk > 2 * 79200)
> > > >         	        return 158400;
> > > >         	else
> > > >         	        return 79200;
> > > > 	}
> > > > 
> > > > [1] Geminilake Clocks
> > > > "158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is
> > > > 96 MHz)
> > > > 316.8 MHz CD
> > > > 79.2 MHz CD (exclusively for resolutions up to 1080p in low power single
> > > > pipe eDP/MIPI configurations, no audio support)"
> > > 
> > > Argh. So it's really about the cdclk freq vs. bclk. Apparently the fact
> > > that the pipe can output two pixels per clock doesn't extend to the HDA
> > > side. OK, then the code looks correct.
> > > 
> > > But how do we know the bclk is really 96Mhz? Or are we just making a
> > > worst case estimate here? Base on the hda spec I think bclk should typically
> > > be 24 MHz, but of course the hda spec is so old that it probably has
> > > little to do with today's realities. I guess ideally we'd like the audio
> > > driver to tell us what the frequency is, or we'd dig that up from
> > > somewhere ourselves.
> > > 
> > > Hmm. AUD_FREQ_CNTRL seems to have something. 96 vs. 48 MHz. But I'm not sure
> > > we could trust that at boot time. Not sure if the audio driver will make
> > > its own choice if BCLK somewhere. Can any alsa folks help us?
> > 
> > Well, I'm not sure which BCLK is referred in this context, but if it's
> > about HD-audio (aka Azalia) BCLK, it's always 24MHz.  It's the
> > specification, AFAIK.
> 
> That's what I read also. But considering the HDA spec is so dated
> (doesn't even have the MST stuff in it) I can't be sure it matches
> any current realities.
> 
> The spec quote from DK clearly shows that the CDCLK programming section
> of our spec clearly seems to make provisions for a 96MHz Azalia BCLK.
> 
> If I look at the AUD_FREQ_CNTRL register I see the following:
> "Audio BCLK Frequency Control
> ...
> [4] 96MHz BCLK
> Default Value: 	1b
> Indicates that iDISPLAY Audio Link will run at 96MHz. This bit is
> defaulted to 1. BIOS or System Software must pre-program B96 before the
> iDISPLAY Audio Link is brought out from reset.
> [3] 48MHz BCLK
> Default Value: 	0b
> Indicates that iDISPLAY Audio Link will run at 48MHz. This bit is
> defaulted to 0. BIOS or System Software must pre-program B96 before the
> iDISPLAY Audio Link is brought out from reset."
> 
> Whether this iDISPLAY BCLK has anything to do with the Azalia BCLK
> I don't know. Maybe they changed it from the standard 24 MHz since it's
> all internal now and thus no need to interface with external parts?
> 

Libin was working on a patch that was reading the bclk frequency, looks
like he has submitted this https://patchwork.kernel.org/patch/9608123/
We could add a new acomp->audio_ops function to get the exact bclk
frequency from the audio driver.

-DK 



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