From: Philipp Zabel <p.zabel@pengutronix.de>
To: Andre Przywara <andre.przywara@arm.com>
Cc: Chen-Yu Tsai <wens@csie.org>,
Maxime Ripard <maxime.ripard@free-electrons.com>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] reset: sunxi: fix for 64-bit compilation
Date: Wed, 08 Mar 2017 10:52:56 +0100 [thread overview]
Message-ID: <1488966776.2467.13.camel@pengutronix.de> (raw)
In-Reply-To: <6a0e362b-8ebf-6254-6387-12967ec8c484@arm.com>
On Wed, 2017-03-08 at 09:26 +0000, Andre Przywara wrote:
> Hi,
>
> On 08/03/17 04:28, Chen-Yu Tsai wrote:
> > On Mon, Mar 6, 2017 at 9:35 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> >> The Allwinner reset controller has 32-bit registers, so translating
> >> the reset cell number into a register and bit offset should not use
> >> any architecture dependent data size. Otherwise this breaks for 64-bit
> >> architectures like arm64.
> >> Fix this by making it clear that it's the hardware register width which
> >> matters here in the calculation.
> >>
> >> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> >
> > Acked-by: Chen-Yu Tsai <wens@csie.org>
>
> Thanks a lot!
Applied, thanks.
> > Though I don't expect this driver to be used with arm64 chips.
>
> Well, weren't we toying with the idea of using this for the A64 PRCM
> support?
>
> Also the driver is actually pretty generic, and I have (renaming)
> patches lying around to make this obvious.
That is interesting, I have an untested patch that unifies sunxi,
socfpga, and stm32 floating around. I suppose this could be extended to
also cover ath79 and zx2967. I'll dust it off and send it out.
regards
Philipp
WARNING: multiple messages have this Message-ID (diff)
From: p.zabel@pengutronix.de (Philipp Zabel)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] reset: sunxi: fix for 64-bit compilation
Date: Wed, 08 Mar 2017 10:52:56 +0100 [thread overview]
Message-ID: <1488966776.2467.13.camel@pengutronix.de> (raw)
In-Reply-To: <6a0e362b-8ebf-6254-6387-12967ec8c484@arm.com>
On Wed, 2017-03-08 at 09:26 +0000, Andre Przywara wrote:
> Hi,
>
> On 08/03/17 04:28, Chen-Yu Tsai wrote:
> > On Mon, Mar 6, 2017 at 9:35 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> >> The Allwinner reset controller has 32-bit registers, so translating
> >> the reset cell number into a register and bit offset should not use
> >> any architecture dependent data size. Otherwise this breaks for 64-bit
> >> architectures like arm64.
> >> Fix this by making it clear that it's the hardware register width which
> >> matters here in the calculation.
> >>
> >> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> >
> > Acked-by: Chen-Yu Tsai <wens@csie.org>
>
> Thanks a lot!
Applied, thanks.
> > Though I don't expect this driver to be used with arm64 chips.
>
> Well, weren't we toying with the idea of using this for the A64 PRCM
> support?
>
> Also the driver is actually pretty generic, and I have (renaming)
> patches lying around to make this obvious.
That is interesting, I have an untested patch that unifies sunxi,
socfpga, and stm32 floating around. I suppose this could be extended to
also cover ath79 and zx2967. I'll dust it off and send it out.
regards
Philipp
next prev parent reply other threads:[~2017-03-08 10:52 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-06 1:35 [PATCH] reset: sunxi: fix for 64-bit compilation Andre Przywara
2017-03-06 1:35 ` Andre Przywara
2017-03-08 4:28 ` Chen-Yu Tsai
2017-03-08 4:28 ` Chen-Yu Tsai
2017-03-08 9:26 ` Andre Przywara
2017-03-08 9:26 ` Andre Przywara
2017-03-08 9:52 ` Philipp Zabel [this message]
2017-03-08 9:52 ` Philipp Zabel
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