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From: Piotr Sroka <piotrs@cadence.com>
To: <linux-mmc@vger.kernel.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>,
	Ulf Hansson <ulf.hansson@linaro.org>,
	<linux-kernel@vger.kernel.org>,
	Masahiro Yamada <yamada.masahiro@socionext.com>,
	Piotr Sroka <piotrs@cadence.com>
Subject: [v3 1/3] mmc: sdhci-cadence: Fix writing PHY delay
Date: Fri, 17 Mar 2017 12:38:22 +0000	[thread overview]
Message-ID: <1489754302-10996-1-git-send-email-piotrs@cadence.com> (raw)

Add polling for ACK to be sure that data are written to PHY register.

Signed-off-by: Piotr Sroka <piotrs@cadence.com>
---
Changes for v2:
- fix indent
---
Changes for v3:
- none
---
 drivers/mmc/host/sdhci-cadence.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 316cfec..b2334ec 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -66,11 +66,12 @@ struct sdhci_cdns_priv {
 	void __iomem *hrs_addr;
 };
 
-static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
-				     u8 addr, u8 data)
+static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
+				    u8 addr, u8 data)
 {
 	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
 	u32 tmp;
+	int ret;
 
 	tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
 	      (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
@@ -79,8 +80,14 @@ static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
 	tmp |= SDHCI_CDNS_HRS04_WR;
 	writel(tmp, reg);
 
+	ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
+	if (ret)
+		return ret;
+
 	tmp &= ~SDHCI_CDNS_HRS04_WR;
 	writel(tmp, reg);
+
+	return 0;
 }
 
 static void sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)
-- 
2.2.2

WARNING: multiple messages have this Message-ID (diff)
From: Piotr Sroka <piotrs@cadence.com>
To: linux-mmc@vger.kernel.org
Cc: Adrian Hunter <adrian.hunter@intel.com>,
	Ulf Hansson <ulf.hansson@linaro.org>,
	linux-kernel@vger.kernel.org,
	Masahiro Yamada <yamada.masahiro@socionext.com>,
	Piotr Sroka <piotrs@cadence.com>
Subject: [v3 1/3] mmc: sdhci-cadence: Fix writing PHY delay
Date: Fri, 17 Mar 2017 12:38:22 +0000	[thread overview]
Message-ID: <1489754302-10996-1-git-send-email-piotrs@cadence.com> (raw)

Add polling for ACK to be sure that data are written to PHY register.

Signed-off-by: Piotr Sroka <piotrs@cadence.com>
---
Changes for v2:
- fix indent
---
Changes for v3:
- none
---
 drivers/mmc/host/sdhci-cadence.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 316cfec..b2334ec 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -66,11 +66,12 @@ struct sdhci_cdns_priv {
 	void __iomem *hrs_addr;
 };
 
-static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
-				     u8 addr, u8 data)
+static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
+				    u8 addr, u8 data)
 {
 	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
 	u32 tmp;
+	int ret;
 
 	tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
 	      (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
@@ -79,8 +80,14 @@ static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
 	tmp |= SDHCI_CDNS_HRS04_WR;
 	writel(tmp, reg);
 
+	ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
+	if (ret)
+		return ret;
+
 	tmp &= ~SDHCI_CDNS_HRS04_WR;
 	writel(tmp, reg);
+
+	return 0;
 }
 
 static void sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)
-- 
2.2.2

             reply	other threads:[~2017-03-17 12:39 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-17 12:38 Piotr Sroka [this message]
2017-03-17 12:38 ` [v3 1/3] mmc: sdhci-cadence: Fix writing PHY delay Piotr Sroka
2017-03-17 12:40 ` [v3 2/3] Documentation: bindings: add description of PHY delays for sdhci-cadence Piotr Sroka
2017-03-17 12:40   ` Piotr Sroka
2017-03-17 17:29   ` Masahiro Yamada
2017-03-17 17:29     ` Masahiro Yamada
2017-03-20  8:49     ` Piotr Sroka
2017-03-17 12:41 ` [v3 3/3] mmc: sdhci-cadence: Update PHY delay configuration Piotr Sroka
2017-03-17 12:41   ` Piotr Sroka
2017-03-17 17:23   ` Masahiro Yamada
2017-03-20  8:47     ` Piotr Sroka
2017-03-21  1:50       ` Masahiro Yamada
2017-03-21  7:19         ` Piotr Sroka
2017-03-17 17:34   ` Masahiro Yamada

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