From: Yuantian Tang <andy.tang@nxp.com>
To: <mturquette@baylibre.com>
Cc: <sboyd@codeaurora.org>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Scott Wood <oss@buserror.net>, Tang Yuantian <andy.tang@nxp.com>
Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Date: Mon, 20 Mar 2017 10:37:22 +0800 [thread overview]
Message-ID: <1489977443-33582-1-git-send-email-andy.tang@nxp.com> (raw)
From: Scott Wood <oss@buserror.net>
ls1012a has separate input root clocks for core PLLs versus the platform
PLL, with the latter described as sysclk in the hw docs.
Update the qoriq-clock binding to allow a second input clock, named
"coreclk". If present, this clock will be used for the core PLLs.
Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v2:
-- change the author to Scott
Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index aa3526f..119cafd 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -56,6 +56,11 @@ Optional properties:
- clocks: If clock-frequency is not specified, sysclk may be provided
as an input clock. Either clock-frequency or clocks must be
provided.
+ A second input clock, called "coreclk", may be provided if
+ core PLLs are based on a different input clock from the
+ platform PLL.
+- clock-names: Required if a coreclk is present. Valid names are
+ "sysclk" and "coreclk".
2. Clock Provider
@@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
2 hwaccel index (n in CLKCGnHWACSR)
3 fman 0 for fm1, 1 for fm2
4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+ 5 coreclk must be 0
3. Example
--
2.1.0.27.g96db324
WARNING: multiple messages have this Message-ID (diff)
From: Yuantian Tang <andy.tang@nxp.com>
To: mturquette@baylibre.com
Cc: sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Scott Wood <oss@buserror.net>, Tang Yuantian <andy.tang@nxp.com>
Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Date: Mon, 20 Mar 2017 10:37:22 +0800 [thread overview]
Message-ID: <1489977443-33582-1-git-send-email-andy.tang@nxp.com> (raw)
From: Scott Wood <oss@buserror.net>
ls1012a has separate input root clocks for core PLLs versus the platform
PLL, with the latter described as sysclk in the hw docs.
Update the qoriq-clock binding to allow a second input clock, named
"coreclk". If present, this clock will be used for the core PLLs.
Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v2:
-- change the author to Scott
Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index aa3526f..119cafd 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -56,6 +56,11 @@ Optional properties:
- clocks: If clock-frequency is not specified, sysclk may be provided
as an input clock. Either clock-frequency or clocks must be
provided.
+ A second input clock, called "coreclk", may be provided if
+ core PLLs are based on a different input clock from the
+ platform PLL.
+- clock-names: Required if a coreclk is present. Valid names are
+ "sysclk" and "coreclk".
2. Clock Provider
@@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
2 hwaccel index (n in CLKCGnHWACSR)
3 fman 0 for fm1, 1 for fm2
4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+ 5 coreclk must be 0
3. Example
--
2.1.0.27.g96db324
WARNING: multiple messages have this Message-ID (diff)
From: andy.tang@nxp.com (Yuantian Tang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Date: Mon, 20 Mar 2017 10:37:22 +0800 [thread overview]
Message-ID: <1489977443-33582-1-git-send-email-andy.tang@nxp.com> (raw)
From: Scott Wood <oss@buserror.net>
ls1012a has separate input root clocks for core PLLs versus the platform
PLL, with the latter described as sysclk in the hw docs.
Update the qoriq-clock binding to allow a second input clock, named
"coreclk". If present, this clock will be used for the core PLLs.
Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v2:
-- change the author to Scott
Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index aa3526f..119cafd 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -56,6 +56,11 @@ Optional properties:
- clocks: If clock-frequency is not specified, sysclk may be provided
as an input clock. Either clock-frequency or clocks must be
provided.
+ A second input clock, called "coreclk", may be provided if
+ core PLLs are based on a different input clock from the
+ platform PLL.
+- clock-names: Required if a coreclk is present. Valid names are
+ "sysclk" and "coreclk".
2. Clock Provider
@@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
2 hwaccel index (n in CLKCGnHWACSR)
3 fman 0 for fm1, 1 for fm2
4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+ 5 coreclk must be 0
3. Example
--
2.1.0.27.g96db324
next reply other threads:[~2017-03-20 2:51 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-20 2:37 Yuantian Tang [this message]
2017-03-20 2:37 ` [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Yuantian Tang
2017-03-20 2:37 ` Yuantian Tang
2017-03-20 2:37 ` [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a Yuantian Tang
2017-03-20 2:37 ` Yuantian Tang
2017-03-20 2:37 ` Yuantian Tang
2017-06-01 8:28 ` Stephen Boyd
2017-06-01 8:28 ` Stephen Boyd
2017-06-01 8:34 ` Andy Tang
2017-06-01 8:34 ` Andy Tang
2017-06-01 8:34 ` Andy Tang
2017-06-01 8:34 ` Andy Tang
2017-06-01 18:17 ` Stephen Boyd
2017-06-01 18:17 ` Stephen Boyd
2017-06-01 18:17 ` Stephen Boyd
2017-06-01 18:17 ` Stephen Boyd
2017-03-27 3:39 ` [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk Andy Tang
2017-03-27 3:39 ` Andy Tang
2017-03-27 3:39 ` Andy Tang
2017-03-27 3:39 ` Andy Tang
2017-04-05 6:16 ` Andy Tang
2017-04-05 6:16 ` Andy Tang
2017-04-05 6:16 ` Andy Tang
2017-04-05 6:16 ` Andy Tang
2017-04-17 1:37 ` Andy Tang
2017-04-17 1:37 ` Andy Tang
2017-04-17 1:37 ` Andy Tang
2017-04-17 1:37 ` Andy Tang
2017-06-01 8:27 ` sboyd
2017-06-01 8:27 ` sboyd at codeaurora.org
2017-06-01 8:27 ` sboyd
2017-04-24 3:14 ` Andy Tang
2017-04-24 3:14 ` Andy Tang
2017-04-24 3:14 ` Andy Tang
2017-04-24 3:14 ` Andy Tang
2017-05-08 5:59 ` Andy Tang
2017-05-08 5:59 ` Andy Tang
2017-05-08 5:59 ` Andy Tang
2017-05-08 5:59 ` Andy Tang
2017-05-31 9:22 ` Andy Tang
2017-05-31 9:22 ` Andy Tang
2017-05-31 9:22 ` Andy Tang
2017-05-31 9:22 ` Andy Tang
2017-06-01 8:27 ` Stephen Boyd
2017-06-01 8:27 ` Stephen Boyd
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