* [PATCH 1/6] drm/amdgpu: add get_clockgating callback for gfx v9
[not found] ` <1490334466-17596-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
@ 2017-03-24 5:47 ` Huang Rui
2017-03-24 5:47 ` [PATCH 2/6] drm/amdgpu: add get_clockgating callback for nbio v6.1 Huang Rui
` (5 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Huang Rui @ 2017-03-24 5:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Alex Deucher
Cc: Alvin Huan, Huang Rui
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 ++
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 43 ++++++++++++++++++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 28a1e04..2c170f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -43,6 +43,8 @@ static const struct cg_flag_name clocks[] = {
{AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
{AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
{AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
+ {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
+ {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
{AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
{AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
{AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 611d68f..0a745ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2374,6 +2374,48 @@ static int gfx_v9_0_set_clockgating_state(void *handle,
return 0;
}
+static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int data;
+
+ if (amdgpu_sriov_vf(adev))
+ *flags = 0;
+
+ /* AMD_CG_SUPPORT_GFX_MGCG */
+ data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
+ if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
+ *flags |= AMD_CG_SUPPORT_GFX_MGCG;
+
+ /* AMD_CG_SUPPORT_GFX_CGCG */
+ data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
+ if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
+ *flags |= AMD_CG_SUPPORT_GFX_CGCG;
+
+ /* AMD_CG_SUPPORT_GFX_CGLS */
+ if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
+ *flags |= AMD_CG_SUPPORT_GFX_CGLS;
+
+ /* AMD_CG_SUPPORT_GFX_RLC_LS */
+ data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
+ if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
+ *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
+
+ /* AMD_CG_SUPPORT_GFX_CP_LS */
+ data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
+ if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
+ *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
+
+ /* AMD_CG_SUPPORT_GFX_3D_CGCG */
+ data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
+ if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
+ *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
+
+ /* AMD_CG_SUPPORT_GFX_3D_CGLS */
+ if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
+ *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
+}
+
static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
{
return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
@@ -2865,6 +2907,7 @@ const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
.soft_reset = gfx_v9_0_soft_reset,
.set_clockgating_state = gfx_v9_0_set_clockgating_state,
.set_powergating_state = gfx_v9_0_set_powergating_state,
+ .get_clockgating_state = gfx_v9_0_get_clockgating_state,
};
static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/6] drm/amdgpu: add get_clockgating callback for nbio v6.1
[not found] ` <1490334466-17596-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
2017-03-24 5:47 ` [PATCH 1/6] drm/amdgpu: add get_clockgating callback for gfx v9 Huang Rui
@ 2017-03-24 5:47 ` Huang Rui
2017-03-24 5:47 ` [PATCH 3/6] drm/amdgpu: add get_clockgating callback for soc15 Huang Rui
` (4 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Huang Rui @ 2017-03-24 5:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Alex Deucher
Cc: Alvin Huan, Huang Rui
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 1 +
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 15 +++++++++++++++
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 1 +
3 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 2c170f1..743a852 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -49,6 +49,7 @@ static const struct cg_flag_name clocks[] = {
{AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
{AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
{AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
+ {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
{AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
{AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
{AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index f517e9a..c0945e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -206,6 +206,21 @@ void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
WREG32_PCIE(smnPCIE_CNTL2, data);
}
+void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
+{
+ int data;
+
+ /* AMD_CG_SUPPORT_BIF_MGCG */
+ data = RREG32_PCIE(smnCPM_CONTROL);
+ if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
+ *flags |= AMD_CG_SUPPORT_BIF_MGCG;
+
+ /* AMD_CG_SUPPORT_BIF_LS */
+ data = RREG32_PCIE(smnPCIE_CNTL2);
+ if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
+ *flags |= AMD_CG_SUPPORT_BIF_LS;
+}
+
struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
index a778d1c..a7e6f39 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
@@ -48,5 +48,6 @@ void nbio_v6_1_ih_control(struct amdgpu_device *adev);
u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev);
void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable);
void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, bool enable);
+void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
#endif
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 3/6] drm/amdgpu: add get_clockgating callback for soc15
[not found] ` <1490334466-17596-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
2017-03-24 5:47 ` [PATCH 1/6] drm/amdgpu: add get_clockgating callback for gfx v9 Huang Rui
2017-03-24 5:47 ` [PATCH 2/6] drm/amdgpu: add get_clockgating callback for nbio v6.1 Huang Rui
@ 2017-03-24 5:47 ` Huang Rui
[not found] ` <1490334466-17596-4-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
2017-03-24 5:47 ` [PATCH 4/6] drm/amdgpu: add get_clockgating for sdma v4 Huang Rui
` (3 subsequent siblings)
6 siblings, 1 reply; 10+ messages in thread
From: Huang Rui @ 2017-03-24 5:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Alex Deucher
Cc: Alvin Huan, Huang Rui
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 +++
drivers/gpu/drm/amd/amdgpu/soc15.c | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 743a852..fef89c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -55,7 +55,10 @@ static const struct cg_flag_name clocks[] = {
{AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
{AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
{AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
+ {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Managment Medium Grain Clock Gating"},
+ {AMD_CG_SUPPORT_DRM_LS, "Digital Right Managment Light Sleep"},
{AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
+ {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
{0, NULL},
};
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index e37c1ff..dd70984 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -782,6 +782,39 @@ static int soc15_common_set_clockgating_state(void *handle,
return 0;
}
+static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int data;
+
+ nbio_v6_1_get_clockgating_state(adev, flags);
+
+ /* AMD_CG_SUPPORT_HDP_LS */
+ data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
+ if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
+ *flags |= AMD_CG_SUPPORT_HDP_LS;
+
+ /* AMD_CG_SUPPORT_DRM_MGCG */
+ data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_CGTT_DRM_CLK_CTRL0));
+ if (!(data & MP0_SMN_CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
+ *flags |= AMD_CG_SUPPORT_DRM_MGCG;
+
+ /* AMD_CG_SUPPORT_DRM_LS */
+ data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_DRM_LIGHT_SLEEP_CTRL));
+ if (data & MP0_SMN_DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK)
+ *flags |= AMD_CG_SUPPORT_DRM_LS;
+
+ /* AMD_CG_SUPPORT_ROM_MGCG */
+ data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
+ if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
+ *flags |= AMD_CG_SUPPORT_ROM_MGCG;
+
+ /* AMD_CG_SUPPORT_DF_MGCG */
+ data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
+ if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
+ *flags |= AMD_CG_SUPPORT_DF_MGCG;
+}
+
static int soc15_common_set_powergating_state(void *handle,
enum amd_powergating_state state)
{
@@ -804,4 +837,5 @@ const struct amd_ip_funcs soc15_common_ip_funcs = {
.soft_reset = soc15_common_soft_reset,
.set_clockgating_state = soc15_common_set_clockgating_state,
.set_powergating_state = soc15_common_set_powergating_state,
+ .get_clockgating_state= soc15_common_get_clockgating_state,
};
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 4/6] drm/amdgpu: add get_clockgating for sdma v4
[not found] ` <1490334466-17596-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2017-03-24 5:47 ` [PATCH 3/6] drm/amdgpu: add get_clockgating callback for soc15 Huang Rui
@ 2017-03-24 5:47 ` Huang Rui
2017-03-24 5:47 ` [PATCH 5/6] drm/amdgpu: add get_clockgating callback for mmhub v1 Huang Rui
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Huang Rui @ 2017-03-24 5:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Alex Deucher
Cc: Alvin Huan, Huang Rui
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 7347326..df4b1d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1389,6 +1389,22 @@ static int sdma_v4_0_set_powergating_state(void *handle,
return 0;
}
+static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int data;
+
+ /* AMD_CG_SUPPORT_SDMA_MGCG */
+ data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
+ if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
+ *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
+
+ /* AMD_CG_SUPPORT_SDMA_LS */
+ data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
+ if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
+ *flags |= AMD_CG_SUPPORT_SDMA_LS;
+}
+
const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
.name = "sdma_v4_0",
.early_init = sdma_v4_0_early_init,
@@ -1404,6 +1420,7 @@ const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
.soft_reset = sdma_v4_0_soft_reset,
.set_clockgating_state = sdma_v4_0_set_clockgating_state,
.set_powergating_state = sdma_v4_0_set_powergating_state,
+ .get_clockgating_state = sdma_v4_0_get_clockgating_state,
};
static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 5/6] drm/amdgpu: add get_clockgating callback for mmhub v1
[not found] ` <1490334466-17596-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2017-03-24 5:47 ` [PATCH 4/6] drm/amdgpu: add get_clockgating for sdma v4 Huang Rui
@ 2017-03-24 5:47 ` Huang Rui
2017-03-24 5:47 ` [PATCH 6/6] drm/amdgpu: fix to remove HDP MGCG on soc15 Huang Rui
2017-03-24 12:57 ` [PATCH 0/6] drm/amdgpu: add get clockgating functions for new asic Edward O'Callaghan
6 siblings, 0 replies; 10+ messages in thread
From: Huang Rui @ 2017-03-24 5:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Alex Deucher
Cc: Alvin Huan, Huang Rui
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index b1e0e6b..68e5f7a 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -552,6 +552,22 @@ static int mmhub_v1_0_set_clockgating_state(void *handle,
return 0;
}
+static void mmhub_v1_0_get_clockgating_state(void *handle, u32 *flags)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int data;
+
+ /* AMD_CG_SUPPORT_MC_MGCG */
+ data = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL));
+ if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
+ *flags |= AMD_CG_SUPPORT_MC_MGCG;
+
+ /* AMD_CG_SUPPORT_MC_LS */
+ data = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG));
+ if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
+ *flags |= AMD_CG_SUPPORT_MC_LS;
+}
+
static int mmhub_v1_0_set_powergating_state(void *handle,
enum amd_powergating_state state)
{
@@ -573,6 +589,7 @@ const struct amd_ip_funcs mmhub_v1_0_ip_funcs = {
.soft_reset = mmhub_v1_0_soft_reset,
.set_clockgating_state = mmhub_v1_0_set_clockgating_state,
.set_powergating_state = mmhub_v1_0_set_powergating_state,
+ .get_clockgating_state = mmhub_v1_0_get_clockgating_state,
};
const struct amdgpu_ip_block_version mmhub_v1_0_ip_block =
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 6/6] drm/amdgpu: fix to remove HDP MGCG on soc15
[not found] ` <1490334466-17596-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2017-03-24 5:47 ` [PATCH 5/6] drm/amdgpu: add get_clockgating callback for mmhub v1 Huang Rui
@ 2017-03-24 5:47 ` Huang Rui
[not found] ` <1490334466-17596-7-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
2017-03-24 12:57 ` [PATCH 0/6] drm/amdgpu: add get clockgating functions for new asic Edward O'Callaghan
6 siblings, 1 reply; 10+ messages in thread
From: Huang Rui @ 2017-03-24 5:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Alex Deucher
Cc: Alvin Huan, Huang Rui
SOC15 doesn't enable HDP MGCG yet.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index dd70984..a7a0c27 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -561,7 +561,6 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_BIF_MGCG |
AMD_CG_SUPPORT_BIF_LS |
- AMD_CG_SUPPORT_HDP_MGCG |
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_DRM_MGCG |
AMD_CG_SUPPORT_DRM_LS |
--
2.7.4
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^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 0/6] drm/amdgpu: add get clockgating functions for new asic
[not found] ` <1490334466-17596-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2017-03-24 5:47 ` [PATCH 6/6] drm/amdgpu: fix to remove HDP MGCG on soc15 Huang Rui
@ 2017-03-24 12:57 ` Edward O'Callaghan
6 siblings, 0 replies; 10+ messages in thread
From: Edward O'Callaghan @ 2017-03-24 12:57 UTC (permalink / raw)
To: Huang Rui, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Alex Deucher
Cc: Alvin Huan
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This series is,
Reviewed-by: Edward O'Callaghan <funfunctor-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org>
On 03/24/2017 04:47 PM, Huang Rui wrote:
> Hi all,
>
> This patch set adds get_clockgating functions, after that, we can use
> debugfs pm to check the dynamic clockgating status.
>
> Thanks,
> Rui
>
> Huang Rui (6):
> drm/amdgpu: add get_clockgating callback for gfx v9
> drm/amdgpu: add get_clockgating callback for nbio v6.1
> drm/amdgpu: add get_clockgating callback for soc15
> drm/amdgpu: add get_clockgating for sdma v4
> drm/amdgpu: add get_clockgating callback for mmhub v1
> drm/amdgpu: fix to remove HDP MGCG on soc15
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 6 +++++
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 43 +++++++++++++++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 17 +++++++++++++
> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 15 ++++++++++++
> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 1 +
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 17 +++++++++++++
> drivers/gpu/drm/amd/amdgpu/soc15.c | 35 ++++++++++++++++++++++++++-
> 7 files changed, 133 insertions(+), 1 deletion(-)
>
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