[PATCH 00/15] *** Multiple level VMPT enablement ***

[PATCH 00/15] *** Multiple level VMPT enablement ***

[Chunming Zhou]

*** BLURB HERE ***
From Vega, ascis start to support multiple level vmpt, the series is to implement it.

Tested successfully with 2/3/4 levels. 

V2: address Christian comments.

Max vm size 256TB tested ok.


Christian König (10):
  drm/amdgpu: rename page_directory_fence to last_dir_update
  drm/amdgpu: add the VM pointer to the amdgpu_pte_update_params as well
  drm/amdgpu: add num_level to the VM manager
  drm/amdgpu: generalize page table level
  drm/amdgpu: handle multi level PD size calculation
  drm/amdgpu: handle multi level PD during validation
  drm/amdgpu: handle multi level PD in the LRU
  drm/amdgpu: handle multi level PD updates V2
  drm/amdgpu: handle multi level PD during PT updates
  drm/amdgpu: add alloc/free for multi level PDs V2

Chunming Zhou (5):
  drm/amdgpu: abstract block size to one function
  drm/amdgpu: limit block size to one page
  drm/amdgpu: adapt vm size for multi vmpt
  drm/amdgpu: set page table depth by num_level
  drm/amdgpu: enable four level VMPT for gmc9

 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     |   6 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  67 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 474 +++++++++++++++++++----------
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h     |  16 +-
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c   |   3 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c      |   1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c      |   1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      |   1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c      |   7 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c    |   2 +-
 11 files changed, 380 insertions(+), 200 deletions(-)

-- 
1.9.1

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[PATCH 01/15] drm/amdgpu: rename page_directory_fence to last_dir_update

[Chunming Zhou]

From: Christian König <christian.koenig@amd.com>

Decribes better what this is used for.

Change-Id: I1bd496522fbdd6531d2c1d17434822b53bec06d0
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 ++++----
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index f225d63..0e5d851 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -791,7 +791,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
 	if (r)
 		return r;
 
-	r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence);
+	r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_dir_update);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 01418c8..66f5b91 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -705,8 +705,8 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 		goto error_free;
 
 	amdgpu_bo_fence(vm->page_directory, fence, true);
-	fence_put(vm->page_directory_fence);
-	vm->page_directory_fence = fence_get(fence);
+	fence_put(vm->last_dir_update);
+	vm->last_dir_update = fence_get(fence);
 	fence_put(fence);
 
 	return 0;
@@ -1596,7 +1596,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	if (r)
 		goto err;
 
-	vm->page_directory_fence = NULL;
+	vm->last_dir_update = NULL;
 
 	r = amdgpu_bo_create(adev, pd_size, align, true,
 			     AMDGPU_GEM_DOMAIN_VRAM,
@@ -1673,7 +1673,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 
 	amdgpu_bo_unref(&vm->page_directory->shadow);
 	amdgpu_bo_unref(&vm->page_directory);
-	fence_put(vm->page_directory_fence);
+	fence_put(vm->last_dir_update);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 1a7922b..6be6c71 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -97,7 +97,7 @@ struct amdgpu_vm {
 	/* contains the page directory */
 	struct amdgpu_bo	*page_directory;
 	unsigned		max_pde_used;
-	struct fence		*page_directory_fence;
+	struct fence		*last_dir_update;
 	uint64_t		last_eviction_counter;
 
 	/* array of page tables, one for each page directory entry */
-- 
1.9.1

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[PATCH 02/15] drm/amdgpu: add the VM pointer to the amdgpu_pte_update_params as well

[Chunming Zhou]

From: Christian König <christian.koenig@amd.com>

This way we save passing it through the different functions.

Change-Id: Id94564a70d106b0ef36c7f45de2b25ca176db2d2
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 66f5b91..1f27300 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -61,6 +61,8 @@
 struct amdgpu_pte_update_params {
 	/* amdgpu device we do this update for */
 	struct amdgpu_device *adev;
+	/* optional amdgpu_vm we do this update for */
+	struct amdgpu_vm *vm;
 	/* address where to copy page table entries from */
 	uint64_t src;
 	/* indirect buffer to fill with commands */
@@ -729,7 +731,6 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
  * Update the page tables in the range @start - @end.
  */
 static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
-				  struct amdgpu_vm *vm,
 				  uint64_t start, uint64_t end,
 				  uint64_t dst, uint64_t flags)
 {
@@ -745,7 +746,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
 	/* initialize the variables */
 	addr = start;
 	pt_idx = addr >> amdgpu_vm_block_size;
-	pt = vm->page_tables[pt_idx].bo;
+	pt = params->vm->page_tables[pt_idx].bo;
 	if (params->shadow) {
 		if (!pt->shadow)
 			return;
@@ -768,7 +769,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
 	/* walk over the address space and update the page tables */
 	while (addr < end) {
 		pt_idx = addr >> amdgpu_vm_block_size;
-		pt = vm->page_tables[pt_idx].bo;
+		pt = params->vm->page_tables[pt_idx].bo;
 		if (params->shadow) {
 			if (!pt->shadow)
 				return;
@@ -819,7 +820,6 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
  * @flags: hw mapping flags
  */
 static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params	*params,
-				struct amdgpu_vm *vm,
 				uint64_t start, uint64_t end,
 				uint64_t dst, uint64_t flags)
 {
@@ -853,25 +853,25 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params	*params,
 	if (params->src || !(flags & AMDGPU_PTE_VALID) ||
 	    (frag_start >= frag_end)) {
 
-		amdgpu_vm_update_ptes(params, vm, start, end, dst, flags);
+		amdgpu_vm_update_ptes(params, start, end, dst, flags);
 		return;
 	}
 
 	/* handle the 4K area at the beginning */
 	if (start != frag_start) {
-		amdgpu_vm_update_ptes(params, vm, start, frag_start,
+		amdgpu_vm_update_ptes(params, start, frag_start,
 				      dst, flags);
 		dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE;
 	}
 
 	/* handle the area in the middle */
-	amdgpu_vm_update_ptes(params, vm, frag_start, frag_end, dst,
+	amdgpu_vm_update_ptes(params, frag_start, frag_end, dst,
 			      flags | frag_flags);
 
 	/* handle the 4K area at the end */
 	if (frag_end != end) {
 		dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE;
-		amdgpu_vm_update_ptes(params, vm, frag_end, end, dst, flags);
+		amdgpu_vm_update_ptes(params, frag_end, end, dst, flags);
 	}
 }
 
@@ -911,6 +911,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 
 	memset(&params, 0, sizeof(params));
 	params.adev = adev;
+	params.vm = vm;
 	params.src = src;
 
 	ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
@@ -992,9 +993,9 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 		goto error_free;
 
 	params.shadow = true;
-	amdgpu_vm_frag_ptes(&params, vm, start, last + 1, addr, flags);
+	amdgpu_vm_frag_ptes(&params, start, last + 1, addr, flags);
 	params.shadow = false;
-	amdgpu_vm_frag_ptes(&params, vm, start, last + 1, addr, flags);
+	amdgpu_vm_frag_ptes(&params, start, last + 1, addr, flags);
 
 	amdgpu_ring_pad_ib(ring, params.ib);
 	WARN_ON(params.ib->length_dw > ndw);
-- 
1.9.1

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[PATCH 03/15] drm/amdgpu: add num_level to the VM manager

[Chunming Zhou]

From: Christian König <christian.koenig@amd.com>

Needs to be filled with handling.

Change-Id: I04881a2b304a020c259ce85e94b12900a77f1c02
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 1 +
 5 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 6be6c71..e208186f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -151,6 +151,7 @@ struct amdgpu_vm_manager {
 	unsigned				seqno[AMDGPU_MAX_RINGS];
 
 	uint32_t				max_pfn;
+	uint32_t				num_level;
 	/* vram base address for page table entry  */
 	u64					vram_base_offset;
 	/* is vm enabled? */
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 7155ae5..0ce0d0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -607,6 +607,7 @@ static int gmc_v6_0_vm_init(struct amdgpu_device *adev)
 	 * amdkfd will use VMIDs 8-15
 	 */
 	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
+	adev->vm_manager.num_level = 1;
 	amdgpu_vm_manager_init(adev);
 
 	/* base offset of vram pages */
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index ff4cc63..f90dba5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -734,6 +734,7 @@ static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
 	 * amdkfd will use VMIDs 8-15
 	 */
 	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
+	adev->vm_manager.num_level = 1;
 	adev->vm_manager.shared_aperture_start = 0x2000000000000000ULL;
 	adev->vm_manager.shared_aperture_end =
 		adev->vm_manager.shared_aperture_start + (4ULL << 30) - 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index d7d025a..fe79328 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -865,6 +865,7 @@ static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
 	 * amdkfd will use VMIDs 8-15
 	 */
 	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
+	adev->vm_manager.num_level = 1;
 	adev->vm_manager.shared_aperture_start = 0x2000000000000000ULL;
 	adev->vm_manager.shared_aperture_end =
 		adev->vm_manager.shared_aperture_start + (4ULL << 30) - 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 58557add8..6625a2f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -508,6 +508,7 @@ static int gmc_v9_0_vm_init(struct amdgpu_device *adev)
 	 * amdkfd will use VMIDs 8-15
 	 */
 	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
+	adev->vm_manager.num_level = 1;
 	amdgpu_vm_manager_init(adev);
 
 	return 0;
-- 
1.9.1

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Re: [PATCH 03/15] drm/amdgpu: add num_level to the VM manager

[William Lewis]

On 03/27/2017 12:53 AM, Chunming Zhou wrote:
> From: Christian König <christian.koenig@amd.com>
>
> Needs to be filled with handling.
>
> Change-Id: I04881a2b304a020c259ce85e94b12900a77f1c02
> Signed-off-by: Christian König <christian.koenig@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  | 1 +
>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  | 1 +
>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  | 1 +
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 1 +
>   5 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 6be6c71..e208186f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -151,6 +151,7 @@ struct amdgpu_vm_manager {
>   	unsigned				seqno[AMDGPU_MAX_RINGS];
>   
>   	uint32_t				max_pfn;
> +	uint32_t				num_level;
>   	/* vram base address for page table entry  */
>   	u64					vram_base_offset;
>   	/* is vm enabled? */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index 7155ae5..0ce0d0a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -607,6 +607,7 @@ static int gmc_v6_0_vm_init(struct amdgpu_device *adev)
>   	 * amdkfd will use VMIDs 8-15
>   	 */
>   	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
> +	adev->vm_manager.num_level = 1;
It seems that consistency here would dictate the variable be named 
"num_levels."
>   	amdgpu_vm_manager_init(adev);
>   
>   	/* base offset of vram pages */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index ff4cc63..f90dba5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -734,6 +734,7 @@ static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
>   	 * amdkfd will use VMIDs 8-15
>   	 */
>   	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
> +	adev->vm_manager.num_level = 1;
>   	adev->vm_manager.shared_aperture_start = 0x2000000000000000ULL;
>   	adev->vm_manager.shared_aperture_end =
>   		adev->vm_manager.shared_aperture_start + (4ULL << 30) - 1;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index d7d025a..fe79328 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -865,6 +865,7 @@ static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
>   	 * amdkfd will use VMIDs 8-15
>   	 */
>   	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
> +	adev->vm_manager.num_level = 1;
>   	adev->vm_manager.shared_aperture_start = 0x2000000000000000ULL;
>   	adev->vm_manager.shared_aperture_end =
>   		adev->vm_manager.shared_aperture_start + (4ULL << 30) - 1;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 58557add8..6625a2f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -508,6 +508,7 @@ static int gmc_v9_0_vm_init(struct amdgpu_device *adev)
>   	 * amdkfd will use VMIDs 8-15
>   	 */
>   	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
> +	adev->vm_manager.num_level = 1;
>   	amdgpu_vm_manager_init(adev);
>   
>   	return 0;

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[PATCH 04/15] drm/amdgpu: generalize page table level

[Chunming Zhou]

From: Christian König <christian.koenig@amd.com>

No functional change, but the base for multi level page tables.

Change-Id: If5729be07e15cc8618ae7bce15c6b27aa4f24393
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 87 +++++++++++++++++-----------------
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  9 ++--
 3 files changed, 50 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 0e5d851..d9308cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -873,7 +873,7 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 	}
 
 	if (p->job->vm) {
-		p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
+		p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.bo);
 
 		r = amdgpu_bo_vm_update_pte(p, vm);
 		if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 1f27300..9172954 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -113,9 +113,9 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
 			 struct list_head *validated,
 			 struct amdgpu_bo_list_entry *entry)
 {
-	entry->robj = vm->page_directory;
+	entry->robj = vm->root.bo;
 	entry->priority = 0;
-	entry->tv.bo = &vm->page_directory->tbo;
+	entry->tv.bo = &entry->robj->tbo;
 	entry->tv.shared = true;
 	entry->user_pages = NULL;
 	list_add(&entry->tv.head, validated);
@@ -147,8 +147,8 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 		return 0;
 
 	/* add the vm page table to the list */
-	for (i = 0; i <= vm->max_pde_used; ++i) {
-		struct amdgpu_bo *bo = vm->page_tables[i].bo;
+	for (i = 0; i <= vm->root.last_entry_used; ++i) {
+		struct amdgpu_bo *bo = vm->root.entries[i].bo;
 
 		if (!bo)
 			continue;
@@ -176,8 +176,8 @@ void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
 	unsigned i;
 
 	spin_lock(&glob->lru_lock);
-	for (i = 0; i <= vm->max_pde_used; ++i) {
-		struct amdgpu_bo *bo = vm->page_tables[i].bo;
+	for (i = 0; i <= vm->root.last_entry_used; ++i) {
+		struct amdgpu_bo *bo = vm->root.entries[i].bo;
 
 		if (!bo)
 			continue;
@@ -597,15 +597,15 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 	int r;
 
 	ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
-	shadow = vm->page_directory->shadow;
+	shadow = vm->root.bo->shadow;
 
 	/* padding, etc. */
 	ndw = 64;
 
 	/* assume the worst case */
-	ndw += vm->max_pde_used * 6;
+	ndw += vm->root.last_entry_used * 6;
 
-	pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
+	pd_addr = amdgpu_bo_gpu_offset(vm->root.bo);
 	if (shadow) {
 		r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem);
 		if (r)
@@ -625,8 +625,8 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 	params.ib = &job->ibs[0];
 
 	/* walk over the address space and update the page directory */
-	for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
-		struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo;
+	for (pt_idx = 0; pt_idx <= vm->root.last_entry_used; ++pt_idx) {
+		struct amdgpu_bo *bo = vm->root.entries[pt_idx].bo;
 		uint64_t pde, pt;
 
 		if (bo == NULL)
@@ -642,10 +642,10 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 		}
 
 		pt = amdgpu_bo_gpu_offset(bo);
-		if (vm->page_tables[pt_idx].addr == pt)
+		if (vm->root.entries[pt_idx].addr == pt)
 			continue;
 
-		vm->page_tables[pt_idx].addr = pt;
+		vm->root.entries[pt_idx].addr = pt;
 
 		pde = pd_addr + pt_idx * 8;
 		if (((last_pde + 8 * count) != pde) ||
@@ -680,7 +680,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 	if (count) {
 		uint64_t pt_addr = amdgpu_vm_adjust_mc_addr(adev, last_pt);
 
-		if (vm->page_directory->shadow)
+		if (vm->root.bo->shadow)
 			amdgpu_vm_do_set_ptes(&params, last_shadow, pt_addr,
 					      count, incr, AMDGPU_PTE_VALID);
 
@@ -694,7 +694,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 	}
 
 	amdgpu_ring_pad_ib(ring, params.ib);
-	amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv,
+	amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv,
 			 AMDGPU_FENCE_OWNER_VM);
 	if (shadow)
 		amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv,
@@ -706,7 +706,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 	if (r)
 		goto error_free;
 
-	amdgpu_bo_fence(vm->page_directory, fence, true);
+	amdgpu_bo_fence(vm->root.bo, fence, true);
 	fence_put(vm->last_dir_update);
 	vm->last_dir_update = fence_get(fence);
 	fence_put(fence);
@@ -746,7 +746,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
 	/* initialize the variables */
 	addr = start;
 	pt_idx = addr >> amdgpu_vm_block_size;
-	pt = params->vm->page_tables[pt_idx].bo;
+	pt = params->vm->root.entries[pt_idx].bo;
 	if (params->shadow) {
 		if (!pt->shadow)
 			return;
@@ -769,7 +769,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
 	/* walk over the address space and update the page tables */
 	while (addr < end) {
 		pt_idx = addr >> amdgpu_vm_block_size;
-		pt = params->vm->page_tables[pt_idx].bo;
+		pt = params->vm->root.entries[pt_idx].bo;
 		if (params->shadow) {
 			if (!pt->shadow)
 				return;
@@ -983,12 +983,12 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 	if (r)
 		goto error_free;
 
-	r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv,
+	r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv,
 			     owner);
 	if (r)
 		goto error_free;
 
-	r = reservation_object_reserve_shared(vm->page_directory->tbo.resv);
+	r = reservation_object_reserve_shared(vm->root.bo->tbo.resv);
 	if (r)
 		goto error_free;
 
@@ -1004,7 +1004,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 	if (r)
 		goto error_free;
 
-	amdgpu_bo_fence(vm->page_directory, f, true);
+	amdgpu_bo_fence(vm->root.bo, f, true);
 	if (fence) {
 		fence_put(*fence);
 		*fence = fence_get(f);
@@ -1395,15 +1395,15 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 
 	BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev));
 
-	if (eaddr > vm->max_pde_used)
-		vm->max_pde_used = eaddr;
+	if (eaddr > vm->root.last_entry_used)
+		vm->root.last_entry_used = eaddr;
 
 	/* walk over the address space and allocate the page tables */
 	for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
-		struct reservation_object *resv = vm->page_directory->tbo.resv;
+		struct reservation_object *resv = vm->root.bo->tbo.resv;
 		struct amdgpu_bo *pt;
 
-		if (vm->page_tables[pt_idx].bo)
+		if (vm->root.entries[pt_idx].bo)
 			continue;
 
 		r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
@@ -1420,10 +1420,10 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 		/* Keep a reference to the page table to avoid freeing
 		 * them up in the wrong order.
 		 */
-		pt->parent = amdgpu_bo_ref(vm->page_directory);
+		pt->parent = amdgpu_bo_ref(vm->root.bo);
 
-		vm->page_tables[pt_idx].bo = pt;
-		vm->page_tables[pt_idx].addr = 0;
+		vm->root.entries[pt_idx].bo = pt;
+		vm->root.entries[pt_idx].addr = 0;
 	}
 
 	return 0;
@@ -1580,8 +1580,9 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	pd_entries = amdgpu_vm_num_pdes(adev);
 
 	/* allocate page table array */
-	vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt));
-	if (vm->page_tables == NULL) {
+	vm->root.entries = drm_calloc_large(pd_entries,
+					    sizeof(struct amdgpu_vm_pt));
+	if (vm->root.entries == NULL) {
 		DRM_ERROR("Cannot allocate memory for page table array\n");
 		return -ENOMEM;
 	}
@@ -1605,29 +1606,29 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 			     AMDGPU_GEM_CREATE_SHADOW |
 			     AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
 			     AMDGPU_GEM_CREATE_VRAM_CLEARED,
-			     NULL, NULL, &vm->page_directory);
+			     NULL, NULL, &vm->root.bo);
 	if (r)
 		goto error_free_sched_entity;
 
-	r = amdgpu_bo_reserve(vm->page_directory, false);
+	r = amdgpu_bo_reserve(vm->root.bo, false);
 	if (r)
-		goto error_free_page_directory;
+		goto error_free_root;
 
 	vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
-	amdgpu_bo_unreserve(vm->page_directory);
+	amdgpu_bo_unreserve(vm->root.bo);
 
 	return 0;
 
-error_free_page_directory:
-	amdgpu_bo_unref(&vm->page_directory->shadow);
-	amdgpu_bo_unref(&vm->page_directory);
-	vm->page_directory = NULL;
+error_free_root:
+	amdgpu_bo_unref(&vm->root.bo->shadow);
+	amdgpu_bo_unref(&vm->root.bo);
+	vm->root.bo = NULL;
 
 error_free_sched_entity:
 	amd_sched_entity_fini(&ring->sched, &vm->entity);
 
 err:
-	drm_free_large(vm->page_tables);
+	drm_free_large(vm->root.entries);
 
 	return r;
 }
@@ -1662,7 +1663,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	}
 
 	for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) {
-		struct amdgpu_bo *pt = vm->page_tables[i].bo;
+		struct amdgpu_bo *pt = vm->root.entries[i].bo;
 
 		if (!pt)
 			continue;
@@ -1670,10 +1671,10 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 		amdgpu_bo_unref(&pt->shadow);
 		amdgpu_bo_unref(&pt);
 	}
-	drm_free_large(vm->page_tables);
+	drm_free_large(vm->root.entries);
 
-	amdgpu_bo_unref(&vm->page_directory->shadow);
-	amdgpu_bo_unref(&vm->page_directory);
+	amdgpu_bo_unref(&vm->root.bo->shadow);
+	amdgpu_bo_unref(&vm->root.bo);
 	fence_put(vm->last_dir_update);
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index e208186f..1f54563 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -76,6 +76,10 @@
 struct amdgpu_vm_pt {
 	struct amdgpu_bo	*bo;
 	uint64_t		addr;
+
+	/* array of page tables, one for each directory entry */
+	struct amdgpu_vm_pt	*entries;
+	unsigned		last_entry_used;
 };
 
 struct amdgpu_vm {
@@ -95,13 +99,10 @@ struct amdgpu_vm {
 	struct list_head	freed;
 
 	/* contains the page directory */
-	struct amdgpu_bo	*page_directory;
-	unsigned		max_pde_used;
+	struct amdgpu_vm_pt     root;
 	struct fence		*last_dir_update;
 	uint64_t		last_eviction_counter;
 
-	/* array of page tables, one for each page directory entry */
-	struct amdgpu_vm_pt	*page_tables;
 
 	/* for id and flush management per ring */
 	struct amdgpu_vm_id	*ids[AMDGPU_MAX_RINGS];
-- 
1.9.1

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[PATCH 05/15] drm/amdgpu: handle multi level PD size calculation

[Chunming Zhou]

From: Christian König <christian.koenig@amd.com>

Allows us to get the size for all levels as well.

Change-Id: Iaf2f9b2bf19c3623018a2215f8cf01a61bdbe8ea
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 ++++++++++++++++++++++------------
 1 file changed, 22 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 9172954..90494ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -76,27 +76,37 @@ struct amdgpu_pte_update_params {
 };
 
 /**
- * amdgpu_vm_num_pde - return the number of page directory entries
+ * amdgpu_vm_num_entries - return the number of entries in a PD/PT
  *
  * @adev: amdgpu_device pointer
  *
- * Calculate the number of page directory entries.
+ * Calculate the number of entries in a page directory or page table.
  */
-static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
+static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
+				      unsigned level)
 {
-	return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;
+	if (level == 0)
+		/* For the root directory */
+		return adev->vm_manager.max_pfn >>
+			(amdgpu_vm_block_size * adev->vm_manager.num_level);
+	else if (level == adev->vm_manager.num_level)
+		/* For the page tables on the leaves */
+		return AMDGPU_VM_PTE_COUNT;
+	else
+		/* Everything in between */
+		return 1 << amdgpu_vm_block_size;
 }
 
 /**
- * amdgpu_vm_directory_size - returns the size of the page directory in bytes
+ * amdgpu_vm_bo_size - returns the size of the BOs in bytes
  *
  * @adev: amdgpu_device pointer
  *
- * Calculate the size of the page directory in bytes.
+ * Calculate the size of the BO for a page directory or page table in bytes.
  */
-static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
+static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
 {
-	return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);
+	return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
 }
 
 /**
@@ -1393,7 +1403,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 	saddr >>= amdgpu_vm_block_size;
 	eaddr >>= amdgpu_vm_block_size;
 
-	BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev));
+	BUG_ON(eaddr >= amdgpu_vm_num_entries(adev, 0));
 
 	if (eaddr > vm->root.last_entry_used)
 		vm->root.last_entry_used = eaddr;
@@ -1576,8 +1586,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	INIT_LIST_HEAD(&vm->cleared);
 	INIT_LIST_HEAD(&vm->freed);
 
-	pd_size = amdgpu_vm_directory_size(adev);
-	pd_entries = amdgpu_vm_num_pdes(adev);
+	pd_size = amdgpu_vm_bo_size(adev, 0);
+	pd_entries = amdgpu_vm_num_entries(adev, 0);
 
 	/* allocate page table array */
 	vm->root.entries = drm_calloc_large(pd_entries,
@@ -1662,7 +1672,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 		kfree(mapping);
 	}
 
-	for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) {
+	for (i = 0; i < amdgpu_vm_num_entries(adev, 0); i++) {
 		struct amdgpu_bo *pt = vm->root.entries[i].bo;
 
 		if (!pt)
-- 
1.9.1

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Re: [PATCH 05/15] drm/amdgpu: handle multi level PD size calculation

[Zhang, Jerry (Junwei)]

On 03/27/2017 01:53 PM, Chunming Zhou wrote:
> From: Christian König <christian.koenig@amd.com>
>
> Allows us to get the size for all levels as well.
>
> Change-Id: Iaf2f9b2bf19c3623018a2215f8cf01a61bdbe8ea
> Signed-off-by: Christian König <christian.koenig@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 ++++++++++++++++++++++------------
>   1 file changed, 22 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 9172954..90494ce 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -76,27 +76,37 @@ struct amdgpu_pte_update_params {
>   };
>
>   /**
> - * amdgpu_vm_num_pde - return the number of page directory entries
> + * amdgpu_vm_num_entries - return the number of entries in a PD/PT
>    *
>    * @adev: amdgpu_device pointer
>    *
> - * Calculate the number of page directory entries.
> + * Calculate the number of entries in a page directory or page table.
>    */
> -static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
> +static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
> +				      unsigned level)
>   {
> -	return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;
> +	if (level == 0)
> +		/* For the root directory */
> +		return adev->vm_manager.max_pfn >>
> +			(amdgpu_vm_block_size * adev->vm_manager.num_level);
> +	else if (level == adev->vm_manager.num_level)
> +		/* For the page tables on the leaves */
> +		return AMDGPU_VM_PTE_COUNT;
> +	else
> +		/* Everything in between */
> +		return 1 << amdgpu_vm_block_size;

We may use AMDGPU_VM_PTE_COUNT directly.

BTW, each PT size is same as amdgpu_vm_block_size.

Jerry

>   }
>
>   /**
> - * amdgpu_vm_directory_size - returns the size of the page directory in bytes
> + * amdgpu_vm_bo_size - returns the size of the BOs in bytes
>    *
>    * @adev: amdgpu_device pointer
>    *
> - * Calculate the size of the page directory in bytes.
> + * Calculate the size of the BO for a page directory or page table in bytes.
>    */
> -static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
> +static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
>   {
> -	return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);
> +	return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
>   }
>
>   /**
> @@ -1393,7 +1403,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
>   	saddr >>= amdgpu_vm_block_size;
>   	eaddr >>= amdgpu_vm_block_size;
>
> -	BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev));
> +	BUG_ON(eaddr >= amdgpu_vm_num_entries(adev, 0));
>
>   	if (eaddr > vm->root.last_entry_used)
>   		vm->root.last_entry_used = eaddr;
> @@ -1576,8 +1586,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
>   	INIT_LIST_HEAD(&vm->cleared);
>   	INIT_LIST_HEAD(&vm->freed);
>
> -	pd_size = amdgpu_vm_directory_size(adev);
> -	pd_entries = amdgpu_vm_num_pdes(adev);
> +	pd_size = amdgpu_vm_bo_size(adev, 0);
> +	pd_entries = amdgpu_vm_num_entries(adev, 0);
>
>   	/* allocate page table array */
>   	vm->root.entries = drm_calloc_large(pd_entries,
> @@ -1662,7 +1672,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
>   		kfree(mapping);
>   	}
>
> -	for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) {
> +	for (i = 0; i < amdgpu_vm_num_entries(adev, 0); i++) {
>   		struct amdgpu_bo *pt = vm->root.entries[i].bo;
>
>   		if (!pt)
>
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[PATCH 06/15] drm/amdgpu: handle multi level PD during validation

[Chunming Zhou]

From: Christian König <christian.koenig@amd.com>

All page directory levels should be in place after this.

Change-Id: Ied101d6e14676acc07fe2d46ecba4563007b5045
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 57 +++++++++++++++++++++++++---------
 1 file changed, 42 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 90494ce..23674ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -132,6 +132,47 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
 }
 
 /**
+ * amdgpu_vm_validate_layer - validate a single page table level
+ *
+ * @parent: parent page table level
+ * @validate: callback to do the validation
+ * @param: parameter for the validation callback
+ *
+ * Validate the page table BOs on command submission if neccessary.
+ */
+static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent,
+				    int (*validate)(void *, struct amdgpu_bo *),
+				    void *param)
+{
+	unsigned i;
+	int r;
+
+	if (!parent->entries)
+		return 0;
+
+	for (i = 0; i <= parent->last_entry_used; ++i) {
+		struct amdgpu_vm_pt *entry = &parent->entries[i];
+
+		if (!entry->bo)
+			continue;
+
+		r = validate(param, entry->bo);
+		if (r)
+			return r;
+
+		/*
+		 * Recurse into the sub directory. This is harmless because we
+		 * have only a maximum of 5 layers.
+		 */
+		r = amdgpu_vm_validate_level(entry, validate, param);
+		if (r)
+			return r;
+	}
+
+	return r;
+}
+
+/**
  * amdgpu_vm_validate_pt_bos - validate the page table BOs
  *
  * @adev: amdgpu device pointer
@@ -146,8 +187,6 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 			      void *param)
 {
 	uint64_t num_evictions;
-	unsigned i;
-	int r;
 
 	/* We only need to validate the page tables
 	 * if they aren't already valid.
@@ -156,19 +195,7 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	if (num_evictions == vm->last_eviction_counter)
 		return 0;
 
-	/* add the vm page table to the list */
-	for (i = 0; i <= vm->root.last_entry_used; ++i) {
-		struct amdgpu_bo *bo = vm->root.entries[i].bo;
-
-		if (!bo)
-			continue;
-
-		r = validate(param, bo);
-		if (r)
-			return r;
-	}
-
-	return 0;
+	return amdgpu_vm_validate_level(&vm->root, validate, param);
 }
 
 /**
-- 
1.9.1

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[PATCH 07/15] drm/amdgpu: handle multi level PD in the LRU

[Chunming Zhou]

From: Christian König <christian.koenig@amd.com>

Move all levels to the end after command submission.

Change-Id: I6d41aac90be29476780b897cf5943a2261580a78
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 36 +++++++++++++++++++++++++---------
 1 file changed, 27 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 23674ed..fe3db17 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -199,28 +199,46 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 }
 
 /**
- * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
+ * amdgpu_vm_move_level_in_lru - move one level of PT BOs to the LRU tail
  *
  * @adev: amdgpu device instance
  * @vm: vm providing the BOs
  *
  * Move the PT BOs to the tail of the LRU.
  */
-void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
-				  struct amdgpu_vm *vm)
+static void amdgpu_vm_move_level_in_lru(struct amdgpu_vm_pt *parent)
 {
-	struct ttm_bo_global *glob = adev->mman.bdev.glob;
 	unsigned i;
 
-	spin_lock(&glob->lru_lock);
-	for (i = 0; i <= vm->root.last_entry_used; ++i) {
-		struct amdgpu_bo *bo = vm->root.entries[i].bo;
+	if (!parent->entries)
+		return;
 
-		if (!bo)
+	for (i = 0; i <= parent->last_entry_used; ++i) {
+		struct amdgpu_vm_pt *entry = &parent->entries[i];
+
+		if (!entry->bo)
 			continue;
 
-		ttm_bo_move_to_lru_tail(&bo->tbo);
+		ttm_bo_move_to_lru_tail(&entry->bo->tbo);
+		amdgpu_vm_move_level_in_lru(entry);
 	}
+}
+
+/**
+ * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
+ *
+ * @adev: amdgpu device instance
+ * @vm: vm providing the BOs
+ *
+ * Move the PT BOs to the tail of the LRU.
+ */
+void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
+				  struct amdgpu_vm *vm)
+{
+	struct ttm_bo_global *glob = adev->mman.bdev.glob;
+
+	spin_lock(&glob->lru_lock);
+	amdgpu_vm_move_level_in_lru(&vm->root);
 	spin_unlock(&glob->lru_lock);
 }
 
-- 
1.9.1

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[PATCH 08/15] drm/amdgpu: handle multi level PD updates V2

[Chunming Zhou]

From: Christian König <christian.koenig@amd.com>

Update all levels of the page directory.

V2:
a. sub level pdes always are written to incorrect place.
b. sub levels need to update regardless of parent updates.

Change-Id: I0ce3fc1fd88397aedf693b0b6e2efb2db704e615
Signed-off-by: Christian König <christian.koenig@amd.com> (V1)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (V1)
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> (V2)
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 97 ++++++++++++++++++++++-----------
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  4 +-
 4 files changed, 68 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index d9308cf..de1c4c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -787,7 +787,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
 	struct amdgpu_bo *bo;
 	int i, r;
 
-	r = amdgpu_vm_update_page_directory(adev, vm);
+	r = amdgpu_vm_update_directories(adev, vm);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 48ab967..008b8ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -691,7 +691,7 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 	if (r)
 		goto error;
 
-	r = amdgpu_vm_update_page_directory(adev, bo_va->vm);
+	r = amdgpu_vm_update_directories(adev, bo_va->vm);
 	if (r)
 		goto error;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index fe3db17..5a62a53 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -625,24 +625,24 @@ static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
 }
 
 /*
- * amdgpu_vm_update_pdes - make sure that page directory is valid
+ * amdgpu_vm_update_level - update a single level in the hierarchy
  *
  * @adev: amdgpu_device pointer
  * @vm: requested vm
- * @start: start of GPU address range
- * @end: end of GPU address range
+ * @parent: parent directory
  *
- * Allocates new page tables if necessary
- * and updates the page directory.
+ * Makes sure all entries in @parent are up to date.
  * Returns 0 for success, error for failure.
  */
-int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
-				    struct amdgpu_vm *vm)
+static int amdgpu_vm_update_level(struct amdgpu_device *adev,
+				  struct amdgpu_vm *vm,
+				  struct amdgpu_vm_pt *parent,
+				  unsigned level)
 {
 	struct amdgpu_bo *shadow;
 	struct amdgpu_ring *ring;
 	uint64_t pd_addr, shadow_addr;
-	uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
+	uint32_t incr = amdgpu_vm_bo_size(adev, level + 1);
 	uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0;
 	unsigned count = 0, pt_idx, ndw;
 	struct amdgpu_job *job;
@@ -651,16 +651,19 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 
 	int r;
 
+	if (!parent->entries)
+		return 0;
 	ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
-	shadow = vm->root.bo->shadow;
 
 	/* padding, etc. */
 	ndw = 64;
 
 	/* assume the worst case */
-	ndw += vm->root.last_entry_used * 6;
+	ndw += parent->last_entry_used * 6;
+
+	pd_addr = amdgpu_bo_gpu_offset(parent->bo);
 
-	pd_addr = amdgpu_bo_gpu_offset(vm->root.bo);
+	shadow = parent->bo->shadow;
 	if (shadow) {
 		r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem);
 		if (r)
@@ -679,9 +682,9 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 	params.adev = adev;
 	params.ib = &job->ibs[0];
 
-	/* walk over the address space and update the page directory */
-	for (pt_idx = 0; pt_idx <= vm->root.last_entry_used; ++pt_idx) {
-		struct amdgpu_bo *bo = vm->root.entries[pt_idx].bo;
+	/* walk over the address space and update the directory */
+	for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
+		struct amdgpu_bo *bo = parent->entries[pt_idx].bo;
 		uint64_t pde, pt;
 
 		if (bo == NULL)
@@ -697,10 +700,10 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 		}
 
 		pt = amdgpu_bo_gpu_offset(bo);
-		if (vm->root.entries[pt_idx].addr == pt)
+		if (parent->entries[pt_idx].addr == pt)
 			continue;
 
-		vm->root.entries[pt_idx].addr = pt;
+		parent->entries[pt_idx].addr = pt;
 
 		pde = pd_addr + pt_idx * 8;
 		if (((last_pde + 8 * count) != pde) ||
@@ -745,26 +748,39 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 
 	if (params.ib->length_dw == 0) {
 		amdgpu_job_free(job);
-		return 0;
-	}
-
-	amdgpu_ring_pad_ib(ring, params.ib);
-	amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv,
-			 AMDGPU_FENCE_OWNER_VM);
-	if (shadow)
-		amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv,
+	} else {
+		amdgpu_ring_pad_ib(ring, params.ib);
+		amdgpu_sync_resv(adev, &job->sync, parent->bo->tbo.resv,
 				 AMDGPU_FENCE_OWNER_VM);
+		if (shadow)
+			amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv,
+					 AMDGPU_FENCE_OWNER_VM);
 
-	WARN_ON(params.ib->length_dw > ndw);
-	r = amdgpu_job_submit(job, ring, &vm->entity,
-			      AMDGPU_FENCE_OWNER_VM, &fence);
-	if (r)
-		goto error_free;
+		WARN_ON(params.ib->length_dw > ndw);
+		r = amdgpu_job_submit(job, ring, &vm->entity,
+				AMDGPU_FENCE_OWNER_VM, &fence);
+		if (r)
+			goto error_free;
 
-	amdgpu_bo_fence(vm->root.bo, fence, true);
-	fence_put(vm->last_dir_update);
-	vm->last_dir_update = fence_get(fence);
-	fence_put(fence);
+		amdgpu_bo_fence(parent->bo, fence, true);
+		fence_put(vm->last_dir_update);
+		vm->last_dir_update = fence_get(fence);
+		fence_put(fence);
+	}
+	/*
+	 * Recurse into the subdirectories. This recursion is harmless because
+	 * we only have a maximum of 5 layers.
+	 */
+	for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
+		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
+
+		if (!entry->bo)
+			continue;
+
+		r = amdgpu_vm_update_level(adev, vm, entry, level + 1);
+		if (r)
+			return r;
+	}
 
 	return 0;
 
@@ -773,6 +789,21 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 	return r;
 }
 
+/*
+ * amdgpu_vm_update_directories - make sure that all directories are valid
+ *
+ * @adev: amdgpu_device pointer
+ * @vm: requested vm
+ *
+ * Makes sure all directories are up to date.
+ * Returns 0 for success, error for failure.
+ */
+int amdgpu_vm_update_directories(struct amdgpu_device *adev,
+				 struct amdgpu_vm *vm)
+{
+	return amdgpu_vm_update_level(adev, vm, &vm->root, 0);
+}
+
 /**
  * amdgpu_vm_update_ptes - make sure that page tables are valid
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 1f54563..117a68a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -191,8 +191,8 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 		      struct amdgpu_job *job);
 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job);
 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
-int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
-				    struct amdgpu_vm *vm);
+int amdgpu_vm_update_directories(struct amdgpu_device *adev,
+				 struct amdgpu_vm *vm);
 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
 			  struct amdgpu_vm *vm);
 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
-- 
1.9.1

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[PATCH 09/15] drm/amdgpu: handle multi level PD during PT updates

[Chunming Zhou]

From: Christian König <christian.koenig@amd.com>

Not the best solution, but good enough for now.

Change-Id: I45ac1a9d8513ebe51bce9a276da39ddf3524b058
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 39 +++++++++++++++++++++++++++++-----
 1 file changed, 34 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 5a62a53..280fa19 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -805,6 +805,32 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev,
 }
 
 /**
+ * amdgpu_vm_find_pt - find the page table for an address
+ *
+ * @p: see amdgpu_pte_update_params definition
+ * @addr: virtual address in question
+ *
+ * Find the page table BO for a virtual address, return NULL when none found.
+ */
+static struct amdgpu_bo *amdgpu_vm_get_pt(struct amdgpu_pte_update_params *p,
+					  uint64_t addr)
+{
+	struct amdgpu_vm_pt *entry = &p->vm->root;
+	unsigned idx, level = p->adev->vm_manager.num_level;
+
+	while (entry->entries) {
+		idx = addr >> (amdgpu_vm_block_size * level--);
+		idx %= amdgpu_bo_size(entry->bo) / 8;
+		entry = &entry->entries[idx];
+	}
+
+	if (level)
+		return NULL;
+
+	return entry->bo;
+}
+
+/**
  * amdgpu_vm_update_ptes - make sure that page tables are valid
  *
  * @params: see amdgpu_pte_update_params definition
@@ -824,15 +850,16 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
 
 	uint64_t cur_pe_start, cur_nptes, cur_dst;
 	uint64_t addr; /* next GPU address to be updated */
-	uint64_t pt_idx;
 	struct amdgpu_bo *pt;
 	unsigned nptes; /* next number of ptes to be updated */
 	uint64_t next_pe_start;
 
 	/* initialize the variables */
 	addr = start;
-	pt_idx = addr >> amdgpu_vm_block_size;
-	pt = params->vm->root.entries[pt_idx].bo;
+	pt = amdgpu_vm_get_pt(params, addr);
+	if (!pt)
+		return;
+
 	if (params->shadow) {
 		if (!pt->shadow)
 			return;
@@ -854,8 +881,10 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
 
 	/* walk over the address space and update the page tables */
 	while (addr < end) {
-		pt_idx = addr >> amdgpu_vm_block_size;
-		pt = params->vm->root.entries[pt_idx].bo;
+		pt = amdgpu_vm_get_pt(params, addr);
+		if (!pt)
+			return;
+
 		if (params->shadow) {
 			if (!pt->shadow)
 				return;
-- 
1.9.1

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[PATCH 10/15] drm/amdgpu: add alloc/free for multi level PDs V2

[Chunming Zhou]

From: Christian König <christian.koenig@amd.com>

Allocate and free page directories on demand.

V2:
a. clear entries allocation
b. fix entries index calculation
c. need alloc sub level even parent bo was allocated

Change-Id: I341b72b911377033257af888dd1a96ca54f586e9
Signed-off-by: Christian König <christian.koenig@amd.com> (v1)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> (v2)
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 179 ++++++++++++++++++++-------------
 1 file changed, 108 insertions(+), 71 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 280fa19..7f54502 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1431,6 +1431,84 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
 	return bo_va;
 }
 
+ /**
+ * amdgpu_vm_alloc_levels - allocate the PD/PT levels
+ *
+ * @adev: amdgpu_device pointer
+ * @vm: requested vm
+ * @saddr: start of the address range
+ * @eaddr: end of the address range
+ *
+ * Make sure the page directories and page tables are allocated
+ */
+static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
+				  struct amdgpu_vm *vm,
+				  struct amdgpu_vm_pt *parent,
+				  uint64_t saddr, uint64_t eaddr,
+				  unsigned level)
+{
+	unsigned shift = (adev->vm_manager.num_level - level) *
+		amdgpu_vm_block_size;
+	unsigned pt_idx, from, to;
+	int r;
+
+	if (!parent->entries) {
+		unsigned num_entries = amdgpu_vm_num_entries(adev, level);
+
+		parent->entries = drm_calloc_large(num_entries,
+						   sizeof(struct amdgpu_vm_pt));
+		if (!parent->entries)
+			return -ENOMEM;
+		memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt));
+	}
+
+	from = (saddr >> shift) % amdgpu_vm_num_entries(adev, level);
+	to = (eaddr >> shift) % amdgpu_vm_num_entries(adev, level);
+
+	if (to > parent->last_entry_used)
+		parent->last_entry_used = to;
+
+	++level;
+
+	/* walk over the address space and allocate the page tables */
+	for (pt_idx = from; pt_idx <= to; ++pt_idx) {
+		struct reservation_object *resv = vm->root.bo->tbo.resv;
+		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
+		struct amdgpu_bo *pt;
+
+		if (!entry->bo) {
+			r = amdgpu_bo_create(adev,
+					     amdgpu_vm_bo_size(adev, level),
+					     AMDGPU_GPU_PAGE_SIZE, true,
+					     AMDGPU_GEM_DOMAIN_VRAM,
+					     AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
+					     AMDGPU_GEM_CREATE_SHADOW |
+					     AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+					     AMDGPU_GEM_CREATE_VRAM_CLEARED,
+					     NULL, resv, &pt);
+			if (r)
+				return r;
+
+			/* Keep a reference to the root directory to avoid
+			* freeing them up in the wrong order.
+			*/
+			pt->parent = amdgpu_bo_ref(vm->root.bo);
+
+			entry->bo = pt;
+			entry->addr = 0;
+		}
+
+		if (level < adev->vm_manager.num_level) {
+			r = amdgpu_vm_alloc_levels(adev, vm, entry, saddr,
+						   eaddr, level);
+			if (r)
+				return r;
+		}
+	}
+
+	return 0;
+}
+
 /**
  * amdgpu_vm_bo_map - map bo inside a vm
  *
@@ -1453,7 +1531,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 	struct amdgpu_bo_va_mapping *mapping;
 	struct amdgpu_vm *vm = bo_va->vm;
 	struct interval_tree_node *it;
-	unsigned last_pfn, pt_idx;
+	unsigned last_pfn;
 	uint64_t eaddr;
 	int r;
 
@@ -1504,46 +1582,10 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 	list_add(&mapping->list, &bo_va->invalids);
 	interval_tree_insert(&mapping->it, &vm->va);
 
-	/* Make sure the page tables are allocated */
-	saddr >>= amdgpu_vm_block_size;
-	eaddr >>= amdgpu_vm_block_size;
-
-	BUG_ON(eaddr >= amdgpu_vm_num_entries(adev, 0));
-
-	if (eaddr > vm->root.last_entry_used)
-		vm->root.last_entry_used = eaddr;
-
-	/* walk over the address space and allocate the page tables */
-	for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
-		struct reservation_object *resv = vm->root.bo->tbo.resv;
-		struct amdgpu_bo *pt;
-
-		if (vm->root.entries[pt_idx].bo)
-			continue;
-
-		r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
-				     AMDGPU_GPU_PAGE_SIZE, true,
-				     AMDGPU_GEM_DOMAIN_VRAM,
-				     AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
-				     AMDGPU_GEM_CREATE_SHADOW |
-				     AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
-				     AMDGPU_GEM_CREATE_VRAM_CLEARED,
-				     NULL, resv, &pt);
-		if (r)
-			goto error_free;
-
-		/* Keep a reference to the page table to avoid freeing
-		 * them up in the wrong order.
-		 */
-		pt->parent = amdgpu_bo_ref(vm->root.bo);
-
-		vm->root.entries[pt_idx].bo = pt;
-		vm->root.entries[pt_idx].addr = 0;
-	}
-
-	return 0;
+	r = amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0);
+	if (!r)
+		return 0;
 
-error_free:
 	list_del(&mapping->list);
 	interval_tree_remove(&mapping->it, &vm->va);
 	trace_amdgpu_vm_bo_unmap(bo_va, mapping);
@@ -1676,7 +1718,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 {
 	const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
 		AMDGPU_VM_PTE_COUNT * 8);
-	unsigned pd_size, pd_entries;
 	unsigned ring_instance;
 	struct amdgpu_ring *ring;
 	struct amd_sched_rq *rq;
@@ -1691,17 +1732,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	INIT_LIST_HEAD(&vm->cleared);
 	INIT_LIST_HEAD(&vm->freed);
 
-	pd_size = amdgpu_vm_bo_size(adev, 0);
-	pd_entries = amdgpu_vm_num_entries(adev, 0);
-
-	/* allocate page table array */
-	vm->root.entries = drm_calloc_large(pd_entries,
-					    sizeof(struct amdgpu_vm_pt));
-	if (vm->root.entries == NULL) {
-		DRM_ERROR("Cannot allocate memory for page table array\n");
-		return -ENOMEM;
-	}
-
 	/* create scheduler entity for page table updates */
 
 	ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
@@ -1711,11 +1741,11 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	r = amd_sched_entity_init(&ring->sched, &vm->entity,
 				  rq, amdgpu_sched_jobs);
 	if (r)
-		goto err;
+		return r;
 
 	vm->last_dir_update = NULL;
 
-	r = amdgpu_bo_create(adev, pd_size, align, true,
+	r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true,
 			     AMDGPU_GEM_DOMAIN_VRAM,
 			     AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
 			     AMDGPU_GEM_CREATE_SHADOW |
@@ -1742,13 +1772,33 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 error_free_sched_entity:
 	amd_sched_entity_fini(&ring->sched, &vm->entity);
 
-err:
-	drm_free_large(vm->root.entries);
-
 	return r;
 }
 
 /**
+ * amdgpu_vm_free_levels - free PD/PT levels
+ *
+ * @level: PD/PT starting level to free
+ *
+ * Free the page directory or page table level and all sub levels.
+ */
+static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level)
+{
+	unsigned i;
+
+	if (level->bo) {
+		amdgpu_bo_unref(&level->bo->shadow);
+		amdgpu_bo_unref(&level->bo);
+	}
+
+	if (level->entries)
+		for (i = 0; i <= level->last_entry_used; i++)
+			amdgpu_vm_free_levels(&level->entries[i]);
+
+	drm_free_large(level->entries);
+}
+
+/**
  * amdgpu_vm_fini - tear down a vm instance
  *
  * @adev: amdgpu_device pointer
@@ -1760,7 +1810,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 {
 	struct amdgpu_bo_va_mapping *mapping, *tmp;
-	int i;
 
 	amd_sched_entity_fini(vm->entity.sched, &vm->entity);
 
@@ -1777,19 +1826,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 		kfree(mapping);
 	}
 
-	for (i = 0; i < amdgpu_vm_num_entries(adev, 0); i++) {
-		struct amdgpu_bo *pt = vm->root.entries[i].bo;
-
-		if (!pt)
-			continue;
-
-		amdgpu_bo_unref(&pt->shadow);
-		amdgpu_bo_unref(&pt);
-	}
-	drm_free_large(vm->root.entries);
-
-	amdgpu_bo_unref(&vm->root.bo->shadow);
-	amdgpu_bo_unref(&vm->root.bo);
+	amdgpu_vm_free_levels(&vm->root);
 	fence_put(vm->last_dir_update);
 }
 
-- 
1.9.1

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[PATCH 11/15] drm/amdgpu: abstract block size to one function

[Chunming Zhou]

Change-Id: I7709a0f7af1365a147659aa0a02b1d41f53af40a
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 59 ++++++++++++++++--------------
 1 file changed, 32 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b0ac610..7bad6b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1077,6 +1077,37 @@ static bool amdgpu_check_pot_argument(int arg)
 	return (arg & (arg - 1)) == 0;
 }
 
+static void amdgpu_get_block_size(struct amdgpu_device *adev)
+{
+	/* defines number of bits in page table versus page directory,
+	 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
+	 * page table and the remaining bits are in the page directory */
+	if (amdgpu_vm_block_size == -1) {
+
+		/* Total bits covered by PD + PTs */
+		unsigned bits = ilog2(amdgpu_vm_size) + 18;
+
+		/* Make sure the PD is 4K in size up to 8GB address space.
+		   Above that split equal between PD and PTs */
+		if (amdgpu_vm_size <= 8)
+			amdgpu_vm_block_size = bits - 9;
+		else
+			amdgpu_vm_block_size = (bits + 3) / 2;
+
+	} else if (amdgpu_vm_block_size < 9) {
+		dev_warn(adev->dev, "VM page table size (%d) too small\n",
+			 amdgpu_vm_block_size);
+		amdgpu_vm_block_size = 9;
+	}
+
+	if (amdgpu_vm_block_size > 24 ||
+	    (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
+		dev_warn(adev->dev, "VM page table size (%d) too large\n",
+			 amdgpu_vm_block_size);
+		amdgpu_vm_block_size = 9;
+	}
+}
+
 /**
  * amdgpu_check_arguments - validate module params
  *
@@ -1127,33 +1158,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
 		amdgpu_vm_size = 8;
 	}
 
-	/* defines number of bits in page table versus page directory,
-	 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
-	 * page table and the remaining bits are in the page directory */
-	if (amdgpu_vm_block_size == -1) {
-
-		/* Total bits covered by PD + PTs */
-		unsigned bits = ilog2(amdgpu_vm_size) + 18;
-
-		/* Make sure the PD is 4K in size up to 8GB address space.
-		   Above that split equal between PD and PTs */
-		if (amdgpu_vm_size <= 8)
-			amdgpu_vm_block_size = bits - 9;
-		else
-			amdgpu_vm_block_size = (bits + 3) / 2;
-
-	} else if (amdgpu_vm_block_size < 9) {
-		dev_warn(adev->dev, "VM page table size (%d) too small\n",
-			 amdgpu_vm_block_size);
-		amdgpu_vm_block_size = 9;
-	}
-
-	if (amdgpu_vm_block_size > 24 ||
-	    (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
-		dev_warn(adev->dev, "VM page table size (%d) too large\n",
-			 amdgpu_vm_block_size);
-		amdgpu_vm_block_size = 9;
-	}
+	amdgpu_get_block_size(adev);
 
 	if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
 	    !amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
-- 
1.9.1

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[PATCH 12/15] drm/amdgpu: limit block size to one page

[Chunming Zhou]

Change-Id: I00ff5d2c7ff29563394cb8af4c57780b91876743
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7bad6b6..4041d72 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1079,6 +1079,14 @@ static bool amdgpu_check_pot_argument(int arg)
 
 static void amdgpu_get_block_size(struct amdgpu_device *adev)
 {
+	/* from AI, asic starts to support multiple level VMPT */
+	if (adev->family >= AMDGPU_FAMILY_AI) {
+		if (amdgpu_vm_block_size != 9)
+			dev_warn(adev->dev, "Multi-VMPT limits block size to"
+				 "one page!\n");
+		amdgpu_vm_block_size = 9;
+		return;
+	}
 	/* defines number of bits in page table versus page directory,
 	 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 	 * page table and the remaining bits are in the page directory */
-- 
1.9.1

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Re: [PATCH 12/15] drm/amdgpu: limit block size to one page

[Zhang, Jerry (Junwei)]

On 03/27/2017 01:53 PM, Chunming Zhou wrote:
> Change-Id: I00ff5d2c7ff29563394cb8af4c57780b91876743
> Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 7bad6b6..4041d72 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1079,6 +1079,14 @@ static bool amdgpu_check_pot_argument(int arg)
>
>   static void amdgpu_get_block_size(struct amdgpu_device *adev)
>   {
> +	/* from AI, asic starts to support multiple level VMPT */
> +	if (adev->family >= AMDGPU_FAMILY_AI) {
> +		if (amdgpu_vm_block_size != 9)
> +			dev_warn(adev->dev, "Multi-VMPT limits block size to"
> +				 "one page!\n");
> +		amdgpu_vm_block_size = 9;

Do you mean for multi-VMPT, the block size must be 9?
Is that related to page level?

Jerry

> +		return;
> +	}
>   	/* defines number of bits in page table versus page directory,
>   	 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
>   	 * page table and the remaining bits are in the page directory */
>
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[PATCH 13/15] drm/amdgpu: adapt vm size for multi vmpt

[Chunming Zhou]

Change-Id: I17b40aec68404e46961a9fda22dfadd1ae9d6f2c
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 6625a2f..613c8f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -508,6 +508,12 @@ static int gmc_v9_0_vm_init(struct amdgpu_device *adev)
 	 * amdkfd will use VMIDs 8-15
 	 */
 	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
+	/* Because of four level VMPTs, vm size at least is 256GB.
+	256TB is OK as well */
+	if (amdgpu_vm_size < 256) {
+		DRM_WARN("vm size at least is 256GB!\n");
+		amdgpu_vm_size = 256;
+	}
 	adev->vm_manager.num_level = 1;
 	amdgpu_vm_manager_init(adev);
 
-- 
1.9.1

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Re: [PATCH 13/15] drm/amdgpu: adapt vm size for multi vmpt

[Zhang, Jerry (Junwei)]

On 03/27/2017 01:53 PM, Chunming Zhou wrote:
> Change-Id: I17b40aec68404e46961a9fda22dfadd1ae9d6f2c
> Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 ++++++
>   1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 6625a2f..613c8f6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -508,6 +508,12 @@ static int gmc_v9_0_vm_init(struct amdgpu_device *adev)
>   	 * amdkfd will use VMIDs 8-15
>   	 */
>   	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
> +	/* Because of four level VMPTs, vm size at least is 256GB.
> +	256TB is OK as well */

If each PT size is 9, and contains 3 levels PT + 1 PD.
9 * 3 + 12(page size) + 1(at least 1 bit for PD) = 40 bits here.

Then it looks 1T is minimum size.
Please confirm it.

Jerry.

> +	if (amdgpu_vm_size < 256) {
> +		DRM_WARN("vm size at least is 256GB!\n");
> +		amdgpu_vm_size = 256;
> +	}
>   	adev->vm_manager.num_level = 1;
>   	amdgpu_vm_manager_init(adev);
>
>
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Re: [PATCH 13/15] drm/amdgpu: adapt vm size for multi vmpt

[zhoucm1]

On 2017年03月28日 11:19, Zhang, Jerry (Junwei) wrote:
> On 03/27/2017 01:53 PM, Chunming Zhou wrote:
>> Change-Id: I17b40aec68404e46961a9fda22dfadd1ae9d6f2c
>> Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> index 6625a2f..613c8f6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> @@ -508,6 +508,12 @@ static int gmc_v9_0_vm_init(struct amdgpu_device 
>> *adev)
>>        * amdkfd will use VMIDs 8-15
>>        */
>>       adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
>> +    /* Because of four level VMPTs, vm size at least is 256GB.
>> +    256TB is OK as well */
>
> If each PT size is 9, and contains 3 levels PT + 1 PD.
> 9 * 3 + 12(page size) + 1(at least 1 bit for PD) = 40 bits here.
block size is 9 means 512 entries each PDB/PTB. then one PDE of 4 levels 
is 512* 512 *512*4KB = 512GB.

will send another patch to correct this typo.

Thanks,
David Zhou
>
> Then it looks 1T is minimum size.
> Please confirm it.
>
> Jerry.
>
>> +    if (amdgpu_vm_size < 256) {
>> +        DRM_WARN("vm size at least is 256GB!\n");
>> +        amdgpu_vm_size = 256;
>> +    }
>>       adev->vm_manager.num_level = 1;
>>       amdgpu_vm_manager_init(adev);
>>
>>

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Re: [PATCH 13/15] drm/amdgpu: adapt vm size for multi vmpt

[Christian König]

Am 28.03.2017 um 05:19 schrieb Zhang, Jerry (Junwei):
> On 03/27/2017 01:53 PM, Chunming Zhou wrote:
>> Change-Id: I17b40aec68404e46961a9fda22dfadd1ae9d6f2c
>> Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> index 6625a2f..613c8f6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> @@ -508,6 +508,12 @@ static int gmc_v9_0_vm_init(struct amdgpu_device 
>> *adev)
>>        * amdkfd will use VMIDs 8-15
>>        */
>>       adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
>> +    /* Because of four level VMPTs, vm size at least is 256GB.
>> +    256TB is OK as well */
>
> If each PT size is 9, and contains 3 levels PT + 1 PD.
> 9 * 3 + 12(page size) + 1(at least 1 bit for PD) = 40 bits here.
>
> Then it looks 1T is minimum size.
> Please confirm it.

I would rather say completely ignore the setting of amdgpu_vm_size here 
and always use 256TB for GFX9.

Allocating a PD smaller than 4K doesn't make much sense cause you don't 
save anything.

So the only valid approach would be to switch between 1, 2, 3 and 4 
levels when the VM size changes and that doesn't make to much sense to 
me because the saved memory is minimal (4K for each level).

Christian.

>
> Jerry.
>
>> +    if (amdgpu_vm_size < 256) {
>> +        DRM_WARN("vm size at least is 256GB!\n");
>> +        amdgpu_vm_size = 256;
>> +    }
>>       adev->vm_manager.num_level = 1;
>>       amdgpu_vm_manager_init(adev);
>>
>>
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[PATCH 14/15] drm/amdgpu: set page table depth by num_level

[Chunming Zhou]

Change-Id: I6180bedb8948398429fb32b36faa35960b3b85e6
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index a47f9dc..3a6f50a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -200,7 +200,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 	for (i = 0; i <= 14; i++) {
 		tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);
 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
-		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
+		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
+				    adev->vm_manager.num_level);
 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 01f3aa5..07af98c 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -218,7 +218,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 				ENABLE_CONTEXT, 1);
 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
-				PAGE_TABLE_DEPTH, 1);
+				PAGE_TABLE_DEPTH, adev->vm_manager.num_level);
 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
-- 
1.9.1

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[PATCH 15/15] drm/amdgpu: enable four level VMPT for gmc9

[Chunming Zhou]

Change-Id: I3bb5f77f0d1b715247bb2bbaf6bce3087883b5ce
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 613c8f6..1da16ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -514,7 +514,7 @@ static int gmc_v9_0_vm_init(struct amdgpu_device *adev)
 		DRM_WARN("vm size at least is 256GB!\n");
 		amdgpu_vm_size = 256;
 	}
-	adev->vm_manager.num_level = 1;
+	adev->vm_manager.num_level = 3;
 	amdgpu_vm_manager_init(adev);
 
 	return 0;
-- 
1.9.1

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Re: [PATCH 00/15] *** Multiple level VMPT enablement ***

[Christian König]

Hi David,

changes to patches #8 and #10 look good to me, but Alex (or somebody 
else? Jerry?) should acknowledge these at least as well.

Patch #11 is Reviewed-by: Christian König <christian.koenig@amd.com>.

Patch #12 we need to clean this up a bit more, otherwise we will run 
into issue with mixed APUs+Vega10 systems (or even Vega10+older dGPU).

Going to take care of this, but for now the patch is Reviewed-by: 
Christian König <christian.koenig@amd.com>.

Patch #13, dito this needs cleanup. But for now Reviewed-by: Christian 
König <christian.koenig@amd.com>.

All other patches are either from me or already reviewed. I would say 
wait till tomorrow for additional comments and then feel free to commit 
to amd-staging-4.9.

Regards,
Christian.

Am 27.03.2017 um 07:53 schrieb Chunming Zhou:
> *** BLURB HERE ***
>  From Vega, ascis start to support multiple level vmpt, the series is to implement it.
>
> Tested successfully with 2/3/4 levels.
>
> V2: address Christian comments.
>
> Max vm size 256TB tested ok.
>
>
> Christian König (10):
>    drm/amdgpu: rename page_directory_fence to last_dir_update
>    drm/amdgpu: add the VM pointer to the amdgpu_pte_update_params as well
>    drm/amdgpu: add num_level to the VM manager
>    drm/amdgpu: generalize page table level
>    drm/amdgpu: handle multi level PD size calculation
>    drm/amdgpu: handle multi level PD during validation
>    drm/amdgpu: handle multi level PD in the LRU
>    drm/amdgpu: handle multi level PD updates V2
>    drm/amdgpu: handle multi level PD during PT updates
>    drm/amdgpu: add alloc/free for multi level PDs V2
>
> Chunming Zhou (5):
>    drm/amdgpu: abstract block size to one function
>    drm/amdgpu: limit block size to one page
>    drm/amdgpu: adapt vm size for multi vmpt
>    drm/amdgpu: set page table depth by num_level
>    drm/amdgpu: enable four level VMPT for gmc9
>
>   drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     |   6 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  67 ++--
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    |   2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 474 +++++++++++++++++++----------
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h     |  16 +-
>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c   |   3 +-
>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c      |   1 +
>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c      |   1 +
>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      |   1 +
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c      |   7 +
>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c    |   2 +-
>   11 files changed, 380 insertions(+), 200 deletions(-)
>

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RE: [PATCH 00/15] *** Multiple level VMPT enablement ***

[Deucher, Alexander]

> -----Original Message-----
> From: Koenig, Christian
> Sent: Monday, March 27, 2017 5:37 AM
> To: Zhou, David(ChunMing); amd-gfx@lists.freedesktop.org; Deucher,
> Alexander
> Subject: Re: [PATCH 00/15] *** Multiple level VMPT enablement ***
> 
> Hi David,
> 
> changes to patches #8 and #10 look good to me, but Alex (or somebody
> else? Jerry?) should acknowledge these at least as well.
> 

Acked-by: Alex Deucher <alexander.deucher@amd.com>

> Patch #11 is Reviewed-by: Christian König <christian.koenig@amd.com>.
> 
> Patch #12 we need to clean this up a bit more, otherwise we will run
> into issue with mixed APUs+Vega10 systems (or even Vega10+older dGPU).

Yes, we need to pull this into the driver rather than using the global variable directly.  Then we can set reasonable defaults per family if the global variable is set to auto.

Alex

> 
> Going to take care of this, but for now the patch is Reviewed-by:
> Christian König <christian.koenig@amd.com>.
> 
> Patch #13, dito this needs cleanup. But for now Reviewed-by: Christian
> König <christian.koenig@amd.com>.
> 
> All other patches are either from me or already reviewed. I would say
> wait till tomorrow for additional comments and then feel free to commit
> to amd-staging-4.9.
> 
> Regards,
> Christian.
> 
> Am 27.03.2017 um 07:53 schrieb Chunming Zhou:
> > *** BLURB HERE ***
> >  From Vega, ascis start to support multiple level vmpt, the series is to
> implement it.
> >
> > Tested successfully with 2/3/4 levels.
> >
> > V2: address Christian comments.
> >
> > Max vm size 256TB tested ok.
> >
> >
> > Christian König (10):
> >    drm/amdgpu: rename page_directory_fence to last_dir_update
> >    drm/amdgpu: add the VM pointer to the amdgpu_pte_update_params
> as well
> >    drm/amdgpu: add num_level to the VM manager
> >    drm/amdgpu: generalize page table level
> >    drm/amdgpu: handle multi level PD size calculation
> >    drm/amdgpu: handle multi level PD during validation
> >    drm/amdgpu: handle multi level PD in the LRU
> >    drm/amdgpu: handle multi level PD updates V2
> >    drm/amdgpu: handle multi level PD during PT updates
> >    drm/amdgpu: add alloc/free for multi level PDs V2
> >
> > Chunming Zhou (5):
> >    drm/amdgpu: abstract block size to one function
> >    drm/amdgpu: limit block size to one page
> >    drm/amdgpu: adapt vm size for multi vmpt
> >    drm/amdgpu: set page table depth by num_level
> >    drm/amdgpu: enable four level VMPT for gmc9
> >
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     |   6 +-
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  67 ++--
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    |   2 +-
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 474
> +++++++++++++++++++----------
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h     |  16 +-
> >   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c   |   3 +-
> >   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c      |   1 +
> >   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c      |   1 +
> >   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      |   1 +
> >   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c      |   7 +
> >   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c    |   2 +-
> >   11 files changed, 380 insertions(+), 200 deletions(-)
> >

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Re: [PATCH 00/15] *** Multiple level VMPT enablement ***

[Zhang, Jerry (Junwei)]

On 03/28/2017 12:05 AM, Deucher, Alexander wrote:
>> -----Original Message-----
>> From: Koenig, Christian
>> Sent: Monday, March 27, 2017 5:37 AM
>> To: Zhou, David(ChunMing); amd-gfx@lists.freedesktop.org; Deucher,
>> Alexander
>> Subject: Re: [PATCH 00/15] *** Multiple level VMPT enablement ***
>>
>> Hi David,
>>
>> changes to patches #8 and #10 look good to me, but Alex (or somebody
>> else? Jerry?) should acknowledge these at least as well.
>>
>
> Acked-by: Alex Deucher <alexander.deucher@amd.com>

Apart from the comment for patch 5, 12, 13.
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

>
>> Patch #11 is Reviewed-by: Christian König <christian.koenig@amd.com>.
>>
>> Patch #12 we need to clean this up a bit more, otherwise we will run
>> into issue with mixed APUs+Vega10 systems (or even Vega10+older dGPU).
>
> Yes, we need to pull this into the driver rather than using the global variable directly.  Then we can set reasonable defaults per family if the global variable is set to auto.
>
> Alex
>
>>
>> Going to take care of this, but for now the patch is Reviewed-by:
>> Christian König <christian.koenig@amd.com>.
>>
>> Patch #13, dito this needs cleanup. But for now Reviewed-by: Christian
>> König <christian.koenig@amd.com>.
>>
>> All other patches are either from me or already reviewed. I would say
>> wait till tomorrow for additional comments and then feel free to commit
>> to amd-staging-4.9.
>>
>> Regards,
>> Christian.
>>
>> Am 27.03.2017 um 07:53 schrieb Chunming Zhou:
>>> *** BLURB HERE ***
>>>   From Vega, ascis start to support multiple level vmpt, the series is to
>> implement it.
>>>
>>> Tested successfully with 2/3/4 levels.
>>>
>>> V2: address Christian comments.
>>>
>>> Max vm size 256TB tested ok.
>>>
>>>
>>> Christian König (10):
>>>     drm/amdgpu: rename page_directory_fence to last_dir_update
>>>     drm/amdgpu: add the VM pointer to the amdgpu_pte_update_params
>> as well
>>>     drm/amdgpu: add num_level to the VM manager
>>>     drm/amdgpu: generalize page table level
>>>     drm/amdgpu: handle multi level PD size calculation
>>>     drm/amdgpu: handle multi level PD during validation
>>>     drm/amdgpu: handle multi level PD in the LRU
>>>     drm/amdgpu: handle multi level PD updates V2
>>>     drm/amdgpu: handle multi level PD during PT updates
>>>     drm/amdgpu: add alloc/free for multi level PDs V2
>>>
>>> Chunming Zhou (5):
>>>     drm/amdgpu: abstract block size to one function
>>>     drm/amdgpu: limit block size to one page
>>>     drm/amdgpu: adapt vm size for multi vmpt
>>>     drm/amdgpu: set page table depth by num_level
>>>     drm/amdgpu: enable four level VMPT for gmc9
>>>
>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     |   6 +-
>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  67 ++--
>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    |   2 +-
>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 474
>> +++++++++++++++++++----------
>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h     |  16 +-
>>>    drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c   |   3 +-
>>>    drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c      |   1 +
>>>    drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c      |   1 +
>>>    drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      |   1 +
>>>    drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c      |   7 +
>>>    drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c    |   2 +-
>>>    11 files changed, 380 insertions(+), 200 deletions(-)
>>>
>
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
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Multilevel page tables broken for high addresses

[Felix Kuehling]

It looks like the multi-level page table changes have been submitted.
They're causing problems when we're trying to integrate them into our
KFD branch.

We resolved the obvious changes and it's working on older ASICs without
problems. But we're getting hangs on Vega10. With my patch to enable
UTCL2 interrupts, I'm seeing lots of VM faults (see below). The
VM_L2_PROTECTION_FAULT_STATUS indicates a WALKER_ERROR (3 = PDE1 value).

If I set adev->vm_manager.num_level = 1 in gmc_v9_0_vm_init, the problem
goes away (basically reverting b98e6b5 drm/amdgpu: enable four level
VMPT for gmc9).

I suspect an issue that's exposed by how the KFD Thunk library manages
shared virtual address space? We typically start at fairly high virtual
addresses and reserve the lower 1/4 of our address space for coherent
mappings (aperture-based scheme for pre-gfx9). The address in the fault
below is 0x0000001000d80000, so a bit above 64GB, near the start of our
non-coherent range.

Simple KFD tests that don't use the non-coherent (high) address range
seem to be working fine. That tells me that the multi-level page table
code has a problem with high addresses.

I'll keep digging ...

Regards,
  Felix

[   24.768477] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0 vm_id:8 pas_id:1)
[   24.777361] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
[   24.784204] amdgpu 0000:03:00.0: VM_L2_PROTECTION_FAULT_STATUS:0x00841157
[   24.791418] amdgpu 0000:03:00.0: IH ring buffer overflow (0x00083E00, 0x00000740, 0x00003E20)
[   24.791421] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0 vm_id:8 pas_id:1)
[   24.800299] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
[   24.807154] amdgpu 0000:03:00.0: VM_L2_PROTECTION_FAULT_STATUS:0x00841157
[   24.814370] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0 vm_id:8 pas_id:1)
[   24.823251] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
[   24.830098] amdgpu 0000:03:00.0: VM_L2_PROTECTION_FAULT_STATUS:0x00841157
[   24.837312] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0 vm_id:8 pas_id:1)
[   24.846190] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
[   24.853056] amdgpu 0000:03:00.0: VM_L2_PROTECTION_FAULT_STATUS:0x00841157
[   24.860273] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0 vm_id:8 pas_id:1)
[   24.869151] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
[   24.875994] amdgpu 0000:03:00.0: VM_L2_PROTECTION_FAULT_STATUS:0x00841157
[   24.883209] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0 vm_id:8 pas_id:1)
[   24.892087] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
[   24.898933] amdgpu 0000:03:00.0: VM_L2_PROTECTION_FAULT_STATUS:0x00841157
[   24.906170] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0 vm_id:8 pas_id:1)
[   24.915059] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
[   24.921910] amdgpu 0000:03:00.0: VM_L2_PROTECTION_FAULT_STATUS:0x00841157
[   24.929143] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0 vm_id:8 pas_id:1)
[   24.938021] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
[   24.944874] amdgpu 0000:03:00.0: VM_L2_PROTECTION_FAULT_STATUS:0x00841157
[   24.952089] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0 vm_id:8 pas_id:1)
[   24.960967] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
[   24.967810] amdgpu 0000:03:00.0: VM_L2_PROTECTION_FAULT_STATUS:0x00841157
[   29.610925] gmc_v9_0_process_interrupt: 3402060 callbacks suppressed
[   29.610926] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0 vm_id:8 pas_id:1)
[   29.628202] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
[   29.641520] amdgpu 0000:03:00.0: VM_L2_PROTECTION_FAULT_STATUS:0x00000000


On 17-03-27 01:53 AM, Chunming Zhou wrote:
> *** BLURB HERE ***
> From Vega, ascis start to support multiple level vmpt, the series is to implement it.
>
> Tested successfully with 2/3/4 levels. 
>
> V2: address Christian comments.
>
> Max vm size 256TB tested ok.
>
>
> Christian König (10):
>   drm/amdgpu: rename page_directory_fence to last_dir_update
>   drm/amdgpu: add the VM pointer to the amdgpu_pte_update_params as well
>   drm/amdgpu: add num_level to the VM manager
>   drm/amdgpu: generalize page table level
>   drm/amdgpu: handle multi level PD size calculation
>   drm/amdgpu: handle multi level PD during validation
>   drm/amdgpu: handle multi level PD in the LRU
>   drm/amdgpu: handle multi level PD updates V2
>   drm/amdgpu: handle multi level PD during PT updates
>   drm/amdgpu: add alloc/free for multi level PDs V2
>
> Chunming Zhou (5):
>   drm/amdgpu: abstract block size to one function
>   drm/amdgpu: limit block size to one page
>   drm/amdgpu: adapt vm size for multi vmpt
>   drm/amdgpu: set page table depth by num_level
>   drm/amdgpu: enable four level VMPT for gmc9
>
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     |   6 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  67 ++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    |   2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 474 +++++++++++++++++++----------
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h     |  16 +-
>  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c   |   3 +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c      |   1 +
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c      |   1 +
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      |   1 +
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c      |   7 +
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c    |   2 +-
>  11 files changed, 380 insertions(+), 200 deletions(-)
>

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RE: Multilevel page tables broken for high addresses

[Deucher, Alexander]

> -----Original Message-----
> From: Kuehling, Felix
> Sent: Tuesday, March 28, 2017 4:15 PM
> To: amd-gfx@lists.freedesktop.org; Koenig, Christian; Zhou,
> David(ChunMing); Deucher, Alexander
> Cc: Russell, Kent
> Subject: Multilevel page tables broken for high addresses
> 
> It looks like the multi-level page table changes have been submitted.
> They're causing problems when we're trying to integrate them into our
> KFD branch.
> 
> We resolved the obvious changes and it's working on older ASICs without
> problems. But we're getting hangs on Vega10. With my patch to enable
> UTCL2 interrupts, I'm seeing lots of VM faults (see below). The
> VM_L2_PROTECTION_FAULT_STATUS indicates a WALKER_ERROR (3 = PDE1
> value).
> 
> If I set adev->vm_manager.num_level = 1 in gmc_v9_0_vm_init, the
> problem
> goes away (basically reverting b98e6b5 drm/amdgpu: enable four level
> VMPT for gmc9).
> 
> I suspect an issue that's exposed by how the KFD Thunk library manages
> shared virtual address space? We typically start at fairly high virtual
> addresses and reserve the lower 1/4 of our address space for coherent
> mappings (aperture-based scheme for pre-gfx9). The address in the fault
> below is 0x0000001000d80000, so a bit above 64GB, near the start of our
> non-coherent range.
> 
> Simple KFD tests that don't use the non-coherent (high) address range
> seem to be working fine. That tells me that the multi-level page table
> code has a problem with high addresses.
> 
> I'll keep digging ...

Do you have multiple GPUs in the system?  There might be issues since some of the vm related settings come from global variables.

Alex

> 
> Regards,
>   Felix
> 
> [   24.768477] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0
> vm_id:8 pas_id:1)
> [   24.777361] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
> [   24.784204] amdgpu 0000:03:00.0:
> VM_L2_PROTECTION_FAULT_STATUS:0x00841157
> [   24.791418] amdgpu 0000:03:00.0: IH ring buffer overflow (0x00083E00,
> 0x00000740, 0x00003E20)
> [   24.791421] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0
> vm_id:8 pas_id:1)
> [   24.800299] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
> [   24.807154] amdgpu 0000:03:00.0:
> VM_L2_PROTECTION_FAULT_STATUS:0x00841157
> [   24.814370] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0
> vm_id:8 pas_id:1)
> [   24.823251] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
> [   24.830098] amdgpu 0000:03:00.0:
> VM_L2_PROTECTION_FAULT_STATUS:0x00841157
> [   24.837312] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0
> vm_id:8 pas_id:1)
> [   24.846190] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
> [   24.853056] amdgpu 0000:03:00.0:
> VM_L2_PROTECTION_FAULT_STATUS:0x00841157
> [   24.860273] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0
> vm_id:8 pas_id:1)
> [   24.869151] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
> [   24.875994] amdgpu 0000:03:00.0:
> VM_L2_PROTECTION_FAULT_STATUS:0x00841157
> [   24.883209] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0
> vm_id:8 pas_id:1)
> [   24.892087] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
> [   24.898933] amdgpu 0000:03:00.0:
> VM_L2_PROTECTION_FAULT_STATUS:0x00841157
> [   24.906170] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0
> vm_id:8 pas_id:1)
> [   24.915059] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
> [   24.921910] amdgpu 0000:03:00.0:
> VM_L2_PROTECTION_FAULT_STATUS:0x00841157
> [   24.929143] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0
> vm_id:8 pas_id:1)
> [   24.938021] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
> [   24.944874] amdgpu 0000:03:00.0:
> VM_L2_PROTECTION_FAULT_STATUS:0x00841157
> [   24.952089] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0
> vm_id:8 pas_id:1)
> [   24.960967] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
> [   24.967810] amdgpu 0000:03:00.0:
> VM_L2_PROTECTION_FAULT_STATUS:0x00841157
> [   29.610925] gmc_v9_0_process_interrupt: 3402060 callbacks suppressed
> [   29.610926] amdgpu 0000:03:00.0: [gfxhub] VMC page fault (src_id:0 ring:0
> vm_id:8 pas_id:1)
> [   29.628202] amdgpu 0000:03:00.0:   at page 0x0000001000d80000 from 27
> [   29.641520] amdgpu 0000:03:00.0:
> VM_L2_PROTECTION_FAULT_STATUS:0x00000000
> 
> 
> On 17-03-27 01:53 AM, Chunming Zhou wrote:
> > *** BLURB HERE ***
> > From Vega, ascis start to support multiple level vmpt, the series is to
> implement it.
> >
> > Tested successfully with 2/3/4 levels.
> >
> > V2: address Christian comments.
> >
> > Max vm size 256TB tested ok.
> >
> >
> > Christian König (10):
> >   drm/amdgpu: rename page_directory_fence to last_dir_update
> >   drm/amdgpu: add the VM pointer to the amdgpu_pte_update_params as
> well
> >   drm/amdgpu: add num_level to the VM manager
> >   drm/amdgpu: generalize page table level
> >   drm/amdgpu: handle multi level PD size calculation
> >   drm/amdgpu: handle multi level PD during validation
> >   drm/amdgpu: handle multi level PD in the LRU
> >   drm/amdgpu: handle multi level PD updates V2
> >   drm/amdgpu: handle multi level PD during PT updates
> >   drm/amdgpu: add alloc/free for multi level PDs V2
> >
> > Chunming Zhou (5):
> >   drm/amdgpu: abstract block size to one function
> >   drm/amdgpu: limit block size to one page
> >   drm/amdgpu: adapt vm size for multi vmpt
> >   drm/amdgpu: set page table depth by num_level
> >   drm/amdgpu: enable four level VMPT for gmc9
> >
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     |   6 +-
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  67 ++--
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    |   2 +-
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 474
> +++++++++++++++++++----------
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h     |  16 +-
> >  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c   |   3 +-
> >  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c      |   1 +
> >  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c      |   1 +
> >  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      |   1 +
> >  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c      |   7 +
> >  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c    |   2 +-
> >  11 files changed, 380 insertions(+), 200 deletions(-)
> >

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Re: Multilevel page tables broken for high addresses

[Felix Kuehling]

On 17-03-28 04:25 PM, Deucher, Alexander wrote:
> Simple KFD tests that don't use the non-coherent (high) address range
> > seem to be working fine. That tells me that the multi-level page table
> > code has a problem with high addresses.
> >
> > I'll keep digging ...
>
> Do you have multiple GPUs in the system?  There might be issues since
> some of the vm related settings come from global variables.

No, it's a pure single-GPU Vega10 system.

>
> Alex

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