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* amdgpu fixes for display watermark calculations.
@ 2017-03-29 20:09 Mario Kleiner
  2017-03-29 20:09 ` [PATCH 1/2] drm/amdgpu: Make display watermark calculations more accurate Mario Kleiner
  2017-03-29 20:09 ` [PATCH 2/2] drm/amdgpu: Avoid overflows/divide-by-zero in latency_watermark calculations Mario Kleiner
  0 siblings, 2 replies; 4+ messages in thread
From: Mario Kleiner @ 2017-03-29 20:09 UTC (permalink / raw)
  To: dri-devel; +Cc: alexander.deucher, amd-gfx

Hi,

attached two patches for amdgpu to improve the accuracy of display wm
calculations, and to avoid some overflow and divide-by-zero errors which
can cause the driver to die.

Both are tested for the DCE-10 code path with a AMD R9 380 Tonga Pro
on two different panels and their various modes. They prevent a driver
crash that happened for the "ASUS ROG PG 279" gaming panel when trying
to set a 2560x1440 video mode at 165 Hz video refresh, due to division
by zero errors in the driver.

Probably material for stable, given it prevents crashes?

That said, while the driver no longer crashes, and sets 2560x1440 modes
at 24, 60, 85, 100 and 120 Hz over DisplayPort just fine on that panel,
i so far failed to make it work with 144 Hz or 165 Hz. Modesetting seems
to succeed in that xrandr reports the mode being set, and no error or
warning messages or anything suspicious in the XOrg or kernel dmesg log
or in drm.debug output at high debug settings. The display however goes
black and the onscreen display reports "DisplayPort: No Signal!". Tested
on Linux 4.9/10/drm-next.

The amdgpu-pro 16.50 driver under DC/DAL has no problems setting a working
144 Hz / 165 Hz mode, whereas the same failure happens if i boot it with
amdgpu.dc=0 to go back to the old modesetting.

Any clues on how to debug the black panel much appreciated.

Thanks,
-mario

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 4+ messages in thread
* [PATCH 1/2] drm/amdgpu: Make display watermark calculations more accurate
  2017-03-29 20:09 amdgpu fixes for display watermark calculations Mario Kleiner
@ 2017-03-29 20:09 ` Mario Kleiner
  2017-03-29 20:09 ` [PATCH 2/2] drm/amdgpu: Avoid overflows/divide-by-zero in latency_watermark calculations Mario Kleiner
  1 sibling, 0 replies; 4+ messages in thread
From: Mario Kleiner @ 2017-03-29 20:09 UTC (permalink / raw)
  To: dri-devel; +Cc: alexander.deucher, amd-gfx

Avoid big roundoff errors in scanline/hactive durations for
high pixel clocks, especially for >= 500 Mhz, and thereby
program more accurate display fifo watermarks.

Implemented here for DCE 6,8,10,11.
Successfully tested on DCE 10 with AMD R9 380 Tonga.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 10 +++++-----
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 10 +++++-----
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c  | 10 +++++-----
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c  | 10 +++++-----
 4 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index d4452d8..d3db921 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -1214,14 +1214,14 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
 {
 	struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
 	struct dce10_wm_params wm_low, wm_high;
-	u32 pixel_period;
+	u32 active_time;
 	u32 line_time = 0;
 	u32 latency_watermark_a = 0, latency_watermark_b = 0;
 	u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
 	if (amdgpu_crtc->base.enabled && num_heads && mode) {
-		pixel_period = 1000000 / (u32)mode->clock;
-		line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
+		active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+		line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
 
 		/* watermark for high clocks */
 		if (adev->pm.dpm_enabled) {
@@ -1236,7 +1236,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
 
 		wm_high.disp_clk = mode->clock;
 		wm_high.src_width = mode->crtc_hdisplay;
-		wm_high.active_time = mode->crtc_hdisplay * pixel_period;
+		wm_high.active_time = active_time;
 		wm_high.blank_time = line_time - wm_high.active_time;
 		wm_high.interlaced = false;
 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1275,7 +1275,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
 
 		wm_low.disp_clk = mode->clock;
 		wm_low.src_width = mode->crtc_hdisplay;
-		wm_low.active_time = mode->crtc_hdisplay * pixel_period;
+		wm_low.active_time = active_time;
 		wm_low.blank_time = line_time - wm_low.active_time;
 		wm_low.interlaced = false;
 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 5b24e89..15ee8eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1183,14 +1183,14 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
 {
 	struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
 	struct dce10_wm_params wm_low, wm_high;
-	u32 pixel_period;
+	u32 active_time;
 	u32 line_time = 0;
 	u32 latency_watermark_a = 0, latency_watermark_b = 0;
 	u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
 	if (amdgpu_crtc->base.enabled && num_heads && mode) {
-		pixel_period = 1000000 / (u32)mode->clock;
-		line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
+		active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+		line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
 
 		/* watermark for high clocks */
 		if (adev->pm.dpm_enabled) {
@@ -1205,7 +1205,7 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
 
 		wm_high.disp_clk = mode->clock;
 		wm_high.src_width = mode->crtc_hdisplay;
-		wm_high.active_time = mode->crtc_hdisplay * pixel_period;
+		wm_high.active_time = active_time;
 		wm_high.blank_time = line_time - wm_high.active_time;
 		wm_high.interlaced = false;
 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1244,7 +1244,7 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
 
 		wm_low.disp_clk = mode->clock;
 		wm_low.src_width = mode->crtc_hdisplay;
-		wm_low.active_time = mode->crtc_hdisplay * pixel_period;
+		wm_low.active_time = active_time;
 		wm_low.blank_time = line_time - wm_low.active_time;
 		wm_low.interlaced = false;
 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 809aa94..cb9158b 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -986,7 +986,7 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
 	struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
 	struct dce6_wm_params wm_low, wm_high;
 	u32 dram_channels;
-	u32 pixel_period;
+	u32 active_time;
 	u32 line_time = 0;
 	u32 latency_watermark_a = 0, latency_watermark_b = 0;
 	u32 priority_a_mark = 0, priority_b_mark = 0;
@@ -996,8 +996,8 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
 	fixed20_12 a, b, c;
 
 	if (amdgpu_crtc->base.enabled && num_heads && mode) {
-		pixel_period = 1000000 / (u32)mode->clock;
-		line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
+		active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+		line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
 		priority_a_cnt = 0;
 		priority_b_cnt = 0;
 
@@ -1016,7 +1016,7 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
 
 		wm_high.disp_clk = mode->clock;
 		wm_high.src_width = mode->crtc_hdisplay;
-		wm_high.active_time = mode->crtc_hdisplay * pixel_period;
+		wm_high.active_time = active_time;
 		wm_high.blank_time = line_time - wm_high.active_time;
 		wm_high.interlaced = false;
 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1043,7 +1043,7 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
 
 		wm_low.disp_clk = mode->clock;
 		wm_low.src_width = mode->crtc_hdisplay;
-		wm_low.active_time = mode->crtc_hdisplay * pixel_period;
+		wm_low.active_time = active_time;
 		wm_low.blank_time = line_time - wm_low.active_time;
 		wm_low.interlaced = false;
 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index d2590d7..d547bcf 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -1098,14 +1098,14 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
 {
 	struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
 	struct dce8_wm_params wm_low, wm_high;
-	u32 pixel_period;
+	u32 active_time;
 	u32 line_time = 0;
 	u32 latency_watermark_a = 0, latency_watermark_b = 0;
 	u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 
 	if (amdgpu_crtc->base.enabled && num_heads && mode) {
-		pixel_period = 1000000 / (u32)mode->clock;
-		line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
+		active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
+		line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
 
 		/* watermark for high clocks */
 		if (adev->pm.dpm_enabled) {
@@ -1120,7 +1120,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
 
 		wm_high.disp_clk = mode->clock;
 		wm_high.src_width = mode->crtc_hdisplay;
-		wm_high.active_time = mode->crtc_hdisplay * pixel_period;
+		wm_high.active_time = active_time;
 		wm_high.blank_time = line_time - wm_high.active_time;
 		wm_high.interlaced = false;
 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -1159,7 +1159,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
 
 		wm_low.disp_clk = mode->clock;
 		wm_low.src_width = mode->crtc_hdisplay;
-		wm_low.active_time = mode->crtc_hdisplay * pixel_period;
+		wm_low.active_time = active_time;
 		wm_low.blank_time = line_time - wm_low.active_time;
 		wm_low.interlaced = false;
 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
-- 
2.7.4

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH 2/2] drm/amdgpu: Avoid overflows/divide-by-zero in latency_watermark calculations.
  2017-03-29 20:09 amdgpu fixes for display watermark calculations Mario Kleiner
  2017-03-29 20:09 ` [PATCH 1/2] drm/amdgpu: Make display watermark calculations more accurate Mario Kleiner
@ 2017-03-29 20:09 ` Mario Kleiner
       [not found]   ` <1490818152-10891-3-git-send-email-mario.kleiner.de-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  1 sibling, 1 reply; 4+ messages in thread
From: Mario Kleiner @ 2017-03-29 20:09 UTC (permalink / raw)
  To: dri-devel; +Cc: alexander.deucher, amd-gfx

At dot clocks > approx. 250 Mhz, some of these calcs will overflow and
cause miscalculation of latency watermarks, and for some overflows also
divide-by-zero driver crash ("divide error: 0000 [#1] PREEMPT SMP" in
"dce_v10_0_latency_watermark+0x12d/0x190").

This zero-divide happened, e.g., on AMD Tonga Pro under DCE-10,
on a Displayport panel when trying to set a video mode of 2560x1440
at 165 Hz vrefresh with a dot clock of 635.540 Mhz.

Refine calculations to avoid the overflows.

Tested for DCE-10 with R9 380 Tonga + ASUS ROG PG279 panel.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 19 +++----------------
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 19 +++----------------
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c  | 19 +++----------------
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c  | 19 +++----------------
 4 files changed, 12 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index d3db921..33541ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -1090,23 +1090,10 @@ static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
 	a.full = dfixed_const(available_bandwidth);
 	b.full = dfixed_const(wm->num_heads);
 	a.full = dfixed_div(a, b);
+	tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
+	tmp = min(dfixed_trunc(a), tmp);
 
-	b.full = dfixed_const(mc_latency + 512);
-	c.full = dfixed_const(wm->disp_clk);
-	b.full = dfixed_div(b, c);
-
-	c.full = dfixed_const(dmif_size);
-	b.full = dfixed_div(c, b);
-
-	tmp = min(dfixed_trunc(a), dfixed_trunc(b));
-
-	b.full = dfixed_const(1000);
-	c.full = dfixed_const(wm->disp_clk);
-	b.full = dfixed_div(c, b);
-	c.full = dfixed_const(wm->bytes_per_pixel);
-	b.full = dfixed_mul(b, c);
-
-	lb_fill_bw = min(tmp, dfixed_trunc(b));
+	lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 
 	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 	b.full = dfixed_const(1000);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 15ee8eb..1388f8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1059,23 +1059,10 @@ static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
 	a.full = dfixed_const(available_bandwidth);
 	b.full = dfixed_const(wm->num_heads);
 	a.full = dfixed_div(a, b);
+	tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
+	tmp = min(dfixed_trunc(a), tmp);
 
-	b.full = dfixed_const(mc_latency + 512);
-	c.full = dfixed_const(wm->disp_clk);
-	b.full = dfixed_div(b, c);
-
-	c.full = dfixed_const(dmif_size);
-	b.full = dfixed_div(c, b);
-
-	tmp = min(dfixed_trunc(a), dfixed_trunc(b));
-
-	b.full = dfixed_const(1000);
-	c.full = dfixed_const(wm->disp_clk);
-	b.full = dfixed_div(c, b);
-	c.full = dfixed_const(wm->bytes_per_pixel);
-	b.full = dfixed_mul(b, c);
-
-	lb_fill_bw = min(tmp, dfixed_trunc(b));
+	lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 
 	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 	b.full = dfixed_const(1000);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index cb9158b..bad52c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -861,23 +861,10 @@ static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm)
 	a.full = dfixed_const(available_bandwidth);
 	b.full = dfixed_const(wm->num_heads);
 	a.full = dfixed_div(a, b);
+	tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
+	tmp = min(dfixed_trunc(a), tmp);
 
-	b.full = dfixed_const(mc_latency + 512);
-	c.full = dfixed_const(wm->disp_clk);
-	b.full = dfixed_div(b, c);
-
-	c.full = dfixed_const(dmif_size);
-	b.full = dfixed_div(c, b);
-
-	tmp = min(dfixed_trunc(a), dfixed_trunc(b));
-
-	b.full = dfixed_const(1000);
-	c.full = dfixed_const(wm->disp_clk);
-	b.full = dfixed_div(c, b);
-	c.full = dfixed_const(wm->bytes_per_pixel);
-	b.full = dfixed_mul(b, c);
-
-	lb_fill_bw = min(tmp, dfixed_trunc(b));
+	lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 
 	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 	b.full = dfixed_const(1000);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index d547bcf..e52fc92 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -974,23 +974,10 @@ static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
 	a.full = dfixed_const(available_bandwidth);
 	b.full = dfixed_const(wm->num_heads);
 	a.full = dfixed_div(a, b);
+	tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
+	tmp = min(dfixed_trunc(a), tmp);
 
-	b.full = dfixed_const(mc_latency + 512);
-	c.full = dfixed_const(wm->disp_clk);
-	b.full = dfixed_div(b, c);
-
-	c.full = dfixed_const(dmif_size);
-	b.full = dfixed_div(c, b);
-
-	tmp = min(dfixed_trunc(a), dfixed_trunc(b));
-
-	b.full = dfixed_const(1000);
-	c.full = dfixed_const(wm->disp_clk);
-	b.full = dfixed_div(c, b);
-	c.full = dfixed_const(wm->bytes_per_pixel);
-	b.full = dfixed_mul(b, c);
-
-	lb_fill_bw = min(tmp, dfixed_trunc(b));
+	lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 
 	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 	b.full = dfixed_const(1000);
-- 
2.7.4

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] drm/amdgpu: Avoid overflows/divide-by-zero in latency_watermark calculations.
       [not found]   ` <1490818152-10891-3-git-send-email-mario.kleiner.de-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2017-03-30 19:24     ` Alex Deucher
  0 siblings, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2017-03-30 19:24 UTC (permalink / raw)
  To: Mario Kleiner
  Cc: Deucher, Alexander, amd-gfx list, Maling list - DRI developers

On Wed, Mar 29, 2017 at 4:09 PM, Mario Kleiner
<mario.kleiner.de@gmail.com> wrote:
> At dot clocks > approx. 250 Mhz, some of these calcs will overflow and
> cause miscalculation of latency watermarks, and for some overflows also
> divide-by-zero driver crash ("divide error: 0000 [#1] PREEMPT SMP" in
> "dce_v10_0_latency_watermark+0x12d/0x190").
>
> This zero-divide happened, e.g., on AMD Tonga Pro under DCE-10,
> on a Displayport panel when trying to set a video mode of 2560x1440
> at 165 Hz vrefresh with a dot clock of 635.540 Mhz.
>
> Refine calculations to avoid the overflows.
>
> Tested for DCE-10 with R9 380 Tonga + ASUS ROG PG279 panel.
>
> Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>

Applied the series.  thanks!

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 19 +++----------------
>  drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 19 +++----------------
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c  | 19 +++----------------
>  drivers/gpu/drm/amd/amdgpu/dce_v8_0.c  | 19 +++----------------
>  4 files changed, 12 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index d3db921..33541ac 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -1090,23 +1090,10 @@ static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
>         a.full = dfixed_const(available_bandwidth);
>         b.full = dfixed_const(wm->num_heads);
>         a.full = dfixed_div(a, b);
> +       tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
> +       tmp = min(dfixed_trunc(a), tmp);
>
> -       b.full = dfixed_const(mc_latency + 512);
> -       c.full = dfixed_const(wm->disp_clk);
> -       b.full = dfixed_div(b, c);
> -
> -       c.full = dfixed_const(dmif_size);
> -       b.full = dfixed_div(c, b);
> -
> -       tmp = min(dfixed_trunc(a), dfixed_trunc(b));
> -
> -       b.full = dfixed_const(1000);
> -       c.full = dfixed_const(wm->disp_clk);
> -       b.full = dfixed_div(c, b);
> -       c.full = dfixed_const(wm->bytes_per_pixel);
> -       b.full = dfixed_mul(b, c);
> -
> -       lb_fill_bw = min(tmp, dfixed_trunc(b));
> +       lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
>
>         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
>         b.full = dfixed_const(1000);
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index 15ee8eb..1388f8a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -1059,23 +1059,10 @@ static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
>         a.full = dfixed_const(available_bandwidth);
>         b.full = dfixed_const(wm->num_heads);
>         a.full = dfixed_div(a, b);
> +       tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
> +       tmp = min(dfixed_trunc(a), tmp);
>
> -       b.full = dfixed_const(mc_latency + 512);
> -       c.full = dfixed_const(wm->disp_clk);
> -       b.full = dfixed_div(b, c);
> -
> -       c.full = dfixed_const(dmif_size);
> -       b.full = dfixed_div(c, b);
> -
> -       tmp = min(dfixed_trunc(a), dfixed_trunc(b));
> -
> -       b.full = dfixed_const(1000);
> -       c.full = dfixed_const(wm->disp_clk);
> -       b.full = dfixed_div(c, b);
> -       c.full = dfixed_const(wm->bytes_per_pixel);
> -       b.full = dfixed_mul(b, c);
> -
> -       lb_fill_bw = min(tmp, dfixed_trunc(b));
> +       lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
>
>         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
>         b.full = dfixed_const(1000);
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index cb9158b..bad52c0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -861,23 +861,10 @@ static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm)
>         a.full = dfixed_const(available_bandwidth);
>         b.full = dfixed_const(wm->num_heads);
>         a.full = dfixed_div(a, b);
> +       tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
> +       tmp = min(dfixed_trunc(a), tmp);
>
> -       b.full = dfixed_const(mc_latency + 512);
> -       c.full = dfixed_const(wm->disp_clk);
> -       b.full = dfixed_div(b, c);
> -
> -       c.full = dfixed_const(dmif_size);
> -       b.full = dfixed_div(c, b);
> -
> -       tmp = min(dfixed_trunc(a), dfixed_trunc(b));
> -
> -       b.full = dfixed_const(1000);
> -       c.full = dfixed_const(wm->disp_clk);
> -       b.full = dfixed_div(c, b);
> -       c.full = dfixed_const(wm->bytes_per_pixel);
> -       b.full = dfixed_mul(b, c);
> -
> -       lb_fill_bw = min(tmp, dfixed_trunc(b));
> +       lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
>
>         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
>         b.full = dfixed_const(1000);
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> index d547bcf..e52fc92 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> @@ -974,23 +974,10 @@ static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
>         a.full = dfixed_const(available_bandwidth);
>         b.full = dfixed_const(wm->num_heads);
>         a.full = dfixed_div(a, b);
> +       tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
> +       tmp = min(dfixed_trunc(a), tmp);
>
> -       b.full = dfixed_const(mc_latency + 512);
> -       c.full = dfixed_const(wm->disp_clk);
> -       b.full = dfixed_div(b, c);
> -
> -       c.full = dfixed_const(dmif_size);
> -       b.full = dfixed_div(c, b);
> -
> -       tmp = min(dfixed_trunc(a), dfixed_trunc(b));
> -
> -       b.full = dfixed_const(1000);
> -       c.full = dfixed_const(wm->disp_clk);
> -       b.full = dfixed_div(c, b);
> -       c.full = dfixed_const(wm->bytes_per_pixel);
> -       b.full = dfixed_mul(b, c);
> -
> -       lb_fill_bw = min(tmp, dfixed_trunc(b));
> +       lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
>
>         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
>         b.full = dfixed_const(1000);
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-03-30 19:24 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-29 20:09 amdgpu fixes for display watermark calculations Mario Kleiner
2017-03-29 20:09 ` [PATCH 1/2] drm/amdgpu: Make display watermark calculations more accurate Mario Kleiner
2017-03-29 20:09 ` [PATCH 2/2] drm/amdgpu: Avoid overflows/divide-by-zero in latency_watermark calculations Mario Kleiner
     [not found]   ` <1490818152-10891-3-git-send-email-mario.kleiner.de-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-03-30 19:24     ` Alex Deucher

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