[PATCH 0/5] Classify the engines in class + instance (v2)

[PATCH 0/5] Classify the engines in class + instance (v2)

[Oscar Mateo]

This refactoring helps simplify a few things here and there.

Daniele Ceraolo Spurio (2):
  drm/i915: Classify the engines in class + instance
  drm/i915: Use the engine class to get the context size

Oscar Mateo (3):
  drm/i915: Use the same vfunc for BSD2 ring init
  drm/i915: Generate the engine name based on the instance number
  drm/i915: Split the engine info table in two levels, using class +
    instance

 drivers/gpu/drm/i915/intel_engine_cs.c       | 88 +++++++++++++++++++---------
 drivers/gpu/drm/i915/intel_lrc.c             | 34 +++++++----
 drivers/gpu/drm/i915/intel_lrc.h             |  7 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.c      | 14 -----
 drivers/gpu/drm/i915/intel_ringbuffer.h      | 15 ++++-
 drivers/gpu/drm/i915/selftests/mock_engine.c |  2 +-
 6 files changed, 102 insertions(+), 58 deletions(-)

-- 
1.9.1

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[PATCH 1/5] drm/i915: Classify the engines in class + instance

[Oscar Mateo]

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

In such a way that vcs and vcs2 are just two different instances (0 and 1)
of the same engine class (VIDEO_DECODE_CLASS).

v2: Align the instance types (Tvrtko)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_ringbuffer.h | 10 ++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 854e8e0..49ca7d1 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -30,6 +30,8 @@
 	const char *name;
 	unsigned int exec_id;
 	unsigned int hw_id;
+	enum intel_engine_class class;
+	u8 instance;
 	u32 mmio_base;
 	unsigned irq_shift;
 	int (*init_legacy)(struct intel_engine_cs *engine);
@@ -39,6 +41,8 @@
 		.name = "rcs",
 		.hw_id = RCS_HW,
 		.exec_id = I915_EXEC_RENDER,
+		.class = RENDER_CLASS,
+		.instance = 0,
 		.mmio_base = RENDER_RING_BASE,
 		.irq_shift = GEN8_RCS_IRQ_SHIFT,
 		.init_execlists = logical_render_ring_init,
@@ -48,6 +52,8 @@
 		.name = "bcs",
 		.hw_id = BCS_HW,
 		.exec_id = I915_EXEC_BLT,
+		.class = COPY_ENGINE_CLASS,
+		.instance = 0,
 		.mmio_base = BLT_RING_BASE,
 		.irq_shift = GEN8_BCS_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -57,6 +63,8 @@
 		.name = "vcs",
 		.hw_id = VCS_HW,
 		.exec_id = I915_EXEC_BSD,
+		.class = VIDEO_DECODE_CLASS,
+		.instance = 0,
 		.mmio_base = GEN6_BSD_RING_BASE,
 		.irq_shift = GEN8_VCS1_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -66,6 +74,8 @@
 		.name = "vcs2",
 		.hw_id = VCS2_HW,
 		.exec_id = I915_EXEC_BSD,
+		.class = VIDEO_DECODE_CLASS,
+		.instance = 1,
 		.mmio_base = GEN8_BSD2_RING_BASE,
 		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -75,6 +85,8 @@
 		.name = "vecs",
 		.hw_id = VECS_HW,
 		.exec_id = I915_EXEC_VEBOX,
+		.class = VIDEO_ENHANCEMENT_CLASS,
+		.instance = 0,
 		.mmio_base = VEBOX_RING_BASE,
 		.irq_shift = GEN8_VECS_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -101,6 +113,8 @@
 	engine->hw_id = engine->guc_id = info->hw_id;
 	engine->mmio_base = info->mmio_base;
 	engine->irq_shift = info->irq_shift;
+	engine->class = info->class;
+	engine->instance = info->instance;
 
 	/* Nothing to do here, execute in order of dependencies */
 	engine->schedule = NULL;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index cbe61d3..4ab590b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -193,6 +193,16 @@ struct intel_engine_cs {
 	enum intel_engine_id id;
 	unsigned int exec_id;
 	unsigned int hw_id;
+
+	enum intel_engine_class {
+		RENDER_CLASS = 0,
+		VIDEO_DECODE_CLASS = 1,
+		VIDEO_ENHANCEMENT_CLASS = 2,
+		COPY_ENGINE_CLASS = 3,
+		OTHER_CLASS = 4
+	} class;
+	u8 instance;
+
 	unsigned int guc_id;
 	u32		mmio_base;
 	unsigned int irq_shift;
-- 
1.9.1

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[PATCH 2/5] drm/i915: Use the same vfunc for BSD2 ring init

[Oscar Mateo]

If we needed to do something different for the init functions, we could
always look at the engine instance to make the distinction. But, in any
case, the two functions are virtually identical already (please notice
that BSD2_RING is only used from gen8 onwards).

With this, the init functions depends excusively on the engine class
(a fact that we will use soon).

v2: Commit message

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c  |  2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c | 14 --------------
 drivers/gpu/drm/i915/intel_ringbuffer.h |  1 -
 3 files changed, 1 insertion(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 49ca7d1..bb10847 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -79,7 +79,7 @@
 		.mmio_base = GEN8_BSD2_RING_BASE,
 		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
-		.init_legacy = intel_init_bsd2_ring_buffer,
+		.init_legacy = intel_init_bsd_ring_buffer,
 	},
 	[VECS] = {
 		.name = "vecs",
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c98acc2..81eee42 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2175,20 +2175,6 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
 	return intel_init_ring_buffer(engine);
 }
 
-/**
- * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
- */
-int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine)
-{
-	struct drm_i915_private *dev_priv = engine->i915;
-
-	intel_ring_default_vfuncs(dev_priv, engine);
-
-	engine->emit_flush = gen6_bsd_ring_flush;
-
-	return intel_init_ring_buffer(engine);
-}
-
 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 4ab590b..5c1a27f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -561,7 +561,6 @@ int intel_ring_pin(struct intel_ring *ring,
 
 int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
-int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine);
 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
 
-- 
1.9.1

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[PATCH 3/5] drm/i915: Generate the engine name based on the instance number

[Oscar Mateo]

Not really needed, but makes the next change a little bit more compact.

v2:
  - Use zero-based numbering for engine names: xcs0, xcs1.. xcsN (Tvrtko, Chris)
  - Make sure the mock engine name is null-terminated (Tvrtko, Chris)

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c       | 6 ++++--
 drivers/gpu/drm/i915/intel_ringbuffer.h      | 4 +++-
 drivers/gpu/drm/i915/selftests/mock_engine.c | 2 +-
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index bb10847..2409908 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -71,7 +71,7 @@
 		.init_legacy = intel_init_bsd_ring_buffer,
 	},
 	[VCS2] = {
-		.name = "vcs2",
+		.name = "vcs",
 		.hw_id = VCS2_HW,
 		.exec_id = I915_EXEC_BSD,
 		.class = VIDEO_DECODE_CLASS,
@@ -100,6 +100,7 @@
 {
 	const struct engine_info *info = &intel_engines[id];
 	struct intel_engine_cs *engine;
+	char instance[3] = "";
 
 	GEM_BUG_ON(dev_priv->engine[id]);
 	engine = kzalloc(sizeof(*engine), GFP_KERNEL);
@@ -108,7 +109,8 @@
 
 	engine->id = id;
 	engine->i915 = dev_priv;
-	engine->name = info->name;
+	snprintf(instance, sizeof(instance), "%u", info->instance);
+	snprintf(engine->name, sizeof(engine->name), "%s%s", info->name, instance);
 	engine->exec_id = info->exec_id;
 	engine->hw_id = engine->guc_id = info->hw_id;
 	engine->mmio_base = info->mmio_base;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 5c1a27f..d617049 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -187,9 +187,11 @@ enum intel_engine_id {
 	VECS
 };
 
+#define INTEL_ENGINE_CS_MAX_NAME 8
+
 struct intel_engine_cs {
 	struct drm_i915_private *i915;
-	const char	*name;
+	char name[INTEL_ENGINE_CS_MAX_NAME];
 	enum intel_engine_id id;
 	unsigned int exec_id;
 	unsigned int hw_id;
diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.c b/drivers/gpu/drm/i915/selftests/mock_engine.c
index b89050e..b8e53bd 100644
--- a/drivers/gpu/drm/i915/selftests/mock_engine.c
+++ b/drivers/gpu/drm/i915/selftests/mock_engine.c
@@ -140,7 +140,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
 
 	/* minimal engine setup for requests */
 	engine->base.i915 = i915;
-	engine->base.name = name;
+	snprintf(engine->base.name, sizeof(engine->base.name), "%s", name);
 	engine->base.id = id++;
 	engine->base.status_page.page_addr = (void *)(engine + 1);
 
-- 
1.9.1

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[PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

[Oscar Mateo]

There are some properties that logically belong to the engine class, and some
that belong to the engine instance. Make it explicit.

v2: Commit message (Tvrtko)

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 72 +++++++++++++++++++++-------------
 1 file changed, 44 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 2409908..506ec952 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -26,71 +26,83 @@
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"
 
-static const struct engine_info {
+struct engine_class_info {
 	const char *name;
 	unsigned int exec_id;
+	int (*init_legacy)(struct intel_engine_cs *engine);
+	int (*init_execlists)(struct intel_engine_cs *engine);
+};
+
+static const struct engine_class_info intel_engine_classes[] = {
+	[RENDER_CLASS] = {
+		.name = "rcs",
+		.exec_id = I915_EXEC_RENDER,
+		.init_execlists = logical_render_ring_init,
+		.init_legacy = intel_init_render_ring_buffer,
+	},
+	[COPY_ENGINE_CLASS] = {
+		.name = "bcs",
+		.exec_id = I915_EXEC_BLT,
+		.init_execlists = logical_xcs_ring_init,
+		.init_legacy = intel_init_blt_ring_buffer,
+	},
+	[VIDEO_DECODE_CLASS] = {
+		.name = "vcs",
+		.exec_id = I915_EXEC_BSD,
+		.init_execlists = logical_xcs_ring_init,
+		.init_legacy = intel_init_bsd_ring_buffer,
+	},
+	[VIDEO_ENHANCEMENT_CLASS] = {
+		.name = "vecs",
+		.exec_id = I915_EXEC_VEBOX,
+		.init_execlists = logical_xcs_ring_init,
+		.init_legacy = intel_init_vebox_ring_buffer,
+	},
+};
+
+struct engine_info {
 	unsigned int hw_id;
 	enum intel_engine_class class;
 	u8 instance;
 	u32 mmio_base;
 	unsigned irq_shift;
-	int (*init_legacy)(struct intel_engine_cs *engine);
-	int (*init_execlists)(struct intel_engine_cs *engine);
-} intel_engines[] = {
+};
+
+static const struct engine_info intel_engines[] = {
 	[RCS] = {
-		.name = "rcs",
 		.hw_id = RCS_HW,
-		.exec_id = I915_EXEC_RENDER,
 		.class = RENDER_CLASS,
 		.instance = 0,
 		.mmio_base = RENDER_RING_BASE,
 		.irq_shift = GEN8_RCS_IRQ_SHIFT,
-		.init_execlists = logical_render_ring_init,
-		.init_legacy = intel_init_render_ring_buffer,
 	},
 	[BCS] = {
-		.name = "bcs",
 		.hw_id = BCS_HW,
-		.exec_id = I915_EXEC_BLT,
 		.class = COPY_ENGINE_CLASS,
 		.instance = 0,
 		.mmio_base = BLT_RING_BASE,
 		.irq_shift = GEN8_BCS_IRQ_SHIFT,
-		.init_execlists = logical_xcs_ring_init,
-		.init_legacy = intel_init_blt_ring_buffer,
 	},
 	[VCS] = {
-		.name = "vcs",
 		.hw_id = VCS_HW,
-		.exec_id = I915_EXEC_BSD,
 		.class = VIDEO_DECODE_CLASS,
 		.instance = 0,
 		.mmio_base = GEN6_BSD_RING_BASE,
 		.irq_shift = GEN8_VCS1_IRQ_SHIFT,
-		.init_execlists = logical_xcs_ring_init,
-		.init_legacy = intel_init_bsd_ring_buffer,
 	},
 	[VCS2] = {
-		.name = "vcs",
 		.hw_id = VCS2_HW,
-		.exec_id = I915_EXEC_BSD,
 		.class = VIDEO_DECODE_CLASS,
 		.instance = 1,
 		.mmio_base = GEN8_BSD2_RING_BASE,
 		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
-		.init_execlists = logical_xcs_ring_init,
-		.init_legacy = intel_init_bsd_ring_buffer,
 	},
 	[VECS] = {
-		.name = "vecs",
 		.hw_id = VECS_HW,
-		.exec_id = I915_EXEC_VEBOX,
 		.class = VIDEO_ENHANCEMENT_CLASS,
 		.instance = 0,
 		.mmio_base = VEBOX_RING_BASE,
 		.irq_shift = GEN8_VECS_IRQ_SHIFT,
-		.init_execlists = logical_xcs_ring_init,
-		.init_legacy = intel_init_vebox_ring_buffer,
 	},
 };
 
@@ -99,6 +111,8 @@
 		   enum intel_engine_id id)
 {
 	const struct engine_info *info = &intel_engines[id];
+	const struct engine_class_info *class_info =
+				&intel_engine_classes[info->class];
 	struct intel_engine_cs *engine;
 	char instance[3] = "";
 
@@ -110,8 +124,8 @@
 	engine->id = id;
 	engine->i915 = dev_priv;
 	snprintf(instance, sizeof(instance), "%u", info->instance);
-	snprintf(engine->name, sizeof(engine->name), "%s%s", info->name, instance);
-	engine->exec_id = info->exec_id;
+	snprintf(engine->name, sizeof(engine->name), "%s%s", class_info->name, instance);
+	engine->exec_id = class_info->exec_id;
 	engine->hw_id = engine->guc_id = info->hw_id;
 	engine->mmio_base = info->mmio_base;
 	engine->irq_shift = info->irq_shift;
@@ -191,12 +205,14 @@ int intel_engines_init(struct drm_i915_private *dev_priv)
 	int err = 0;
 
 	for_each_engine(engine, dev_priv, id) {
+		const struct engine_class_info *class_info =
+					&intel_engine_classes[engine->class];
 		int (*init)(struct intel_engine_cs *engine);
 
 		if (i915.enable_execlists)
-			init = intel_engines[id].init_execlists;
+			init = class_info->init_execlists;
 		else
-			init = intel_engines[id].init_legacy;
+			init = class_info->init_legacy;
 		if (!init) {
 			kfree(engine);
 			dev_priv->engine[id] = NULL;
-- 
1.9.1

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[PATCH 5/5] drm/i915: Use the engine class to get the context size

[Oscar Mateo]

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Technically speaking, the context size is per engine class, not per
instance.

v2: Add MISSING_CASE (Tvrtko)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 34 ++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_lrc.h |  7 ++++++-
 2 files changed, 28 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0dc1cc4..c8abf89 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1908,8 +1908,10 @@ static void execlists_init_reg_state(u32 *regs,
 }
 
 /**
- * intel_lr_context_size() - return the size of the context for an engine
- * @engine: which engine to find the context size for
+ * intel_lr_class_context_size() - return the size of the context for a given
+ * engine class
+ * @dev_priv: i915 device private
+ * @class: which engine class to find the context size for
  *
  * Each engine may require a different amount of space for a context image,
  * so when allocating (or copying) an image, this function can be used to
@@ -1921,25 +1923,33 @@ static void execlists_init_reg_state(u32 *regs,
  * in LRC mode, but does not include the "shared data page" used with
  * GuC submission. The caller should account for this if using the GuC.
  */
-uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
+uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv,
+				     enum intel_engine_class class)
 {
 	int ret = 0;
 
-	WARN_ON(INTEL_GEN(engine->i915) < 8);
+	WARN_ON(INTEL_GEN(dev_priv) < 8);
 
-	switch (engine->id) {
-	case RCS:
-		if (INTEL_GEN(engine->i915) >= 9)
+	switch (class) {
+	case RENDER_CLASS:
+		switch (INTEL_GEN(dev_priv)) {
+		default:
+			MISSING_CASE(INTEL_GEN(dev_priv));
+		case 9:
 			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
-		else
+			break;
+		case 8:
 			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
+			break;
+		}
 		break;
-	case VCS:
-	case BCS:
-	case VECS:
-	case VCS2:
+	case VIDEO_DECODE_CLASS:
+	case VIDEO_ENHANCEMENT_CLASS:
+	case COPY_ENGINE_CLASS:
 		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
 		break;
+	default:
+		MISSING_CASE(class);
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index e8015e7..b3a4331 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -78,7 +78,12 @@ enum {
 struct drm_i915_private;
 struct i915_gem_context;
 
-uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
+uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv,
+				     enum intel_engine_class class);
+static inline uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
+{
+	return intel_lr_class_context_size(engine->i915, engine->class);
+}
 
 void intel_lr_context_resume(struct drm_i915_private *dev_priv);
 uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
-- 
1.9.1

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Re: [PATCH 3/5] drm/i915: Generate the engine name based on the instance number

[Oscar Mateo]

On 04/06/2017 01:10 PM, Chris Wilson wrote:
> On Thu, Apr 06, 2017 at 05:55:42AM -0700, Oscar Mateo wrote:
>> Not really needed, but makes the next change a little bit more compact.
>>
>> v2:
>>    - Use zero-based numbering for engine names: xcs0, xcs1.. xcsN (Tvrtko, Chris)
>>    - Make sure the mock engine name is null-terminated (Tvrtko, Chris)
>>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_engine_cs.c       | 6 ++++--
>>   drivers/gpu/drm/i915/intel_ringbuffer.h      | 4 +++-
>>   drivers/gpu/drm/i915/selftests/mock_engine.c | 2 +-
>>   3 files changed, 8 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index bb10847..2409908 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -71,7 +71,7 @@
>>   		.init_legacy = intel_init_bsd_ring_buffer,
>>   	},
>>   	[VCS2] = {
>> -		.name = "vcs2",
>> +		.name = "vcs",
>>   		.hw_id = VCS2_HW,
>>   		.exec_id = I915_EXEC_BSD,
>>   		.class = VIDEO_DECODE_CLASS,
>> @@ -100,6 +100,7 @@
>>   {
>>   	const struct engine_info *info = &intel_engines[id];
>>   	struct intel_engine_cs *engine;
>> +	char instance[3] = "";
>>   
>>   	GEM_BUG_ON(dev_priv->engine[id]);
>>   	engine = kzalloc(sizeof(*engine), GFP_KERNEL);
>> @@ -108,7 +109,8 @@
>>   
>>   	engine->id = id;
>>   	engine->i915 = dev_priv;
>> -	engine->name = info->name;
>> +	snprintf(instance, sizeof(instance), "%u", info->instance);
>> +	snprintf(engine->name, sizeof(engine->name), "%s%s", info->name, instance);
> Huh? Please explain why not "%s%u", I'm feeling stupid.
> -Chris
>
No, I am the one feeling stupid. Please ignore...
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Re: [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

[Oscar Mateo]

On 04/06/2017 01:12 PM, Chris Wilson wrote:
> On Thu, Apr 06, 2017 at 05:55:43AM -0700, Oscar Mateo wrote:
>> There are some properties that logically belong to the engine class, and some
>> that belong to the engine instance. Make it explicit.
>>
>> v2: Commit message (Tvrtko)
>>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_engine_cs.c | 72 +++++++++++++++++++++-------------
>>   1 file changed, 44 insertions(+), 28 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index 2409908..506ec952 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -26,71 +26,83 @@
>>   #include "intel_ringbuffer.h"
>>   #include "intel_lrc.h"
>>   
>> -static const struct engine_info {
>> +struct engine_class_info {
>>   	const char *name;
>>   	unsigned int exec_id;
> Ugh. What??? Each engine will have a unique exec/uabi id.
> -Chris
Ok, I'll move it back to the instance if it matches better the VLC load 
balancing work?
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[PATCH v3] drm/i915: Generate the engine name based on the instance number

[Oscar Mateo]

Not really needed, but makes the next change a little bit more compact.

v2:
  - Use zero-based numbering for engine names: xcs0, xcs1.. xcsN (Tvrtko, Chris)
  - Make sure the mock engine name is null-terminated (Tvrtko, Chris)

v3: Because I'm stupid (Chris)

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c       | 5 +++--
 drivers/gpu/drm/i915/intel_ringbuffer.h      | 4 +++-
 drivers/gpu/drm/i915/selftests/mock_engine.c | 2 +-
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index bb10847..c6a73d0 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -71,7 +71,7 @@
 		.init_legacy = intel_init_bsd_ring_buffer,
 	},
 	[VCS2] = {
-		.name = "vcs2",
+		.name = "vcs",
 		.hw_id = VCS2_HW,
 		.exec_id = I915_EXEC_BSD,
 		.class = VIDEO_DECODE_CLASS,
@@ -108,7 +108,8 @@
 
 	engine->id = id;
 	engine->i915 = dev_priv;
-	engine->name = info->name;
+	snprintf(engine->name, sizeof(engine->name), "%s%u",
+				info->name, info->instance);
 	engine->exec_id = info->exec_id;
 	engine->hw_id = engine->guc_id = info->hw_id;
 	engine->mmio_base = info->mmio_base;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 5c1a27f..d617049 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -187,9 +187,11 @@ enum intel_engine_id {
 	VECS
 };
 
+#define INTEL_ENGINE_CS_MAX_NAME 8
+
 struct intel_engine_cs {
 	struct drm_i915_private *i915;
-	const char	*name;
+	char name[INTEL_ENGINE_CS_MAX_NAME];
 	enum intel_engine_id id;
 	unsigned int exec_id;
 	unsigned int hw_id;
diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.c b/drivers/gpu/drm/i915/selftests/mock_engine.c
index b89050e..b8e53bd 100644
--- a/drivers/gpu/drm/i915/selftests/mock_engine.c
+++ b/drivers/gpu/drm/i915/selftests/mock_engine.c
@@ -140,7 +140,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
 
 	/* minimal engine setup for requests */
 	engine->base.i915 = i915;
-	engine->base.name = name;
+	snprintf(engine->base.name, sizeof(engine->base.name), "%s", name);
 	engine->base.id = id++;
 	engine->base.status_page.page_addr = (void *)(engine + 1);
 
-- 
1.9.1

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Re: [PATCH 3/5] drm/i915: Generate the engine name based on the instance number

[Chris Wilson]

On Thu, Apr 06, 2017 at 05:55:42AM -0700, Oscar Mateo wrote:
> Not really needed, but makes the next change a little bit more compact.
> 
> v2:
>   - Use zero-based numbering for engine names: xcs0, xcs1.. xcsN (Tvrtko, Chris)
>   - Make sure the mock engine name is null-terminated (Tvrtko, Chris)
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c       | 6 ++++--
>  drivers/gpu/drm/i915/intel_ringbuffer.h      | 4 +++-
>  drivers/gpu/drm/i915/selftests/mock_engine.c | 2 +-
>  3 files changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index bb10847..2409908 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -71,7 +71,7 @@
>  		.init_legacy = intel_init_bsd_ring_buffer,
>  	},
>  	[VCS2] = {
> -		.name = "vcs2",
> +		.name = "vcs",
>  		.hw_id = VCS2_HW,
>  		.exec_id = I915_EXEC_BSD,
>  		.class = VIDEO_DECODE_CLASS,
> @@ -100,6 +100,7 @@
>  {
>  	const struct engine_info *info = &intel_engines[id];
>  	struct intel_engine_cs *engine;
> +	char instance[3] = "";
>  
>  	GEM_BUG_ON(dev_priv->engine[id]);
>  	engine = kzalloc(sizeof(*engine), GFP_KERNEL);
> @@ -108,7 +109,8 @@
>  
>  	engine->id = id;
>  	engine->i915 = dev_priv;
> -	engine->name = info->name;
> +	snprintf(instance, sizeof(instance), "%u", info->instance);
> +	snprintf(engine->name, sizeof(engine->name), "%s%s", info->name, instance);

Huh? Please explain why not "%s%u", I'm feeling stupid.
-Chris

-- 
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Re: [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

[Chris Wilson]

On Thu, Apr 06, 2017 at 05:55:43AM -0700, Oscar Mateo wrote:
> There are some properties that logically belong to the engine class, and some
> that belong to the engine instance. Make it explicit.
> 
> v2: Commit message (Tvrtko)
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 72 +++++++++++++++++++++-------------
>  1 file changed, 44 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 2409908..506ec952 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -26,71 +26,83 @@
>  #include "intel_ringbuffer.h"
>  #include "intel_lrc.h"
>  
> -static const struct engine_info {
> +struct engine_class_info {
>  	const char *name;
>  	unsigned int exec_id;

Ugh. What??? Each engine will have a unique exec/uabi id.
-Chris

-- 
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✓ Fi.CI.BAT: success for Classify the engines in class + instance (rev2)

[Patchwork]

== Series Details ==

Series: Classify the engines in class + instance (rev2)
URL   : https://patchwork.freedesktop.org/series/22535/
State : success

== Summary ==

Series 22535v2 Classify the engines in class + instance
https://patchwork.freedesktop.org/api/1.0/series/22535/revisions/2/mbox/

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 431s
fi-bdw-gvtdvm    total:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  time: 429s
fi-bsw-n3050     total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  time: 570s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 506s
fi-bxt-t5700     total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  time: 540s
fi-byt-j1900     total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  time: 486s
fi-byt-n2820     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 484s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 410s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 414s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 427s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 486s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 461s
fi-kbl-7500u     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 457s
fi-kbl-7560u     total:278  pass:267  dwarn:1   dfail:0   fail:0   skip:10  time: 567s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 450s
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  time: 568s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time: 458s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 489s
fi-skl-gvtdvm    total:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  time: 430s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 533s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time: 402s

3d39d8905c145cdae5a79fe6d0a3c6fd70ff8a2f drm-tip: 2017y-04m-06d-19h-30m-56s UTC integration manifest
fe8a49c drm/i915: Use the engine class to get the context size
afe54be drm/i915: Split the engine info table in two levels, using class + instance
1489950 drm/i915: Generate the engine name based on the instance number
7358f06 drm/i915: Use the same vfunc for BSD2 ring init
d13f0f9 drm/i915: Classify the engines in class + instance

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4428/
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✗ Fi.CI.BAT: failure for Classify the engines in class + instance (rev3)

[Patchwork]

== Series Details ==

Series: Classify the engines in class + instance (rev3)
URL   : https://patchwork.freedesktop.org/series/22535/
State : failure

== Summary ==

  CC [M]  drivers/gpu/drm/i915/intel_lpe_audio.o
  LD      drivers/usb/storage/usb-storage.o
  LD      drivers/usb/storage/built-in.o
  LD      drivers/thermal/thermal_sys.o
  LD      drivers/pci/pcie/aer/aerdriver.o
  LD      drivers/tty/serial/8250/8250.o
  LD      drivers/iommu/built-in.o
  LD      drivers/thermal/built-in.o
  LD      drivers/pci/pcie/aer/built-in.o
  LD      drivers/pci/pcie/built-in.o
  LD      drivers/acpi/acpica/acpi.o
  LD      kernel/sched/built-in.o
  LD      drivers/video/fbdev/core/fb.o
  LD [M]  sound/pci/hda/snd-hda-codec-generic.o
  LD      drivers/video/fbdev/core/built-in.o
  LD      kernel/built-in.o
  LD      sound/pci/built-in.o
  LD      drivers/acpi/acpica/built-in.o
  LD      drivers/acpi/built-in.o
  LD      sound/built-in.o
  LD      drivers/gpu/drm/drm.o
  AR      lib/lib.a
  EXPORTS lib/lib-ksyms.o
  LD      drivers/usb/gadget/libcomposite.o
  LD      drivers/video/fbdev/built-in.o
  LD      drivers/scsi/scsi_mod.o
  LD      lib/built-in.o
drivers/gpu/drm/i915/intel_engine_cs.c: In function ‘intel_engine_setup’:
drivers/gpu/drm/i915/intel_engine_cs.c:125:1: error: expected expression before ‘<<’ token
 <<<<<<< 67d0dd529857e865d75eda5f49785963dcb98621
 ^
drivers/gpu/drm/i915/intel_engine_cs.c:125:9: error: invalid suffix "d0dd529857e865d75eda5f49785963dcb98621" on integer constant
 <<<<<<< 67d0dd529857e865d75eda5f49785963dcb98621
         ^
drivers/gpu/drm/i915/intel_engine_cs.c:128:24: error: ‘const struct engine_info’ has no member named ‘exec_id’
  engine->exec_id = info->exec_id;
                        ^
drivers/gpu/drm/i915/intel_engine_cs.c:129:1: error: expected expression before ‘==’ token
 =======
 ^
drivers/gpu/drm/i915/intel_engine_cs.c:131:73: error: ‘instance’ undeclared (first use in this function)
  snprintf(engine->name, sizeof(engine->name), "%s%s", class_info->name, instance);
                                                                         ^
drivers/gpu/drm/i915/intel_engine_cs.c:131:73: note: each undeclared identifier is reported only once for each function it appears in
drivers/gpu/drm/i915/intel_engine_cs.c:133:1: error: expected expression before ‘>>’ token
 >>>>>>> drm/i915: Split the engine info table in two levels, using class + instance
 ^
  LD      net/ipv6/ipv6.o
  LD      drivers/usb/gadget/udc/udc-core.o
  LD      drivers/usb/gadget/udc/built-in.o
  LD [M]  drivers/net/ethernet/intel/igbvf/igbvf.o
  LD      drivers/usb/gadget/built-in.o
scripts/Makefile.build:294: recipe for target 'drivers/gpu/drm/i915/intel_engine_cs.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_engine_cs.o] Error 1
make[4]: *** Waiting for unfinished jobs....
  LD      net/ipv6/built-in.o
  LD      drivers/spi/built-in.o
  LD      drivers/pci/built-in.o
  LD [M]  drivers/net/ethernet/intel/e1000/e1000.o
  LD      net/xfrm/built-in.o
  LD      drivers/video/console/built-in.o
  LD      drivers/video/built-in.o
  LD      drivers/scsi/sd_mod.o
  LD      drivers/scsi/built-in.o
  LD      drivers/tty/serial/8250/8250_base.o
  LD      drivers/tty/serial/8250/built-in.o
  LD      drivers/tty/serial/built-in.o
  LD      fs/btrfs/btrfs.o
  LD      drivers/usb/core/usbcore.o
  LD      drivers/usb/core/built-in.o
  LD      fs/btrfs/built-in.o
  LD      drivers/md/md-mod.o
  LD      drivers/md/built-in.o
  LD      drivers/tty/vt/built-in.o
  LD      drivers/tty/built-in.o
  LD [M]  drivers/net/ethernet/intel/igb/igb.o
  CC      arch/x86/kernel/cpu/capflags.o
  LD      arch/x86/kernel/cpu/built-in.o
  LD      arch/x86/kernel/built-in.o
  LD      arch/x86/built-in.o
  LD      drivers/usb/host/xhci-hcd.o
  LD      net/ipv4/built-in.o
  LD      drivers/usb/host/built-in.o
  LD      drivers/usb/built-in.o
  LD      fs/ext4/ext4.o
  LD      fs/ext4/built-in.o
  LD      fs/built-in.o
  LD      net/core/built-in.o
  LD      net/built-in.o
  LD [M]  drivers/net/ethernet/intel/e1000e/e1000e.o
  LD      drivers/net/ethernet/built-in.o
  LD      drivers/net/built-in.o
scripts/Makefile.build:553: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:553: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:553: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1002: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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Re: [PATCH 5/5] drm/i915: Use the engine class to get the context size

[Chris Wilson]

On Tue, Apr 11, 2017 at 12:32:14PM +0100, Tvrtko Ursulin wrote:
> 
> On 11/04/2017 11:25, Chris Wilson wrote:
> >On Mon, Apr 10, 2017 at 07:34:33AM -0700, Oscar Mateo wrote:
> >>From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> >>
> >>Technically speaking, the context size is per engine class, not per
> >>instance.
> >>
> >>---
> >>diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> >>index e8015e7..bde2b6e 100644
> >>--- a/drivers/gpu/drm/i915/intel_lrc.h
> >>+++ b/drivers/gpu/drm/i915/intel_lrc.h
> >>@@ -78,7 +78,11 @@ enum {
> >> struct drm_i915_private;
> >> struct i915_gem_context;
> >>
> >>-uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
> >>+uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv, u8 class);
> >>+static inline uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
> >>+{
> >>+	return intel_lr_class_context_size(engine->i915, engine->class);
> >>+}
> >
> >I'm not understanding why you want to push this to the caller.
> >
> >Patches 1-4 are r-b me, and I'll apply once we have put out the fire.
> 
> Just to say you can keep my r-b if you change this detail. I
> wondered the same myself but didn't consider it too critical.

I've pushed the first 4 patches. Patch 5 is good to go once we have
clarification why you want to expose the per-class lookup to
context_size (or restore the interface back to hiding the class lookup).
-Chris

-- 
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Re: [PATCH 5/5] drm/i915: Use the engine class to get the context size

[Tvrtko Ursulin]

On 11/04/2017 11:25, Chris Wilson wrote:
> On Mon, Apr 10, 2017 at 07:34:33AM -0700, Oscar Mateo wrote:
>> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>
>> Technically speaking, the context size is per engine class, not per
>> instance.
>>
>> v2: Add MISSING_CASE (Tvrtko)
>>
>> v3: Rebased
>>
>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_lrc.c | 33 +++++++++++++++++++++------------
>>  drivers/gpu/drm/i915/intel_lrc.h |  6 +++++-
>>  2 files changed, 26 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>> index 0dc1cc4..1c6672c 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -1908,8 +1908,10 @@ static void execlists_init_reg_state(u32 *regs,
>>  }
>>
>>  /**
>> - * intel_lr_context_size() - return the size of the context for an engine
>> - * @engine: which engine to find the context size for
>> + * intel_lr_class_context_size() - return the size of the context for a given
>> + * engine class
>> + * @dev_priv: i915 device private
>> + * @class: which engine class to find the context size for
>>   *
>>   * Each engine may require a different amount of space for a context image,
>>   * so when allocating (or copying) an image, this function can be used to
>> @@ -1921,25 +1923,32 @@ static void execlists_init_reg_state(u32 *regs,
>>   * in LRC mode, but does not include the "shared data page" used with
>>   * GuC submission. The caller should account for this if using the GuC.
>>   */
>> -uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
>> +uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv, u8 class)
>>  {
>>  	int ret = 0;
>>
>> -	WARN_ON(INTEL_GEN(engine->i915) < 8);
>> +	WARN_ON(INTEL_GEN(dev_priv) < 8);
>>
>> -	switch (engine->id) {
>> -	case RCS:
>> -		if (INTEL_GEN(engine->i915) >= 9)
>> +	switch (class) {
>> +	case RENDER_CLASS:
>> +		switch (INTEL_GEN(dev_priv)) {
>> +		default:
>> +			MISSING_CASE(INTEL_GEN(dev_priv));
>> +		case 9:
>>  			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
>> -		else
>> +			break;
>> +		case 8:
>>  			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
>> +			break;
>> +		}
>>  		break;
>> -	case VCS:
>> -	case BCS:
>> -	case VECS:
>> -	case VCS2:
>> +	case VIDEO_DECODE_CLASS:
>> +	case VIDEO_ENHANCEMENT_CLASS:
>> +	case COPY_ENGINE_CLASS:
>>  		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
>>  		break;
>> +	default:
>> +		MISSING_CASE(class);
>>  	}
>>
>>  	return ret;
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
>> index e8015e7..bde2b6e 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.h
>> +++ b/drivers/gpu/drm/i915/intel_lrc.h
>> @@ -78,7 +78,11 @@ enum {
>>  struct drm_i915_private;
>>  struct i915_gem_context;
>>
>> -uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
>> +uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv, u8 class);
>> +static inline uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
>> +{
>> +	return intel_lr_class_context_size(engine->i915, engine->class);
>> +}
>
> I'm not understanding why you want to push this to the caller.
>
> Patches 1-4 are r-b me, and I'll apply once we have put out the fire.

Just to say you can keep my r-b if you change this detail. I wondered 
the same myself but didn't consider it too critical.

Regards,

Tvrtko
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Re: [PATCH 5/5] drm/i915: Use the engine class to get the context size

[Chris Wilson]

On Mon, Apr 10, 2017 at 07:34:33AM -0700, Oscar Mateo wrote:
> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> 
> Technically speaking, the context size is per engine class, not per
> instance.
> 
> v2: Add MISSING_CASE (Tvrtko)
> 
> v3: Rebased
> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 33 +++++++++++++++++++++------------
>  drivers/gpu/drm/i915/intel_lrc.h |  6 +++++-
>  2 files changed, 26 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 0dc1cc4..1c6672c 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1908,8 +1908,10 @@ static void execlists_init_reg_state(u32 *regs,
>  }
>  
>  /**
> - * intel_lr_context_size() - return the size of the context for an engine
> - * @engine: which engine to find the context size for
> + * intel_lr_class_context_size() - return the size of the context for a given
> + * engine class
> + * @dev_priv: i915 device private
> + * @class: which engine class to find the context size for
>   *
>   * Each engine may require a different amount of space for a context image,
>   * so when allocating (or copying) an image, this function can be used to
> @@ -1921,25 +1923,32 @@ static void execlists_init_reg_state(u32 *regs,
>   * in LRC mode, but does not include the "shared data page" used with
>   * GuC submission. The caller should account for this if using the GuC.
>   */
> -uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
> +uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv, u8 class)
>  {
>  	int ret = 0;
>  
> -	WARN_ON(INTEL_GEN(engine->i915) < 8);
> +	WARN_ON(INTEL_GEN(dev_priv) < 8);
>  
> -	switch (engine->id) {
> -	case RCS:
> -		if (INTEL_GEN(engine->i915) >= 9)
> +	switch (class) {
> +	case RENDER_CLASS:
> +		switch (INTEL_GEN(dev_priv)) {
> +		default:
> +			MISSING_CASE(INTEL_GEN(dev_priv));
> +		case 9:
>  			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
> -		else
> +			break;
> +		case 8:
>  			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
> +			break;
> +		}
>  		break;
> -	case VCS:
> -	case BCS:
> -	case VECS:
> -	case VCS2:
> +	case VIDEO_DECODE_CLASS:
> +	case VIDEO_ENHANCEMENT_CLASS:
> +	case COPY_ENGINE_CLASS:
>  		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
>  		break;
> +	default:
> +		MISSING_CASE(class);
>  	}
>  
>  	return ret;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index e8015e7..bde2b6e 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -78,7 +78,11 @@ enum {
>  struct drm_i915_private;
>  struct i915_gem_context;
>  
> -uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
> +uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv, u8 class);
> +static inline uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
> +{
> +	return intel_lr_class_context_size(engine->i915, engine->class);
> +}

I'm not understanding why you want to push this to the caller.

Patches 1-4 are r-b me, and I'll apply once we have put out the fire.
-Chris

-- 
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[PATCH 5/5] drm/i915: Use the engine class to get the context size

[Oscar Mateo]

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Technically speaking, the context size is per engine class, not per
instance.

v2: Add MISSING_CASE (Tvrtko)

v3: Rebased

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 33 +++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_lrc.h |  6 +++++-
 2 files changed, 26 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0dc1cc4..1c6672c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1908,8 +1908,10 @@ static void execlists_init_reg_state(u32 *regs,
 }
 
 /**
- * intel_lr_context_size() - return the size of the context for an engine
- * @engine: which engine to find the context size for
+ * intel_lr_class_context_size() - return the size of the context for a given
+ * engine class
+ * @dev_priv: i915 device private
+ * @class: which engine class to find the context size for
  *
  * Each engine may require a different amount of space for a context image,
  * so when allocating (or copying) an image, this function can be used to
@@ -1921,25 +1923,32 @@ static void execlists_init_reg_state(u32 *regs,
  * in LRC mode, but does not include the "shared data page" used with
  * GuC submission. The caller should account for this if using the GuC.
  */
-uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
+uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv, u8 class)
 {
 	int ret = 0;
 
-	WARN_ON(INTEL_GEN(engine->i915) < 8);
+	WARN_ON(INTEL_GEN(dev_priv) < 8);
 
-	switch (engine->id) {
-	case RCS:
-		if (INTEL_GEN(engine->i915) >= 9)
+	switch (class) {
+	case RENDER_CLASS:
+		switch (INTEL_GEN(dev_priv)) {
+		default:
+			MISSING_CASE(INTEL_GEN(dev_priv));
+		case 9:
 			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
-		else
+			break;
+		case 8:
 			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
+			break;
+		}
 		break;
-	case VCS:
-	case BCS:
-	case VECS:
-	case VCS2:
+	case VIDEO_DECODE_CLASS:
+	case VIDEO_ENHANCEMENT_CLASS:
+	case COPY_ENGINE_CLASS:
 		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
 		break;
+	default:
+		MISSING_CASE(class);
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index e8015e7..bde2b6e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -78,7 +78,11 @@ enum {
 struct drm_i915_private;
 struct i915_gem_context;
 
-uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
+uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv, u8 class);
+static inline uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
+{
+	return intel_lr_class_context_size(engine->i915, engine->class);
+}
 
 void intel_lr_context_resume(struct drm_i915_private *dev_priv);
 uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
-- 
1.9.1

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[PATCH 5/5] drm/i915: Use the engine class to get the context size

[Oscar Mateo]

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Technically speaking, the context size is per engine class, not per
instance.

v2: Add MISSING_CASE (Tvrtko)

v3: Rebased

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 33 +++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_lrc.h |  6 +++++-
 2 files changed, 26 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0dc1cc4..1c6672c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1908,8 +1908,10 @@ static void execlists_init_reg_state(u32 *regs,
 }
 
 /**
- * intel_lr_context_size() - return the size of the context for an engine
- * @engine: which engine to find the context size for
+ * intel_lr_class_context_size() - return the size of the context for a given
+ * engine class
+ * @dev_priv: i915 device private
+ * @class: which engine class to find the context size for
  *
  * Each engine may require a different amount of space for a context image,
  * so when allocating (or copying) an image, this function can be used to
@@ -1921,25 +1923,32 @@ static void execlists_init_reg_state(u32 *regs,
  * in LRC mode, but does not include the "shared data page" used with
  * GuC submission. The caller should account for this if using the GuC.
  */
-uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
+uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv, u8 class)
 {
 	int ret = 0;
 
-	WARN_ON(INTEL_GEN(engine->i915) < 8);
+	WARN_ON(INTEL_GEN(dev_priv) < 8);
 
-	switch (engine->id) {
-	case RCS:
-		if (INTEL_GEN(engine->i915) >= 9)
+	switch (class) {
+	case RENDER_CLASS:
+		switch (INTEL_GEN(dev_priv)) {
+		default:
+			MISSING_CASE(INTEL_GEN(dev_priv));
+		case 9:
 			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
-		else
+			break;
+		case 8:
 			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
+			break;
+		}
 		break;
-	case VCS:
-	case BCS:
-	case VECS:
-	case VCS2:
+	case VIDEO_DECODE_CLASS:
+	case VIDEO_ENHANCEMENT_CLASS:
+	case COPY_ENGINE_CLASS:
 		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
 		break;
+	default:
+		MISSING_CASE(class);
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index e8015e7..bde2b6e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -78,7 +78,11 @@ enum {
 struct drm_i915_private;
 struct i915_gem_context;
 
-uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
+uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv, u8 class);
+static inline uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
+{
+	return intel_lr_class_context_size(engine->i915, engine->class);
+}
 
 void intel_lr_context_resume(struct drm_i915_private *dev_priv);
 uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
-- 
1.9.1

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Re: [PATCH 5/5] drm/i915: Use the engine class to get the context size

[Tvrtko Ursulin]

On 05/04/2017 10:30, Oscar Mateo wrote:
> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>
> Technically speaking, the context size is per engine class, not per
> instance.

It is very nice to have the code match the documentation!

> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 34 ++++++++++++++++++++++------------
>  drivers/gpu/drm/i915/intel_lrc.h |  7 ++++++-
>  2 files changed, 28 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 0dc1cc4..6b1fc4a 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1908,8 +1908,10 @@ static void execlists_init_reg_state(u32 *regs,
>  }
>
>  /**
> - * intel_lr_context_size() - return the size of the context for an engine
> - * @engine: which engine to find the context size for
> + * intel_lr_class_context_size() - return the size of the context for a given
> + * engine class
> + * @dev_priv: i915 device private
> + * @class: which engine class to find the context size for
>   *
>   * Each engine may require a different amount of space for a context image,
>   * so when allocating (or copying) an image, this function can be used to
> @@ -1921,25 +1923,33 @@ static void execlists_init_reg_state(u32 *regs,
>   * in LRC mode, but does not include the "shared data page" used with
>   * GuC submission. The caller should account for this if using the GuC.
>   */
> -uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
> +uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv,
> +				     enum intel_engine_class class)
>  {
>  	int ret = 0;
>
> -	WARN_ON(INTEL_GEN(engine->i915) < 8);
> +	WARN_ON(INTEL_GEN(dev_priv) < 8);
>
> -	switch (engine->id) {
> -	case RCS:
> -		if (INTEL_GEN(engine->i915) >= 9)
> +	switch (class) {
> +	case RENDER_CLASS:
> +		switch (INTEL_GEN(dev_priv)) {
> +		default:
> +			DRM_ERROR("Unknown context size for GEN\n");

MISSING_CASE I think, otherwise it is too easy to miss in the noise. And 
it is MISSING_CASE for the class below which looks appropriate to me for 
this layer.

> +		case 9:
>  			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
> -		else
> +			break;
> +		case 8:
>  			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
> +			break;
> +		}
>  		break;
> -	case VCS:
> -	case BCS:
> -	case VECS:
> -	case VCS2:
> +	case VIDEO_DECODE_CLASS:
> +	case VIDEO_ENHANCEMENT_CLASS:
> +	case COPY_ENGINE_CLASS:
>  		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
>  		break;
> +	default:
> +		MISSING_CASE(class);
>  	}
>
>  	return ret;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index e8015e7..b3a4331 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -78,7 +78,12 @@ enum {
>  struct drm_i915_private;
>  struct i915_gem_context;
>
> -uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
> +uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv,
> +				     enum intel_engine_class class);
> +static inline uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
> +{
> +	return intel_lr_class_context_size(engine->i915, engine->class);
> +}
>
>  void intel_lr_context_resume(struct drm_i915_private *dev_priv);
>  uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
>

Otherwise looks fine to me. I also really hope to be able to use the 
class/instance cleanup in scope of the better VCS load balancing which 
is currently being looked at.

Regards,

Tvrtko
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[PATCH 5/5] drm/i915: Use the engine class to get the context size

[Oscar Mateo]

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Technically speaking, the context size is per engine class, not per
instance.

v2: Add MISSING_CASE (Tvrtko)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 34 ++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_lrc.h |  7 ++++++-
 2 files changed, 28 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0dc1cc4..c8abf89 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1908,8 +1908,10 @@ static void execlists_init_reg_state(u32 *regs,
 }
 
 /**
- * intel_lr_context_size() - return the size of the context for an engine
- * @engine: which engine to find the context size for
+ * intel_lr_class_context_size() - return the size of the context for a given
+ * engine class
+ * @dev_priv: i915 device private
+ * @class: which engine class to find the context size for
  *
  * Each engine may require a different amount of space for a context image,
  * so when allocating (or copying) an image, this function can be used to
@@ -1921,25 +1923,33 @@ static void execlists_init_reg_state(u32 *regs,
  * in LRC mode, but does not include the "shared data page" used with
  * GuC submission. The caller should account for this if using the GuC.
  */
-uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
+uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv,
+				     enum intel_engine_class class)
 {
 	int ret = 0;
 
-	WARN_ON(INTEL_GEN(engine->i915) < 8);
+	WARN_ON(INTEL_GEN(dev_priv) < 8);
 
-	switch (engine->id) {
-	case RCS:
-		if (INTEL_GEN(engine->i915) >= 9)
+	switch (class) {
+	case RENDER_CLASS:
+		switch (INTEL_GEN(dev_priv)) {
+		default:
+			MISSING_CASE(INTEL_GEN(dev_priv));
+		case 9:
 			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
-		else
+			break;
+		case 8:
 			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
+			break;
+		}
 		break;
-	case VCS:
-	case BCS:
-	case VECS:
-	case VCS2:
+	case VIDEO_DECODE_CLASS:
+	case VIDEO_ENHANCEMENT_CLASS:
+	case COPY_ENGINE_CLASS:
 		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
 		break;
+	default:
+		MISSING_CASE(class);
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index e8015e7..b3a4331 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -78,7 +78,12 @@ enum {
 struct drm_i915_private;
 struct i915_gem_context;
 
-uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
+uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv,
+				     enum intel_engine_class class);
+static inline uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
+{
+	return intel_lr_class_context_size(engine->i915, engine->class);
+}
 
 void intel_lr_context_resume(struct drm_i915_private *dev_priv);
 uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
-- 
1.9.1

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[PATCH 5/5] drm/i915: Use the engine class to get the context size

[Oscar Mateo]

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Technically speaking, the context size is per engine class, not per
instance.

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 34 ++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_lrc.h |  7 ++++++-
 2 files changed, 28 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0dc1cc4..6b1fc4a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1908,8 +1908,10 @@ static void execlists_init_reg_state(u32 *regs,
 }
 
 /**
- * intel_lr_context_size() - return the size of the context for an engine
- * @engine: which engine to find the context size for
+ * intel_lr_class_context_size() - return the size of the context for a given
+ * engine class
+ * @dev_priv: i915 device private
+ * @class: which engine class to find the context size for
  *
  * Each engine may require a different amount of space for a context image,
  * so when allocating (or copying) an image, this function can be used to
@@ -1921,25 +1923,33 @@ static void execlists_init_reg_state(u32 *regs,
  * in LRC mode, but does not include the "shared data page" used with
  * GuC submission. The caller should account for this if using the GuC.
  */
-uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
+uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv,
+				     enum intel_engine_class class)
 {
 	int ret = 0;
 
-	WARN_ON(INTEL_GEN(engine->i915) < 8);
+	WARN_ON(INTEL_GEN(dev_priv) < 8);
 
-	switch (engine->id) {
-	case RCS:
-		if (INTEL_GEN(engine->i915) >= 9)
+	switch (class) {
+	case RENDER_CLASS:
+		switch (INTEL_GEN(dev_priv)) {
+		default:
+			DRM_ERROR("Unknown context size for GEN\n");
+		case 9:
 			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
-		else
+			break;
+		case 8:
 			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
+			break;
+		}
 		break;
-	case VCS:
-	case BCS:
-	case VECS:
-	case VCS2:
+	case VIDEO_DECODE_CLASS:
+	case VIDEO_ENHANCEMENT_CLASS:
+	case COPY_ENGINE_CLASS:
 		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
 		break;
+	default:
+		MISSING_CASE(class);
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index e8015e7..b3a4331 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -78,7 +78,12 @@ enum {
 struct drm_i915_private;
 struct i915_gem_context;
 
-uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
+uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv,
+				     enum intel_engine_class class);
+static inline uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
+{
+	return intel_lr_class_context_size(engine->i915, engine->class);
+}
 
 void intel_lr_context_resume(struct drm_i915_private *dev_priv);
 uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
-- 
1.9.1

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