From: Laxman Dewangan <ldewangan@nvidia.com> To: thierry.reding@gmail.com, robh+dt@kernel.org, jonathanh@nvidia.com Cc: mark.rutland@arm.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Laxman Dewangan <ldewangan@nvidia.com> Subject: [PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume Date: Fri, 7 Apr 2017 15:04:01 +0530 [thread overview] Message-ID: <1491557642-15940-4-git-send-email-ldewangan@nvidia.com> (raw) In-Reply-To: <1491557642-15940-1-git-send-email-ldewangan@nvidia.com> In some of NVIDIA Tegra's platform, PWM controller is used to control the PWM controlled regulators. PWM signal is connected to the VID pin of the regulator where duty cycle of PWM signal decide the voltage level of the regulator output. When system enters suspend, some PWM client/slave regulator devices require the PWM output to be tristated. Add DT binding details to provide the pin configuration state from PWM and pinctrl DT node in suspend and active state of the system. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> --- Changes from v1: - Use standard pinctrl names for sleep and active state. Changes from V2: - Fix the commit message and details --- .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index b4e7377..c57e11b 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt @@ -19,6 +19,19 @@ Required properties: - reset-names: Must include the following entries: - pwm +Optional properties: +============================ +In some of the interface like PWM based regulator device, it is required +to configure the pins differently in different states, especially in suspend +state of the system. The configuration of pin is provided via the pinctrl +DT node as detailed in the pinctrl DT binding document + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +The PWM node will have following optional properties. +pinctrl-names: Pin state names. Must be "default" and "sleep". +pinctrl-0: phandle for the default/active state of pin configurations. +pinctrl-1: phandle for the sleep state of pin configurations. + Example: pwm: pwm@7000a000 { @@ -29,3 +42,35 @@ Example: resets = <&tegra_car 17>; reset-names = "pwm"; }; + + +Example with the pin configuration for suspend and resume: +========================================================= +Suppose pin PE7 (On Tegra210) interfaced with the regulator device and +it requires PWM output to be tristated when system enters suspend. +Following will be DT binding to achieve this: + +#include <dt-bindings/pinctrl/pinctrl-tegra.h> + + pinmux@700008d4 { + pwm_active_state: pwm_active_state { + pe7 { + nvidia,pins = "pe7"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + }; + + pwm_sleep_state: pwm_sleep_state { + pe7 { + nvidia,pins = "pe7"; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + }; + }; + + pwm@7000a000 { + /* Mandatory PWM properties */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm_active_state>; + pinctrl-1 = <&pwm_sleep_state>; + }; -- 2.1.4
WARNING: multiple messages have this Message-ID (diff)
From: Laxman Dewangan <ldewangan@nvidia.com> To: <thierry.reding@gmail.com>, <robh+dt@kernel.org>, <jonathanh@nvidia.com> Cc: <mark.rutland@arm.com>, <linux-pwm@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Laxman Dewangan <ldewangan@nvidia.com> Subject: [PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume Date: Fri, 7 Apr 2017 15:04:01 +0530 [thread overview] Message-ID: <1491557642-15940-4-git-send-email-ldewangan@nvidia.com> (raw) In-Reply-To: <1491557642-15940-1-git-send-email-ldewangan@nvidia.com> In some of NVIDIA Tegra's platform, PWM controller is used to control the PWM controlled regulators. PWM signal is connected to the VID pin of the regulator where duty cycle of PWM signal decide the voltage level of the regulator output. When system enters suspend, some PWM client/slave regulator devices require the PWM output to be tristated. Add DT binding details to provide the pin configuration state from PWM and pinctrl DT node in suspend and active state of the system. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> --- Changes from v1: - Use standard pinctrl names for sleep and active state. Changes from V2: - Fix the commit message and details --- .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index b4e7377..c57e11b 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt @@ -19,6 +19,19 @@ Required properties: - reset-names: Must include the following entries: - pwm +Optional properties: +============================ +In some of the interface like PWM based regulator device, it is required +to configure the pins differently in different states, especially in suspend +state of the system. The configuration of pin is provided via the pinctrl +DT node as detailed in the pinctrl DT binding document + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +The PWM node will have following optional properties. +pinctrl-names: Pin state names. Must be "default" and "sleep". +pinctrl-0: phandle for the default/active state of pin configurations. +pinctrl-1: phandle for the sleep state of pin configurations. + Example: pwm: pwm@7000a000 { @@ -29,3 +42,35 @@ Example: resets = <&tegra_car 17>; reset-names = "pwm"; }; + + +Example with the pin configuration for suspend and resume: +========================================================= +Suppose pin PE7 (On Tegra210) interfaced with the regulator device and +it requires PWM output to be tristated when system enters suspend. +Following will be DT binding to achieve this: + +#include <dt-bindings/pinctrl/pinctrl-tegra.h> + + pinmux@700008d4 { + pwm_active_state: pwm_active_state { + pe7 { + nvidia,pins = "pe7"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + }; + + pwm_sleep_state: pwm_sleep_state { + pe7 { + nvidia,pins = "pe7"; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + }; + }; + + pwm@7000a000 { + /* Mandatory PWM properties */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm_active_state>; + pinctrl-1 = <&pwm_sleep_state>; + }; -- 2.1.4
next prev parent reply other threads:[~2017-04-07 9:34 UTC|newest] Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-04-07 9:33 [PATCH V3 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups Laxman Dewangan 2017-04-07 9:33 ` Laxman Dewangan 2017-04-07 9:34 ` Laxman Dewangan [this message] 2017-04-07 9:34 ` [PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume Laxman Dewangan [not found] ` <1491557642-15940-4-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2017-04-07 10:25 ` Jon Hunter 2017-04-07 10:25 ` Jon Hunter 2017-04-10 20:13 ` Rob Herring [not found] ` <1491557642-15940-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2017-04-07 9:33 ` [PATCH V3 1/4] pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation Laxman Dewangan 2017-04-07 9:33 ` Laxman Dewangan 2017-04-07 9:34 ` [PATCH V3 2/4] pwm: tegra: Increase precision in pwm rate calculation Laxman Dewangan 2017-04-07 9:34 ` Laxman Dewangan [not found] ` <1491557642-15940-3-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2017-04-12 17:19 ` Thierry Reding 2017-04-12 17:19 ` Thierry Reding 2017-04-07 9:34 ` [PATCH V3 4/4] pwm: tegra: Add support to configure pin state in suspends/resume Laxman Dewangan 2017-04-07 9:34 ` Laxman Dewangan [not found] ` <1491557642-15940-5-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2017-04-07 10:27 ` Jon Hunter 2017-04-07 10:27 ` Jon Hunter 2017-04-12 17:18 ` [PATCH V3 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups Thierry Reding 2017-04-12 17:18 ` Thierry Reding -- strict thread matches above, loose matches on Subject: below -- 2017-04-06 14:20 [PATCH V2 " Laxman Dewangan [not found] ` <1491488461-24621-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2017-04-06 14:21 ` [PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume Laxman Dewangan 2017-04-06 14:21 ` Laxman Dewangan 2017-04-06 15:26 ` Jon Hunter 2017-04-06 15:26 ` Jon Hunter [not found] ` <f43c83a9-8ae0-73b0-d41d-97d3bc6c253e-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2017-04-06 16:48 ` Laxman Dewangan 2017-04-06 16:48 ` Laxman Dewangan [not found] ` <58E67152.1080400-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2017-04-07 7:49 ` Jon Hunter 2017-04-07 7:49 ` Jon Hunter
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