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From: Jon Hunter <jonathanh@nvidia.com>
To: Laxman Dewangan <ldewangan@nvidia.com>,
	thierry.reding@gmail.com, robh+dt@kernel.org
Cc: mark.rutland@arm.com, linux-pwm@vger.kernel.org,
	devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume
Date: Thu, 6 Apr 2017 16:26:16 +0100	[thread overview]
Message-ID: <f43c83a9-8ae0-73b0-d41d-97d3bc6c253e@nvidia.com> (raw)
In-Reply-To: <1491488461-24621-4-git-send-email-ldewangan@nvidia.com>


On 06/04/17 15:21, Laxman Dewangan wrote:
> In some of NVIDIA Tegra's platform, PWM controller is used to
> control the PWM controlled regulators. PWM signal is connected to
> the VID pin of the regulator where duty cycle of PWM signal decide
> the voltage level of the regulator output.
> 
> The tristate (high impedance of PWM pin form Tegra) also define

s/form/from/
s/define/defines/

> one of the state of PWM regulator which needs to be configure in
> suspend state of system.

It maybe clearer to say that when the system enters suspend the
regulator requires the pwm output to be tristated.

> Add DT binding details to provide the pin configuration state
> from PWM and pinctrl DT node in suspend and active state of
> the system.
> 
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> ---
> Changes from v1:
> - Use standard pinctrl names for sleep and active state.
> 
>  .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 43 ++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> index b4e7377..4128cdc 100644
> --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> @@ -19,6 +19,19 @@ Required properties:
>  - reset-names: Must include the following entries:
>    - pwm
>  
> +Optional properties:
> +============================
> +In some of the interface like PWM based regulator device, it is required
> +to configure the pins differently in different states, especially in suspend
> +state of the system. The configuration of pin is provided via the pinctrl
> +DT node as detailed in the pinctrl DT binding document
> +	Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> +
> +The PWM node will have following optional properties.
> +pinctrl-names:	Pin state names. Must be "default" and "sleep".
> +pinctrl-0:	Node handle for the default/active state of pi configurations.

s/pi/pin/
s/Node handle/phandle/

> +pinctrl-1:	Node handle for the sleep state of pin configurations.
> +
>  Example:
>  
>  	pwm: pwm@7000a000 {
> @@ -29,3 +42,33 @@ Example:
>  		resets = <&tegra_car 17>;
>  		reset-names = "pwm";
>  	};
> +
> +
> +Example with the pin configuration for suspend and resume:
> +=========================================================
> +Pin PE7 is used as PWM interface.

Nit-pick. On what devices? Sounds like this is verbatim. Maybe state
what device this is an example for.

Jon

-- 
nvpublic

WARNING: multiple messages have this Message-ID (diff)
From: Jon Hunter <jonathanh@nvidia.com>
To: Laxman Dewangan <ldewangan@nvidia.com>,
	<thierry.reding@gmail.com>, <robh+dt@kernel.org>
Cc: <mark.rutland@arm.com>, <linux-pwm@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume
Date: Thu, 6 Apr 2017 16:26:16 +0100	[thread overview]
Message-ID: <f43c83a9-8ae0-73b0-d41d-97d3bc6c253e@nvidia.com> (raw)
In-Reply-To: <1491488461-24621-4-git-send-email-ldewangan@nvidia.com>


On 06/04/17 15:21, Laxman Dewangan wrote:
> In some of NVIDIA Tegra's platform, PWM controller is used to
> control the PWM controlled regulators. PWM signal is connected to
> the VID pin of the regulator where duty cycle of PWM signal decide
> the voltage level of the regulator output.
> 
> The tristate (high impedance of PWM pin form Tegra) also define

s/form/from/
s/define/defines/

> one of the state of PWM regulator which needs to be configure in
> suspend state of system.

It maybe clearer to say that when the system enters suspend the
regulator requires the pwm output to be tristated.

> Add DT binding details to provide the pin configuration state
> from PWM and pinctrl DT node in suspend and active state of
> the system.
> 
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> ---
> Changes from v1:
> - Use standard pinctrl names for sleep and active state.
> 
>  .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 43 ++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> index b4e7377..4128cdc 100644
> --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> @@ -19,6 +19,19 @@ Required properties:
>  - reset-names: Must include the following entries:
>    - pwm
>  
> +Optional properties:
> +============================
> +In some of the interface like PWM based regulator device, it is required
> +to configure the pins differently in different states, especially in suspend
> +state of the system. The configuration of pin is provided via the pinctrl
> +DT node as detailed in the pinctrl DT binding document
> +	Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> +
> +The PWM node will have following optional properties.
> +pinctrl-names:	Pin state names. Must be "default" and "sleep".
> +pinctrl-0:	Node handle for the default/active state of pi configurations.

s/pi/pin/
s/Node handle/phandle/

> +pinctrl-1:	Node handle for the sleep state of pin configurations.
> +
>  Example:
>  
>  	pwm: pwm@7000a000 {
> @@ -29,3 +42,33 @@ Example:
>  		resets = <&tegra_car 17>;
>  		reset-names = "pwm";
>  	};
> +
> +
> +Example with the pin configuration for suspend and resume:
> +=========================================================
> +Pin PE7 is used as PWM interface.

Nit-pick. On what devices? Sounds like this is verbatim. Maybe state
what device this is an example for.

Jon

-- 
nvpublic

  reply	other threads:[~2017-04-06 15:26 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-06 14:20 [PATCH V2 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups Laxman Dewangan
2017-04-06 14:20 ` Laxman Dewangan
2017-04-06 14:20 ` [PATCH V2 2/4] pwm: tegra: Increase precision in pwm rate calculation Laxman Dewangan
2017-04-06 14:20   ` Laxman Dewangan
     [not found]   ` <1491488461-24621-3-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-04-06 16:24     ` Thierry Reding
2017-04-06 16:24       ` Thierry Reding
2017-04-06 17:03       ` Laxman Dewangan
2017-04-06 16:28     ` Thierry Reding
2017-04-06 16:28       ` Thierry Reding
     [not found] ` <1491488461-24621-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-04-06 14:20   ` [PATCH V2 1/4] pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation Laxman Dewangan
2017-04-06 14:20     ` Laxman Dewangan
2017-04-06 16:28     ` Thierry Reding
2017-04-06 14:21   ` [PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume Laxman Dewangan
2017-04-06 14:21     ` Laxman Dewangan
2017-04-06 15:26     ` Jon Hunter [this message]
2017-04-06 15:26       ` Jon Hunter
     [not found]       ` <f43c83a9-8ae0-73b0-d41d-97d3bc6c253e-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-04-06 16:48         ` Laxman Dewangan
2017-04-06 16:48           ` Laxman Dewangan
     [not found]           ` <58E67152.1080400-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-04-07  7:49             ` Jon Hunter
2017-04-07  7:49               ` Jon Hunter
2017-04-06 14:21   ` [PATCH V4 4/4] pwm: tegra: Add support to configure pin state " Laxman Dewangan
2017-04-06 14:21     ` Laxman Dewangan
2017-04-06 15:17     ` Jon Hunter
2017-04-06 15:17       ` Jon Hunter
2017-04-06 16:40       ` Laxman Dewangan
2017-04-06 16:40         ` Laxman Dewangan
     [not found]         ` <58E66F8F.1030802-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-04-07  7:51           ` Jon Hunter
2017-04-07  7:51             ` Jon Hunter
2017-04-07  9:33 [PATCH V3 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups Laxman Dewangan
2017-04-07  9:34 ` [PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume Laxman Dewangan
2017-04-07  9:34   ` Laxman Dewangan
     [not found]   ` <1491557642-15940-4-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-04-07 10:25     ` Jon Hunter
2017-04-07 10:25       ` Jon Hunter
2017-04-10 20:13   ` Rob Herring

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