[PATCH linux dev-4.10 0/3] aspeed-g4: Enable mbox and lpc devices

[PATCH linux dev-4.10 0/3] aspeed-g4: Enable mbox and lpc devices

[Andrew Jeffery]

Hello,

This series is a small piece of enablement work for mboxd on P8, as requested
by Adriana. The first patch is a cherry-pick of the upstream equivalent, which
appeared to have been missed in the pinctrl chaos.

The remaining two patches simply copy the g5 LPC nodes into the g4, switch the
compatible strings, then enable the nodes (and reserve a small amount of
memory).

Please review.

Cheers,

Andrew

Andrew Jeffery (3):
  mfd: dt: Add Aspeed Low Pin Count Controller bindings
  arm: aspeed: Add LPC devicetree node and children
  arm: aspeed: Configure mbox and lpc nodes on Palmetto

 .../devicetree/bindings/mfd/aspeed-lpc.txt         | 111 +++++++++++++++++++++
 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts      |  15 +++
 arch/arm/boot/dts/aspeed-g4.dtsi                   |  38 +++++++
 3 files changed, 164 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt

-- 
2.11.0

[PATCH linux dev-4.10 1/3] mfd: dt: Add Aspeed Low Pin Count Controller bindings

[Andrew Jeffery]

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
(cherry picked from commit 3bca0e552f693a7d815d24d8fda1196f2c668074)
---
 .../devicetree/bindings/mfd/aspeed-lpc.txt         | 111 +++++++++++++++++++++
 1 file changed, 111 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt

diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
new file mode 100644
index 000000000000..a97131aba446
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
@@ -0,0 +1,111 @@
+======================================================================
+Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
+======================================================================
+
+The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
+peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
+primary use case of the Aspeed LPC controller is as a slave on the bus
+(typically in a Baseboard Management Controller SoC), but under certain
+conditions it can also take the role of bus master.
+
+The LPC controller is represented as a multi-function device to account for the
+mix of functionality it provides. The principle split is between the register
+layout at the start of the I/O space which is, to quote the Aspeed datasheet,
+"basically compatible with the [LPC registers from the] popular BMC controller
+H8S/2168[1]", and everything else, where everything else is an eclectic
+collection of functions with a esoteric register layout. "Everything else",
+here labeled the "host" portion of the controller, includes, but is not limited
+to:
+
+* An IPMI Block Transfer[2] Controller
+
+* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
+  physical properties of some LPC pins, configuration of serial IRQs, and
+  APB-to-LPC bridging amonst other functions.
+
+* An LPC Host Interface Controller: Manages functions exposed to the host such
+  as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
+  management and bus snoop configuration.
+
+* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
+  hardware management protocols for handover between the host and baseboard
+  management controller.
+
+Additionally the state of the LPC controller influences the pinmux
+configuration, therefore the host portion of the controller is exposed as a
+syscon as a means to arbitrate access.
+
+[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
+[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
+[2] http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
+[3] https://en.wikipedia.org/wiki/Super_I/O
+
+Required properties
+===================
+
+- compatible:	One of:
+		"aspeed,ast2400-lpc", "simple-mfd"
+		"aspeed,ast2500-lpc", "simple-mfd"
+
+- reg:		contains the physical address and length values of the Aspeed
+                LPC memory region.
+
+- #address-cells: <1>
+- #size-cells:	<1>
+- ranges: 	Maps 0 to the physical address and length of the LPC memory
+                region
+
+Required LPC Child nodes
+========================
+
+BMC Node
+--------
+
+- compatible:	One of:
+		"aspeed,ast2400-lpc-bmc"
+		"aspeed,ast2500-lpc-bmc"
+
+- reg:		contains the physical address and length values of the
+                H8S/2168-compatible LPC controller memory region
+
+Host Node
+---------
+
+- compatible:   One of:
+		"aspeed,ast2400-lpc-host", "simple-mfd", "syscon"
+		"aspeed,ast2500-lpc-host", "simple-mfd", "syscon"
+
+- reg:		contains the address and length values of the host-related
+                register space for the Aspeed LPC controller
+
+- #address-cells: <1>
+- #size-cells:	<1>
+- ranges: 	Maps 0 to the address and length of the host-related LPC memory
+                region
+
+Example:
+
+lpc: lpc@1e789000 {
+	compatible = "aspeed,ast2500-lpc", "simple-mfd";
+	reg = <0x1e789000 0x1000>;
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x0 0x1e789000 0x1000>;
+
+	lpc_bmc: lpc-bmc@0 {
+		compatible = "aspeed,ast2500-lpc-bmc";
+		reg = <0x0 0x80>;
+	};
+
+	lpc_host: lpc-host@80 {
+		compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
+		reg = <0x80 0x1e0>;
+		reg-io-width = <4>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x80 0x1e0>;
+	};
+};
+
-- 
2.11.0

[PATCH linux dev-4.10 2/3] arm: aspeed: Add LPC devicetree node and children

[Andrew Jeffery]

This is enablement for mbox protocol support on P8. Expose
/dev/aspeed-lpc-ctrl and /dev/aspeed-mbox for use by mboxd.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 arch/arm/boot/dts/aspeed-g4.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 9b0291061925..a998a00a2728 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -78,6 +78,44 @@
 			};
 		};
 
+		lpc: lpc@1e789000 {
+			compatible = "aspeed,ast2400-lpc", "simple-mfd";
+			reg = <0x1e789000 0x1000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x1e789000 0x1000>;
+
+			lpc_bmc: lpc-bmc@0 {
+				compatible = "aspeed,ast2400-lpc-bmc";
+				reg = <0x0 0x80>;
+			};
+
+			lpc_host: lpc-host@80 {
+				compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
+				reg = <0x80 0x1e0>;
+				reg-io-width = <4>;
+
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0x80 0x1e0>;
+
+				lpc_ctrl: lpc-ctrl@0 {
+					compatible = "aspeed,ast2400-lpc-ctrl";
+					reg = <0x0 0x80>;
+					status = "disabled";
+				};
+
+				mbox: mbox@180 {
+					compatible = "aspeed,ast2400-mbox";
+					reg = <0x180 0x5c>;
+					interrupts = <46>;
+					#mbox-cells = <1>;
+					status = "disabled";
+				};
+			};
+		};
+
 		vic: interrupt-controller@1e6c0080 {
 			compatible = "aspeed,ast2400-vic";
 			interrupt-controller;
-- 
2.11.0

[PATCH linux dev-4.10 3/3] arm: aspeed: Configure mbox and lpc nodes on Palmetto

[Andrew Jeffery]

Assign 16MB of reserved memory for mboxd to make use of via the
aspeed-lpc-ctrl device.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index 60792f6ff7ec..8ebed01e7725 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -29,6 +29,11 @@
 			no-map;
 			reg = <0x5f000000 0x01000000>; /* 16MB */
 		};
+
+		flash_memory: region@98000000 {
+			no-map;
+			reg = <0x98000000 0x01000000>; /* 16MB */
+		};
 	};
 
         leds {
@@ -309,3 +314,13 @@
 &vuart {
 	status = "okay";
 };
+
+&lpc_ctrl {
+	status = "okay";
+	memory-region = <&flash_memory>;
+	flash = <&spi>;
+};
+
+&mbox {
+	status = "okay";
+};
-- 
2.11.0

Re: [PATCH linux dev-4.10 0/3] aspeed-g4: Enable mbox and lpc devices

[Joel Stanley]

On Fri, Jun 2, 2017 at 5:58 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
> Hello,
>
> This series is a small piece of enablement work for mboxd on P8, as requested
> by Adriana. The first patch is a cherry-pick of the upstream equivalent, which
> appeared to have been missed in the pinctrl chaos.
>
> The remaining two patches simply copy the g5 LPC nodes into the g4, switch the
> compatible strings, then enable the nodes (and reserve a small amount of
> memory).
>

Thanks, applied to dev-4.10.

Cheers,

Joel

Re: [PATCH linux dev-4.10 1/3] mfd: dt: Add Aspeed Low Pin Count Controller bindings

[Lee Jones]

On Fri, 02 Jun 2017, Andrew Jeffery wrote:

> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Lee Jones <lee.jones@linaro.org>
> (cherry picked from commit 3bca0e552f693a7d815d24d8fda1196f2c668074)

What is this patch for?  What's the intention?

> ---
>  .../devicetree/bindings/mfd/aspeed-lpc.txt         | 111 +++++++++++++++++++++
>  1 file changed, 111 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> 
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> new file mode 100644
> index 000000000000..a97131aba446
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> @@ -0,0 +1,111 @@
> +======================================================================
> +Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
> +======================================================================
> +
> +The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
> +peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
> +primary use case of the Aspeed LPC controller is as a slave on the bus
> +(typically in a Baseboard Management Controller SoC), but under certain
> +conditions it can also take the role of bus master.
> +
> +The LPC controller is represented as a multi-function device to account for the
> +mix of functionality it provides. The principle split is between the register
> +layout at the start of the I/O space which is, to quote the Aspeed datasheet,
> +"basically compatible with the [LPC registers from the] popular BMC controller
> +H8S/2168[1]", and everything else, where everything else is an eclectic
> +collection of functions with a esoteric register layout. "Everything else",
> +here labeled the "host" portion of the controller, includes, but is not limited
> +to:
> +
> +* An IPMI Block Transfer[2] Controller
> +
> +* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
> +  physical properties of some LPC pins, configuration of serial IRQs, and
> +  APB-to-LPC bridging amonst other functions.
> +
> +* An LPC Host Interface Controller: Manages functions exposed to the host such
> +  as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
> +  management and bus snoop configuration.
> +
> +* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
> +  hardware management protocols for handover between the host and baseboard
> +  management controller.
> +
> +Additionally the state of the LPC controller influences the pinmux
> +configuration, therefore the host portion of the controller is exposed as a
> +syscon as a means to arbitrate access.
> +
> +[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
> +[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
> +[2] http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
> +[3] https://en.wikipedia.org/wiki/Super_I/O
> +
> +Required properties
> +===================
> +
> +- compatible:	One of:
> +		"aspeed,ast2400-lpc", "simple-mfd"
> +		"aspeed,ast2500-lpc", "simple-mfd"
> +
> +- reg:		contains the physical address and length values of the Aspeed
> +                LPC memory region.
> +
> +- #address-cells: <1>
> +- #size-cells:	<1>
> +- ranges: 	Maps 0 to the physical address and length of the LPC memory
> +                region
> +
> +Required LPC Child nodes
> +========================
> +
> +BMC Node
> +--------
> +
> +- compatible:	One of:
> +		"aspeed,ast2400-lpc-bmc"
> +		"aspeed,ast2500-lpc-bmc"
> +
> +- reg:		contains the physical address and length values of the
> +                H8S/2168-compatible LPC controller memory region
> +
> +Host Node
> +---------
> +
> +- compatible:   One of:
> +		"aspeed,ast2400-lpc-host", "simple-mfd", "syscon"
> +		"aspeed,ast2500-lpc-host", "simple-mfd", "syscon"
> +
> +- reg:		contains the address and length values of the host-related
> +                register space for the Aspeed LPC controller
> +
> +- #address-cells: <1>
> +- #size-cells:	<1>
> +- ranges: 	Maps 0 to the address and length of the host-related LPC memory
> +                region
> +
> +Example:
> +
> +lpc: lpc@1e789000 {
> +	compatible = "aspeed,ast2500-lpc", "simple-mfd";
> +	reg = <0x1e789000 0x1000>;
> +
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	ranges = <0x0 0x1e789000 0x1000>;
> +
> +	lpc_bmc: lpc-bmc@0 {
> +		compatible = "aspeed,ast2500-lpc-bmc";
> +		reg = <0x0 0x80>;
> +	};
> +
> +	lpc_host: lpc-host@80 {
> +		compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
> +		reg = <0x80 0x1e0>;
> +		reg-io-width = <4>;
> +
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x0 0x80 0x1e0>;
> +	};
> +};
> +

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH linux dev-4.10 1/3] mfd: dt: Add Aspeed Low Pin Count Controller bindings

[Andrew Jeffery]

[-- Attachment #1: Type: text/plain, Size: 6006 bytes --]

On Mon, 2017-06-05 at 09:05 +0100, Lee Jones wrote:
> On Fri, 02 Jun 2017, Andrew Jeffery wrote:
> 
> > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > > > Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
> > > > Reviewed-by: Joel Stanley <joel@jms.id.au>
> > > > Acked-by: Rob Herring <robh@kernel.org>
> > > > Signed-off-by: Lee Jones <lee.jones@linaro.org>
> > (cherry picked from commit 3bca0e552f693a7d815d24d8fda1196f2c668074)
> 
> What is this patch for?  What's the intention?

I failed at git send-email. Joel maintains our OpenBMC distro kernel,
and I was backporting the patch for completeness. I should've added --
suppress-cc=body when sending but forgot.

Sorry for the noise.

andrew

> 
> > ---
> >  .../devicetree/bindings/mfd/aspeed-lpc.txt         | 111 +++++++++++++++++++++
> >  1 file changed, 111 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > new file mode 100644
> > index 000000000000..a97131aba446
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > @@ -0,0 +1,111 @@
> > +======================================================================
> > +Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
> > +======================================================================
> > +
> > +The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
> > +peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
> > +primary use case of the Aspeed LPC controller is as a slave on the bus
> > +(typically in a Baseboard Management Controller SoC), but under certain
> > +conditions it can also take the role of bus master.
> > +
> > +The LPC controller is represented as a multi-function device to account for the
> > +mix of functionality it provides. The principle split is between the register
> > +layout at the start of the I/O space which is, to quote the Aspeed datasheet,
> > +"basically compatible with the [LPC registers from the] popular BMC controller
> > +H8S/2168[1]", and everything else, where everything else is an eclectic
> > +collection of functions with a esoteric register layout. "Everything else",
> > +here labeled the "host" portion of the controller, includes, but is not limited
> > +to:
> > +
> > +* An IPMI Block Transfer[2] Controller
> > +
> > +* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
> > +  physical properties of some LPC pins, configuration of serial IRQs, and
> > +  APB-to-LPC bridging amonst other functions.
> > +
> > +* An LPC Host Interface Controller: Manages functions exposed to the host such
> > +  as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
> > +  management and bus snoop configuration.
> > +
> > +* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
> > +  hardware management protocols for handover between the host and baseboard
> > +  management controller.
> > +
> > +Additionally the state of the LPC controller influences the pinmux
> > +configuration, therefore the host portion of the controller is exposed as a
> > +syscon as a means to arbitrate access.
> > +
> > +[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
> > +[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
> > +[2] http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
> > +[3] https://en.wikipedia.org/wiki/Super_I/O
> > +
> > +Required properties
> > +===================
> > +
> > > > +- compatible:	One of:
> > > > +		"aspeed,ast2400-lpc", "simple-mfd"
> > > > +		"aspeed,ast2500-lpc", "simple-mfd"
> > +
> > > > +- reg:		contains the physical address and length values of the Aspeed
> > +                LPC memory region.
> > +
> > +- #address-cells: <1>
> > > > +- #size-cells:	<1>
> > > > +- ranges: 	Maps 0 to the physical address and length of the LPC memory
> > +                region
> > +
> > +Required LPC Child nodes
> > +========================
> > +
> > +BMC Node
> > +--------
> > +
> > > > +- compatible:	One of:
> > > > +		"aspeed,ast2400-lpc-bmc"
> > > > +		"aspeed,ast2500-lpc-bmc"
> > +
> > > > +- reg:		contains the physical address and length values of the
> > +                H8S/2168-compatible LPC controller memory region
> > +
> > +Host Node
> > +---------
> > +
> > +- compatible:   One of:
> > > > +		"aspeed,ast2400-lpc-host", "simple-mfd", "syscon"
> > > > +		"aspeed,ast2500-lpc-host", "simple-mfd", "syscon"
> > +
> > > > +- reg:		contains the address and length values of the host-related
> > +                register space for the Aspeed LPC controller
> > +
> > +- #address-cells: <1>
> > > > +- #size-cells:	<1>
> > > > +- ranges: 	Maps 0 to the address and length of the host-related LPC memory
> > +                region
> > +
> > +Example:
> > +
> > > > +lpc: lpc@1e789000 {
> > > > +	compatible = "aspeed,ast2500-lpc", "simple-mfd";
> > > > +	reg = <0x1e789000 0x1000>;
> > +
> > > > +	#address-cells = <1>;
> > > > +	#size-cells = <1>;
> > > > +	ranges = <0x0 0x1e789000 0x1000>;
> > +
> > > > > > +	lpc_bmc: lpc-bmc@0 {
> > > > +		compatible = "aspeed,ast2500-lpc-bmc";
> > > > +		reg = <0x0 0x80>;
> > > > +	};
> > +
> > > > > > +	lpc_host: lpc-host@80 {
> > > > +		compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
> > > > +		reg = <0x80 0x1e0>;
> > > > +		reg-io-width = <4>;
> > +
> > > > +		#address-cells = <1>;
> > > > +		#size-cells = <1>;
> > > > +		ranges = <0x0 0x80 0x1e0>;
> > > > +	};
> > +};
> > +
> 
> 

[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 801 bytes --]