[PATCH 00/14] Add QCOM QPIC NAND support

[PATCH 00/14] Add QCOM QPIC NAND support

[Abhishek Sahu]

The current QCOM NAND driver only support EBI2 NAND which uses
ADM DMA. The latest QCOM controller supports QPIC NAND which uses
BAM DMA. NAND registers and programming sequence are same for EBI2
and QPIC NAND so the same driver can support QPIC NAND also by
adding the BAM DMA support. This patch series adds the support for
QPIC NAND controller version 1.4.0 available in IPQ4019 and QPIC
NAND controller version 1.5.0 available in IPQ8074.

The kernel MTD tests have been run to validate all these patches
in IPQ8064 AP148, IPQ4019 DK04 and IPQ8074 HK01 boards and all
the MTD tests are passing on these boards.

The QPIC NAND requires the command channel support for BAM DMA
engine and currently BAM engine does not support the command
descriptors so the following patches have been posted for the
same in dmaengine mailing list. The above patches are dependent
upon these BAM DMA patches.

https://www.spinics.net/lists/kernel/msg2542483.html

Abhishek Sahu (14):
  qcom: mtd: nand: Add driver data for QPIC DMA
  qcom: mtd: nand: add and initialize QPIC DMA resources
  qcom: mtd: nand: Fixed config error for BCH
  qcom: mtd: nand: reorganize nand devices probing
  qcom: mtd: nand: allocate bam transaction
  qcom: mtd: nand: add bam dma descriptor handling
  qcom: mtd: nand: support for passing flags in transfer functions
  qcom: mtd: nand: Add support for additional CSRs
  qcom: mtd: nand: BAM support for read page
  qcom: mtd: nand: support for QPIC Page read/write
  qcom: mtd: nand: BAM raw read and write support
  qcom: mtd: nand: change register offset defines with enums
  qcom: mtd: nand: support for QPIC version 1.5.0
  qcom: mtd: nand: programmed NAND_DEV_CMD_VLD register

 .../devicetree/bindings/mtd/qcom_nandc.txt         |  110 +-
 drivers/mtd/nand/qcom_nandc.c                      | 1114 +++++++++++++++++---
 2 files changed, 1050 insertions(+), 174 deletions(-)

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[PATCH 00/14] Add QCOM QPIC NAND support

[Abhishek Sahu]

The current QCOM NAND driver only support EBI2 NAND which uses
ADM DMA. The latest QCOM controller supports QPIC NAND which uses
BAM DMA. NAND registers and programming sequence are same for EBI2
and QPIC NAND so the same driver can support QPIC NAND also by
adding the BAM DMA support. This patch series adds the support for
QPIC NAND controller version 1.4.0 available in IPQ4019 and QPIC
NAND controller version 1.5.0 available in IPQ8074.

The kernel MTD tests have been run to validate all these patches
in IPQ8064 AP148, IPQ4019 DK04 and IPQ8074 HK01 boards and all
the MTD tests are passing on these boards.

The QPIC NAND requires the command channel support for BAM DMA
engine and currently BAM engine does not support the command
descriptors so the following patches have been posted for the
same in dmaengine mailing list. The above patches are dependent
upon these BAM DMA patches.

https://www.spinics.net/lists/kernel/msg2542483.html

Abhishek Sahu (14):
  qcom: mtd: nand: Add driver data for QPIC DMA
  qcom: mtd: nand: add and initialize QPIC DMA resources
  qcom: mtd: nand: Fixed config error for BCH
  qcom: mtd: nand: reorganize nand devices probing
  qcom: mtd: nand: allocate bam transaction
  qcom: mtd: nand: add bam dma descriptor handling
  qcom: mtd: nand: support for passing flags in transfer functions
  qcom: mtd: nand: Add support for additional CSRs
  qcom: mtd: nand: BAM support for read page
  qcom: mtd: nand: support for QPIC Page read/write
  qcom: mtd: nand: BAM raw read and write support
  qcom: mtd: nand: change register offset defines with enums
  qcom: mtd: nand: support for QPIC version 1.5.0
  qcom: mtd: nand: programmed NAND_DEV_CMD_VLD register

 .../devicetree/bindings/mtd/qcom_nandc.txt         |  110 +-
 drivers/mtd/nand/qcom_nandc.c                      | 1114 +++++++++++++++++---
 2 files changed, 1050 insertions(+), 174 deletions(-)

-- 
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[PATCH 03/14] qcom: mtd: nand: Fixed config error for BCH

[Abhishek Sahu]

The configuration for BCH is not correct in the current
driver so this patch fixed the same.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/mtd/nand/qcom_nandc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 520add9..410ee53 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -1919,7 +1919,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
 				| wide_bus << WIDE_FLASH
 				| 1 << DEV0_CFG1_ECC_DISABLE;
 
-	host->ecc_bch_cfg = host->bch_enabled << ECC_CFG_ECC_DISABLE
+	host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
 				| 0 << ECC_SW_RESET
 				| host->cw_data << ECC_NUM_DATA_BYTES
 				| 1 << ECC_FORCE_CLK_OPEN
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 03/14] qcom: mtd: nand: Fixed config error for BCH

[Marek Vasut]

On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
> The configuration for BCH is not correct in the current
> driver so this patch fixed the same.

Fix the commit message, I have no idea what this patch does or fixes.

> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>  drivers/mtd/nand/qcom_nandc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 520add9..410ee53 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -1919,7 +1919,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
>  				| wide_bus << WIDE_FLASH
>  				| 1 << DEV0_CFG1_ECC_DISABLE;
>  
> -	host->ecc_bch_cfg = host->bch_enabled << ECC_CFG_ECC_DISABLE
> +	host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
>  				| 0 << ECC_SW_RESET
>  				| host->cw_data << ECC_NUM_DATA_BYTES
>  				| 1 << ECC_FORCE_CLK_OPEN
> 


-- 
Best regards,
Marek Vasut

Re: [PATCH 03/14] qcom: mtd: nand: Fixed config error for BCH

[Boris Brezillon]

On Thu, 29 Jun 2017 11:49:07 +0200
Marek Vasut <marek.vasut@gmail.com> wrote:

> On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
> > The configuration for BCH is not correct in the current
> > driver so this patch fixed the same.  
> 
> Fix the commit message, I have no idea what this patch does or fixes.

And please add a Fixes tag and Cc stable. 

> 
> > Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> > ---
> >  drivers/mtd/nand/qcom_nandc.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> > index 520add9..410ee53 100644
> > --- a/drivers/mtd/nand/qcom_nandc.c
> > +++ b/drivers/mtd/nand/qcom_nandc.c
> > @@ -1919,7 +1919,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
> >  				| wide_bus << WIDE_FLASH
> >  				| 1 << DEV0_CFG1_ECC_DISABLE;
> >  
> > -	host->ecc_bch_cfg = host->bch_enabled << ECC_CFG_ECC_DISABLE
> > +	host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
> >  				| 0 << ECC_SW_RESET
> >  				| host->cw_data << ECC_NUM_DATA_BYTES
> >  				| 1 << ECC_FORCE_CLK_OPEN
> >   
> 
> 

Re: [PATCH 03/14] qcom: mtd: nand: Fixed config error for BCH

[Abhishek Sahu]

On 2017-07-04 01:17, Boris Brezillon wrote:
> On Thu, 29 Jun 2017 11:49:07 +0200
> Marek Vasut <marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> 
>> On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
>> > The configuration for BCH is not correct in the current
>> > driver so this patch fixed the same.
>> 
>> Fix the commit message, I have no idea what this patch does or fixes.
> 
> And please add a Fixes tag and Cc stable.
> 

  Sure. I will amend the commit message to make it
  more clear and will include these tags.

>> 
>> > Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>> > ---
>> >  drivers/mtd/nand/qcom_nandc.c | 2 +-
>> >  1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/mtd/nand/qcom_nandc.c
> b/drivers/mtd/nand/qcom_nandc.c
>> > index 520add9..410ee53 100644
>> > --- a/drivers/mtd/nand/qcom_nandc.c
>> > +++ b/drivers/mtd/nand/qcom_nandc.c
>> > @@ -1919,7 +1919,7 @@ static int qcom_nand_host_setup(struct
> qcom_nand_host *host)
>> >  				| wide_bus << WIDE_FLASH
>> >  				| 1 << DEV0_CFG1_ECC_DISABLE;
>> >
>> > -	host->ecc_bch_cfg = host->bch_enabled << ECC_CFG_ECC_DISABLE
>> > +	host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
>> >  				| 0 << ECC_SW_RESET
>> >  				| host->cw_data << ECC_NUM_DATA_BYTES
>> >  				| 1 << ECC_FORCE_CLK_OPEN
>> >
>> 
>> 

-- 
Abhishek Sahu
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Re: [PATCH 03/14] qcom: mtd: nand: Fixed config error for BCH

[Abhishek Sahu]

On 2017-07-04 01:17, Boris Brezillon wrote:
> On Thu, 29 Jun 2017 11:49:07 +0200
> Marek Vasut <marek.vasut@gmail.com> wrote:
> 
>> On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
>> > The configuration for BCH is not correct in the current
>> > driver so this patch fixed the same.
>> 
>> Fix the commit message, I have no idea what this patch does or fixes.
> 
> And please add a Fixes tag and Cc stable.
> 

  Sure. I will amend the commit message to make it
  more clear and will include these tags.

>> 
>> > Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> > ---
>> >  drivers/mtd/nand/qcom_nandc.c | 2 +-
>> >  1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/mtd/nand/qcom_nandc.c
> b/drivers/mtd/nand/qcom_nandc.c
>> > index 520add9..410ee53 100644
>> > --- a/drivers/mtd/nand/qcom_nandc.c
>> > +++ b/drivers/mtd/nand/qcom_nandc.c
>> > @@ -1919,7 +1919,7 @@ static int qcom_nand_host_setup(struct
> qcom_nand_host *host)
>> >  				| wide_bus << WIDE_FLASH
>> >  				| 1 << DEV0_CFG1_ECC_DISABLE;
>> >
>> > -	host->ecc_bch_cfg = host->bch_enabled << ECC_CFG_ECC_DISABLE
>> > +	host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
>> >  				| 0 << ECC_SW_RESET
>> >  				| host->cw_data << ECC_NUM_DATA_BYTES
>> >  				| 1 << ECC_FORCE_CLK_OPEN
>> >
>> 
>> 

-- 
Abhishek Sahu

Re: [PATCH 03/14] qcom: mtd: nand: Fixed config error for BCH

[Sricharan R]

Hi Abhishek,

On 6/29/2017 12:45 PM, Abhishek Sahu wrote:
> The configuration for BCH is not correct in the current
> driver so this patch fixed the same.
> 
> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>  drivers/mtd/nand/qcom_nandc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 520add9..410ee53 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -1919,7 +1919,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
>  				| wide_bus << WIDE_FLASH
>  				| 1 << DEV0_CFG1_ECC_DISABLE;
>  
> -	host->ecc_bch_cfg = host->bch_enabled << ECC_CFG_ECC_DISABLE
> +	host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
>  				| 0 << ECC_SW_RESET
>  				| host->cw_data << ECC_NUM_DATA_BYTES
>  				| 1 << ECC_FORCE_CLK_OPEN
> 

 This could be patch #1, so basically all fixes first and then support
 for bam after that.

Regards,
 Sricharan

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Re: [PATCH 03/14] qcom: mtd: nand: Fixed config error for BCH

[Sricharan R]

Hi Abhishek,

On 6/29/2017 12:45 PM, Abhishek Sahu wrote:
> The configuration for BCH is not correct in the current
> driver so this patch fixed the same.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>  drivers/mtd/nand/qcom_nandc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 520add9..410ee53 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -1919,7 +1919,7 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
>  				| wide_bus << WIDE_FLASH
>  				| 1 << DEV0_CFG1_ECC_DISABLE;
>  
> -	host->ecc_bch_cfg = host->bch_enabled << ECC_CFG_ECC_DISABLE
> +	host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
>  				| 0 << ECC_SW_RESET
>  				| host->cw_data << ECC_NUM_DATA_BYTES
>  				| 1 << ECC_FORCE_CLK_OPEN
> 

 This could be patch #1, so basically all fixes first and then support
 for bam after that.

Regards,
 Sricharan

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[PATCH 04/14] qcom: mtd: nand: reorganize nand devices probing

[Abhishek Sahu]

This is reorganization of exiting code and will not change any
functionality. The NAND controller supports multiple NAND device
with different page size. The subsequent patch allocate memory
which depends upon the maximum number of codewords so this patch
reorganizes the NAND device probing. First the ONFI parameter
page will be read from each connected device followed by MTD
device registration.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/mtd/nand/qcom_nandc.c | 92 ++++++++++++++++++++++++++++---------------
 1 file changed, 61 insertions(+), 31 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 410ee53..eb0ec19 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -2102,14 +2102,69 @@ static int qcom_nand_host_init(struct qcom_nand_controller *nandc,
 		return ret;
 
 	ret = qcom_nand_host_setup(host);
-	if (ret)
-		return ret;
+
+	return ret;
+}
+
+static int qcom_nand_mtd_register(struct qcom_nand_controller *nandc,
+				  struct qcom_nand_host *host,
+				  struct device_node *dn)
+{
+	struct nand_chip *chip = &host->chip;
+	struct mtd_info *mtd = nand_to_mtd(chip);
+	int ret;
 
 	ret = nand_scan_tail(mtd);
 	if (ret)
 		return ret;
 
-	return mtd_device_register(mtd, NULL, 0);
+	ret = mtd_device_register(mtd, NULL, 0);
+	if (ret)
+		nand_cleanup(mtd_to_nand(mtd));
+
+	return ret;
+}
+
+static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
+{
+	struct device *dev = nandc->dev;
+	struct device_node *dn = dev->of_node, *child;
+	struct qcom_nand_host *host, *tmp;
+	int ret;
+
+	for_each_available_child_of_node(dn, child) {
+		if (of_device_is_compatible(child, "qcom,nandcs")) {
+			host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
+			if (!host) {
+				of_node_put(child);
+				return -ENOMEM;
+			}
+
+			ret = qcom_nand_host_init(nandc, host, child);
+			if (ret) {
+				devm_kfree(dev, host);
+				continue;
+			}
+
+			list_add_tail(&host->node, &nandc->host_list);
+		}
+	}
+
+	if (list_empty(&nandc->host_list))
+		return -ENODEV;
+
+	list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
+		ret = qcom_nand_mtd_register(nandc, host, child);
+		if (ret) {
+			list_del(&host->node);
+			devm_kfree(dev, host);
+		}
+	}
+
+	if (list_empty(&nandc->host_list))
+		return -ENODEV;
+
+	return 0;
 }
 
 /* parse custom DT properties here */
@@ -2141,10 +2196,8 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
 static int qcom_nandc_probe(struct platform_device *pdev)
 {
 	struct qcom_nand_controller *nandc;
-	struct qcom_nand_host *host;
 	const void *dev_data;
 	struct device *dev = &pdev->dev;
-	struct device_node *dn = dev->of_node, *child;
 	struct resource *res;
 	int ret;
 	const struct qcom_nand_driver_data *driver_data;
@@ -2202,35 +2255,12 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_setup;
 
-	for_each_available_child_of_node(dn, child) {
-		if (of_device_is_compatible(child, "qcom,nandcs")) {
-			host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
-			if (!host) {
-				of_node_put(child);
-				ret = -ENOMEM;
-				goto err_cs_init;
-			}
-
-			ret = qcom_nand_host_init(nandc, host, child);
-			if (ret) {
-				devm_kfree(dev, host);
-				continue;
-			}
-
-			list_add_tail(&host->node, &nandc->host_list);
-		}
-	}
-
-	if (list_empty(&nandc->host_list)) {
-		ret = -ENODEV;
-		goto err_cs_init;
-	}
+	ret = qcom_probe_nand_devices(nandc);
+	if (ret)
+		goto err_setup;
 
 	return 0;
 
-err_cs_init:
-	list_for_each_entry(host, &nandc->host_list, node)
-		nand_release(nand_to_mtd(&host->chip));
 err_setup:
 	clk_disable_unprepare(nandc->aon_clk);
 err_aon_clk:
-- 
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[PATCH 04/14] qcom: mtd: nand: reorganize nand devices probing

[Abhishek Sahu]

This is reorganization of exiting code and will not change any
functionality. The NAND controller supports multiple NAND device
with different page size. The subsequent patch allocate memory
which depends upon the maximum number of codewords so this patch
reorganizes the NAND device probing. First the ONFI parameter
page will be read from each connected device followed by MTD
device registration.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/mtd/nand/qcom_nandc.c | 92 ++++++++++++++++++++++++++++---------------
 1 file changed, 61 insertions(+), 31 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 410ee53..eb0ec19 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -2102,14 +2102,69 @@ static int qcom_nand_host_init(struct qcom_nand_controller *nandc,
 		return ret;
 
 	ret = qcom_nand_host_setup(host);
-	if (ret)
-		return ret;
+
+	return ret;
+}
+
+static int qcom_nand_mtd_register(struct qcom_nand_controller *nandc,
+				  struct qcom_nand_host *host,
+				  struct device_node *dn)
+{
+	struct nand_chip *chip = &host->chip;
+	struct mtd_info *mtd = nand_to_mtd(chip);
+	int ret;
 
 	ret = nand_scan_tail(mtd);
 	if (ret)
 		return ret;
 
-	return mtd_device_register(mtd, NULL, 0);
+	ret = mtd_device_register(mtd, NULL, 0);
+	if (ret)
+		nand_cleanup(mtd_to_nand(mtd));
+
+	return ret;
+}
+
+static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
+{
+	struct device *dev = nandc->dev;
+	struct device_node *dn = dev->of_node, *child;
+	struct qcom_nand_host *host, *tmp;
+	int ret;
+
+	for_each_available_child_of_node(dn, child) {
+		if (of_device_is_compatible(child, "qcom,nandcs")) {
+			host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
+			if (!host) {
+				of_node_put(child);
+				return -ENOMEM;
+			}
+
+			ret = qcom_nand_host_init(nandc, host, child);
+			if (ret) {
+				devm_kfree(dev, host);
+				continue;
+			}
+
+			list_add_tail(&host->node, &nandc->host_list);
+		}
+	}
+
+	if (list_empty(&nandc->host_list))
+		return -ENODEV;
+
+	list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
+		ret = qcom_nand_mtd_register(nandc, host, child);
+		if (ret) {
+			list_del(&host->node);
+			devm_kfree(dev, host);
+		}
+	}
+
+	if (list_empty(&nandc->host_list))
+		return -ENODEV;
+
+	return 0;
 }
 
 /* parse custom DT properties here */
@@ -2141,10 +2196,8 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
 static int qcom_nandc_probe(struct platform_device *pdev)
 {
 	struct qcom_nand_controller *nandc;
-	struct qcom_nand_host *host;
 	const void *dev_data;
 	struct device *dev = &pdev->dev;
-	struct device_node *dn = dev->of_node, *child;
 	struct resource *res;
 	int ret;
 	const struct qcom_nand_driver_data *driver_data;
@@ -2202,35 +2255,12 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_setup;
 
-	for_each_available_child_of_node(dn, child) {
-		if (of_device_is_compatible(child, "qcom,nandcs")) {
-			host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
-			if (!host) {
-				of_node_put(child);
-				ret = -ENOMEM;
-				goto err_cs_init;
-			}
-
-			ret = qcom_nand_host_init(nandc, host, child);
-			if (ret) {
-				devm_kfree(dev, host);
-				continue;
-			}
-
-			list_add_tail(&host->node, &nandc->host_list);
-		}
-	}
-
-	if (list_empty(&nandc->host_list)) {
-		ret = -ENODEV;
-		goto err_cs_init;
-	}
+	ret = qcom_probe_nand_devices(nandc);
+	if (ret)
+		goto err_setup;
 
 	return 0;
 
-err_cs_init:
-	list_for_each_entry(host, &nandc->host_list, node)
-		nand_release(nand_to_mtd(&host->chip));
 err_setup:
 	clk_disable_unprepare(nandc->aon_clk);
 err_aon_clk:
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 05/14] qcom: mtd: nand: allocate bam transaction

[Abhishek Sahu]

The BAM transaction is the core data structure which will be used
for all the data transfers in QPIC NAND. Since the base layer is
serializing all the NAND requests so allocating BAM transaction
before every transfer will be overhead. The memory for it be
allocated during probe time and before every transfer, it will be
cleared. The BAM transaction contains the array of command
elements, command and data scatter gather list and indexes. For
every transfer, all the resource will be taken from bam
transaction.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/mtd/nand/qcom_nandc.c | 116 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 116 insertions(+)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index eb0ec19..f8d0bde 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -22,6 +22,7 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/delay.h>
+#include <linux/dma/qcom_bam_dma.h>
 
 /* NANDc reg offsets */
 #define	NAND_FLASH_CMD			0x00
@@ -169,6 +170,45 @@
 #define	ECC_BCH_4BIT	BIT(2)
 #define	ECC_BCH_8BIT	BIT(3)
 
+#define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
+#define QPIC_PER_CW_MAX_CMD_SGL		(32)
+#define QPIC_PER_CW_MAX_DATA_SGL	(8)
+
+/*
+ * This data type corresponds to the BAM transaction which will be used for all
+ * NAND transfers.
+ * @bam_ce - the array of bam command elements
+ * @cmd_sgl - sgl for nand bam command pipe
+ * @data_sgl - sgl for nand bam consumer/producer pipe
+ * @bam_ce_pos - the index in bam_ce which is available for next sgl request
+ * @bam_ce_start - the index in bam_ce which marks the start position ce
+ *		   for current sgl. It will be used for size calculation
+ *		   for current sgl
+ * @cmd_sgl_pos - current index in command sgl.
+ * @tx_sgl_pos - current index in data sgl for tx.
+ * @rx_sgl_pos - current index in data sgl for rx.
+ */
+struct bam_transaction {
+	struct bam_cmd_element *bam_ce;
+	struct scatterlist *cmd_sgl;
+	struct scatterlist *data_sg;
+	u32 bam_ce_pos;
+	u32 bam_ce_start;
+	u32 cmd_sgl_pos;
+	u32 cmd_sgl_start;
+	u32 tx_sgl_pos;
+	u32 tx_sgl_start;
+	u32 rx_sgl_pos;
+	u32 rx_sgl_start;
+};
+
+/*
+ * This data type corresponds to the nand dma descriptor
+ * @list - list for desc_info
+ * @dir - DMA transfer direction
+ * @sgl - sgl which will be used for single sgl dma descriptor
+ * @dma_desc - low level dma engine descriptor
+ */
 struct desc_info {
 	struct list_head node;
 
@@ -217,6 +257,7 @@ struct nandc_regs {
  * @aon_clk:			another controller clock
  *
  * @chan:			dma channel
+ * @bam_txn:			contains the bam transaction buffer
  * @cmd_crci:			ADM DMA CRCI for command flow control
  * @data_crci:			ADM DMA CRCI for data flow control
  * @desc_list:			DMA descriptor list (list of desc_infos)
@@ -237,6 +278,8 @@ struct nandc_regs {
  *				initialized via DT match data
  * @dma_bam_enabled:		flag to tell whether nand controller is using
  *				bam dma
+ * @max_cwperpage:		maximum qpic codeword required. calcualted
+ *				from all nand device pagesize
  */
 struct qcom_nand_controller {
 	struct nand_hw_control controller;
@@ -264,12 +307,14 @@ struct qcom_nand_controller {
 	};
 
 	struct list_head desc_list;
+	struct bam_transaction *bam_txn;
 
 	u8		*data_buffer;
 	bool		dma_bam_enabled;
 	int		buf_size;
 	int		buf_count;
 	int		buf_start;
+	unsigned int	max_cwperpage;
 
 	__le32 *reg_read_buf;
 	dma_addr_t reg_read_buf_phys;
@@ -342,6 +387,51 @@ struct qcom_nand_driver_data {
 	bool dma_bam_enabled;
 };
 
+/* Frees the BAM transaction memory */
+static void free_bam_transaction(struct qcom_nand_controller *nandc)
+{
+	struct bam_transaction *bam_txn = nandc->bam_txn;
+
+	devm_kfree(nandc->dev, bam_txn->bam_ce);
+	devm_kfree(nandc->dev, bam_txn->cmd_sgl);
+	devm_kfree(nandc->dev, bam_txn->data_sg);
+	devm_kfree(nandc->dev, bam_txn);
+}
+
+/* Allocates and Initializes the BAM transaction */
+static struct bam_transaction *
+alloc_bam_transaction(struct qcom_nand_controller *nandc, unsigned int num_cw)
+{
+	struct bam_transaction *bam_txn;
+
+	bam_txn = devm_kzalloc(nandc->dev, sizeof(*bam_txn), GFP_KERNEL);
+
+	if (!bam_txn)
+		return NULL;
+
+	bam_txn->bam_ce =
+		devm_kzalloc(nandc->dev, sizeof(*bam_txn->bam_ce) *
+			     num_cw * QPIC_PER_CW_MAX_CMD_ELEMENTS, GFP_KERNEL);
+	if (!bam_txn->bam_ce)
+		return NULL;
+
+	bam_txn->cmd_sgl =
+		devm_kzalloc(nandc->dev, sizeof(*bam_txn->cmd_sgl) * num_cw *
+			     QPIC_PER_CW_MAX_CMD_SGL, GFP_KERNEL);
+	if (!bam_txn->cmd_sgl)
+		return NULL;
+
+	bam_txn->data_sg =
+		devm_kzalloc(nandc->dev, sizeof(*bam_txn->data_sg) *
+			     num_cw * QPIC_PER_CW_MAX_DATA_SGL, GFP_KERNEL);
+	if (!bam_txn->data_sg)
+		return NULL;
+
+	nandc->max_cwperpage = num_cw;
+
+	return bam_txn;
+}
+
 static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
 {
 	return container_of(chip, struct qcom_nand_host, chip);
@@ -1868,6 +1958,8 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
 	mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
 
 	cwperpage = mtd->writesize / ecc->size;
+	nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
+					cwperpage);
 
 	/*
 	 * DATA_UD_BYTES varies based on whether the read/write command protects
@@ -2010,6 +2102,19 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
 			dev_err(nandc->dev, "failed to request cmd channel\n");
 			return -ENODEV;
 		}
+
+		/*
+		 * Initially allocate BAM transaction to read ONFI param page.
+		 * After detecting all the devices, this BAM transaction will
+		 * be freed and the next BAM tranasction will be allocated with
+		 * maximum codeword size
+		 */
+		nandc->bam_txn = alloc_bam_transaction(nandc, 1);
+		if (!nandc->bam_txn) {
+			dev_err(nandc->dev,
+				"failed to allocate bam transaction\n");
+			return -ENOMEM;
+		}
 	}
 
 	INIT_LIST_HEAD(&nandc->desc_list);
@@ -2153,6 +2258,17 @@ static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
 	if (list_empty(&nandc->host_list))
 		return -ENODEV;
 
+	if (nandc->dma_bam_enabled) {
+		free_bam_transaction(nandc);
+		nandc->bam_txn = alloc_bam_transaction(nandc,
+						       nandc->max_cwperpage);
+		if (!nandc->bam_txn) {
+			dev_err(nandc->dev,
+				"failed to allocate bam transaction\n");
+			return -ENOMEM;
+		}
+	}
+
 	list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
 		ret = qcom_nand_mtd_register(nandc, host, child);
 		if (ret) {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 05/14] qcom: mtd: nand: allocate bam transaction

[Marek Vasut]

On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
> The BAM transaction is the core data structure which will be used
> for all the data transfers in QPIC NAND. Since the base layer is
> serializing all the NAND requests so allocating BAM transaction
> before every transfer will be overhead. The memory for it be
> allocated during probe time and before every transfer, it will be
> cleared. The BAM transaction contains the array of command
> elements, command and data scatter gather list and indexes. For
> every transfer, all the resource will be taken from bam
> transaction.
> 
> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>  drivers/mtd/nand/qcom_nandc.c | 116 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 116 insertions(+)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index eb0ec19..f8d0bde 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -22,6 +22,7 @@
>  #include <linux/of.h>
>  #include <linux/of_device.h>
>  #include <linux/delay.h>
> +#include <linux/dma/qcom_bam_dma.h>
>  
>  /* NANDc reg offsets */
>  #define	NAND_FLASH_CMD			0x00
> @@ -169,6 +170,45 @@
>  #define	ECC_BCH_4BIT	BIT(2)
>  #define	ECC_BCH_8BIT	BIT(3)
>  
> +#define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
> +#define QPIC_PER_CW_MAX_CMD_SGL		(32)
> +#define QPIC_PER_CW_MAX_DATA_SGL	(8)
> +
> +/*
> + * This data type corresponds to the BAM transaction which will be used for all
> + * NAND transfers.
> + * @bam_ce - the array of bam command elements
> + * @cmd_sgl - sgl for nand bam command pipe
> + * @data_sgl - sgl for nand bam consumer/producer pipe
> + * @bam_ce_pos - the index in bam_ce which is available for next sgl request
> + * @bam_ce_start - the index in bam_ce which marks the start position ce
> + *		   for current sgl. It will be used for size calculation
> + *		   for current sgl
> + * @cmd_sgl_pos - current index in command sgl.
> + * @tx_sgl_pos - current index in data sgl for tx.
> + * @rx_sgl_pos - current index in data sgl for rx.
> + */
> +struct bam_transaction {
> +	struct bam_cmd_element *bam_ce;
> +	struct scatterlist *cmd_sgl;
> +	struct scatterlist *data_sg;
> +	u32 bam_ce_pos;
> +	u32 bam_ce_start;
> +	u32 cmd_sgl_pos;
> +	u32 cmd_sgl_start;
> +	u32 tx_sgl_pos;
> +	u32 tx_sgl_start;
> +	u32 rx_sgl_pos;
> +	u32 rx_sgl_start;
> +};
> +
> +/*
> + * This data type corresponds to the nand dma descriptor
> + * @list - list for desc_info
> + * @dir - DMA transfer direction
> + * @sgl - sgl which will be used for single sgl dma descriptor
> + * @dma_desc - low level dma engine descriptor
> + */
>  struct desc_info {
>  	struct list_head node;
>  
> @@ -217,6 +257,7 @@ struct nandc_regs {
>   * @aon_clk:			another controller clock
>   *
>   * @chan:			dma channel
> + * @bam_txn:			contains the bam transaction buffer
>   * @cmd_crci:			ADM DMA CRCI for command flow control
>   * @data_crci:			ADM DMA CRCI for data flow control
>   * @desc_list:			DMA descriptor list (list of desc_infos)
> @@ -237,6 +278,8 @@ struct nandc_regs {
>   *				initialized via DT match data
>   * @dma_bam_enabled:		flag to tell whether nand controller is using
>   *				bam dma
> + * @max_cwperpage:		maximum qpic codeword required. calcualted
> + *				from all nand device pagesize
>   */
>  struct qcom_nand_controller {
>  	struct nand_hw_control controller;
> @@ -264,12 +307,14 @@ struct qcom_nand_controller {
>  	};
>  
>  	struct list_head desc_list;
> +	struct bam_transaction *bam_txn;
>  
>  	u8		*data_buffer;
>  	bool		dma_bam_enabled;
>  	int		buf_size;
>  	int		buf_count;
>  	int		buf_start;
> +	unsigned int	max_cwperpage;
>  
>  	__le32 *reg_read_buf;
>  	dma_addr_t reg_read_buf_phys;
> @@ -342,6 +387,51 @@ struct qcom_nand_driver_data {
>  	bool dma_bam_enabled;
>  };
>  
> +/* Frees the BAM transaction memory */
> +static void free_bam_transaction(struct qcom_nand_controller *nandc)
> +{
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> +	devm_kfree(nandc->dev, bam_txn->bam_ce);
> +	devm_kfree(nandc->dev, bam_txn->cmd_sgl);
> +	devm_kfree(nandc->dev, bam_txn->data_sg);
> +	devm_kfree(nandc->dev, bam_txn);
> +}
> +
> +/* Allocates and Initializes the BAM transaction */
> +static struct bam_transaction *
> +alloc_bam_transaction(struct qcom_nand_controller *nandc, unsigned int num_cw)
> +{
> +	struct bam_transaction *bam_txn;
> +
> +	bam_txn = devm_kzalloc(nandc->dev, sizeof(*bam_txn), GFP_KERNEL);

Can you make these four allocations into a single allocation ?

> +	if (!bam_txn)
> +		return NULL;
> +
> +	bam_txn->bam_ce =
> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->bam_ce) *
> +			     num_cw * QPIC_PER_CW_MAX_CMD_ELEMENTS, GFP_KERNEL);
> +	if (!bam_txn->bam_ce)
> +		return NULL;
> +
> +	bam_txn->cmd_sgl =
> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->cmd_sgl) * num_cw *
> +			     QPIC_PER_CW_MAX_CMD_SGL, GFP_KERNEL);
> +	if (!bam_txn->cmd_sgl)
> +		return NULL;
> +
> +	bam_txn->data_sg =
> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->data_sg) *
> +			     num_cw * QPIC_PER_CW_MAX_DATA_SGL, GFP_KERNEL);
> +	if (!bam_txn->data_sg)
> +		return NULL;
> +
> +	nandc->max_cwperpage = num_cw;
> +
> +	return bam_txn;
> +}
> +
>  static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>  {
>  	return container_of(chip, struct qcom_nand_host, chip);
> @@ -1868,6 +1958,8 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
>  	mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
>  
>  	cwperpage = mtd->writesize / ecc->size;
> +	nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
> +					cwperpage);
>  
>  	/*
>  	 * DATA_UD_BYTES varies based on whether the read/write command protects
> @@ -2010,6 +2102,19 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>  			dev_err(nandc->dev, "failed to request cmd channel\n");
>  			return -ENODEV;
>  		}
> +
> +		/*
> +		 * Initially allocate BAM transaction to read ONFI param page.
> +		 * After detecting all the devices, this BAM transaction will
> +		 * be freed and the next BAM tranasction will be allocated with
> +		 * maximum codeword size
> +		 */
> +		nandc->bam_txn = alloc_bam_transaction(nandc, 1);
> +		if (!nandc->bam_txn) {
> +			dev_err(nandc->dev,
> +				"failed to allocate bam transaction\n");
> +			return -ENOMEM;
> +		}
>  	}
>  
>  	INIT_LIST_HEAD(&nandc->desc_list);
> @@ -2153,6 +2258,17 @@ static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
>  	if (list_empty(&nandc->host_list))
>  		return -ENODEV;
>  
> +	if (nandc->dma_bam_enabled) {
> +		free_bam_transaction(nandc);
> +		nandc->bam_txn = alloc_bam_transaction(nandc,
> +						       nandc->max_cwperpage);
> +		if (!nandc->bam_txn) {
> +			dev_err(nandc->dev,
> +				"failed to allocate bam transaction\n");
> +			return -ENOMEM;
> +		}
> +	}
> +
>  	list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
>  		ret = qcom_nand_mtd_register(nandc, host, child);
>  		if (ret) {
> 


-- 
Best regards,
Marek Vasut
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Re: [PATCH 05/14] qcom: mtd: nand: allocate bam transaction

[Marek Vasut]

On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
> The BAM transaction is the core data structure which will be used
> for all the data transfers in QPIC NAND. Since the base layer is
> serializing all the NAND requests so allocating BAM transaction
> before every transfer will be overhead. The memory for it be
> allocated during probe time and before every transfer, it will be
> cleared. The BAM transaction contains the array of command
> elements, command and data scatter gather list and indexes. For
> every transfer, all the resource will be taken from bam
> transaction.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>  drivers/mtd/nand/qcom_nandc.c | 116 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 116 insertions(+)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index eb0ec19..f8d0bde 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -22,6 +22,7 @@
>  #include <linux/of.h>
>  #include <linux/of_device.h>
>  #include <linux/delay.h>
> +#include <linux/dma/qcom_bam_dma.h>
>  
>  /* NANDc reg offsets */
>  #define	NAND_FLASH_CMD			0x00
> @@ -169,6 +170,45 @@
>  #define	ECC_BCH_4BIT	BIT(2)
>  #define	ECC_BCH_8BIT	BIT(3)
>  
> +#define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
> +#define QPIC_PER_CW_MAX_CMD_SGL		(32)
> +#define QPIC_PER_CW_MAX_DATA_SGL	(8)
> +
> +/*
> + * This data type corresponds to the BAM transaction which will be used for all
> + * NAND transfers.
> + * @bam_ce - the array of bam command elements
> + * @cmd_sgl - sgl for nand bam command pipe
> + * @data_sgl - sgl for nand bam consumer/producer pipe
> + * @bam_ce_pos - the index in bam_ce which is available for next sgl request
> + * @bam_ce_start - the index in bam_ce which marks the start position ce
> + *		   for current sgl. It will be used for size calculation
> + *		   for current sgl
> + * @cmd_sgl_pos - current index in command sgl.
> + * @tx_sgl_pos - current index in data sgl for tx.
> + * @rx_sgl_pos - current index in data sgl for rx.
> + */
> +struct bam_transaction {
> +	struct bam_cmd_element *bam_ce;
> +	struct scatterlist *cmd_sgl;
> +	struct scatterlist *data_sg;
> +	u32 bam_ce_pos;
> +	u32 bam_ce_start;
> +	u32 cmd_sgl_pos;
> +	u32 cmd_sgl_start;
> +	u32 tx_sgl_pos;
> +	u32 tx_sgl_start;
> +	u32 rx_sgl_pos;
> +	u32 rx_sgl_start;
> +};
> +
> +/*
> + * This data type corresponds to the nand dma descriptor
> + * @list - list for desc_info
> + * @dir - DMA transfer direction
> + * @sgl - sgl which will be used for single sgl dma descriptor
> + * @dma_desc - low level dma engine descriptor
> + */
>  struct desc_info {
>  	struct list_head node;
>  
> @@ -217,6 +257,7 @@ struct nandc_regs {
>   * @aon_clk:			another controller clock
>   *
>   * @chan:			dma channel
> + * @bam_txn:			contains the bam transaction buffer
>   * @cmd_crci:			ADM DMA CRCI for command flow control
>   * @data_crci:			ADM DMA CRCI for data flow control
>   * @desc_list:			DMA descriptor list (list of desc_infos)
> @@ -237,6 +278,8 @@ struct nandc_regs {
>   *				initialized via DT match data
>   * @dma_bam_enabled:		flag to tell whether nand controller is using
>   *				bam dma
> + * @max_cwperpage:		maximum qpic codeword required. calcualted
> + *				from all nand device pagesize
>   */
>  struct qcom_nand_controller {
>  	struct nand_hw_control controller;
> @@ -264,12 +307,14 @@ struct qcom_nand_controller {
>  	};
>  
>  	struct list_head desc_list;
> +	struct bam_transaction *bam_txn;
>  
>  	u8		*data_buffer;
>  	bool		dma_bam_enabled;
>  	int		buf_size;
>  	int		buf_count;
>  	int		buf_start;
> +	unsigned int	max_cwperpage;
>  
>  	__le32 *reg_read_buf;
>  	dma_addr_t reg_read_buf_phys;
> @@ -342,6 +387,51 @@ struct qcom_nand_driver_data {
>  	bool dma_bam_enabled;
>  };
>  
> +/* Frees the BAM transaction memory */
> +static void free_bam_transaction(struct qcom_nand_controller *nandc)
> +{
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> +	devm_kfree(nandc->dev, bam_txn->bam_ce);
> +	devm_kfree(nandc->dev, bam_txn->cmd_sgl);
> +	devm_kfree(nandc->dev, bam_txn->data_sg);
> +	devm_kfree(nandc->dev, bam_txn);
> +}
> +
> +/* Allocates and Initializes the BAM transaction */
> +static struct bam_transaction *
> +alloc_bam_transaction(struct qcom_nand_controller *nandc, unsigned int num_cw)
> +{
> +	struct bam_transaction *bam_txn;
> +
> +	bam_txn = devm_kzalloc(nandc->dev, sizeof(*bam_txn), GFP_KERNEL);

Can you make these four allocations into a single allocation ?

> +	if (!bam_txn)
> +		return NULL;
> +
> +	bam_txn->bam_ce =
> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->bam_ce) *
> +			     num_cw * QPIC_PER_CW_MAX_CMD_ELEMENTS, GFP_KERNEL);
> +	if (!bam_txn->bam_ce)
> +		return NULL;
> +
> +	bam_txn->cmd_sgl =
> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->cmd_sgl) * num_cw *
> +			     QPIC_PER_CW_MAX_CMD_SGL, GFP_KERNEL);
> +	if (!bam_txn->cmd_sgl)
> +		return NULL;
> +
> +	bam_txn->data_sg =
> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->data_sg) *
> +			     num_cw * QPIC_PER_CW_MAX_DATA_SGL, GFP_KERNEL);
> +	if (!bam_txn->data_sg)
> +		return NULL;
> +
> +	nandc->max_cwperpage = num_cw;
> +
> +	return bam_txn;
> +}
> +
>  static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>  {
>  	return container_of(chip, struct qcom_nand_host, chip);
> @@ -1868,6 +1958,8 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
>  	mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
>  
>  	cwperpage = mtd->writesize / ecc->size;
> +	nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
> +					cwperpage);
>  
>  	/*
>  	 * DATA_UD_BYTES varies based on whether the read/write command protects
> @@ -2010,6 +2102,19 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>  			dev_err(nandc->dev, "failed to request cmd channel\n");
>  			return -ENODEV;
>  		}
> +
> +		/*
> +		 * Initially allocate BAM transaction to read ONFI param page.
> +		 * After detecting all the devices, this BAM transaction will
> +		 * be freed and the next BAM tranasction will be allocated with
> +		 * maximum codeword size
> +		 */
> +		nandc->bam_txn = alloc_bam_transaction(nandc, 1);
> +		if (!nandc->bam_txn) {
> +			dev_err(nandc->dev,
> +				"failed to allocate bam transaction\n");
> +			return -ENOMEM;
> +		}
>  	}
>  
>  	INIT_LIST_HEAD(&nandc->desc_list);
> @@ -2153,6 +2258,17 @@ static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
>  	if (list_empty(&nandc->host_list))
>  		return -ENODEV;
>  
> +	if (nandc->dma_bam_enabled) {
> +		free_bam_transaction(nandc);
> +		nandc->bam_txn = alloc_bam_transaction(nandc,
> +						       nandc->max_cwperpage);
> +		if (!nandc->bam_txn) {
> +			dev_err(nandc->dev,
> +				"failed to allocate bam transaction\n");
> +			return -ENOMEM;
> +		}
> +	}
> +
>  	list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
>  		ret = qcom_nand_mtd_register(nandc, host, child);
>  		if (ret) {
> 


-- 
Best regards,
Marek Vasut

Re: [PATCH 05/14] qcom: mtd: nand: allocate bam transaction

[Abhishek Sahu]

On 2017-06-29 15:20, Marek Vasut wrote:
> On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
>> The BAM transaction is the core data structure which will be used
>> for all the data transfers in QPIC NAND. Since the base layer is
>> serializing all the NAND requests so allocating BAM transaction
>> before every transfer will be overhead. The memory for it be
>> allocated during probe time and before every transfer, it will be
>> cleared. The BAM transaction contains the array of command
>> elements, command and data scatter gather list and indexes. For
>> every transfer, all the resource will be taken from bam
>> transaction.
>> 
>> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>> ---
>>  drivers/mtd/nand/qcom_nandc.c | 116
>> ++++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 116 insertions(+)
>> 
>> diff --git a/drivers/mtd/nand/qcom_nandc.c 
>> b/drivers/mtd/nand/qcom_nandc.c
>> index eb0ec19..f8d0bde 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -22,6 +22,7 @@
>>  #include <linux/of.h>
>>  #include <linux/of_device.h>
>>  #include <linux/delay.h>
>> +#include <linux/dma/qcom_bam_dma.h>
>> 
>>  /* NANDc reg offsets */
>>  #define	NAND_FLASH_CMD			0x00
>> @@ -169,6 +170,45 @@
>>  #define	ECC_BCH_4BIT	BIT(2)
>>  #define	ECC_BCH_8BIT	BIT(3)
>> 
>> +#define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
>> +#define QPIC_PER_CW_MAX_CMD_SGL		(32)
>> +#define QPIC_PER_CW_MAX_DATA_SGL	(8)
>> +
>> +/*
>> + * This data type corresponds to the BAM transaction which will be 
>> used
>> for all
>> + * NAND transfers.
>> + * @bam_ce - the array of bam command elements
>> + * @cmd_sgl - sgl for nand bam command pipe
>> + * @data_sgl - sgl for nand bam consumer/producer pipe
>> + * @bam_ce_pos - the index in bam_ce which is available for next sgl
>> request
>> + * @bam_ce_start - the index in bam_ce which marks the start position 
>> ce
>> + *		   for current sgl. It will be used for size calculation
>> + *		   for current sgl
>> + * @cmd_sgl_pos - current index in command sgl.
>> + * @tx_sgl_pos - current index in data sgl for tx.
>> + * @rx_sgl_pos - current index in data sgl for rx.
>> + */
>> +struct bam_transaction {
>> +	struct bam_cmd_element *bam_ce;
>> +	struct scatterlist *cmd_sgl;
>> +	struct scatterlist *data_sg;
>> +	u32 bam_ce_pos;
>> +	u32 bam_ce_start;
>> +	u32 cmd_sgl_pos;
>> +	u32 cmd_sgl_start;
>> +	u32 tx_sgl_pos;
>> +	u32 tx_sgl_start;
>> +	u32 rx_sgl_pos;
>> +	u32 rx_sgl_start;
>> +};
>> +
>> +/*
>> + * This data type corresponds to the nand dma descriptor
>> + * @list - list for desc_info
>> + * @dir - DMA transfer direction
>> + * @sgl - sgl which will be used for single sgl dma descriptor
>> + * @dma_desc - low level dma engine descriptor
>> + */
>>  struct desc_info {
>>  	struct list_head node;
>> 
>> @@ -217,6 +257,7 @@ struct nandc_regs {
>>   * @aon_clk:			another controller clock
>>   *
>>   * @chan:			dma channel
>> + * @bam_txn:			contains the bam transaction buffer
>>   * @cmd_crci:			ADM DMA CRCI for command flow control
>>   * @data_crci:			ADM DMA CRCI for data flow control
>>   * @desc_list:			DMA descriptor list (list of desc_infos)
>> @@ -237,6 +278,8 @@ struct nandc_regs {
>>   *				initialized via DT match data
>>   * @dma_bam_enabled:		flag to tell whether nand controller is using
>>   *				bam dma
>> + * @max_cwperpage:		maximum qpic codeword required. calcualted
>> + *				from all nand device pagesize
>>   */
>>  struct qcom_nand_controller {
>>  	struct nand_hw_control controller;
>> @@ -264,12 +307,14 @@ struct qcom_nand_controller {
>>  	};
>> 
>>  	struct list_head desc_list;
>> +	struct bam_transaction *bam_txn;
>> 
>>  	u8		*data_buffer;
>>  	bool		dma_bam_enabled;
>>  	int		buf_size;
>>  	int		buf_count;
>>  	int		buf_start;
>> +	unsigned int	max_cwperpage;
>> 
>>  	__le32 *reg_read_buf;
>>  	dma_addr_t reg_read_buf_phys;
>> @@ -342,6 +387,51 @@ struct qcom_nand_driver_data {
>>  	bool dma_bam_enabled;
>>  };
>> 
>> +/* Frees the BAM transaction memory */
>> +static void free_bam_transaction(struct qcom_nand_controller *nandc)
>> +{
>> +	struct bam_transaction *bam_txn = nandc->bam_txn;
>> +
>> +	devm_kfree(nandc->dev, bam_txn->bam_ce);
>> +	devm_kfree(nandc->dev, bam_txn->cmd_sgl);
>> +	devm_kfree(nandc->dev, bam_txn->data_sg);
>> +	devm_kfree(nandc->dev, bam_txn);
>> +}
>> +
>> +/* Allocates and Initializes the BAM transaction */
>> +static struct bam_transaction *
>> +alloc_bam_transaction(struct qcom_nand_controller *nandc, unsigned 
>> int
>> num_cw)
>> +{
>> +	struct bam_transaction *bam_txn;
>> +
>> +	bam_txn = devm_kzalloc(nandc->dev, sizeof(*bam_txn), GFP_KERNEL);
> 
> Can you make these four allocations into a single allocation ?
> 

  Sure. I will do the same in v2.

>> +	if (!bam_txn)
>> +		return NULL;
>> +
>> +	bam_txn->bam_ce =
>> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->bam_ce) *
>> +			     num_cw * QPIC_PER_CW_MAX_CMD_ELEMENTS, GFP_KERNEL);
>> +	if (!bam_txn->bam_ce)
>> +		return NULL;
>> +
>> +	bam_txn->cmd_sgl =
>> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->cmd_sgl) * num_cw *
>> +			     QPIC_PER_CW_MAX_CMD_SGL, GFP_KERNEL);
>> +	if (!bam_txn->cmd_sgl)
>> +		return NULL;
>> +
>> +	bam_txn->data_sg =
>> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->data_sg) *
>> +			     num_cw * QPIC_PER_CW_MAX_DATA_SGL, GFP_KERNEL);
>> +	if (!bam_txn->data_sg)
>> +		return NULL;
>> +
>> +	nandc->max_cwperpage = num_cw;
>> +
>> +	return bam_txn;
>> +}
>> +
>>  static inline struct qcom_nand_host *to_qcom_nand_host(struct 
>> nand_chip
>> *chip)
>>  {
>>  	return container_of(chip, struct qcom_nand_host, chip);
>> @@ -1868,6 +1958,8 @@ static int qcom_nand_host_setup(struct
>> qcom_nand_host *host)
>>  	mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
>> 
>>  	cwperpage = mtd->writesize / ecc->size;
>> +	nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
>> +					cwperpage);
>> 
>>  	/*
>>  	 * DATA_UD_BYTES varies based on whether the read/write command 
>> protects
>> @@ -2010,6 +2102,19 @@ static int qcom_nandc_alloc(struct
>> qcom_nand_controller *nandc)
>>  			dev_err(nandc->dev, "failed to request cmd channel\n");
>>  			return -ENODEV;
>>  		}
>> +
>> +		/*
>> +		 * Initially allocate BAM transaction to read ONFI param page.
>> +		 * After detecting all the devices, this BAM transaction will
>> +		 * be freed and the next BAM tranasction will be allocated with
>> +		 * maximum codeword size
>> +		 */
>> +		nandc->bam_txn = alloc_bam_transaction(nandc, 1);
>> +		if (!nandc->bam_txn) {
>> +			dev_err(nandc->dev,
>> +				"failed to allocate bam transaction\n");
>> +			return -ENOMEM;
>> +		}
>>  	}
>> 
>>  	INIT_LIST_HEAD(&nandc->desc_list);
>> @@ -2153,6 +2258,17 @@ static int qcom_probe_nand_devices(struct
>> qcom_nand_controller *nandc)
>>  	if (list_empty(&nandc->host_list))
>>  		return -ENODEV;
>> 
>> +	if (nandc->dma_bam_enabled) {
>> +		free_bam_transaction(nandc);
>> +		nandc->bam_txn = alloc_bam_transaction(nandc,
>> +						       nandc->max_cwperpage);
>> +		if (!nandc->bam_txn) {
>> +			dev_err(nandc->dev,
>> +				"failed to allocate bam transaction\n");
>> +			return -ENOMEM;
>> +		}
>> +	}
>> +
>>  	list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
>>  		ret = qcom_nand_mtd_register(nandc, host, child);
>>  		if (ret) {
>> 

-- 
Abhishek Sahu
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Re: [PATCH 05/14] qcom: mtd: nand: allocate bam transaction

[Abhishek Sahu]

On 2017-06-29 15:20, Marek Vasut wrote:
> On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
>> The BAM transaction is the core data structure which will be used
>> for all the data transfers in QPIC NAND. Since the base layer is
>> serializing all the NAND requests so allocating BAM transaction
>> before every transfer will be overhead. The memory for it be
>> allocated during probe time and before every transfer, it will be
>> cleared. The BAM transaction contains the array of command
>> elements, command and data scatter gather list and indexes. For
>> every transfer, all the resource will be taken from bam
>> transaction.
>> 
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> ---
>>  drivers/mtd/nand/qcom_nandc.c | 116
>> ++++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 116 insertions(+)
>> 
>> diff --git a/drivers/mtd/nand/qcom_nandc.c 
>> b/drivers/mtd/nand/qcom_nandc.c
>> index eb0ec19..f8d0bde 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -22,6 +22,7 @@
>>  #include <linux/of.h>
>>  #include <linux/of_device.h>
>>  #include <linux/delay.h>
>> +#include <linux/dma/qcom_bam_dma.h>
>> 
>>  /* NANDc reg offsets */
>>  #define	NAND_FLASH_CMD			0x00
>> @@ -169,6 +170,45 @@
>>  #define	ECC_BCH_4BIT	BIT(2)
>>  #define	ECC_BCH_8BIT	BIT(3)
>> 
>> +#define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
>> +#define QPIC_PER_CW_MAX_CMD_SGL		(32)
>> +#define QPIC_PER_CW_MAX_DATA_SGL	(8)
>> +
>> +/*
>> + * This data type corresponds to the BAM transaction which will be 
>> used
>> for all
>> + * NAND transfers.
>> + * @bam_ce - the array of bam command elements
>> + * @cmd_sgl - sgl for nand bam command pipe
>> + * @data_sgl - sgl for nand bam consumer/producer pipe
>> + * @bam_ce_pos - the index in bam_ce which is available for next sgl
>> request
>> + * @bam_ce_start - the index in bam_ce which marks the start position 
>> ce
>> + *		   for current sgl. It will be used for size calculation
>> + *		   for current sgl
>> + * @cmd_sgl_pos - current index in command sgl.
>> + * @tx_sgl_pos - current index in data sgl for tx.
>> + * @rx_sgl_pos - current index in data sgl for rx.
>> + */
>> +struct bam_transaction {
>> +	struct bam_cmd_element *bam_ce;
>> +	struct scatterlist *cmd_sgl;
>> +	struct scatterlist *data_sg;
>> +	u32 bam_ce_pos;
>> +	u32 bam_ce_start;
>> +	u32 cmd_sgl_pos;
>> +	u32 cmd_sgl_start;
>> +	u32 tx_sgl_pos;
>> +	u32 tx_sgl_start;
>> +	u32 rx_sgl_pos;
>> +	u32 rx_sgl_start;
>> +};
>> +
>> +/*
>> + * This data type corresponds to the nand dma descriptor
>> + * @list - list for desc_info
>> + * @dir - DMA transfer direction
>> + * @sgl - sgl which will be used for single sgl dma descriptor
>> + * @dma_desc - low level dma engine descriptor
>> + */
>>  struct desc_info {
>>  	struct list_head node;
>> 
>> @@ -217,6 +257,7 @@ struct nandc_regs {
>>   * @aon_clk:			another controller clock
>>   *
>>   * @chan:			dma channel
>> + * @bam_txn:			contains the bam transaction buffer
>>   * @cmd_crci:			ADM DMA CRCI for command flow control
>>   * @data_crci:			ADM DMA CRCI for data flow control
>>   * @desc_list:			DMA descriptor list (list of desc_infos)
>> @@ -237,6 +278,8 @@ struct nandc_regs {
>>   *				initialized via DT match data
>>   * @dma_bam_enabled:		flag to tell whether nand controller is using
>>   *				bam dma
>> + * @max_cwperpage:		maximum qpic codeword required. calcualted
>> + *				from all nand device pagesize
>>   */
>>  struct qcom_nand_controller {
>>  	struct nand_hw_control controller;
>> @@ -264,12 +307,14 @@ struct qcom_nand_controller {
>>  	};
>> 
>>  	struct list_head desc_list;
>> +	struct bam_transaction *bam_txn;
>> 
>>  	u8		*data_buffer;
>>  	bool		dma_bam_enabled;
>>  	int		buf_size;
>>  	int		buf_count;
>>  	int		buf_start;
>> +	unsigned int	max_cwperpage;
>> 
>>  	__le32 *reg_read_buf;
>>  	dma_addr_t reg_read_buf_phys;
>> @@ -342,6 +387,51 @@ struct qcom_nand_driver_data {
>>  	bool dma_bam_enabled;
>>  };
>> 
>> +/* Frees the BAM transaction memory */
>> +static void free_bam_transaction(struct qcom_nand_controller *nandc)
>> +{
>> +	struct bam_transaction *bam_txn = nandc->bam_txn;
>> +
>> +	devm_kfree(nandc->dev, bam_txn->bam_ce);
>> +	devm_kfree(nandc->dev, bam_txn->cmd_sgl);
>> +	devm_kfree(nandc->dev, bam_txn->data_sg);
>> +	devm_kfree(nandc->dev, bam_txn);
>> +}
>> +
>> +/* Allocates and Initializes the BAM transaction */
>> +static struct bam_transaction *
>> +alloc_bam_transaction(struct qcom_nand_controller *nandc, unsigned 
>> int
>> num_cw)
>> +{
>> +	struct bam_transaction *bam_txn;
>> +
>> +	bam_txn = devm_kzalloc(nandc->dev, sizeof(*bam_txn), GFP_KERNEL);
> 
> Can you make these four allocations into a single allocation ?
> 

  Sure. I will do the same in v2.

>> +	if (!bam_txn)
>> +		return NULL;
>> +
>> +	bam_txn->bam_ce =
>> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->bam_ce) *
>> +			     num_cw * QPIC_PER_CW_MAX_CMD_ELEMENTS, GFP_KERNEL);
>> +	if (!bam_txn->bam_ce)
>> +		return NULL;
>> +
>> +	bam_txn->cmd_sgl =
>> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->cmd_sgl) * num_cw *
>> +			     QPIC_PER_CW_MAX_CMD_SGL, GFP_KERNEL);
>> +	if (!bam_txn->cmd_sgl)
>> +		return NULL;
>> +
>> +	bam_txn->data_sg =
>> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->data_sg) *
>> +			     num_cw * QPIC_PER_CW_MAX_DATA_SGL, GFP_KERNEL);
>> +	if (!bam_txn->data_sg)
>> +		return NULL;
>> +
>> +	nandc->max_cwperpage = num_cw;
>> +
>> +	return bam_txn;
>> +}
>> +
>>  static inline struct qcom_nand_host *to_qcom_nand_host(struct 
>> nand_chip
>> *chip)
>>  {
>>  	return container_of(chip, struct qcom_nand_host, chip);
>> @@ -1868,6 +1958,8 @@ static int qcom_nand_host_setup(struct
>> qcom_nand_host *host)
>>  	mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
>> 
>>  	cwperpage = mtd->writesize / ecc->size;
>> +	nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
>> +					cwperpage);
>> 
>>  	/*
>>  	 * DATA_UD_BYTES varies based on whether the read/write command 
>> protects
>> @@ -2010,6 +2102,19 @@ static int qcom_nandc_alloc(struct
>> qcom_nand_controller *nandc)
>>  			dev_err(nandc->dev, "failed to request cmd channel\n");
>>  			return -ENODEV;
>>  		}
>> +
>> +		/*
>> +		 * Initially allocate BAM transaction to read ONFI param page.
>> +		 * After detecting all the devices, this BAM transaction will
>> +		 * be freed and the next BAM tranasction will be allocated with
>> +		 * maximum codeword size
>> +		 */
>> +		nandc->bam_txn = alloc_bam_transaction(nandc, 1);
>> +		if (!nandc->bam_txn) {
>> +			dev_err(nandc->dev,
>> +				"failed to allocate bam transaction\n");
>> +			return -ENOMEM;
>> +		}
>>  	}
>> 
>>  	INIT_LIST_HEAD(&nandc->desc_list);
>> @@ -2153,6 +2258,17 @@ static int qcom_probe_nand_devices(struct
>> qcom_nand_controller *nandc)
>>  	if (list_empty(&nandc->host_list))
>>  		return -ENODEV;
>> 
>> +	if (nandc->dma_bam_enabled) {
>> +		free_bam_transaction(nandc);
>> +		nandc->bam_txn = alloc_bam_transaction(nandc,
>> +						       nandc->max_cwperpage);
>> +		if (!nandc->bam_txn) {
>> +			dev_err(nandc->dev,
>> +				"failed to allocate bam transaction\n");
>> +			return -ENOMEM;
>> +		}
>> +	}
>> +
>>  	list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
>>  		ret = qcom_nand_mtd_register(nandc, host, child);
>>  		if (ret) {
>> 

-- 
Abhishek Sahu

Re: [PATCH 05/14] qcom: mtd: nand: allocate bam transaction

[Sricharan R]

Hi Abhishek,

<..>

> +/* Allocates and Initializes the BAM transaction */
> +static struct bam_transaction *
> +alloc_bam_transaction(struct qcom_nand_controller *nandc, unsigned int num_cw)
> +{
> +	struct bam_transaction *bam_txn;
> +
> +	bam_txn = devm_kzalloc(nandc->dev, sizeof(*bam_txn), GFP_KERNEL);
> +
> +	if (!bam_txn)
> +		return NULL;
> +
> +	bam_txn->bam_ce =
> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->bam_ce) *
> +			     num_cw * QPIC_PER_CW_MAX_CMD_ELEMENTS, GFP_KERNEL);
> +	if (!bam_txn->bam_ce)
> +		return NULL;
> +
> +	bam_txn->cmd_sgl =
> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->cmd_sgl) * num_cw *
> +			     QPIC_PER_CW_MAX_CMD_SGL, GFP_KERNEL);
> +	if (!bam_txn->cmd_sgl)
> +		return NULL;
> +
> +	bam_txn->data_sg =
> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->data_sg) *
> +			     num_cw * QPIC_PER_CW_MAX_DATA_SGL, GFP_KERNEL);
> +	if (!bam_txn->data_sg)
> +		return NULL;
> +
> +	nandc->max_cwperpage = num_cw;
> +
> +	return bam_txn;
> +}
> +
>  static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>  {
>  	return container_of(chip, struct qcom_nand_host, chip);
> @@ -1868,6 +1958,8 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
>  	mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
>  
>  	cwperpage = mtd->writesize / ecc->size;
> +	nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
> +					cwperpage);
>  
>  	/*
>  	 * DATA_UD_BYTES varies based on whether the read/write command protects
> @@ -2010,6 +2102,19 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>  			dev_err(nandc->dev, "failed to request cmd channel\n");
>  			return -ENODEV;
>  		}
> +
> +		/*
> +		 * Initially allocate BAM transaction to read ONFI param page.
> +		 * After detecting all the devices, this BAM transaction will
> +		 * be freed and the next BAM tranasction will be allocated with
> +		 * maximum codeword size
> +		 */
> +		nandc->bam_txn = alloc_bam_transaction(nandc, 1);
> +		if (!nandc->bam_txn) {
> +			dev_err(nandc->dev,
> +				"failed to allocate bam transaction\n");
> +			return -ENOMEM;
> +		}
>  	}
>  
>  	INIT_LIST_HEAD(&nandc->desc_list);
> @@ -2153,6 +2258,17 @@ static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
>  	if (list_empty(&nandc->host_list))
>  		return -ENODEV;
>  
> +	if (nandc->dma_bam_enabled) {
> +		free_bam_transaction(nandc);
> +		nandc->bam_txn = alloc_bam_transaction(nandc,
> +						       nandc->max_cwperpage);

 Somehow, looks like something is missing because, nandc->max_cwperpage passed from
 here is used in alloc_bam_transaction, but it is assigned in the same function ?

Regards,
 Sricharan

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Re: [PATCH 05/14] qcom: mtd: nand: allocate bam transaction

[Abhishek Sahu]

On 2017-07-03 13:52, Sricharan R wrote:
> Hi Abhishek,
> 
> <..>
> 
>> +/* Allocates and Initializes the BAM transaction */
>> +static struct bam_transaction *
>> +alloc_bam_transaction(struct qcom_nand_controller *nandc, unsigned 
>> int
>> num_cw)
>> +{
>> +	struct bam_transaction *bam_txn;
>> +
>> +	bam_txn = devm_kzalloc(nandc->dev, sizeof(*bam_txn), GFP_KERNEL);
>> +
>> +	if (!bam_txn)
>> +		return NULL;
>> +
>> +	bam_txn->bam_ce =
>> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->bam_ce) *
>> +			     num_cw * QPIC_PER_CW_MAX_CMD_ELEMENTS, GFP_KERNEL);
>> +	if (!bam_txn->bam_ce)
>> +		return NULL;
>> +
>> +	bam_txn->cmd_sgl =
>> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->cmd_sgl) * num_cw *
>> +			     QPIC_PER_CW_MAX_CMD_SGL, GFP_KERNEL);
>> +	if (!bam_txn->cmd_sgl)
>> +		return NULL;
>> +
>> +	bam_txn->data_sg =
>> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->data_sg) *
>> +			     num_cw * QPIC_PER_CW_MAX_DATA_SGL, GFP_KERNEL);
>> +	if (!bam_txn->data_sg)
>> +		return NULL;
>> +
>> +	nandc->max_cwperpage = num_cw;
>> +
>> +	return bam_txn;
>> +}
>> +
>>  static inline struct qcom_nand_host *to_qcom_nand_host(struct 
>> nand_chip
>> *chip)
>>  {
>>  	return container_of(chip, struct qcom_nand_host, chip);
>> @@ -1868,6 +1958,8 @@ static int qcom_nand_host_setup(struct
>> qcom_nand_host *host)
>>  	mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
>> 
>>  	cwperpage = mtd->writesize / ecc->size;
>> +	nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
>> +					cwperpage);
>> 
>>  	/*
>>  	 * DATA_UD_BYTES varies based on whether the read/write command 
>> protects
>> @@ -2010,6 +2102,19 @@ static int qcom_nandc_alloc(struct
>> qcom_nand_controller *nandc)
>>  			dev_err(nandc->dev, "failed to request cmd channel\n");
>>  			return -ENODEV;
>>  		}
>> +
>> +		/*
>> +		 * Initially allocate BAM transaction to read ONFI param page.
>> +		 * After detecting all the devices, this BAM transaction will
>> +		 * be freed and the next BAM tranasction will be allocated with
>> +		 * maximum codeword size
>> +		 */
>> +		nandc->bam_txn = alloc_bam_transaction(nandc, 1);
>> +		if (!nandc->bam_txn) {
>> +			dev_err(nandc->dev,
>> +				"failed to allocate bam transaction\n");
>> +			return -ENOMEM;
>> +		}
>>  	}
>> 
>>  	INIT_LIST_HEAD(&nandc->desc_list);
>> @@ -2153,6 +2258,17 @@ static int qcom_probe_nand_devices(struct
>> qcom_nand_controller *nandc)
>>  	if (list_empty(&nandc->host_list))
>>  		return -ENODEV;
>> 
>> +	if (nandc->dma_bam_enabled) {
>> +		free_bam_transaction(nandc);
>> +		nandc->bam_txn = alloc_bam_transaction(nandc,
>> +						       nandc->max_cwperpage);
> 
>  Somehow, looks like something is missing because, nandc->max_cwperpage
> passed from
>  here is used in alloc_bam_transaction, but it is assigned in the same
> function ?
> 

  Yes. This assignment is not required. I will fix this in v2.

> Regards,
>  Sricharan

-- 
Abhishek Sahu
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Re: [PATCH 05/14] qcom: mtd: nand: allocate bam transaction

[Abhishek Sahu]

On 2017-07-03 13:52, Sricharan R wrote:
> Hi Abhishek,
> 
> <..>
> 
>> +/* Allocates and Initializes the BAM transaction */
>> +static struct bam_transaction *
>> +alloc_bam_transaction(struct qcom_nand_controller *nandc, unsigned 
>> int
>> num_cw)
>> +{
>> +	struct bam_transaction *bam_txn;
>> +
>> +	bam_txn = devm_kzalloc(nandc->dev, sizeof(*bam_txn), GFP_KERNEL);
>> +
>> +	if (!bam_txn)
>> +		return NULL;
>> +
>> +	bam_txn->bam_ce =
>> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->bam_ce) *
>> +			     num_cw * QPIC_PER_CW_MAX_CMD_ELEMENTS, GFP_KERNEL);
>> +	if (!bam_txn->bam_ce)
>> +		return NULL;
>> +
>> +	bam_txn->cmd_sgl =
>> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->cmd_sgl) * num_cw *
>> +			     QPIC_PER_CW_MAX_CMD_SGL, GFP_KERNEL);
>> +	if (!bam_txn->cmd_sgl)
>> +		return NULL;
>> +
>> +	bam_txn->data_sg =
>> +		devm_kzalloc(nandc->dev, sizeof(*bam_txn->data_sg) *
>> +			     num_cw * QPIC_PER_CW_MAX_DATA_SGL, GFP_KERNEL);
>> +	if (!bam_txn->data_sg)
>> +		return NULL;
>> +
>> +	nandc->max_cwperpage = num_cw;
>> +
>> +	return bam_txn;
>> +}
>> +
>>  static inline struct qcom_nand_host *to_qcom_nand_host(struct 
>> nand_chip
>> *chip)
>>  {
>>  	return container_of(chip, struct qcom_nand_host, chip);
>> @@ -1868,6 +1958,8 @@ static int qcom_nand_host_setup(struct
>> qcom_nand_host *host)
>>  	mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
>> 
>>  	cwperpage = mtd->writesize / ecc->size;
>> +	nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
>> +					cwperpage);
>> 
>>  	/*
>>  	 * DATA_UD_BYTES varies based on whether the read/write command 
>> protects
>> @@ -2010,6 +2102,19 @@ static int qcom_nandc_alloc(struct
>> qcom_nand_controller *nandc)
>>  			dev_err(nandc->dev, "failed to request cmd channel\n");
>>  			return -ENODEV;
>>  		}
>> +
>> +		/*
>> +		 * Initially allocate BAM transaction to read ONFI param page.
>> +		 * After detecting all the devices, this BAM transaction will
>> +		 * be freed and the next BAM tranasction will be allocated with
>> +		 * maximum codeword size
>> +		 */
>> +		nandc->bam_txn = alloc_bam_transaction(nandc, 1);
>> +		if (!nandc->bam_txn) {
>> +			dev_err(nandc->dev,
>> +				"failed to allocate bam transaction\n");
>> +			return -ENOMEM;
>> +		}
>>  	}
>> 
>>  	INIT_LIST_HEAD(&nandc->desc_list);
>> @@ -2153,6 +2258,17 @@ static int qcom_probe_nand_devices(struct
>> qcom_nand_controller *nandc)
>>  	if (list_empty(&nandc->host_list))
>>  		return -ENODEV;
>> 
>> +	if (nandc->dma_bam_enabled) {
>> +		free_bam_transaction(nandc);
>> +		nandc->bam_txn = alloc_bam_transaction(nandc,
>> +						       nandc->max_cwperpage);
> 
>  Somehow, looks like something is missing because, nandc->max_cwperpage
> passed from
>  here is used in alloc_bam_transaction, but it is assigned in the same
> function ?
> 

  Yes. This assignment is not required. I will fix this in v2.

> Regards,
>  Sricharan

-- 
Abhishek Sahu

[PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA

[Abhishek Sahu]

The current driver only support EBI2 NAND which uses ADM DMA. The
latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
registers and programming sequence are same for EBI2 and QPIC
NAND so the same driver can support QPIC NAND also by adding the
BAM DMA support. This patch adds the QPIC NAND support in current
NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
maps it with different configuration parameter in driver data.

Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 .../devicetree/bindings/mtd/qcom_nandc.txt         | 41 +++++++++++++++++++++-
 drivers/mtd/nand/qcom_nandc.c                      | 37 ++++++++++++++++---
 2 files changed, 73 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index 70dd511..5d0f7ae 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -1,7 +1,9 @@
 * Qualcomm NAND controller
 
 Required properties:
-- compatible:		should be "qcom,ipq806x-nand"
+- compatible:		must be one of the following:
+	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
+	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
 - reg:			MMIO address range
 - clocks:		must contain core clock and always on clock
 - clock-names:		must contain "core" for the core clock and "aon" for the
@@ -84,3 +86,40 @@ nand@1ac00000 {
 		};
 	};
 };
+
+nand@79b0000 {
+	compatible = "qcom,qpic-nandc-v1.4.0";
+	reg = <0x79b0000 0x1000>;
+
+	clocks = <&gcc GCC_QPIC_CLK>,
+		<&gcc GCC_QPIC_AHB_CLK>;
+	clock-names = "core", "aon";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@0 {
+		compatible = "qcom,nandcs";
+		reg = <0>;
+
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "boot-nand";
+				reg = <0 0x58a0000>;
+			};
+
+			partition@58a0000 {
+				label = "fs-nand";
+				reg = <0x58a0000 0x4000000>;
+			};
+		};
+	};
+};
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 57d483a..f55f728 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -234,6 +234,8 @@ struct nandc_regs {
  * @cmd1/vld:			some fixed controller register values
  * @ecc_modes:			supported ECC modes by the current controller,
  *				initialized via DT match data
+ * @dma_bam_enabled:		flag to tell whether nand controller is using
+ *				bam dma
  */
 struct qcom_nand_controller {
 	struct nand_hw_control controller;
@@ -253,6 +255,7 @@ struct qcom_nand_controller {
 	struct list_head desc_list;
 
 	u8		*data_buffer;
+	bool		dma_bam_enabled;
 	int		buf_size;
 	int		buf_count;
 	int		buf_start;
@@ -316,6 +319,17 @@ struct qcom_nand_host {
 	u32 clrreadstatus;
 };
 
+/*
+ * This data type corresponds to the nand driver data which will be used at
+ * driver probe time
+ * @ecc_modes - ecc mode for nand
+ * @dma_bam_enabled - whether this driver is using bam
+ */
+struct qcom_nand_driver_data {
+	u32 ecc_modes;
+	bool dma_bam_enabled;
+};
+
 static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
 {
 	return container_of(chip, struct qcom_nand_host, chip);
@@ -2073,6 +2087,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 	struct device_node *dn = dev->of_node, *child;
 	struct resource *res;
 	int ret;
+	const struct qcom_nand_driver_data *driver_data;
 
 	nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
 	if (!nandc)
@@ -2087,7 +2102,10 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	nandc->ecc_modes = (unsigned long)dev_data;
+	driver_data = (const struct qcom_nand_driver_data *)dev_data;
+
+	nandc->ecc_modes = driver_data->ecc_modes;
+	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	nandc->base = devm_ioremap_resource(dev, res);
@@ -2179,15 +2197,26 @@ static int qcom_nandc_remove(struct platform_device *pdev)
 	return 0;
 }
 
-#define EBI2_NANDC_ECC_MODES	(ECC_RS_4BIT | ECC_BCH_8BIT)
 
+static const struct qcom_nand_driver_data ebi2_nandc_data = {
+	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
+	.dma_bam_enabled = false,
+};
+
+static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
+	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
+	.dma_bam_enabled = true,
+};
 /*
  * data will hold a struct pointer containing more differences once we support
  * more controller variants
  */
 static const struct of_device_id qcom_nandc_of_match[] = {
 	{	.compatible = "qcom,ipq806x-nand",
-		.data = (void *)EBI2_NANDC_ECC_MODES,
+		.data = (void *)&ebi2_nandc_data,
+	},
+	{	.compatible = "qcom,qpic-nandc-v1.4.0",
+		.data = (void *)&qpic_nandc_v1_4_0_data,
 	},
 	{}
 };
-- 
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[PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA

[Abhishek Sahu]

The current driver only support EBI2 NAND which uses ADM DMA. The
latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
registers and programming sequence are same for EBI2 and QPIC
NAND so the same driver can support QPIC NAND also by adding the
BAM DMA support. This patch adds the QPIC NAND support in current
NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
maps it with different configuration parameter in driver data.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 .../devicetree/bindings/mtd/qcom_nandc.txt         | 41 +++++++++++++++++++++-
 drivers/mtd/nand/qcom_nandc.c                      | 37 ++++++++++++++++---
 2 files changed, 73 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index 70dd511..5d0f7ae 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -1,7 +1,9 @@
 * Qualcomm NAND controller
 
 Required properties:
-- compatible:		should be "qcom,ipq806x-nand"
+- compatible:		must be one of the following:
+	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
+	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
 - reg:			MMIO address range
 - clocks:		must contain core clock and always on clock
 - clock-names:		must contain "core" for the core clock and "aon" for the
@@ -84,3 +86,40 @@ nand@1ac00000 {
 		};
 	};
 };
+
+nand@79b0000 {
+	compatible = "qcom,qpic-nandc-v1.4.0";
+	reg = <0x79b0000 0x1000>;
+
+	clocks = <&gcc GCC_QPIC_CLK>,
+		<&gcc GCC_QPIC_AHB_CLK>;
+	clock-names = "core", "aon";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@0 {
+		compatible = "qcom,nandcs";
+		reg = <0>;
+
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "boot-nand";
+				reg = <0 0x58a0000>;
+			};
+
+			partition@58a0000 {
+				label = "fs-nand";
+				reg = <0x58a0000 0x4000000>;
+			};
+		};
+	};
+};
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 57d483a..f55f728 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -234,6 +234,8 @@ struct nandc_regs {
  * @cmd1/vld:			some fixed controller register values
  * @ecc_modes:			supported ECC modes by the current controller,
  *				initialized via DT match data
+ * @dma_bam_enabled:		flag to tell whether nand controller is using
+ *				bam dma
  */
 struct qcom_nand_controller {
 	struct nand_hw_control controller;
@@ -253,6 +255,7 @@ struct qcom_nand_controller {
 	struct list_head desc_list;
 
 	u8		*data_buffer;
+	bool		dma_bam_enabled;
 	int		buf_size;
 	int		buf_count;
 	int		buf_start;
@@ -316,6 +319,17 @@ struct qcom_nand_host {
 	u32 clrreadstatus;
 };
 
+/*
+ * This data type corresponds to the nand driver data which will be used at
+ * driver probe time
+ * @ecc_modes - ecc mode for nand
+ * @dma_bam_enabled - whether this driver is using bam
+ */
+struct qcom_nand_driver_data {
+	u32 ecc_modes;
+	bool dma_bam_enabled;
+};
+
 static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
 {
 	return container_of(chip, struct qcom_nand_host, chip);
@@ -2073,6 +2087,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 	struct device_node *dn = dev->of_node, *child;
 	struct resource *res;
 	int ret;
+	const struct qcom_nand_driver_data *driver_data;
 
 	nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
 	if (!nandc)
@@ -2087,7 +2102,10 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	nandc->ecc_modes = (unsigned long)dev_data;
+	driver_data = (const struct qcom_nand_driver_data *)dev_data;
+
+	nandc->ecc_modes = driver_data->ecc_modes;
+	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	nandc->base = devm_ioremap_resource(dev, res);
@@ -2179,15 +2197,26 @@ static int qcom_nandc_remove(struct platform_device *pdev)
 	return 0;
 }
 
-#define EBI2_NANDC_ECC_MODES	(ECC_RS_4BIT | ECC_BCH_8BIT)
 
+static const struct qcom_nand_driver_data ebi2_nandc_data = {
+	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
+	.dma_bam_enabled = false,
+};
+
+static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
+	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
+	.dma_bam_enabled = true,
+};
 /*
  * data will hold a struct pointer containing more differences once we support
  * more controller variants
  */
 static const struct of_device_id qcom_nandc_of_match[] = {
 	{	.compatible = "qcom,ipq806x-nand",
-		.data = (void *)EBI2_NANDC_ECC_MODES,
+		.data = (void *)&ebi2_nandc_data,
+	},
+	{	.compatible = "qcom,qpic-nandc-v1.4.0",
+		.data = (void *)&qpic_nandc_v1_4_0_data,
 	},
 	{}
 };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA

[Marek Vasut]

On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
> The current driver only support EBI2 NAND which uses ADM DMA. The
> latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
> registers and programming sequence are same for EBI2 and QPIC
> NAND so the same driver can support QPIC NAND also by adding the
> BAM DMA support. This patch adds the QPIC NAND support in current
> NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
> maps it with different configuration parameter in driver data.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>

Split this into DT bindings patch and code patch ...

> ---
>  .../devicetree/bindings/mtd/qcom_nandc.txt         | 41 +++++++++++++++++++++-
>  drivers/mtd/nand/qcom_nandc.c                      | 37 ++++++++++++++++---
>  2 files changed, 73 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 70dd511..5d0f7ae 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -1,7 +1,9 @@
>  * Qualcomm NAND controller
>  
>  Required properties:
> -- compatible:		should be "qcom,ipq806x-nand"
> +- compatible:		must be one of the following:
> +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
> +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
>  - reg:			MMIO address range
>  - clocks:		must contain core clock and always on clock
>  - clock-names:		must contain "core" for the core clock and "aon" for the
> @@ -84,3 +86,40 @@ nand@1ac00000 {
>  		};
>  	};
>  };
> +
> +nand@79b0000 {
> +	compatible = "qcom,qpic-nandc-v1.4.0";
> +	reg = <0x79b0000 0x1000>;
> +
> +	clocks = <&gcc GCC_QPIC_CLK>,
> +		<&gcc GCC_QPIC_AHB_CLK>;
> +	clock-names = "core", "aon";
> +
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	nandcs@0 {
> +		compatible = "qcom,nandcs";
> +		reg = <0>;
> +
> +		nand-ecc-strength = <4>;
> +		nand-ecc-step-size = <512>;
> +		nand-bus-width = <8>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				label = "boot-nand";
> +				reg = <0 0x58a0000>;
> +			};
> +
> +			partition@58a0000 {
> +				label = "fs-nand";
> +				reg = <0x58a0000 0x4000000>;
> +			};
> +		};
> +	};
> +};
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 57d483a..f55f728 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
>   *
>   * This software is licensed under the terms of the GNU General Public
>   * License version 2, as published by the Free Software Foundation, and
> @@ -234,6 +234,8 @@ struct nandc_regs {
>   * @cmd1/vld:			some fixed controller register values
>   * @ecc_modes:			supported ECC modes by the current controller,
>   *				initialized via DT match data
> + * @dma_bam_enabled:		flag to tell whether nand controller is using
> + *				bam dma
>   */
>  struct qcom_nand_controller {
>  	struct nand_hw_control controller;
> @@ -253,6 +255,7 @@ struct qcom_nand_controller {
>  	struct list_head desc_list;
>  
>  	u8		*data_buffer;
> +	bool		dma_bam_enabled;
>  	int		buf_size;
>  	int		buf_count;
>  	int		buf_start;
> @@ -316,6 +319,17 @@ struct qcom_nand_host {
>  	u32 clrreadstatus;
>  };
>  
> +/*
> + * This data type corresponds to the nand driver data which will be used at
> + * driver probe time
> + * @ecc_modes - ecc mode for nand
> + * @dma_bam_enabled - whether this driver is using bam
> + */
> +struct qcom_nand_driver_data {
> +	u32 ecc_modes;
> +	bool dma_bam_enabled;
> +};
> +
>  static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>  {
>  	return container_of(chip, struct qcom_nand_host, chip);
> @@ -2073,6 +2087,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>  	struct device_node *dn = dev->of_node, *child;
>  	struct resource *res;
>  	int ret;
> +	const struct qcom_nand_driver_data *driver_data;
>  
>  	nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
>  	if (!nandc)
> @@ -2087,7 +2102,10 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>  		return -ENODEV;
>  	}
>  
> -	nandc->ecc_modes = (unsigned long)dev_data;
> +	driver_data = (const struct qcom_nand_driver_data *)dev_data;
> +
> +	nandc->ecc_modes = driver_data->ecc_modes;
> +	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
>  
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	nandc->base = devm_ioremap_resource(dev, res);
> @@ -2179,15 +2197,26 @@ static int qcom_nandc_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -#define EBI2_NANDC_ECC_MODES	(ECC_RS_4BIT | ECC_BCH_8BIT)
>  
> +static const struct qcom_nand_driver_data ebi2_nandc_data = {
> +	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
> +	.dma_bam_enabled = false,
> +};
> +
> +static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
> +	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
> +	.dma_bam_enabled = true,
> +};
>  /*
>   * data will hold a struct pointer containing more differences once we support
>   * more controller variants
>   */
>  static const struct of_device_id qcom_nandc_of_match[] = {
>  	{	.compatible = "qcom,ipq806x-nand",
> -		.data = (void *)EBI2_NANDC_ECC_MODES,
> +		.data = (void *)&ebi2_nandc_data,
> +	},
> +	{	.compatible = "qcom,qpic-nandc-v1.4.0",
> +		.data = (void *)&qpic_nandc_v1_4_0_data,
>  	},
>  	{}
>  };
> 


-- 
Best regards,
Marek Vasut

Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA

[Archit Taneja]

On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
> The current driver only support EBI2 NAND which uses ADM DMA. The
> latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
> registers and programming sequence are same for EBI2 and QPIC
> NAND so the same driver can support QPIC NAND also by adding the
> BAM DMA support. This patch adds the QPIC NAND support in current
> NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
> maps it with different configuration parameter in driver data.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>   .../devicetree/bindings/mtd/qcom_nandc.txt         | 41 +++++++++++++++++++++-
>   drivers/mtd/nand/qcom_nandc.c                      | 37 ++++++++++++++++---
>   2 files changed, 73 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 70dd511..5d0f7ae 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -1,7 +1,9 @@
>   * Qualcomm NAND controller
>   
>   Required properties:
> -- compatible:		should be "qcom,ipq806x-nand"

Since you're changing the compatible string, could you mention in the commit message that
it's okay to do so since there aren't any upstream dtsi files using this binding?

> +- compatible:		must be one of the following:
> +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.

Are we sure that all EBI2 based NAND controllers would work by this single binding?
Should we put a version here too like we've done for QPIC?

> +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
>   - reg:			MMIO address range
>   - clocks:		must contain core clock and always on clock
>   - clock-names:		must contain "core" for the core clock and "aon" for the
> @@ -84,3 +86,40 @@ nand@1ac00000 {
>   		};
>   	};
>   };
> +
> +nand@79b0000 {
> +	compatible = "qcom,qpic-nandc-v1.4.0";
> +	reg = <0x79b0000 0x1000>;
> +
> +	clocks = <&gcc GCC_QPIC_CLK>,
> +		<&gcc GCC_QPIC_AHB_CLK>;
> +	clock-names = "core", "aon";
> +
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	nandcs@0 {
> +		compatible = "qcom,nandcs";
> +		reg = <0>;
> +
> +		nand-ecc-strength = <4>;
> +		nand-ecc-step-size = <512>;
> +		nand-bus-width = <8>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				label = "boot-nand";
> +				reg = <0 0x58a0000>;
> +			};
> +
> +			partition@58a0000 {
> +				label = "fs-nand";
> +				reg = <0x58a0000 0x4000000>;
> +			};
> +		};
> +	};
> +};
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 57d483a..f55f728 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -1,5 +1,5 @@
>   /*
> - * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
>    *
>    * This software is licensed under the terms of the GNU General Public
>    * License version 2, as published by the Free Software Foundation, and
> @@ -234,6 +234,8 @@ struct nandc_regs {
>    * @cmd1/vld:			some fixed controller register values
>    * @ecc_modes:			supported ECC modes by the current controller,
>    *				initialized via DT match data
> + * @dma_bam_enabled:		flag to tell whether nand controller is using
> + *				bam dma
>    */
>   struct qcom_nand_controller {
>   	struct nand_hw_control controller;
> @@ -253,6 +255,7 @@ struct qcom_nand_controller {
>   	struct list_head desc_list;
>   
>   	u8		*data_buffer;
> +	bool		dma_bam_enabled;
>   	int		buf_size;
>   	int		buf_count;
>   	int		buf_start;
> @@ -316,6 +319,17 @@ struct qcom_nand_host {
>   	u32 clrreadstatus;
>   };
>   
> +/*
> + * This data type corresponds to the nand driver data which will be used at
> + * driver probe time
> + * @ecc_modes - ecc mode for nand
> + * @dma_bam_enabled - whether this driver is using bam
> + */
> +struct qcom_nand_driver_data {
> +	u32 ecc_modes;
> +	bool dma_bam_enabled;
> +};
> +
>   static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>   {
>   	return container_of(chip, struct qcom_nand_host, chip);
> @@ -2073,6 +2087,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>   	struct device_node *dn = dev->of_node, *child;
>   	struct resource *res;
>   	int ret;
> +	const struct qcom_nand_driver_data *driver_data;
>   
>   	nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
>   	if (!nandc)
> @@ -2087,7 +2102,10 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>   		return -ENODEV;
>   	}
>   
> -	nandc->ecc_modes = (unsigned long)dev_data;
> +	driver_data = (const struct qcom_nand_driver_data *)dev_data;
> +
> +	nandc->ecc_modes = driver_data->ecc_modes;
> +	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
>   
>   	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>   	nandc->base = devm_ioremap_resource(dev, res);
> @@ -2179,15 +2197,26 @@ static int qcom_nandc_remove(struct platform_device *pdev)
>   	return 0;
>   }
>   
> -#define EBI2_NANDC_ECC_MODES	(ECC_RS_4BIT | ECC_BCH_8BIT)
>   
> +static const struct qcom_nand_driver_data ebi2_nandc_data = {
> +	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
> +	.dma_bam_enabled = false,
> +};
> +
> +static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
> +	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
> +	.dma_bam_enabled = true,
> +};
>   /*
>    * data will hold a struct pointer containing more differences once we support
>    * more controller variants
>    */
>   static const struct of_device_id qcom_nandc_of_match[] = {
>   	{	.compatible = "qcom,ipq806x-nand",

Please make sure that you update the compatible string above too.

Thanks,
Archit

> -		.data = (void *)EBI2_NANDC_ECC_MODES,
> +		.data = (void *)&ebi2_nandc_data,
> +	},
> +	{	.compatible = "qcom,qpic-nandc-v1.4.0",
> +		.data = (void *)&qpic_nandc_v1_4_0_data,
>   	},
>   	{}
>   };
> 

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA

[Boris Brezillon]

On Mon, 3 Jul 2017 10:08:32 +0530
Archit Taneja <architt@codeaurora.org> wrote:

> On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
> > The current driver only support EBI2 NAND which uses ADM DMA. The
> > latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
> > registers and programming sequence are same for EBI2 and QPIC
> > NAND so the same driver can support QPIC NAND also by adding the
> > BAM DMA support. This patch adds the QPIC NAND support in current
> > NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
> > maps it with different configuration parameter in driver data.
> > 
> > Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> > ---
> >   .../devicetree/bindings/mtd/qcom_nandc.txt         | 41 +++++++++++++++++++++-
> >   drivers/mtd/nand/qcom_nandc.c                      | 37 ++++++++++++++++---
> >   2 files changed, 73 insertions(+), 5 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> > index 70dd511..5d0f7ae 100644
> > --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> > +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> > @@ -1,7 +1,9 @@
> >   * Qualcomm NAND controller
> >   
> >   Required properties:
> > -- compatible:		should be "qcom,ipq806x-nand"  
> 
> Since you're changing the compatible string, could you mention in the commit message that
> it's okay to do so since there aren't any upstream dtsi files using this binding?

Yep. I was going to ask about backward compat, but I guess it's fine if
there's no user in mainline yet, just mention it in the commit message
as suggested by Archit.

> 
> > +- compatible:		must be one of the following:
> > +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.  
> 
> Are we sure that all EBI2 based NAND controllers would work by this single binding?
> Should we put a version here too like we've done for QPIC?
> 
> > +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
> >   - reg:			MMIO address range
> >   - clocks:		must contain core clock and always on clock
> >   - clock-names:		must contain "core" for the core clock and "aon" for the
> > @@ -84,3 +86,40 @@ nand@1ac00000 {
> >   		};
> >   	};
> >   };
> > +
> > +nand@79b0000 {

nand-controller@xxxx {

BTW, glad to see another driver moving to the new DT representation :-).

> > +	compatible = "qcom,qpic-nandc-v1.4.0";
> > +	reg = <0x79b0000 0x1000>;
> > +
> > +	clocks = <&gcc GCC_QPIC_CLK>,
> > +		<&gcc GCC_QPIC_AHB_CLK>;
> > +	clock-names = "core", "aon";
> > +
> > +	#address-cells = <1>;
> > +	#size-cells = <0>;
> > +
> > +	nandcs@0 {

	nand@0 {

> > +		compatible = "qcom,nandcs";

Why do you need a compatible here?

> > +		reg = <0>;
> > +
> > +		nand-ecc-strength = <4>;
> > +		nand-ecc-step-size = <512>;
> > +		nand-bus-width = <8>;
> > +
> > +		partitions {
> > +			compatible = "fixed-partitions";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +
> > +			partition@0 {
> > +				label = "boot-nand";
> > +				reg = <0 0x58a0000>;
> > +			};
> > +
> > +			partition@58a0000 {
> > +				label = "fs-nand";
> > +				reg = <0x58a0000 0x4000000>;
> > +			};
> > +		};
> > +	};
> > +};
> > diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> > index 57d483a..f55f728 100644
> > --- a/drivers/mtd/nand/qcom_nandc.c
> > +++ b/drivers/mtd/nand/qcom_nandc.c
> > @@ -1,5 +1,5 @@
> >   /*
> > - * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> > + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
> >    *
> >    * This software is licensed under the terms of the GNU General Public
> >    * License version 2, as published by the Free Software Foundation, and
> > @@ -234,6 +234,8 @@ struct nandc_regs {
> >    * @cmd1/vld:			some fixed controller register values
> >    * @ecc_modes:			supported ECC modes by the current controller,
> >    *				initialized via DT match data
> > + * @dma_bam_enabled:		flag to tell whether nand controller is using
> > + *				bam dma
> >    */
> >   struct qcom_nand_controller {
> >   	struct nand_hw_control controller;
> > @@ -253,6 +255,7 @@ struct qcom_nand_controller {
> >   	struct list_head desc_list;
> >   
> >   	u8		*data_buffer;
> > +	bool		dma_bam_enabled;
> >   	int		buf_size;
> >   	int		buf_count;
> >   	int		buf_start;
> > @@ -316,6 +319,17 @@ struct qcom_nand_host {
> >   	u32 clrreadstatus;
> >   };
> >   
> > +/*
> > + * This data type corresponds to the nand driver data which will be used at
> > + * driver probe time
> > + * @ecc_modes - ecc mode for nand
> > + * @dma_bam_enabled - whether this driver is using bam
> > + */
> > +struct qcom_nand_driver_data {
> > +	u32 ecc_modes;
> > +	bool dma_bam_enabled;
> > +};
> > +
> >   static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
> >   {
> >   	return container_of(chip, struct qcom_nand_host, chip);
> > @@ -2073,6 +2087,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
> >   	struct device_node *dn = dev->of_node, *child;
> >   	struct resource *res;
> >   	int ret;
> > +	const struct qcom_nand_driver_data *driver_data;
> >   
> >   	nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
> >   	if (!nandc)
> > @@ -2087,7 +2102,10 @@ static int qcom_nandc_probe(struct platform_device *pdev)
> >   		return -ENODEV;
> >   	}
> >   
> > -	nandc->ecc_modes = (unsigned long)dev_data;
> > +	driver_data = (const struct qcom_nand_driver_data *)dev_data;

Cast is unneeded here.

> > +
> > +	nandc->ecc_modes = driver_data->ecc_modes;
> > +	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;

Why don't you store a pointer to the driver data object in your nandc
struct?

> >   
> >   	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >   	nandc->base = devm_ioremap_resource(dev, res);
> > @@ -2179,15 +2197,26 @@ static int qcom_nandc_remove(struct platform_device *pdev)
> >   	return 0;
> >   }
> >   
> > -#define EBI2_NANDC_ECC_MODES	(ECC_RS_4BIT | ECC_BCH_8BIT)
> >   
> > +static const struct qcom_nand_driver_data ebi2_nandc_data = {
> > +	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
> > +	.dma_bam_enabled = false,
> > +};
> > +
> > +static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
> > +	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
> > +	.dma_bam_enabled = true,
> > +};

This patch should be split in 2 IMO:
1/ introduce the qcom_nand_driver_data struct (which I'd prefer to call
qcom_nand_controller_caps, or something like that) and use it for the
existing compatible
2/ add the new compat with its own set of capabilities.

> >   /*
> >    * data will hold a struct pointer containing more differences once we support
> >    * more controller variants
> >    */
> >   static const struct of_device_id qcom_nandc_of_match[] = {
> >   	{	.compatible = "qcom,ipq806x-nand",  
> 
> Please make sure that you update the compatible string above too.
> 
> Thanks,
> Archit
> 
> > -		.data = (void *)EBI2_NANDC_ECC_MODES,
> > +		.data = (void *)&ebi2_nandc_data,

Cast unneeded.

> > +	},
> > +	{	.compatible = "qcom,qpic-nandc-v1.4.0",
> > +		.data = (void *)&qpic_nandc_v1_4_0_data,

Ditto.

> >   	},
> >   	{}
> >   };
> >   
> 

Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA

[Abhishek Sahu]

On 2017-07-04 01:11, Boris Brezillon wrote:
> On Mon, 3 Jul 2017 10:08:32 +0530
> Archit Taneja <architt@codeaurora.org> wrote:
> 
>> On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
>> > The current driver only support EBI2 NAND which uses ADM DMA. The
>> > latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
>> > registers and programming sequence are same for EBI2 and QPIC
>> > NAND so the same driver can support QPIC NAND also by adding the
>> > BAM DMA support. This patch adds the QPIC NAND support in current
>> > NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
>> > maps it with different configuration parameter in driver data.
>> >
>> > Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> > ---
>> >   .../devicetree/bindings/mtd/qcom_nandc.txt         | 41
> +++++++++++++++++++++-
>> >   drivers/mtd/nand/qcom_nandc.c                      | 37
> ++++++++++++++++---
>> >   2 files changed, 73 insertions(+), 5 deletions(-)
>> >
>> > diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> > index 70dd511..5d0f7ae 100644
>> > --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> > +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> > @@ -1,7 +1,9 @@
>> >   * Qualcomm NAND controller
>> >
>> >   Required properties:
>> > -- compatible:		should be "qcom,ipq806x-nand"
>> 
>> Since you're changing the compatible string, could you mention in the
> commit message that
>> it's okay to do so since there aren't any upstream dtsi files using 
>> this
> binding?
> 
> Yep. I was going to ask about backward compat, but I guess it's fine if
> there's no user in mainline yet, just mention it in the commit message
> as suggested by Archit.
> 
>> 
>> > +- compatible:		must be one of the following:
>> > +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
>> 
>> Are we sure that all EBI2 based NAND controllers would work by this
> single binding?
>> Should we put a version here too like we've done for QPIC?

The offsets are different in QPIC version 1.4.0 and 1.5.0 that's
why I put different version. For EBI2, it uses same reg offsets
as QPIC version 1.4.0.

The EBI2 version for IPQ806x is 4.3.0 and if put like 4.3.0
then it will imply that NANDC driver only supports this
particular version. since the original driver does not specifies
any version, qcom,ebi2-nandc will support all the versions.

>> 
>> > +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA
> like IPQ4019.
>> >   - reg:			MMIO address range
>> >   - clocks:		must contain core clock and always on clock
>> >   - clock-names:		must contain "core" for the core clock and
> "aon" for the
>> > @@ -84,3 +86,40 @@ nand@1ac00000 {
>> >   		};
>> >   	};
>> >   };
>> > +
>> > +nand@79b0000 {
> 
> nand-controller@xxxx {
> 
> BTW, glad to see another driver moving to the new DT representation 
> :-).
> 
>> > +	compatible = "qcom,qpic-nandc-v1.4.0";
>> > +	reg = <0x79b0000 0x1000>;
>> > +
>> > +	clocks = <&gcc GCC_QPIC_CLK>,
>> > +		<&gcc GCC_QPIC_AHB_CLK>;
>> > +	clock-names = "core", "aon";
>> > +
>> > +	#address-cells = <1>;
>> > +	#size-cells = <0>;
>> > +
>> > +	nandcs@0 {
> 
> 	nand@0 {
> 
>> > +		compatible = "qcom,nandcs";
> 
> Why do you need a compatible here?
It is the part of original driver. We can connect multiple
NAND devices in the same bus and qcom,nandcs is being used
for each connected NAND device. Each NAND device can use
different  chip select, ecc strength etc which we can specify
under this sub node.
> 
>> > +		reg = <0>;
>> > +
>> > +		nand-ecc-strength = <4>;
>> > +		nand-ecc-step-size = <512>;
>> > +		nand-bus-width = <8>;
>> > +
>> > +		partitions {
>> > +			compatible = "fixed-partitions";
>> > +			#address-cells = <1>;
>> > +			#size-cells = <1>;
>> > +
>> > +			partition@0 {
>> > +				label = "boot-nand";
>> > +				reg = <0 0x58a0000>;
>> > +			};
>> > +
>> > +			partition@58a0000 {
>> > +				label = "fs-nand";
>> > +				reg = <0x58a0000 0x4000000>;
>> > +			};
>> > +		};
>> > +	};
>> > +};
>> > diff --git a/drivers/mtd/nand/qcom_nandc.c
> b/drivers/mtd/nand/qcom_nandc.c
>> > index 57d483a..f55f728 100644
>> > --- a/drivers/mtd/nand/qcom_nandc.c
>> > +++ b/drivers/mtd/nand/qcom_nandc.c
>> > @@ -1,5 +1,5 @@
>> >   /*
>> > - * Copyright (c) 2016, The Linux Foundation. All rights reserved.
>> > + * Copyright (c) 2016-2017, The Linux Foundation. All rights
> reserved.
>> >    *
>> >    * This software is licensed under the terms of the GNU General
> Public
>> >    * License version 2, as published by the Free Software Foundation,
> and
>> > @@ -234,6 +234,8 @@ struct nandc_regs {
>> >    * @cmd1/vld:			some fixed controller register
> values
>> >    * @ecc_modes:			supported ECC modes by the current
> controller,
>> >    *				initialized via DT match data
>> > + * @dma_bam_enabled:		flag to tell whether nand
> controller is using
>> > + *				bam dma
>> >    */
>> >   struct qcom_nand_controller {
>> >   	struct nand_hw_control controller;
>> > @@ -253,6 +255,7 @@ struct qcom_nand_controller {
>> >   	struct list_head desc_list;
>> >
>> >   	u8		*data_buffer;
>> > +	bool		dma_bam_enabled;
>> >   	int		buf_size;
>> >   	int		buf_count;
>> >   	int		buf_start;
>> > @@ -316,6 +319,17 @@ struct qcom_nand_host {
>> >   	u32 clrreadstatus;
>> >   };
>> >
>> > +/*
>> > + * This data type corresponds to the nand driver data which will be
> used at
>> > + * driver probe time
>> > + * @ecc_modes - ecc mode for nand
>> > + * @dma_bam_enabled - whether this driver is using bam
>> > + */
>> > +struct qcom_nand_driver_data {
>> > +	u32 ecc_modes;
>> > +	bool dma_bam_enabled;
>> > +};
>> > +
>> >   static inline struct qcom_nand_host *to_qcom_nand_host(struct
> nand_chip *chip)
>> >   {
>> >   	return container_of(chip, struct qcom_nand_host, chip);
>> > @@ -2073,6 +2087,7 @@ static int qcom_nandc_probe(struct
> platform_device *pdev)
>> >   	struct device_node *dn = dev->of_node, *child;
>> >   	struct resource *res;
>> >   	int ret;
>> > +	const struct qcom_nand_driver_data *driver_data;
>> >
>> >   	nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
>> >   	if (!nandc)
>> > @@ -2087,7 +2102,10 @@ static int qcom_nandc_probe(struct
> platform_device *pdev)
>> >   		return -ENODEV;
>> >   	}
>> >
>> > -	nandc->ecc_modes = (unsigned long)dev_data;
>> > +	driver_data = (const struct qcom_nand_driver_data *)dev_data;
> 
> Cast is unneeded here.
Sure. Will remove in v2.
> 
>> > +
>> > +	nandc->ecc_modes = driver_data->ecc_modes;
>> > +	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
> 
> Why don't you store a pointer to the driver data object in your nandc
> struct?
Storing driver data would be better. I will do the same in v2.
> 
>> >
>> >   	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> >   	nandc->base = devm_ioremap_resource(dev, res);
>> > @@ -2179,15 +2197,26 @@ static int qcom_nandc_remove(struct
> platform_device *pdev)
>> >   	return 0;
>> >   }
>> >
>> > -#define EBI2_NANDC_ECC_MODES	(ECC_RS_4BIT | ECC_BCH_8BIT)
>> >
>> > +static const struct qcom_nand_driver_data ebi2_nandc_data = {
>> > +	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
>> > +	.dma_bam_enabled = false,
>> > +};
>> > +
>> > +static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
>> > +	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
>> > +	.dma_bam_enabled = true,
>> > +};
> 
> This patch should be split in 2 IMO:
> 1/ introduce the qcom_nand_driver_data struct (which I'd prefer to call
> qcom_nand_controller_caps, or something like that) and use it for the
> existing compatible
> 2/ add the new compat with its own set of capabilities.
Yes. Will do the same in v2.
> 
>> >   /*
>> >    * data will hold a struct pointer containing more differences once
> we support
>> >    * more controller variants
>> >    */
>> >   static const struct of_device_id qcom_nandc_of_match[] = {
>> >   	{	.compatible = "qcom,ipq806x-nand",
>> 
>> Please make sure that you update the compatible string above too.
>> 
>> Thanks,
>> Archit
>> 
>> > -		.data = (void *)EBI2_NANDC_ECC_MODES,
>> > +		.data = (void *)&ebi2_nandc_data,
> 
> Cast unneeded.
> 
>> > +	},
>> > +	{	.compatible = "qcom,qpic-nandc-v1.4.0",
>> > +		.data = (void *)&qpic_nandc_v1_4_0_data,
> 
> Ditto.
Will remove in v2.
> 
>> >   	},
>> >   	{}
>> >   };
>> >
>> 

-- 
Abhishek Sahu

Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA

[Boris Brezillon]

On Mon, 17 Jul 2017 11:41:01 +0530
Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:

> >> > +
> >> > +nand@79b0000 {  
> > 
> > nand-controller@xxxx {
> > 
> > BTW, glad to see another driver moving to the new DT representation 
> > :-).
> >   
> >> > +	compatible = "qcom,qpic-nandc-v1.4.0";
> >> > +	reg = <0x79b0000 0x1000>;
> >> > +
> >> > +	clocks = <&gcc GCC_QPIC_CLK>,
> >> > +		<&gcc GCC_QPIC_AHB_CLK>;
> >> > +	clock-names = "core", "aon";
> >> > +
> >> > +	#address-cells = <1>;
> >> > +	#size-cells = <0>;
> >> > +
> >> > +	nandcs@0 {  
> > 
> > 	nand@0 {
> >   
> >> > +		compatible = "qcom,nandcs";  
> > 
> > Why do you need a compatible here?  
> It is the part of original driver. We can connect multiple
> NAND devices in the same bus and qcom,nandcs is being used
> for each connected NAND device. Each NAND device can use
> different  chip select, ecc strength etc which we can specify
> under this sub node.


Still don't understand why you need a compatible? Is this a memory bus
where you can connect other kind of memories (parallel NORs,
SRAMs, ...)?

If that's not the case, then considering all subnodes of the
nand-controller node containing a reg property as NAND devices is fine,
you don't need this compatible = "nand,cs" (see sunxi-nand bindings
[1]).

If the bus is generic and can be attached non-NAND devices, I'd
recommend looking at atmel's binding [2], because you're likely to
have one instance of the NAND controller logic for all NAND devices
connected on this bus.
And more importantly, if the bus a generic, the node should not be
named nand or nand-controller, and the compatible should not contain
'nandc' in it.

[1]http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/mtd/sunxi-nand.txt#L34
[2]http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/mtd/atmel-nand.txt#L70
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Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA

[Boris Brezillon]

On Mon, 17 Jul 2017 11:41:01 +0530
Abhishek Sahu <absahu@codeaurora.org> wrote:

> >> > +
> >> > +nand@79b0000 {  
> > 
> > nand-controller@xxxx {
> > 
> > BTW, glad to see another driver moving to the new DT representation 
> > :-).
> >   
> >> > +	compatible = "qcom,qpic-nandc-v1.4.0";
> >> > +	reg = <0x79b0000 0x1000>;
> >> > +
> >> > +	clocks = <&gcc GCC_QPIC_CLK>,
> >> > +		<&gcc GCC_QPIC_AHB_CLK>;
> >> > +	clock-names = "core", "aon";
> >> > +
> >> > +	#address-cells = <1>;
> >> > +	#size-cells = <0>;
> >> > +
> >> > +	nandcs@0 {  
> > 
> > 	nand@0 {
> >   
> >> > +		compatible = "qcom,nandcs";  
> > 
> > Why do you need a compatible here?  
> It is the part of original driver. We can connect multiple
> NAND devices in the same bus and qcom,nandcs is being used
> for each connected NAND device. Each NAND device can use
> different  chip select, ecc strength etc which we can specify
> under this sub node.


Still don't understand why you need a compatible? Is this a memory bus
where you can connect other kind of memories (parallel NORs,
SRAMs, ...)?

If that's not the case, then considering all subnodes of the
nand-controller node containing a reg property as NAND devices is fine,
you don't need this compatible = "nand,cs" (see sunxi-nand bindings
[1]).

If the bus is generic and can be attached non-NAND devices, I'd
recommend looking at atmel's binding [2], because you're likely to
have one instance of the NAND controller logic for all NAND devices
connected on this bus.
And more importantly, if the bus a generic, the node should not be
named nand or nand-controller, and the compatible should not contain
'nandc' in it.

[1]http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/mtd/sunxi-nand.txt#L34
[2]http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/mtd/atmel-nand.txt#L70

Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA

[Abhishek Sahu]

On 2017-07-17 12:52, Boris Brezillon wrote:
> On Mon, 17 Jul 2017 11:41:01 +0530
> Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:
> 
>> >> > +
>> >> > +nand@79b0000 {
>> >
>> > nand-controller@xxxx {
>> >
>> > BTW, glad to see another driver moving to the new DT representation
>> > :-).
>> >
>> >> > +	compatible = "qcom,qpic-nandc-v1.4.0";
>> >> > +	reg = <0x79b0000 0x1000>;
>> >> > +
>> >> > +	clocks = <&gcc GCC_QPIC_CLK>,
>> >> > +		<&gcc GCC_QPIC_AHB_CLK>;
>> >> > +	clock-names = "core", "aon";
>> >> > +
>> >> > +	#address-cells = <1>;
>> >> > +	#size-cells = <0>;
>> >> > +
>> >> > +	nandcs@0 {
>> >
>> > 	nand@0 {
>> >
>> >> > +		compatible = "qcom,nandcs";
>> >
>> > Why do you need a compatible here?
>> It is the part of original driver. We can connect multiple
>> NAND devices in the same bus and qcom,nandcs is being used
>> for each connected NAND device. Each NAND device can use
>> different  chip select, ecc strength etc which we can specify
>> under this sub node.
> 
> 
> Still don't understand why you need a compatible? Is this a memory bus
> where you can connect other kind of memories (parallel NORs,
> SRAMs, ...)?
> 
> If that's not the case, then considering all subnodes of the
> nand-controller node containing a reg property as NAND devices is fine,
> you don't need this compatible = "nand,cs" (see sunxi-nand bindings
> [1]).
> 

  Thanks Boris for giving detailed references.

  We can connect other parallel devices also but we have
  different hardware wrappers over generic EBI2/QPIC which
  will MUX/arbitrate the device access from the hardware itself.
  So this NAND driver will only control multiple NAND devices.

  We can remove this compatible and use the bindings
  similar to sunxi-nand. I will do the required changes and
  will post in v2 of the same patch series.

> If the bus is generic and can be attached non-NAND devices, I'd
> recommend looking at atmel's binding [2], because you're likely to
> have one instance of the NAND controller logic for all NAND devices
> connected on this bus.
> And more importantly, if the bus a generic, the node should not be
> named nand or nand-controller, and the compatible should not contain
> 'nandc' in it.
> 
> [1]http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/mtd/sunxi-nand.txt#L34
> [2]http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/mtd/atmel-nand.txt#L70

-- 
Abhishek Sahu
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Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA

[Abhishek Sahu]

On 2017-07-17 12:52, Boris Brezillon wrote:
> On Mon, 17 Jul 2017 11:41:01 +0530
> Abhishek Sahu <absahu@codeaurora.org> wrote:
> 
>> >> > +
>> >> > +nand@79b0000 {
>> >
>> > nand-controller@xxxx {
>> >
>> > BTW, glad to see another driver moving to the new DT representation
>> > :-).
>> >
>> >> > +	compatible = "qcom,qpic-nandc-v1.4.0";
>> >> > +	reg = <0x79b0000 0x1000>;
>> >> > +
>> >> > +	clocks = <&gcc GCC_QPIC_CLK>,
>> >> > +		<&gcc GCC_QPIC_AHB_CLK>;
>> >> > +	clock-names = "core", "aon";
>> >> > +
>> >> > +	#address-cells = <1>;
>> >> > +	#size-cells = <0>;
>> >> > +
>> >> > +	nandcs@0 {
>> >
>> > 	nand@0 {
>> >
>> >> > +		compatible = "qcom,nandcs";
>> >
>> > Why do you need a compatible here?
>> It is the part of original driver. We can connect multiple
>> NAND devices in the same bus and qcom,nandcs is being used
>> for each connected NAND device. Each NAND device can use
>> different  chip select, ecc strength etc which we can specify
>> under this sub node.
> 
> 
> Still don't understand why you need a compatible? Is this a memory bus
> where you can connect other kind of memories (parallel NORs,
> SRAMs, ...)?
> 
> If that's not the case, then considering all subnodes of the
> nand-controller node containing a reg property as NAND devices is fine,
> you don't need this compatible = "nand,cs" (see sunxi-nand bindings
> [1]).
> 

  Thanks Boris for giving detailed references.

  We can connect other parallel devices also but we have
  different hardware wrappers over generic EBI2/QPIC which
  will MUX/arbitrate the device access from the hardware itself.
  So this NAND driver will only control multiple NAND devices.

  We can remove this compatible and use the bindings
  similar to sunxi-nand. I will do the required changes and
  will post in v2 of the same patch series.

> If the bus is generic and can be attached non-NAND devices, I'd
> recommend looking at atmel's binding [2], because you're likely to
> have one instance of the NAND controller logic for all NAND devices
> connected on this bus.
> And more importantly, if the bus a generic, the node should not be
> named nand or nand-controller, and the compatible should not contain
> 'nandc' in it.
> 
> [1]http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/mtd/sunxi-nand.txt#L34
> [2]http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/mtd/atmel-nand.txt#L70

-- 
Abhishek Sahu

Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA

[Sricharan R]

Hi Abhishek,

On 6/29/2017 12:45 PM, Abhishek Sahu wrote:
> The current driver only support EBI2 NAND which uses ADM DMA. The
> latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
> registers and programming sequence are same for EBI2 and QPIC
> NAND so the same driver can support QPIC NAND also by adding the
> BAM DMA support. This patch adds the QPIC NAND support in current
> NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
> maps it with different configuration parameter in driver data.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>  .../devicetree/bindings/mtd/qcom_nandc.txt         | 41 +++++++++++++++++++++-
>  drivers/mtd/nand/qcom_nandc.c                      | 37 ++++++++++++++++---
>  2 files changed, 73 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 70dd511..5d0f7ae 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -1,7 +1,9 @@
>  * Qualcomm NAND controller
>  
>  Required properties:
> -- compatible:		should be "qcom,ipq806x-nand"
> +- compatible:		must be one of the following:
> +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
> +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
>  - reg:			MMIO address range
>  - clocks:		must contain core clock and always on clock
>  - clock-names:		must contain "core" for the core clock and "aon" for the
> @@ -84,3 +86,40 @@ nand@1ac00000 {
>  		};
>  	};
>  };
> +
> +nand@79b0000 {
> +	compatible = "qcom,qpic-nandc-v1.4.0";
> +	reg = <0x79b0000 0x1000>;
> +
> +	clocks = <&gcc GCC_QPIC_CLK>,
> +		<&gcc GCC_QPIC_AHB_CLK>;
> +	clock-names = "core", "aon";
> +
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	nandcs@0 {
> +		compatible = "qcom,nandcs";
> +		reg = <0>;
> +
> +		nand-ecc-strength = <4>;
> +		nand-ecc-step-size = <512>;
> +		nand-bus-width = <8>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				label = "boot-nand";
> +				reg = <0 0x58a0000>;
> +			};
> +
> +			partition@58a0000 {
> +				label = "fs-nand";
> +				reg = <0x58a0000 0x4000000>;
> +			};
> +		};
> +	};
> +};
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 57d483a..f55f728 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
>   *
>   * This software is licensed under the terms of the GNU General Public
>   * License version 2, as published by the Free Software Foundation, and
> @@ -234,6 +234,8 @@ struct nandc_regs {
>   * @cmd1/vld:			some fixed controller register values
>   * @ecc_modes:			supported ECC modes by the current controller,
>   *				initialized via DT match data
> + * @dma_bam_enabled:		flag to tell whether nand controller is using
> + *				bam dma
>   */

 simply is_bam ?

>  struct qcom_nand_controller {
>  	struct nand_hw_control controller;
> @@ -253,6 +255,7 @@ struct qcom_nand_controller {
>  	struct list_head desc_list;
>  
>  	u8		*data_buffer;
> +	bool		dma_bam_enabled;
>  	int		buf_size;
>  	int		buf_count;
>  	int		buf_start;
> @@ -316,6 +319,17 @@ struct qcom_nand_host {
>  	u32 clrreadstatus;
>  };
>  
> +/*
> + * This data type corresponds to the nand driver data which will be used at
> + * driver probe time
> + * @ecc_modes - ecc mode for nand
> + * @dma_bam_enabled - whether this driver is using bam
> + */
> +struct qcom_nand_driver_data {
> +	u32 ecc_modes;
> +	bool dma_bam_enabled;
> +};
> +
>  static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>  {
>  	return container_of(chip, struct qcom_nand_host, chip);
> @@ -2073,6 +2087,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>  	struct device_node *dn = dev->of_node, *child;
>  	struct resource *res;
>  	int ret;
> +	const struct qcom_nand_driver_data *driver_data;

  Directly assign of the of_device_match_data here and avoid additional variable, cast.

Regards,
 Sricharan



>  
>  	nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
>  	if (!nandc)
> @@ -2087,7 +2102,10 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>  		return -ENODEV;
>  	}
>  
> -	nandc->ecc_modes = (unsigned long)dev_data;
> +	driver_data = (const struct qcom_nand_driver_data *)dev_data;
> +
> +	nandc->ecc_modes = driver_data->ecc_modes;
> +	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
>  
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	nandc->base = devm_ioremap_resource(dev, res);
> @@ -2179,15 +2197,26 @@ static int qcom_nandc_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -#define EBI2_NANDC_ECC_MODES	(ECC_RS_4BIT | ECC_BCH_8BIT)
>  
> +static const struct qcom_nand_driver_data ebi2_nandc_data = {
> +	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
> +	.dma_bam_enabled = false,
> +};
> +
> +static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
> +	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
> +	.dma_bam_enabled = true,
> +};
>  /*
>   * data will hold a struct pointer containing more differences once we support
>   * more controller variants
>   */
>  static const struct of_device_id qcom_nandc_of_match[] = {
>  	{	.compatible = "qcom,ipq806x-nand",
> -		.data = (void *)EBI2_NANDC_ECC_MODES,
> +		.data = (void *)&ebi2_nandc_data,
> +	},
> +	{	.compatible = "qcom,qpic-nandc-v1.4.0",
> +		.data = (void *)&qpic_nandc_v1_4_0_data,
>  	},
>  	{}
>  };
> 

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[PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources

[Abhishek Sahu]

1. The QPIC NAND uses 3 BAM channels: command, data tx and
   data rx while EBI2 NAND uses only single ADM channel.

2. The EBI2 NAND uses normal register read buffer since this
   buffer will be remapped with dma_map_sg. The QPIC NAND will give
   register read buffer in command descriptor and the command
   descriptor will be mapped with dma_map_sg so the register buffer
   should be DMA coherent.

Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 .../devicetree/bindings/mtd/qcom_nandc.txt         |  25 +++--
 drivers/mtd/nand/qcom_nandc.c                      | 106 ++++++++++++++++-----
 2 files changed, 99 insertions(+), 32 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index 5d0f7ae..87b9a56 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -9,15 +9,17 @@ Required properties:
 - clock-names:		must contain "core" for the core clock and "aon" for the
 			always on clock
 - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
-			controller node and the channel number to be used for
-			NAND. Refer to dma.txt and qcom_adm.txt for more details
-- dma-names:		must be "rxtx"
-- qcom,cmd-crci:	must contain the ADM command type CRCI block instance
-			number specified for the NAND controller on the given
-			platform
-- qcom,data-crci:	must contain the ADM data type CRCI block instance
-			number specified for the NAND controller on the given
-			platform
+			or BAM DMA controller node and the channel number to
+			be used for NAND. Refer to dma.txt, qcom_adm.txt(ADM)
+			and qcom/bam_dma.txt(BAM) for more details
+- dma-names:		"rxtx" - ADM
+			"tx", "rx", "cmd" - BAM
+- qcom,cmd-crci:	Only required for ADM DMA. must contain the ADM command
+			type CRCI block instance number specified for the NAND
+			controller on the given platform.
+- qcom,data-crci:	Only required for ADM DMA. must contain the ADM data
+			type CRCI block instance number specified for the NAND
+			controller on the given platform.
 - #address-cells:	<1> - subnodes give the chip-select number
 - #size-cells:		<0>
 
@@ -95,6 +97,11 @@ nand@79b0000 {
 		<&gcc GCC_QPIC_AHB_CLK>;
 	clock-names = "core", "aon";
 
+	dmas = <&qpicbam 0>,
+		<&qpicbam 1>,
+		<&qpicbam 2>;
+	dma-names = "tx", "rx", "cmd";
+
 	#address-cells = <1>;
 	#size-cells = <0>;
 
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index f55f728..520add9 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -226,6 +226,7 @@ struct nandc_regs {
  *				by upper layers directly
  * @buf_size/count/start:	markers for chip->read_buf/write_buf functions
  * @reg_read_buf:		local buffer for reading back registers via DMA
+ * @reg_read_buf_phys:		contains dma address for register read buffer
  * @reg_read_pos:		marker for data read in reg_read_buf
  *
  * @regs:			a contiguous chunk of memory for DMA register
@@ -249,9 +250,19 @@ struct qcom_nand_controller {
 	struct clk *core_clk;
 	struct clk *aon_clk;
 
-	struct dma_chan *chan;
-	unsigned int cmd_crci;
-	unsigned int data_crci;
+	union {
+		struct {
+			struct dma_chan *tx_chan;
+			struct dma_chan *rx_chan;
+			struct dma_chan *cmd_chan;
+		};
+		struct {
+			struct dma_chan *chan;
+			unsigned int cmd_crci;
+			unsigned int data_crci;
+		};
+	};
+
 	struct list_head desc_list;
 
 	u8		*data_buffer;
@@ -261,6 +272,7 @@ struct qcom_nand_controller {
 	int		buf_start;
 
 	__le32 *reg_read_buf;
+	dma_addr_t reg_read_buf_phys;
 	int reg_read_pos;
 
 	struct nandc_regs *regs;
@@ -1956,16 +1968,48 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
 	if (!nandc->regs)
 		return -ENOMEM;
 
-	nandc->reg_read_buf = devm_kzalloc(nandc->dev,
-				MAX_REG_RD * sizeof(*nandc->reg_read_buf),
-				GFP_KERNEL);
-	if (!nandc->reg_read_buf)
-		return -ENOMEM;
 
-	nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
-	if (!nandc->chan) {
-		dev_err(nandc->dev, "failed to request slave channel\n");
-		return -ENODEV;
+	if (!nandc->dma_bam_enabled) {
+		nandc->reg_read_buf =
+			devm_kzalloc(nandc->dev, MAX_REG_RD *
+				     sizeof(*nandc->reg_read_buf), GFP_KERNEL);
+
+		if (!nandc->reg_read_buf)
+			return -ENOMEM;
+
+		nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
+		if (!nandc->chan) {
+			dev_err(nandc->dev,
+				"failed to request slave channel\n");
+			return -ENODEV;
+		}
+	} else {
+		nandc->reg_read_buf =
+			dmam_alloc_coherent(nandc->dev, MAX_REG_RD *
+					    sizeof(*nandc->reg_read_buf),
+					    &nandc->reg_read_buf_phys,
+					    GFP_KERNEL);
+
+		if (!nandc->reg_read_buf)
+			return -ENOMEM;
+
+		nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
+		if (!nandc->tx_chan) {
+			dev_err(nandc->dev, "failed to request tx channel\n");
+			return -ENODEV;
+		}
+
+		nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
+		if (!nandc->rx_chan) {
+			dev_err(nandc->dev, "failed to request rx channel\n");
+			return -ENODEV;
+		}
+
+		nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
+		if (!nandc->cmd_chan) {
+			dev_err(nandc->dev, "failed to request cmd channel\n");
+			return -ENODEV;
+		}
 	}
 
 	INIT_LIST_HEAD(&nandc->desc_list);
@@ -1978,7 +2022,19 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
 
 static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
 {
-	dma_release_channel(nandc->chan);
+	if (nandc->dma_bam_enabled) {
+		if (nandc->tx_chan)
+			dma_release_channel(nandc->tx_chan);
+
+		if (nandc->rx_chan)
+			dma_release_channel(nandc->rx_chan);
+
+		if (nandc->cmd_chan)
+			dma_release_channel(nandc->cmd_chan);
+	} else {
+		if (nandc->chan)
+			dma_release_channel(nandc->chan);
+	}
 }
 
 /* one time setup of a few nand controller registers */
@@ -2063,16 +2119,20 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
 	struct device_node *np = nandc->dev->of_node;
 	int ret;
 
-	ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
-	if (ret) {
-		dev_err(nandc->dev, "command CRCI unspecified\n");
-		return ret;
-	}
+	if (!nandc->dma_bam_enabled) {
+		ret = of_property_read_u32(np, "qcom,cmd-crci",
+					   &nandc->cmd_crci);
+		if (ret) {
+			dev_err(nandc->dev, "command CRCI unspecified\n");
+			return ret;
+		}
 
-	ret = of_property_read_u32(np, "qcom,data-crci", &nandc->data_crci);
-	if (ret) {
-		dev_err(nandc->dev, "data CRCI unspecified\n");
-		return ret;
+		ret = of_property_read_u32(np, "qcom,data-crci",
+					   &nandc->data_crci);
+		if (ret) {
+			dev_err(nandc->dev, "data CRCI unspecified\n");
+			return ret;
+		}
 	}
 
 	return 0;
@@ -2128,7 +2188,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 
 	ret = qcom_nandc_alloc(nandc);
 	if (ret)
-		return ret;
+		goto err_core_clk;
 
 	ret = clk_prepare_enable(nandc->core_clk);
 	if (ret)
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[PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources

[Abhishek Sahu]

1. The QPIC NAND uses 3 BAM channels: command, data tx and
   data rx while EBI2 NAND uses only single ADM channel.

2. The EBI2 NAND uses normal register read buffer since this
   buffer will be remapped with dma_map_sg. The QPIC NAND will give
   register read buffer in command descriptor and the command
   descriptor will be mapped with dma_map_sg so the register buffer
   should be DMA coherent.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 .../devicetree/bindings/mtd/qcom_nandc.txt         |  25 +++--
 drivers/mtd/nand/qcom_nandc.c                      | 106 ++++++++++++++++-----
 2 files changed, 99 insertions(+), 32 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index 5d0f7ae..87b9a56 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -9,15 +9,17 @@ Required properties:
 - clock-names:		must contain "core" for the core clock and "aon" for the
 			always on clock
 - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
-			controller node and the channel number to be used for
-			NAND. Refer to dma.txt and qcom_adm.txt for more details
-- dma-names:		must be "rxtx"
-- qcom,cmd-crci:	must contain the ADM command type CRCI block instance
-			number specified for the NAND controller on the given
-			platform
-- qcom,data-crci:	must contain the ADM data type CRCI block instance
-			number specified for the NAND controller on the given
-			platform
+			or BAM DMA controller node and the channel number to
+			be used for NAND. Refer to dma.txt, qcom_adm.txt(ADM)
+			and qcom/bam_dma.txt(BAM) for more details
+- dma-names:		"rxtx" - ADM
+			"tx", "rx", "cmd" - BAM
+- qcom,cmd-crci:	Only required for ADM DMA. must contain the ADM command
+			type CRCI block instance number specified for the NAND
+			controller on the given platform.
+- qcom,data-crci:	Only required for ADM DMA. must contain the ADM data
+			type CRCI block instance number specified for the NAND
+			controller on the given platform.
 - #address-cells:	<1> - subnodes give the chip-select number
 - #size-cells:		<0>
 
@@ -95,6 +97,11 @@ nand@79b0000 {
 		<&gcc GCC_QPIC_AHB_CLK>;
 	clock-names = "core", "aon";
 
+	dmas = <&qpicbam 0>,
+		<&qpicbam 1>,
+		<&qpicbam 2>;
+	dma-names = "tx", "rx", "cmd";
+
 	#address-cells = <1>;
 	#size-cells = <0>;
 
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index f55f728..520add9 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -226,6 +226,7 @@ struct nandc_regs {
  *				by upper layers directly
  * @buf_size/count/start:	markers for chip->read_buf/write_buf functions
  * @reg_read_buf:		local buffer for reading back registers via DMA
+ * @reg_read_buf_phys:		contains dma address for register read buffer
  * @reg_read_pos:		marker for data read in reg_read_buf
  *
  * @regs:			a contiguous chunk of memory for DMA register
@@ -249,9 +250,19 @@ struct qcom_nand_controller {
 	struct clk *core_clk;
 	struct clk *aon_clk;
 
-	struct dma_chan *chan;
-	unsigned int cmd_crci;
-	unsigned int data_crci;
+	union {
+		struct {
+			struct dma_chan *tx_chan;
+			struct dma_chan *rx_chan;
+			struct dma_chan *cmd_chan;
+		};
+		struct {
+			struct dma_chan *chan;
+			unsigned int cmd_crci;
+			unsigned int data_crci;
+		};
+	};
+
 	struct list_head desc_list;
 
 	u8		*data_buffer;
@@ -261,6 +272,7 @@ struct qcom_nand_controller {
 	int		buf_start;
 
 	__le32 *reg_read_buf;
+	dma_addr_t reg_read_buf_phys;
 	int reg_read_pos;
 
 	struct nandc_regs *regs;
@@ -1956,16 +1968,48 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
 	if (!nandc->regs)
 		return -ENOMEM;
 
-	nandc->reg_read_buf = devm_kzalloc(nandc->dev,
-				MAX_REG_RD * sizeof(*nandc->reg_read_buf),
-				GFP_KERNEL);
-	if (!nandc->reg_read_buf)
-		return -ENOMEM;
 
-	nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
-	if (!nandc->chan) {
-		dev_err(nandc->dev, "failed to request slave channel\n");
-		return -ENODEV;
+	if (!nandc->dma_bam_enabled) {
+		nandc->reg_read_buf =
+			devm_kzalloc(nandc->dev, MAX_REG_RD *
+				     sizeof(*nandc->reg_read_buf), GFP_KERNEL);
+
+		if (!nandc->reg_read_buf)
+			return -ENOMEM;
+
+		nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
+		if (!nandc->chan) {
+			dev_err(nandc->dev,
+				"failed to request slave channel\n");
+			return -ENODEV;
+		}
+	} else {
+		nandc->reg_read_buf =
+			dmam_alloc_coherent(nandc->dev, MAX_REG_RD *
+					    sizeof(*nandc->reg_read_buf),
+					    &nandc->reg_read_buf_phys,
+					    GFP_KERNEL);
+
+		if (!nandc->reg_read_buf)
+			return -ENOMEM;
+
+		nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
+		if (!nandc->tx_chan) {
+			dev_err(nandc->dev, "failed to request tx channel\n");
+			return -ENODEV;
+		}
+
+		nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
+		if (!nandc->rx_chan) {
+			dev_err(nandc->dev, "failed to request rx channel\n");
+			return -ENODEV;
+		}
+
+		nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
+		if (!nandc->cmd_chan) {
+			dev_err(nandc->dev, "failed to request cmd channel\n");
+			return -ENODEV;
+		}
 	}
 
 	INIT_LIST_HEAD(&nandc->desc_list);
@@ -1978,7 +2022,19 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
 
 static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
 {
-	dma_release_channel(nandc->chan);
+	if (nandc->dma_bam_enabled) {
+		if (nandc->tx_chan)
+			dma_release_channel(nandc->tx_chan);
+
+		if (nandc->rx_chan)
+			dma_release_channel(nandc->rx_chan);
+
+		if (nandc->cmd_chan)
+			dma_release_channel(nandc->cmd_chan);
+	} else {
+		if (nandc->chan)
+			dma_release_channel(nandc->chan);
+	}
 }
 
 /* one time setup of a few nand controller registers */
@@ -2063,16 +2119,20 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
 	struct device_node *np = nandc->dev->of_node;
 	int ret;
 
-	ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
-	if (ret) {
-		dev_err(nandc->dev, "command CRCI unspecified\n");
-		return ret;
-	}
+	if (!nandc->dma_bam_enabled) {
+		ret = of_property_read_u32(np, "qcom,cmd-crci",
+					   &nandc->cmd_crci);
+		if (ret) {
+			dev_err(nandc->dev, "command CRCI unspecified\n");
+			return ret;
+		}
 
-	ret = of_property_read_u32(np, "qcom,data-crci", &nandc->data_crci);
-	if (ret) {
-		dev_err(nandc->dev, "data CRCI unspecified\n");
-		return ret;
+		ret = of_property_read_u32(np, "qcom,data-crci",
+					   &nandc->data_crci);
+		if (ret) {
+			dev_err(nandc->dev, "data CRCI unspecified\n");
+			return ret;
+		}
 	}
 
 	return 0;
@@ -2128,7 +2188,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 
 	ret = qcom_nandc_alloc(nandc);
 	if (ret)
-		return ret;
+		goto err_core_clk;
 
 	ret = clk_prepare_enable(nandc->core_clk);
 	if (ret)
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources

[Marek Vasut]

On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
> 1. The QPIC NAND uses 3 BAM channels: command, data tx and
>    data rx while EBI2 NAND uses only single ADM channel.
> 
> 2. The EBI2 NAND uses normal register read buffer since this
>    buffer will be remapped with dma_map_sg. The QPIC NAND will give
>    register read buffer in command descriptor and the command
>    descriptor will be mapped with dma_map_sg so the register buffer
>    should be DMA coherent.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>

The patch does two things, so make two patches. Also split the DT
changes into separate patch ...

> ---
>  .../devicetree/bindings/mtd/qcom_nandc.txt         |  25 +++--
>  drivers/mtd/nand/qcom_nandc.c                      | 106 ++++++++++++++++-----
>  2 files changed, 99 insertions(+), 32 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 5d0f7ae..87b9a56 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -9,15 +9,17 @@ Required properties:
>  - clock-names:		must contain "core" for the core clock and "aon" for the
>  			always on clock
>  - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
> -			controller node and the channel number to be used for
> -			NAND. Refer to dma.txt and qcom_adm.txt for more details
> -- dma-names:		must be "rxtx"
> -- qcom,cmd-crci:	must contain the ADM command type CRCI block instance
> -			number specified for the NAND controller on the given
> -			platform
> -- qcom,data-crci:	must contain the ADM data type CRCI block instance
> -			number specified for the NAND controller on the given
> -			platform
> +			or BAM DMA controller node and the channel number to
> +			be used for NAND. Refer to dma.txt, qcom_adm.txt(ADM)
> +			and qcom/bam_dma.txt(BAM) for more details
> +- dma-names:		"rxtx" - ADM
> +			"tx", "rx", "cmd" - BAM
> +- qcom,cmd-crci:	Only required for ADM DMA. must contain the ADM command
> +			type CRCI block instance number specified for the NAND
> +			controller on the given platform.
> +- qcom,data-crci:	Only required for ADM DMA. must contain the ADM data
> +			type CRCI block instance number specified for the NAND
> +			controller on the given platform.
>  - #address-cells:	<1> - subnodes give the chip-select number
>  - #size-cells:		<0>
>  
> @@ -95,6 +97,11 @@ nand@79b0000 {
>  		<&gcc GCC_QPIC_AHB_CLK>;
>  	clock-names = "core", "aon";
>  
> +	dmas = <&qpicbam 0>,
> +		<&qpicbam 1>,
> +		<&qpicbam 2>;
> +	dma-names = "tx", "rx", "cmd";
> +
>  	#address-cells = <1>;
>  	#size-cells = <0>;
>  
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index f55f728..520add9 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -226,6 +226,7 @@ struct nandc_regs {
>   *				by upper layers directly
>   * @buf_size/count/start:	markers for chip->read_buf/write_buf functions
>   * @reg_read_buf:		local buffer for reading back registers via DMA
> + * @reg_read_buf_phys:		contains dma address for register read buffer
>   * @reg_read_pos:		marker for data read in reg_read_buf
>   *
>   * @regs:			a contiguous chunk of memory for DMA register
> @@ -249,9 +250,19 @@ struct qcom_nand_controller {
>  	struct clk *core_clk;
>  	struct clk *aon_clk;
>  
> -	struct dma_chan *chan;
> -	unsigned int cmd_crci;
> -	unsigned int data_crci;
> +	union {
> +		struct {
> +			struct dma_chan *tx_chan;
> +			struct dma_chan *rx_chan;
> +			struct dma_chan *cmd_chan;
> +		};
> +		struct {
> +			struct dma_chan *chan;
> +			unsigned int cmd_crci;
> +			unsigned int data_crci;
> +		};
> +	};
> +
>  	struct list_head desc_list;
>  
>  	u8		*data_buffer;
> @@ -261,6 +272,7 @@ struct qcom_nand_controller {
>  	int		buf_start;
>  
>  	__le32 *reg_read_buf;
> +	dma_addr_t reg_read_buf_phys;
>  	int reg_read_pos;
>  
>  	struct nandc_regs *regs;
> @@ -1956,16 +1968,48 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>  	if (!nandc->regs)
>  		return -ENOMEM;
>  
> -	nandc->reg_read_buf = devm_kzalloc(nandc->dev,
> -				MAX_REG_RD * sizeof(*nandc->reg_read_buf),
> -				GFP_KERNEL);
> -	if (!nandc->reg_read_buf)
> -		return -ENOMEM;
>  
> -	nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> -	if (!nandc->chan) {
> -		dev_err(nandc->dev, "failed to request slave channel\n");
> -		return -ENODEV;
> +	if (!nandc->dma_bam_enabled) {
> +		nandc->reg_read_buf =
> +			devm_kzalloc(nandc->dev, MAX_REG_RD *
> +				     sizeof(*nandc->reg_read_buf), GFP_KERNEL);
> +
> +		if (!nandc->reg_read_buf)
> +			return -ENOMEM;
> +
> +		nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> +		if (!nandc->chan) {
> +			dev_err(nandc->dev,
> +				"failed to request slave channel\n");
> +			return -ENODEV;
> +		}
> +	} else {
> +		nandc->reg_read_buf =
> +			dmam_alloc_coherent(nandc->dev, MAX_REG_RD *
> +					    sizeof(*nandc->reg_read_buf),
> +					    &nandc->reg_read_buf_phys,
> +					    GFP_KERNEL);
> +
> +		if (!nandc->reg_read_buf)
> +			return -ENOMEM;
> +
> +		nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
> +		if (!nandc->tx_chan) {
> +			dev_err(nandc->dev, "failed to request tx channel\n");
> +			return -ENODEV;
> +		}
> +
> +		nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
> +		if (!nandc->rx_chan) {
> +			dev_err(nandc->dev, "failed to request rx channel\n");
> +			return -ENODEV;
> +		}
> +
> +		nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
> +		if (!nandc->cmd_chan) {
> +			dev_err(nandc->dev, "failed to request cmd channel\n");
> +			return -ENODEV;
> +		}
>  	}
>  
>  	INIT_LIST_HEAD(&nandc->desc_list);
> @@ -1978,7 +2022,19 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>  
>  static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
>  {
> -	dma_release_channel(nandc->chan);
> +	if (nandc->dma_bam_enabled) {
> +		if (nandc->tx_chan)
> +			dma_release_channel(nandc->tx_chan);
> +
> +		if (nandc->rx_chan)
> +			dma_release_channel(nandc->rx_chan);
> +
> +		if (nandc->cmd_chan)
> +			dma_release_channel(nandc->cmd_chan);
> +	} else {
> +		if (nandc->chan)
> +			dma_release_channel(nandc->chan);
> +	}
>  }
>  
>  /* one time setup of a few nand controller registers */
> @@ -2063,16 +2119,20 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
>  	struct device_node *np = nandc->dev->of_node;
>  	int ret;
>  
> -	ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
> -	if (ret) {
> -		dev_err(nandc->dev, "command CRCI unspecified\n");
> -		return ret;
> -	}
> +	if (!nandc->dma_bam_enabled) {
> +		ret = of_property_read_u32(np, "qcom,cmd-crci",
> +					   &nandc->cmd_crci);
> +		if (ret) {
> +			dev_err(nandc->dev, "command CRCI unspecified\n");
> +			return ret;
> +		}
>  
> -	ret = of_property_read_u32(np, "qcom,data-crci", &nandc->data_crci);
> -	if (ret) {
> -		dev_err(nandc->dev, "data CRCI unspecified\n");
> -		return ret;
> +		ret = of_property_read_u32(np, "qcom,data-crci",
> +					   &nandc->data_crci);
> +		if (ret) {
> +			dev_err(nandc->dev, "data CRCI unspecified\n");
> +			return ret;
> +		}
>  	}
>  
>  	return 0;
> @@ -2128,7 +2188,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>  
>  	ret = qcom_nandc_alloc(nandc);
>  	if (ret)
> -		return ret;
> +		goto err_core_clk;
>  
>  	ret = clk_prepare_enable(nandc->core_clk);
>  	if (ret)
> 

Can you please fix your mailer to stop adding "QUALCOMM INDIA, on behalf
of Qualcomm Innovation Center"... stuff at the bottom of the patches ?

-- 
Best regards,
Marek Vasut

Re: [PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources

[Abhishek Sahu]

On 2017-06-29 15:18, Marek Vasut wrote:
> On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
>> 1. The QPIC NAND uses 3 BAM channels: command, data tx and
>>    data rx while EBI2 NAND uses only single ADM channel.
>> 
>> 2. The EBI2 NAND uses normal register read buffer since this
>>    buffer will be remapped with dma_map_sg. The QPIC NAND will give
>>    register read buffer in command descriptor and the command
>>    descriptor will be mapped with dma_map_sg so the register buffer
>>    should be DMA coherent.
>> 
>> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> 
> The patch does two things, so make two patches. Also split the DT
> changes into separate patch ...

  Sure. I will do the same in v2.

> 
>> ---
>>  .../devicetree/bindings/mtd/qcom_nandc.txt         |  25 +++--
>>  drivers/mtd/nand/qcom_nandc.c                      | 106
>> ++++++++++++++++-----
>>  2 files changed, 99 insertions(+), 32 deletions(-)
>> 
>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> index 5d0f7ae..87b9a56 100644
>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> @@ -9,15 +9,17 @@ Required properties:
>>  - clock-names:		must contain "core" for the core clock and "aon" for 
>> the
>>  			always on clock
>>  - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
>> -			controller node and the channel number to be used for
>> -			NAND. Refer to dma.txt and qcom_adm.txt for more details
>> -- dma-names:		must be "rxtx"
>> -- qcom,cmd-crci:	must contain the ADM command type CRCI block 
>> instance
>> -			number specified for the NAND controller on the given
>> -			platform
>> -- qcom,data-crci:	must contain the ADM data type CRCI block instance
>> -			number specified for the NAND controller on the given
>> -			platform
>> +			or BAM DMA controller node and the channel number to
>> +			be used for NAND. Refer to dma.txt, qcom_adm.txt(ADM)
>> +			and qcom/bam_dma.txt(BAM) for more details
>> +- dma-names:		"rxtx" - ADM
>> +			"tx", "rx", "cmd" - BAM
>> +- qcom,cmd-crci:	Only required for ADM DMA. must contain the ADM 
>> command
>> +			type CRCI block instance number specified for the NAND
>> +			controller on the given platform.
>> +- qcom,data-crci:	Only required for ADM DMA. must contain the ADM 
>> data
>> +			type CRCI block instance number specified for the NAND
>> +			controller on the given platform.
>>  - #address-cells:	<1> - subnodes give the chip-select number
>>  - #size-cells:		<0>
>> 
>> @@ -95,6 +97,11 @@ nand@79b0000 {
>>  		<&gcc GCC_QPIC_AHB_CLK>;
>>  	clock-names = "core", "aon";
>> 
>> +	dmas = <&qpicbam 0>,
>> +		<&qpicbam 1>,
>> +		<&qpicbam 2>;
>> +	dma-names = "tx", "rx", "cmd";
>> +
>>  	#address-cells = <1>;
>>  	#size-cells = <0>;
>> 
>> diff --git a/drivers/mtd/nand/qcom_nandc.c 
>> b/drivers/mtd/nand/qcom_nandc.c
>> index f55f728..520add9 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -226,6 +226,7 @@ struct nandc_regs {
>>   *				by upper layers directly
>>   * @buf_size/count/start:	markers for chip->read_buf/write_buf 
>> functions
>>   * @reg_read_buf:		local buffer for reading back registers via DMA
>> + * @reg_read_buf_phys:		contains dma address for register read buffer
>>   * @reg_read_pos:		marker for data read in reg_read_buf
>>   *
>>   * @regs:			a contiguous chunk of memory for DMA register
>> @@ -249,9 +250,19 @@ struct qcom_nand_controller {
>>  	struct clk *core_clk;
>>  	struct clk *aon_clk;
>> 
>> -	struct dma_chan *chan;
>> -	unsigned int cmd_crci;
>> -	unsigned int data_crci;
>> +	union {
>> +		struct {
>> +			struct dma_chan *tx_chan;
>> +			struct dma_chan *rx_chan;
>> +			struct dma_chan *cmd_chan;
>> +		};
>> +		struct {
>> +			struct dma_chan *chan;
>> +			unsigned int cmd_crci;
>> +			unsigned int data_crci;
>> +		};
>> +	};
>> +
>>  	struct list_head desc_list;
>> 
>>  	u8		*data_buffer;
>> @@ -261,6 +272,7 @@ struct qcom_nand_controller {
>>  	int		buf_start;
>> 
>>  	__le32 *reg_read_buf;
>> +	dma_addr_t reg_read_buf_phys;
>>  	int reg_read_pos;
>> 
>>  	struct nandc_regs *regs;
>> @@ -1956,16 +1968,48 @@ static int qcom_nandc_alloc(struct
>> qcom_nand_controller *nandc)
>>  	if (!nandc->regs)
>>  		return -ENOMEM;
>> 
>> -	nandc->reg_read_buf = devm_kzalloc(nandc->dev,
>> -				MAX_REG_RD * sizeof(*nandc->reg_read_buf),
>> -				GFP_KERNEL);
>> -	if (!nandc->reg_read_buf)
>> -		return -ENOMEM;
>> 
>> -	nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
>> -	if (!nandc->chan) {
>> -		dev_err(nandc->dev, "failed to request slave channel\n");
>> -		return -ENODEV;
>> +	if (!nandc->dma_bam_enabled) {
>> +		nandc->reg_read_buf =
>> +			devm_kzalloc(nandc->dev, MAX_REG_RD *
>> +				     sizeof(*nandc->reg_read_buf), GFP_KERNEL);
>> +
>> +		if (!nandc->reg_read_buf)
>> +			return -ENOMEM;
>> +
>> +		nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
>> +		if (!nandc->chan) {
>> +			dev_err(nandc->dev,
>> +				"failed to request slave channel\n");
>> +			return -ENODEV;
>> +		}
>> +	} else {
>> +		nandc->reg_read_buf =
>> +			dmam_alloc_coherent(nandc->dev, MAX_REG_RD *
>> +					    sizeof(*nandc->reg_read_buf),
>> +					    &nandc->reg_read_buf_phys,
>> +					    GFP_KERNEL);
>> +
>> +		if (!nandc->reg_read_buf)
>> +			return -ENOMEM;
>> +
>> +		nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
>> +		if (!nandc->tx_chan) {
>> +			dev_err(nandc->dev, "failed to request tx channel\n");
>> +			return -ENODEV;
>> +		}
>> +
>> +		nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
>> +		if (!nandc->rx_chan) {
>> +			dev_err(nandc->dev, "failed to request rx channel\n");
>> +			return -ENODEV;
>> +		}
>> +
>> +		nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
>> +		if (!nandc->cmd_chan) {
>> +			dev_err(nandc->dev, "failed to request cmd channel\n");
>> +			return -ENODEV;
>> +		}
>>  	}
>> 
>>  	INIT_LIST_HEAD(&nandc->desc_list);
>> @@ -1978,7 +2022,19 @@ static int qcom_nandc_alloc(struct
>> qcom_nand_controller *nandc)
>> 
>>  static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
>>  {
>> -	dma_release_channel(nandc->chan);
>> +	if (nandc->dma_bam_enabled) {
>> +		if (nandc->tx_chan)
>> +			dma_release_channel(nandc->tx_chan);
>> +
>> +		if (nandc->rx_chan)
>> +			dma_release_channel(nandc->rx_chan);
>> +
>> +		if (nandc->cmd_chan)
>> +			dma_release_channel(nandc->cmd_chan);
>> +	} else {
>> +		if (nandc->chan)
>> +			dma_release_channel(nandc->chan);
>> +	}
>>  }
>> 
>>  /* one time setup of a few nand controller registers */
>> @@ -2063,16 +2119,20 @@ static int qcom_nandc_parse_dt(struct
>> platform_device *pdev)
>>  	struct device_node *np = nandc->dev->of_node;
>>  	int ret;
>> 
>> -	ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
>> -	if (ret) {
>> -		dev_err(nandc->dev, "command CRCI unspecified\n");
>> -		return ret;
>> -	}
>> +	if (!nandc->dma_bam_enabled) {
>> +		ret = of_property_read_u32(np, "qcom,cmd-crci",
>> +					   &nandc->cmd_crci);
>> +		if (ret) {
>> +			dev_err(nandc->dev, "command CRCI unspecified\n");
>> +			return ret;
>> +		}
>> 
>> -	ret = of_property_read_u32(np, "qcom,data-crci", &nandc->data_crci);
>> -	if (ret) {
>> -		dev_err(nandc->dev, "data CRCI unspecified\n");
>> -		return ret;
>> +		ret = of_property_read_u32(np, "qcom,data-crci",
>> +					   &nandc->data_crci);
>> +		if (ret) {
>> +			dev_err(nandc->dev, "data CRCI unspecified\n");
>> +			return ret;
>> +		}
>>  	}
>> 
>>  	return 0;
>> @@ -2128,7 +2188,7 @@ static int qcom_nandc_probe(struct 
>> platform_device
>> *pdev)
>> 
>>  	ret = qcom_nandc_alloc(nandc);
>>  	if (ret)
>> -		return ret;
>> +		goto err_core_clk;
>> 
>>  	ret = clk_prepare_enable(nandc->core_clk);
>>  	if (ret)
>> 
> 
> Can you please fix your mailer to stop adding "QUALCOMM INDIA, on 
> behalf
> of Qualcomm Innovation Center"... stuff at the bottom of the patches ?

  Sorry Marek. We can't remove this line since it is our legal
  team requirement and we need to follow this while submitting
  the patches.

  All the Qualcomm patches need be sent from codeaurora
  and this line implies that these patches are submitted from Qualcomm.
  this line will come only for the patches. For replying
  , this line will not come.

-- 
Abhishek Sahu
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Re: [PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources

[Abhishek Sahu]

On 2017-06-29 15:18, Marek Vasut wrote:
> On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
>> 1. The QPIC NAND uses 3 BAM channels: command, data tx and
>>    data rx while EBI2 NAND uses only single ADM channel.
>> 
>> 2. The EBI2 NAND uses normal register read buffer since this
>>    buffer will be remapped with dma_map_sg. The QPIC NAND will give
>>    register read buffer in command descriptor and the command
>>    descriptor will be mapped with dma_map_sg so the register buffer
>>    should be DMA coherent.
>> 
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> 
> The patch does two things, so make two patches. Also split the DT
> changes into separate patch ...

  Sure. I will do the same in v2.

> 
>> ---
>>  .../devicetree/bindings/mtd/qcom_nandc.txt         |  25 +++--
>>  drivers/mtd/nand/qcom_nandc.c                      | 106
>> ++++++++++++++++-----
>>  2 files changed, 99 insertions(+), 32 deletions(-)
>> 
>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> index 5d0f7ae..87b9a56 100644
>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> @@ -9,15 +9,17 @@ Required properties:
>>  - clock-names:		must contain "core" for the core clock and "aon" for 
>> the
>>  			always on clock
>>  - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
>> -			controller node and the channel number to be used for
>> -			NAND. Refer to dma.txt and qcom_adm.txt for more details
>> -- dma-names:		must be "rxtx"
>> -- qcom,cmd-crci:	must contain the ADM command type CRCI block 
>> instance
>> -			number specified for the NAND controller on the given
>> -			platform
>> -- qcom,data-crci:	must contain the ADM data type CRCI block instance
>> -			number specified for the NAND controller on the given
>> -			platform
>> +			or BAM DMA controller node and the channel number to
>> +			be used for NAND. Refer to dma.txt, qcom_adm.txt(ADM)
>> +			and qcom/bam_dma.txt(BAM) for more details
>> +- dma-names:		"rxtx" - ADM
>> +			"tx", "rx", "cmd" - BAM
>> +- qcom,cmd-crci:	Only required for ADM DMA. must contain the ADM 
>> command
>> +			type CRCI block instance number specified for the NAND
>> +			controller on the given platform.
>> +- qcom,data-crci:	Only required for ADM DMA. must contain the ADM 
>> data
>> +			type CRCI block instance number specified for the NAND
>> +			controller on the given platform.
>>  - #address-cells:	<1> - subnodes give the chip-select number
>>  - #size-cells:		<0>
>> 
>> @@ -95,6 +97,11 @@ nand@79b0000 {
>>  		<&gcc GCC_QPIC_AHB_CLK>;
>>  	clock-names = "core", "aon";
>> 
>> +	dmas = <&qpicbam 0>,
>> +		<&qpicbam 1>,
>> +		<&qpicbam 2>;
>> +	dma-names = "tx", "rx", "cmd";
>> +
>>  	#address-cells = <1>;
>>  	#size-cells = <0>;
>> 
>> diff --git a/drivers/mtd/nand/qcom_nandc.c 
>> b/drivers/mtd/nand/qcom_nandc.c
>> index f55f728..520add9 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -226,6 +226,7 @@ struct nandc_regs {
>>   *				by upper layers directly
>>   * @buf_size/count/start:	markers for chip->read_buf/write_buf 
>> functions
>>   * @reg_read_buf:		local buffer for reading back registers via DMA
>> + * @reg_read_buf_phys:		contains dma address for register read buffer
>>   * @reg_read_pos:		marker for data read in reg_read_buf
>>   *
>>   * @regs:			a contiguous chunk of memory for DMA register
>> @@ -249,9 +250,19 @@ struct qcom_nand_controller {
>>  	struct clk *core_clk;
>>  	struct clk *aon_clk;
>> 
>> -	struct dma_chan *chan;
>> -	unsigned int cmd_crci;
>> -	unsigned int data_crci;
>> +	union {
>> +		struct {
>> +			struct dma_chan *tx_chan;
>> +			struct dma_chan *rx_chan;
>> +			struct dma_chan *cmd_chan;
>> +		};
>> +		struct {
>> +			struct dma_chan *chan;
>> +			unsigned int cmd_crci;
>> +			unsigned int data_crci;
>> +		};
>> +	};
>> +
>>  	struct list_head desc_list;
>> 
>>  	u8		*data_buffer;
>> @@ -261,6 +272,7 @@ struct qcom_nand_controller {
>>  	int		buf_start;
>> 
>>  	__le32 *reg_read_buf;
>> +	dma_addr_t reg_read_buf_phys;
>>  	int reg_read_pos;
>> 
>>  	struct nandc_regs *regs;
>> @@ -1956,16 +1968,48 @@ static int qcom_nandc_alloc(struct
>> qcom_nand_controller *nandc)
>>  	if (!nandc->regs)
>>  		return -ENOMEM;
>> 
>> -	nandc->reg_read_buf = devm_kzalloc(nandc->dev,
>> -				MAX_REG_RD * sizeof(*nandc->reg_read_buf),
>> -				GFP_KERNEL);
>> -	if (!nandc->reg_read_buf)
>> -		return -ENOMEM;
>> 
>> -	nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
>> -	if (!nandc->chan) {
>> -		dev_err(nandc->dev, "failed to request slave channel\n");
>> -		return -ENODEV;
>> +	if (!nandc->dma_bam_enabled) {
>> +		nandc->reg_read_buf =
>> +			devm_kzalloc(nandc->dev, MAX_REG_RD *
>> +				     sizeof(*nandc->reg_read_buf), GFP_KERNEL);
>> +
>> +		if (!nandc->reg_read_buf)
>> +			return -ENOMEM;
>> +
>> +		nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
>> +		if (!nandc->chan) {
>> +			dev_err(nandc->dev,
>> +				"failed to request slave channel\n");
>> +			return -ENODEV;
>> +		}
>> +	} else {
>> +		nandc->reg_read_buf =
>> +			dmam_alloc_coherent(nandc->dev, MAX_REG_RD *
>> +					    sizeof(*nandc->reg_read_buf),
>> +					    &nandc->reg_read_buf_phys,
>> +					    GFP_KERNEL);
>> +
>> +		if (!nandc->reg_read_buf)
>> +			return -ENOMEM;
>> +
>> +		nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
>> +		if (!nandc->tx_chan) {
>> +			dev_err(nandc->dev, "failed to request tx channel\n");
>> +			return -ENODEV;
>> +		}
>> +
>> +		nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
>> +		if (!nandc->rx_chan) {
>> +			dev_err(nandc->dev, "failed to request rx channel\n");
>> +			return -ENODEV;
>> +		}
>> +
>> +		nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
>> +		if (!nandc->cmd_chan) {
>> +			dev_err(nandc->dev, "failed to request cmd channel\n");
>> +			return -ENODEV;
>> +		}
>>  	}
>> 
>>  	INIT_LIST_HEAD(&nandc->desc_list);
>> @@ -1978,7 +2022,19 @@ static int qcom_nandc_alloc(struct
>> qcom_nand_controller *nandc)
>> 
>>  static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
>>  {
>> -	dma_release_channel(nandc->chan);
>> +	if (nandc->dma_bam_enabled) {
>> +		if (nandc->tx_chan)
>> +			dma_release_channel(nandc->tx_chan);
>> +
>> +		if (nandc->rx_chan)
>> +			dma_release_channel(nandc->rx_chan);
>> +
>> +		if (nandc->cmd_chan)
>> +			dma_release_channel(nandc->cmd_chan);
>> +	} else {
>> +		if (nandc->chan)
>> +			dma_release_channel(nandc->chan);
>> +	}
>>  }
>> 
>>  /* one time setup of a few nand controller registers */
>> @@ -2063,16 +2119,20 @@ static int qcom_nandc_parse_dt(struct
>> platform_device *pdev)
>>  	struct device_node *np = nandc->dev->of_node;
>>  	int ret;
>> 
>> -	ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
>> -	if (ret) {
>> -		dev_err(nandc->dev, "command CRCI unspecified\n");
>> -		return ret;
>> -	}
>> +	if (!nandc->dma_bam_enabled) {
>> +		ret = of_property_read_u32(np, "qcom,cmd-crci",
>> +					   &nandc->cmd_crci);
>> +		if (ret) {
>> +			dev_err(nandc->dev, "command CRCI unspecified\n");
>> +			return ret;
>> +		}
>> 
>> -	ret = of_property_read_u32(np, "qcom,data-crci", &nandc->data_crci);
>> -	if (ret) {
>> -		dev_err(nandc->dev, "data CRCI unspecified\n");
>> -		return ret;
>> +		ret = of_property_read_u32(np, "qcom,data-crci",
>> +					   &nandc->data_crci);
>> +		if (ret) {
>> +			dev_err(nandc->dev, "data CRCI unspecified\n");
>> +			return ret;
>> +		}
>>  	}
>> 
>>  	return 0;
>> @@ -2128,7 +2188,7 @@ static int qcom_nandc_probe(struct 
>> platform_device
>> *pdev)
>> 
>>  	ret = qcom_nandc_alloc(nandc);
>>  	if (ret)
>> -		return ret;
>> +		goto err_core_clk;
>> 
>>  	ret = clk_prepare_enable(nandc->core_clk);
>>  	if (ret)
>> 
> 
> Can you please fix your mailer to stop adding "QUALCOMM INDIA, on 
> behalf
> of Qualcomm Innovation Center"... stuff at the bottom of the patches ?

  Sorry Marek. We can't remove this line since it is our legal
  team requirement and we need to follow this while submitting
  the patches.

  All the Qualcomm patches need be sent from codeaurora
  and this line implies that these patches are submitted from Qualcomm.
  this line will come only for the patches. For replying
  , this line will not come.

-- 
Abhishek Sahu

Re: [PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources

[Archit Taneja]

On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
> 1. The QPIC NAND uses 3 BAM channels: command, data tx and
>     data rx while EBI2 NAND uses only single ADM channel.
> 
> 2. The EBI2 NAND uses normal register read buffer since this
>     buffer will be remapped with dma_map_sg. The QPIC NAND will give
>     register read buffer in command descriptor and the command
>     descriptor will be mapped with dma_map_sg so the register buffer
>     should be DMA coherent.

It isn't entirely clear from this commit message why we require
reg_read_buf to be DMA coherent for QPIC NAND. Could you please explain this
better?

Besides Marek's comment to splitting the patch, it looks okay to me.

Thanks,
Archit

> 
> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>   .../devicetree/bindings/mtd/qcom_nandc.txt         |  25 +++--
>   drivers/mtd/nand/qcom_nandc.c                      | 106 ++++++++++++++++-----
>   2 files changed, 99 insertions(+), 32 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 5d0f7ae..87b9a56 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -9,15 +9,17 @@ Required properties:
>   - clock-names:		must contain "core" for the core clock and "aon" for the
>   			always on clock
>   - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
> -			controller node and the channel number to be used for
> -			NAND. Refer to dma.txt and qcom_adm.txt for more details
> -- dma-names:		must be "rxtx"
> -- qcom,cmd-crci:	must contain the ADM command type CRCI block instance
> -			number specified for the NAND controller on the given
> -			platform
> -- qcom,data-crci:	must contain the ADM data type CRCI block instance
> -			number specified for the NAND controller on the given
> -			platform
> +			or BAM DMA controller node and the channel number to
> +			be used for NAND. Refer to dma.txt, qcom_adm.txt(ADM)
> +			and qcom/bam_dma.txt(BAM) for more details
> +- dma-names:		"rxtx" - ADM
> +			"tx", "rx", "cmd" - BAM
> +- qcom,cmd-crci:	Only required for ADM DMA. must contain the ADM command
> +			type CRCI block instance number specified for the NAND
> +			controller on the given platform.
> +- qcom,data-crci:	Only required for ADM DMA. must contain the ADM data
> +			type CRCI block instance number specified for the NAND
> +			controller on the given platform.
>   - #address-cells:	<1> - subnodes give the chip-select number
>   - #size-cells:		<0>
>   
> @@ -95,6 +97,11 @@ nand@79b0000 {
>   		<&gcc GCC_QPIC_AHB_CLK>;
>   	clock-names = "core", "aon";
>   
> +	dmas = <&qpicbam 0>,
> +		<&qpicbam 1>,
> +		<&qpicbam 2>;
> +	dma-names = "tx", "rx", "cmd";
> +
>   	#address-cells = <1>;
>   	#size-cells = <0>;
>   
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index f55f728..520add9 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -226,6 +226,7 @@ struct nandc_regs {
>    *				by upper layers directly
>    * @buf_size/count/start:	markers for chip->read_buf/write_buf functions
>    * @reg_read_buf:		local buffer for reading back registers via DMA
> + * @reg_read_buf_phys:		contains dma address for register read buffer
>    * @reg_read_pos:		marker for data read in reg_read_buf
>    *
>    * @regs:			a contiguous chunk of memory for DMA register
> @@ -249,9 +250,19 @@ struct qcom_nand_controller {
>   	struct clk *core_clk;
>   	struct clk *aon_clk;
>   
> -	struct dma_chan *chan;
> -	unsigned int cmd_crci;
> -	unsigned int data_crci;
> +	union {
> +		struct {
> +			struct dma_chan *tx_chan;
> +			struct dma_chan *rx_chan;
> +			struct dma_chan *cmd_chan;
> +		};
> +		struct {
> +			struct dma_chan *chan;
> +			unsigned int cmd_crci;
> +			unsigned int data_crci;
> +		};
> +	};
> +
>   	struct list_head desc_list;
>   
>   	u8		*data_buffer;
> @@ -261,6 +272,7 @@ struct qcom_nand_controller {
>   	int		buf_start;
>   
>   	__le32 *reg_read_buf;
> +	dma_addr_t reg_read_buf_phys;
>   	int reg_read_pos;
>   
>   	struct nandc_regs *regs;
> @@ -1956,16 +1968,48 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>   	if (!nandc->regs)
>   		return -ENOMEM;
>   
> -	nandc->reg_read_buf = devm_kzalloc(nandc->dev,
> -				MAX_REG_RD * sizeof(*nandc->reg_read_buf),
> -				GFP_KERNEL);
> -	if (!nandc->reg_read_buf)
> -		return -ENOMEM;
>   
> -	nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> -	if (!nandc->chan) {
> -		dev_err(nandc->dev, "failed to request slave channel\n");
> -		return -ENODEV;
> +	if (!nandc->dma_bam_enabled) {
> +		nandc->reg_read_buf =
> +			devm_kzalloc(nandc->dev, MAX_REG_RD *
> +				     sizeof(*nandc->reg_read_buf), GFP_KERNEL);
> +
> +		if (!nandc->reg_read_buf)
> +			return -ENOMEM;
> +
> +		nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> +		if (!nandc->chan) {
> +			dev_err(nandc->dev,
> +				"failed to request slave channel\n");
> +			return -ENODEV;
> +		}
> +	} else {
> +		nandc->reg_read_buf =
> +			dmam_alloc_coherent(nandc->dev, MAX_REG_RD *
> +					    sizeof(*nandc->reg_read_buf),
> +					    &nandc->reg_read_buf_phys,
> +					    GFP_KERNEL);
> +
> +		if (!nandc->reg_read_buf)
> +			return -ENOMEM;
> +
> +		nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
> +		if (!nandc->tx_chan) {
> +			dev_err(nandc->dev, "failed to request tx channel\n");
> +			return -ENODEV;
> +		}
> +
> +		nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
> +		if (!nandc->rx_chan) {
> +			dev_err(nandc->dev, "failed to request rx channel\n");
> +			return -ENODEV;
> +		}
> +
> +		nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
> +		if (!nandc->cmd_chan) {
> +			dev_err(nandc->dev, "failed to request cmd channel\n");
> +			return -ENODEV;
> +		}
>   	}
>   
>   	INIT_LIST_HEAD(&nandc->desc_list);
> @@ -1978,7 +2022,19 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>   
>   static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
>   {
> -	dma_release_channel(nandc->chan);
> +	if (nandc->dma_bam_enabled) {
> +		if (nandc->tx_chan)
> +			dma_release_channel(nandc->tx_chan);
> +
> +		if (nandc->rx_chan)
> +			dma_release_channel(nandc->rx_chan);
> +
> +		if (nandc->cmd_chan)
> +			dma_release_channel(nandc->cmd_chan);
> +	} else {
> +		if (nandc->chan)
> +			dma_release_channel(nandc->chan);
> +	}
>   }
>   
>   /* one time setup of a few nand controller registers */
> @@ -2063,16 +2119,20 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
>   	struct device_node *np = nandc->dev->of_node;
>   	int ret;
>   
> -	ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
> -	if (ret) {
> -		dev_err(nandc->dev, "command CRCI unspecified\n");
> -		return ret;
> -	}
> +	if (!nandc->dma_bam_enabled) {
> +		ret = of_property_read_u32(np, "qcom,cmd-crci",
> +					   &nandc->cmd_crci);
> +		if (ret) {
> +			dev_err(nandc->dev, "command CRCI unspecified\n");
> +			return ret;
> +		}
>   
> -	ret = of_property_read_u32(np, "qcom,data-crci", &nandc->data_crci);
> -	if (ret) {
> -		dev_err(nandc->dev, "data CRCI unspecified\n");
> -		return ret;
> +		ret = of_property_read_u32(np, "qcom,data-crci",
> +					   &nandc->data_crci);
> +		if (ret) {
> +			dev_err(nandc->dev, "data CRCI unspecified\n");
> +			return ret;
> +		}
>   	}
>   
>   	return 0;
> @@ -2128,7 +2188,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>   
>   	ret = qcom_nandc_alloc(nandc);
>   	if (ret)
> -		return ret;
> +		goto err_core_clk;
>   
>   	ret = clk_prepare_enable(nandc->core_clk);
>   	if (ret)
> 

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Re: [PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources

[Archit Taneja]

On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
> 1. The QPIC NAND uses 3 BAM channels: command, data tx and
>     data rx while EBI2 NAND uses only single ADM channel.
> 
> 2. The EBI2 NAND uses normal register read buffer since this
>     buffer will be remapped with dma_map_sg. The QPIC NAND will give
>     register read buffer in command descriptor and the command
>     descriptor will be mapped with dma_map_sg so the register buffer
>     should be DMA coherent.

It isn't entirely clear from this commit message why we require
reg_read_buf to be DMA coherent for QPIC NAND. Could you please explain this
better?

Besides Marek's comment to splitting the patch, it looks okay to me.

Thanks,
Archit

> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>   .../devicetree/bindings/mtd/qcom_nandc.txt         |  25 +++--
>   drivers/mtd/nand/qcom_nandc.c                      | 106 ++++++++++++++++-----
>   2 files changed, 99 insertions(+), 32 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 5d0f7ae..87b9a56 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -9,15 +9,17 @@ Required properties:
>   - clock-names:		must contain "core" for the core clock and "aon" for the
>   			always on clock
>   - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
> -			controller node and the channel number to be used for
> -			NAND. Refer to dma.txt and qcom_adm.txt for more details
> -- dma-names:		must be "rxtx"
> -- qcom,cmd-crci:	must contain the ADM command type CRCI block instance
> -			number specified for the NAND controller on the given
> -			platform
> -- qcom,data-crci:	must contain the ADM data type CRCI block instance
> -			number specified for the NAND controller on the given
> -			platform
> +			or BAM DMA controller node and the channel number to
> +			be used for NAND. Refer to dma.txt, qcom_adm.txt(ADM)
> +			and qcom/bam_dma.txt(BAM) for more details
> +- dma-names:		"rxtx" - ADM
> +			"tx", "rx", "cmd" - BAM
> +- qcom,cmd-crci:	Only required for ADM DMA. must contain the ADM command
> +			type CRCI block instance number specified for the NAND
> +			controller on the given platform.
> +- qcom,data-crci:	Only required for ADM DMA. must contain the ADM data
> +			type CRCI block instance number specified for the NAND
> +			controller on the given platform.
>   - #address-cells:	<1> - subnodes give the chip-select number
>   - #size-cells:		<0>
>   
> @@ -95,6 +97,11 @@ nand@79b0000 {
>   		<&gcc GCC_QPIC_AHB_CLK>;
>   	clock-names = "core", "aon";
>   
> +	dmas = <&qpicbam 0>,
> +		<&qpicbam 1>,
> +		<&qpicbam 2>;
> +	dma-names = "tx", "rx", "cmd";
> +
>   	#address-cells = <1>;
>   	#size-cells = <0>;
>   
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index f55f728..520add9 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -226,6 +226,7 @@ struct nandc_regs {
>    *				by upper layers directly
>    * @buf_size/count/start:	markers for chip->read_buf/write_buf functions
>    * @reg_read_buf:		local buffer for reading back registers via DMA
> + * @reg_read_buf_phys:		contains dma address for register read buffer
>    * @reg_read_pos:		marker for data read in reg_read_buf
>    *
>    * @regs:			a contiguous chunk of memory for DMA register
> @@ -249,9 +250,19 @@ struct qcom_nand_controller {
>   	struct clk *core_clk;
>   	struct clk *aon_clk;
>   
> -	struct dma_chan *chan;
> -	unsigned int cmd_crci;
> -	unsigned int data_crci;
> +	union {
> +		struct {
> +			struct dma_chan *tx_chan;
> +			struct dma_chan *rx_chan;
> +			struct dma_chan *cmd_chan;
> +		};
> +		struct {
> +			struct dma_chan *chan;
> +			unsigned int cmd_crci;
> +			unsigned int data_crci;
> +		};
> +	};
> +
>   	struct list_head desc_list;
>   
>   	u8		*data_buffer;
> @@ -261,6 +272,7 @@ struct qcom_nand_controller {
>   	int		buf_start;
>   
>   	__le32 *reg_read_buf;
> +	dma_addr_t reg_read_buf_phys;
>   	int reg_read_pos;
>   
>   	struct nandc_regs *regs;
> @@ -1956,16 +1968,48 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>   	if (!nandc->regs)
>   		return -ENOMEM;
>   
> -	nandc->reg_read_buf = devm_kzalloc(nandc->dev,
> -				MAX_REG_RD * sizeof(*nandc->reg_read_buf),
> -				GFP_KERNEL);
> -	if (!nandc->reg_read_buf)
> -		return -ENOMEM;
>   
> -	nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> -	if (!nandc->chan) {
> -		dev_err(nandc->dev, "failed to request slave channel\n");
> -		return -ENODEV;
> +	if (!nandc->dma_bam_enabled) {
> +		nandc->reg_read_buf =
> +			devm_kzalloc(nandc->dev, MAX_REG_RD *
> +				     sizeof(*nandc->reg_read_buf), GFP_KERNEL);
> +
> +		if (!nandc->reg_read_buf)
> +			return -ENOMEM;
> +
> +		nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> +		if (!nandc->chan) {
> +			dev_err(nandc->dev,
> +				"failed to request slave channel\n");
> +			return -ENODEV;
> +		}
> +	} else {
> +		nandc->reg_read_buf =
> +			dmam_alloc_coherent(nandc->dev, MAX_REG_RD *
> +					    sizeof(*nandc->reg_read_buf),
> +					    &nandc->reg_read_buf_phys,
> +					    GFP_KERNEL);
> +
> +		if (!nandc->reg_read_buf)
> +			return -ENOMEM;
> +
> +		nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
> +		if (!nandc->tx_chan) {
> +			dev_err(nandc->dev, "failed to request tx channel\n");
> +			return -ENODEV;
> +		}
> +
> +		nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
> +		if (!nandc->rx_chan) {
> +			dev_err(nandc->dev, "failed to request rx channel\n");
> +			return -ENODEV;
> +		}
> +
> +		nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
> +		if (!nandc->cmd_chan) {
> +			dev_err(nandc->dev, "failed to request cmd channel\n");
> +			return -ENODEV;
> +		}
>   	}
>   
>   	INIT_LIST_HEAD(&nandc->desc_list);
> @@ -1978,7 +2022,19 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>   
>   static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
>   {
> -	dma_release_channel(nandc->chan);
> +	if (nandc->dma_bam_enabled) {
> +		if (nandc->tx_chan)
> +			dma_release_channel(nandc->tx_chan);
> +
> +		if (nandc->rx_chan)
> +			dma_release_channel(nandc->rx_chan);
> +
> +		if (nandc->cmd_chan)
> +			dma_release_channel(nandc->cmd_chan);
> +	} else {
> +		if (nandc->chan)
> +			dma_release_channel(nandc->chan);
> +	}
>   }
>   
>   /* one time setup of a few nand controller registers */
> @@ -2063,16 +2119,20 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
>   	struct device_node *np = nandc->dev->of_node;
>   	int ret;
>   
> -	ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
> -	if (ret) {
> -		dev_err(nandc->dev, "command CRCI unspecified\n");
> -		return ret;
> -	}
> +	if (!nandc->dma_bam_enabled) {
> +		ret = of_property_read_u32(np, "qcom,cmd-crci",
> +					   &nandc->cmd_crci);
> +		if (ret) {
> +			dev_err(nandc->dev, "command CRCI unspecified\n");
> +			return ret;
> +		}
>   
> -	ret = of_property_read_u32(np, "qcom,data-crci", &nandc->data_crci);
> -	if (ret) {
> -		dev_err(nandc->dev, "data CRCI unspecified\n");
> -		return ret;
> +		ret = of_property_read_u32(np, "qcom,data-crci",
> +					   &nandc->data_crci);
> +		if (ret) {
> +			dev_err(nandc->dev, "data CRCI unspecified\n");
> +			return ret;
> +		}
>   	}
>   
>   	return 0;
> @@ -2128,7 +2188,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>   
>   	ret = qcom_nandc_alloc(nandc);
>   	if (ret)
> -		return ret;
> +		goto err_core_clk;
>   
>   	ret = clk_prepare_enable(nandc->core_clk);
>   	if (ret)
> 

-- 
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a Linux Foundation Collaborative Project

Re: [PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources

[Abhishek Sahu]

On 2017-07-03 10:47, Archit Taneja wrote:
> On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
>> 1. The QPIC NAND uses 3 BAM channels: command, data tx and
>>     data rx while EBI2 NAND uses only single ADM channel.
>> 
>> 2. The EBI2 NAND uses normal register read buffer since this
>>     buffer will be remapped with dma_map_sg. The QPIC NAND will give
>>     register read buffer in command descriptor and the command
>>     descriptor will be mapped with dma_map_sg so the register buffer
>>     should be DMA coherent.
> 
> It isn't entirely clear from this commit message why we require
> reg_read_buf to be DMA coherent for QPIC NAND. Could you please explain 
> this
> better?

  I have used DMA coherent since we need to pass this memory in
  command descriptor where BAM will fill the register contents.
  Now for v2, I have planned to use streaming DMA API's and its
  working fine.



> 
> Besides Marek's comment to splitting the patch, it looks okay to me.
> 
> Thanks,
> Archit
> 
>> 
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> ---
>>   .../devicetree/bindings/mtd/qcom_nandc.txt         |  25 +++--
>>   drivers/mtd/nand/qcom_nandc.c                      | 106 
>> ++++++++++++++++-----
>>   2 files changed, 99 insertions(+), 32 deletions(-)
>> 
>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt 
>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> index 5d0f7ae..87b9a56 100644
>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> @@ -9,15 +9,17 @@ Required properties:
>>   - clock-names:		must contain "core" for the core clock and "aon" for 
>> the
>>   			always on clock
>>   - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
>> -			controller node and the channel number to be used for
>> -			NAND. Refer to dma.txt and qcom_adm.txt for more details
>> -- dma-names:		must be "rxtx"
>> -- qcom,cmd-crci:	must contain the ADM command type CRCI block 
>> instance
>> -			number specified for the NAND controller on the given
>> -			platform
>> -- qcom,data-crci:	must contain the ADM data type CRCI block instance
>> -			number specified for the NAND controller on the given
>> -			platform
>> +			or BAM DMA controller node and the channel number to
>> +			be used for NAND. Refer to dma.txt, qcom_adm.txt(ADM)
>> +			and qcom/bam_dma.txt(BAM) for more details
>> +- dma-names:		"rxtx" - ADM
>> +			"tx", "rx", "cmd" - BAM
>> +- qcom,cmd-crci:	Only required for ADM DMA. must contain the ADM 
>> command
>> +			type CRCI block instance number specified for the NAND
>> +			controller on the given platform.
>> +- qcom,data-crci:	Only required for ADM DMA. must contain the ADM 
>> data
>> +			type CRCI block instance number specified for the NAND
>> +			controller on the given platform.
>>   - #address-cells:	<1> - subnodes give the chip-select number
>>   - #size-cells:		<0>
>> 
>> @@ -95,6 +97,11 @@ nand@79b0000 {
>>   		<&gcc GCC_QPIC_AHB_CLK>;
>>   	clock-names = "core", "aon";
>> 
>> +	dmas = <&qpicbam 0>,
>> +		<&qpicbam 1>,
>> +		<&qpicbam 2>;
>> +	dma-names = "tx", "rx", "cmd";
>> +
>>   	#address-cells = <1>;
>>   	#size-cells = <0>;
>> 
>> diff --git a/drivers/mtd/nand/qcom_nandc.c 
>> b/drivers/mtd/nand/qcom_nandc.c
>> index f55f728..520add9 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -226,6 +226,7 @@ struct nandc_regs {
>>    *				by upper layers directly
>>    * @buf_size/count/start:	markers for chip->read_buf/write_buf 
>> functions
>>    * @reg_read_buf:		local buffer for reading back registers via DMA
>> + * @reg_read_buf_phys:		contains dma address for register read buffer
>>    * @reg_read_pos:		marker for data read in reg_read_buf
>>    *
>>    * @regs:			a contiguous chunk of memory for DMA register
>> @@ -249,9 +250,19 @@ struct qcom_nand_controller {
>>   	struct clk *core_clk;
>>   	struct clk *aon_clk;
>> 
>> -	struct dma_chan *chan;
>> -	unsigned int cmd_crci;
>> -	unsigned int data_crci;
>> +	union {
>> +		struct {
>> +			struct dma_chan *tx_chan;
>> +			struct dma_chan *rx_chan;
>> +			struct dma_chan *cmd_chan;
>> +		};
>> +		struct {
>> +			struct dma_chan *chan;
>> +			unsigned int cmd_crci;
>> +			unsigned int data_crci;
>> +		};
>> +	};
>> +
>>   	struct list_head desc_list;
>> 
>>   	u8		*data_buffer;
>> @@ -261,6 +272,7 @@ struct qcom_nand_controller {
>>   	int		buf_start;
>> 
>>   	__le32 *reg_read_buf;
>> +	dma_addr_t reg_read_buf_phys;
>>   	int reg_read_pos;
>> 
>>   	struct nandc_regs *regs;
>> @@ -1956,16 +1968,48 @@ static int qcom_nandc_alloc(struct 
>> qcom_nand_controller *nandc)
>>   	if (!nandc->regs)
>>   		return -ENOMEM;
>> 
>> -	nandc->reg_read_buf = devm_kzalloc(nandc->dev,
>> -				MAX_REG_RD * sizeof(*nandc->reg_read_buf),
>> -				GFP_KERNEL);
>> -	if (!nandc->reg_read_buf)
>> -		return -ENOMEM;
>> 
>> -	nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
>> -	if (!nandc->chan) {
>> -		dev_err(nandc->dev, "failed to request slave channel\n");
>> -		return -ENODEV;
>> +	if (!nandc->dma_bam_enabled) {
>> +		nandc->reg_read_buf =
>> +			devm_kzalloc(nandc->dev, MAX_REG_RD *
>> +				     sizeof(*nandc->reg_read_buf), GFP_KERNEL);
>> +
>> +		if (!nandc->reg_read_buf)
>> +			return -ENOMEM;
>> +
>> +		nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
>> +		if (!nandc->chan) {
>> +			dev_err(nandc->dev,
>> +				"failed to request slave channel\n");
>> +			return -ENODEV;
>> +		}
>> +	} else {
>> +		nandc->reg_read_buf =
>> +			dmam_alloc_coherent(nandc->dev, MAX_REG_RD *
>> +					    sizeof(*nandc->reg_read_buf),
>> +					    &nandc->reg_read_buf_phys,
>> +					    GFP_KERNEL);
>> +
>> +		if (!nandc->reg_read_buf)
>> +			return -ENOMEM;
>> +
>> +		nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
>> +		if (!nandc->tx_chan) {
>> +			dev_err(nandc->dev, "failed to request tx channel\n");
>> +			return -ENODEV;
>> +		}
>> +
>> +		nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
>> +		if (!nandc->rx_chan) {
>> +			dev_err(nandc->dev, "failed to request rx channel\n");
>> +			return -ENODEV;
>> +		}
>> +
>> +		nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
>> +		if (!nandc->cmd_chan) {
>> +			dev_err(nandc->dev, "failed to request cmd channel\n");
>> +			return -ENODEV;
>> +		}
>>   	}
>> 
>>   	INIT_LIST_HEAD(&nandc->desc_list);
>> @@ -1978,7 +2022,19 @@ static int qcom_nandc_alloc(struct 
>> qcom_nand_controller *nandc)
>> 
>>   static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
>>   {
>> -	dma_release_channel(nandc->chan);
>> +	if (nandc->dma_bam_enabled) {
>> +		if (nandc->tx_chan)
>> +			dma_release_channel(nandc->tx_chan);
>> +
>> +		if (nandc->rx_chan)
>> +			dma_release_channel(nandc->rx_chan);
>> +
>> +		if (nandc->cmd_chan)
>> +			dma_release_channel(nandc->cmd_chan);
>> +	} else {
>> +		if (nandc->chan)
>> +			dma_release_channel(nandc->chan);
>> +	}
>>   }
>> 
>>   /* one time setup of a few nand controller registers */
>> @@ -2063,16 +2119,20 @@ static int qcom_nandc_parse_dt(struct 
>> platform_device *pdev)
>>   	struct device_node *np = nandc->dev->of_node;
>>   	int ret;
>> 
>> -	ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
>> -	if (ret) {
>> -		dev_err(nandc->dev, "command CRCI unspecified\n");
>> -		return ret;
>> -	}
>> +	if (!nandc->dma_bam_enabled) {
>> +		ret = of_property_read_u32(np, "qcom,cmd-crci",
>> +					   &nandc->cmd_crci);
>> +		if (ret) {
>> +			dev_err(nandc->dev, "command CRCI unspecified\n");
>> +			return ret;
>> +		}
>> 
>> -	ret = of_property_read_u32(np, "qcom,data-crci", &nandc->data_crci);
>> -	if (ret) {
>> -		dev_err(nandc->dev, "data CRCI unspecified\n");
>> -		return ret;
>> +		ret = of_property_read_u32(np, "qcom,data-crci",
>> +					   &nandc->data_crci);
>> +		if (ret) {
>> +			dev_err(nandc->dev, "data CRCI unspecified\n");
>> +			return ret;
>> +		}
>>   	}
>> 
>>   	return 0;
>> @@ -2128,7 +2188,7 @@ static int qcom_nandc_probe(struct 
>> platform_device *pdev)
>> 
>>   	ret = qcom_nandc_alloc(nandc);
>>   	if (ret)
>> -		return ret;
>> +		goto err_core_clk;
>> 
>>   	ret = clk_prepare_enable(nandc->core_clk);
>>   	if (ret)
>> 

-- 
Abhishek Sahu

Re: [PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources

[Sricharan R]

Hi Abhishek,


On 6/29/2017 12:45 PM, Abhishek Sahu wrote:
> 1. The QPIC NAND uses 3 BAM channels: command, data tx and
>    data rx while EBI2 NAND uses only single ADM channel.
> 
> 2. The EBI2 NAND uses normal register read buffer since this
>    buffer will be remapped with dma_map_sg. The QPIC NAND will give
>    register read buffer in command descriptor and the command
>    descriptor will be mapped with dma_map_sg so the register buffer
>    should be DMA coherent.
> 
> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>  .../devicetree/bindings/mtd/qcom_nandc.txt         |  25 +++--
>  drivers/mtd/nand/qcom_nandc.c                      | 106 ++++++++++++++++-----
>  2 files changed, 99 insertions(+), 32 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 5d0f7ae..87b9a56 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -9,15 +9,17 @@ Required properties:
>  - clock-names:		must contain "core" for the core clock and "aon" for the
>  			always on clock
>  - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
> -			controller node and the channel number to be used for
> -			NAND. Refer to dma.txt and qcom_adm.txt for more details
> -- dma-names:		must be "rxtx"
> -- qcom,cmd-crci:	must contain the ADM command type CRCI block instance
> -			number specified for the NAND controller on the given
> -			platform
> -- qcom,data-crci:	must contain the ADM data type CRCI block instance
> -			number specified for the NAND controller on the given
> -			platform
> +			or BAM DMA controller node and the channel number to
> +			be used for NAND. Refer to dma.txt, qcom_adm.txt(ADM)
> +			and qcom/bam_dma.txt(BAM) for more details
> +- dma-names:		"rxtx" - ADM
> +			"tx", "rx", "cmd" - BAM
> +- qcom,cmd-crci:	Only required for ADM DMA. must contain the ADM command
> +			type CRCI block instance number specified for the NAND
> +			controller on the given platform.
> +- qcom,data-crci:	Only required for ADM DMA. must contain the ADM data
> +			type CRCI block instance number specified for the NAND
> +			controller on the given platform.

  May be better to put the parameter list that are specific to ADMA and BAM under
  seperate groups and those common for both in one group, instead of mentioning
  at each of the property level.

>  - #address-cells:	<1> - subnodes give the chip-select number
>  - #size-cells:		<0>
>  
> @@ -95,6 +97,11 @@ nand@79b0000 {
>  		<&gcc GCC_QPIC_AHB_CLK>;
>  	clock-names = "core", "aon";
>  
> +	dmas = <&qpicbam 0>,
> +		<&qpicbam 1>,
> +		<&qpicbam 2>;
> +	dma-names = "tx", "rx", "cmd";
> +
>  	#address-cells = <1>;
>  	#size-cells = <0>;
>  
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index f55f728..520add9 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -226,6 +226,7 @@ struct nandc_regs {
>   *				by upper layers directly
>   * @buf_size/count/start:	markers for chip->read_buf/write_buf functions
>   * @reg_read_buf:		local buffer for reading back registers via DMA
> + * @reg_read_buf_phys:		contains dma address for register read buffer
>   * @reg_read_pos:		marker for data read in reg_read_buf
>   *
>   * @regs:			a contiguous chunk of memory for DMA register
> @@ -249,9 +250,19 @@ struct qcom_nand_controller {
>  	struct clk *core_clk;
>  	struct clk *aon_clk;
>  
> -	struct dma_chan *chan;
> -	unsigned int cmd_crci;
> -	unsigned int data_crci;
> +	union {
> +		struct {
> +			struct dma_chan *tx_chan;
> +			struct dma_chan *rx_chan;
> +			struct dma_chan *cmd_chan;
> +		};
> +		struct {
> +			struct dma_chan *chan;
> +			unsigned int cmd_crci;
> +			unsigned int data_crci;
> +		};
> +	};
> +
>  	struct list_head desc_list;
>  
>  	u8		*data_buffer;
> @@ -261,6 +272,7 @@ struct qcom_nand_controller {
>  	int		buf_start;
>  
>  	__le32 *reg_read_buf;
> +	dma_addr_t reg_read_buf_phys;
>  	int reg_read_pos;
>  
>  	struct nandc_regs *regs;
> @@ -1956,16 +1968,48 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>  	if (!nandc->regs)
>  		return -ENOMEM;
>  
> -	nandc->reg_read_buf = devm_kzalloc(nandc->dev,
> -				MAX_REG_RD * sizeof(*nandc->reg_read_buf),
> -				GFP_KERNEL);
> -	if (!nandc->reg_read_buf)
> -		return -ENOMEM;
>  
> -	nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> -	if (!nandc->chan) {
> -		dev_err(nandc->dev, "failed to request slave channel\n");
> -		return -ENODEV;
> +	if (!nandc->dma_bam_enabled) {

 Better to swap if, else part to avoid !

> +		nandc->reg_read_buf =
> +			devm_kzalloc(nandc->dev, MAX_REG_RD *
> +				     sizeof(*nandc->reg_read_buf), GFP_KERNEL);
> +
> +		if (!nandc->reg_read_buf)
> +			return -ENOMEM;
> +
> +		nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> +		if (!nandc->chan) {
> +			dev_err(nandc->dev,
> +				"failed to request slave channel\n");
> +			return -ENODEV;
> +		}
> +	} else {
> +		nandc->reg_read_buf =
> +			dmam_alloc_coherent(nandc->dev, MAX_REG_RD *
> +					    sizeof(*nandc->reg_read_buf),
> +					    &nandc->reg_read_buf_phys,
> +					    GFP_KERNEL);
> +
> +		if (!nandc->reg_read_buf)
> +			return -ENOMEM;
> +
> +		nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
> +		if (!nandc->tx_chan) {
> +			dev_err(nandc->dev, "failed to request tx channel\n");
> +			return -ENODEV;
> +		}
> +
> +		nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
> +		if (!nandc->rx_chan) {
> +			dev_err(nandc->dev, "failed to request rx channel\n");
> +			return -ENODEV;
> +		}
> +
> +		nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
> +		if (!nandc->cmd_chan) {
> +			dev_err(nandc->dev, "failed to request cmd channel\n");
> +			return -ENODEV;
> +		}
>  	}
>  
>  	INIT_LIST_HEAD(&nandc->desc_list);
> @@ -1978,7 +2022,19 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>  
>  static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
>  {
> -	dma_release_channel(nandc->chan);
> +	if (nandc->dma_bam_enabled) {
> +		if (nandc->tx_chan)
> +			dma_release_channel(nandc->tx_chan);
> +
> +		if (nandc->rx_chan)
> +			dma_release_channel(nandc->rx_chan);
> +
> +		if (nandc->cmd_chan)
> +			dma_release_channel(nandc->cmd_chan);
> +	} else {
> +		if (nandc->chan)
> +			dma_release_channel(nandc->chan);
> +	}
>  }
>  
>  /* one time setup of a few nand controller registers */
> @@ -2063,16 +2119,20 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
>  	struct device_node *np = nandc->dev->of_node;
>  	int ret;
>  
> -	ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
> -	if (ret) {
> -		dev_err(nandc->dev, "command CRCI unspecified\n");
> -		return ret;
> -	}
> +	if (!nandc->dma_bam_enabled) {

 instead, can we simply do if (is_bam) return; here ?

Regards,
 Sricharan

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Re: [PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources

[Sricharan R]

Hi Abhishek,


On 6/29/2017 12:45 PM, Abhishek Sahu wrote:
> 1. The QPIC NAND uses 3 BAM channels: command, data tx and
>    data rx while EBI2 NAND uses only single ADM channel.
> 
> 2. The EBI2 NAND uses normal register read buffer since this
>    buffer will be remapped with dma_map_sg. The QPIC NAND will give
>    register read buffer in command descriptor and the command
>    descriptor will be mapped with dma_map_sg so the register buffer
>    should be DMA coherent.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>  .../devicetree/bindings/mtd/qcom_nandc.txt         |  25 +++--
>  drivers/mtd/nand/qcom_nandc.c                      | 106 ++++++++++++++++-----
>  2 files changed, 99 insertions(+), 32 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 5d0f7ae..87b9a56 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -9,15 +9,17 @@ Required properties:
>  - clock-names:		must contain "core" for the core clock and "aon" for the
>  			always on clock
>  - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
> -			controller node and the channel number to be used for
> -			NAND. Refer to dma.txt and qcom_adm.txt for more details
> -- dma-names:		must be "rxtx"
> -- qcom,cmd-crci:	must contain the ADM command type CRCI block instance
> -			number specified for the NAND controller on the given
> -			platform
> -- qcom,data-crci:	must contain the ADM data type CRCI block instance
> -			number specified for the NAND controller on the given
> -			platform
> +			or BAM DMA controller node and the channel number to
> +			be used for NAND. Refer to dma.txt, qcom_adm.txt(ADM)
> +			and qcom/bam_dma.txt(BAM) for more details
> +- dma-names:		"rxtx" - ADM
> +			"tx", "rx", "cmd" - BAM
> +- qcom,cmd-crci:	Only required for ADM DMA. must contain the ADM command
> +			type CRCI block instance number specified for the NAND
> +			controller on the given platform.
> +- qcom,data-crci:	Only required for ADM DMA. must contain the ADM data
> +			type CRCI block instance number specified for the NAND
> +			controller on the given platform.

  May be better to put the parameter list that are specific to ADMA and BAM under
  seperate groups and those common for both in one group, instead of mentioning
  at each of the property level.

>  - #address-cells:	<1> - subnodes give the chip-select number
>  - #size-cells:		<0>
>  
> @@ -95,6 +97,11 @@ nand@79b0000 {
>  		<&gcc GCC_QPIC_AHB_CLK>;
>  	clock-names = "core", "aon";
>  
> +	dmas = <&qpicbam 0>,
> +		<&qpicbam 1>,
> +		<&qpicbam 2>;
> +	dma-names = "tx", "rx", "cmd";
> +
>  	#address-cells = <1>;
>  	#size-cells = <0>;
>  
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index f55f728..520add9 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -226,6 +226,7 @@ struct nandc_regs {
>   *				by upper layers directly
>   * @buf_size/count/start:	markers for chip->read_buf/write_buf functions
>   * @reg_read_buf:		local buffer for reading back registers via DMA
> + * @reg_read_buf_phys:		contains dma address for register read buffer
>   * @reg_read_pos:		marker for data read in reg_read_buf
>   *
>   * @regs:			a contiguous chunk of memory for DMA register
> @@ -249,9 +250,19 @@ struct qcom_nand_controller {
>  	struct clk *core_clk;
>  	struct clk *aon_clk;
>  
> -	struct dma_chan *chan;
> -	unsigned int cmd_crci;
> -	unsigned int data_crci;
> +	union {
> +		struct {
> +			struct dma_chan *tx_chan;
> +			struct dma_chan *rx_chan;
> +			struct dma_chan *cmd_chan;
> +		};
> +		struct {
> +			struct dma_chan *chan;
> +			unsigned int cmd_crci;
> +			unsigned int data_crci;
> +		};
> +	};
> +
>  	struct list_head desc_list;
>  
>  	u8		*data_buffer;
> @@ -261,6 +272,7 @@ struct qcom_nand_controller {
>  	int		buf_start;
>  
>  	__le32 *reg_read_buf;
> +	dma_addr_t reg_read_buf_phys;
>  	int reg_read_pos;
>  
>  	struct nandc_regs *regs;
> @@ -1956,16 +1968,48 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>  	if (!nandc->regs)
>  		return -ENOMEM;
>  
> -	nandc->reg_read_buf = devm_kzalloc(nandc->dev,
> -				MAX_REG_RD * sizeof(*nandc->reg_read_buf),
> -				GFP_KERNEL);
> -	if (!nandc->reg_read_buf)
> -		return -ENOMEM;
>  
> -	nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> -	if (!nandc->chan) {
> -		dev_err(nandc->dev, "failed to request slave channel\n");
> -		return -ENODEV;
> +	if (!nandc->dma_bam_enabled) {

 Better to swap if, else part to avoid !

> +		nandc->reg_read_buf =
> +			devm_kzalloc(nandc->dev, MAX_REG_RD *
> +				     sizeof(*nandc->reg_read_buf), GFP_KERNEL);
> +
> +		if (!nandc->reg_read_buf)
> +			return -ENOMEM;
> +
> +		nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> +		if (!nandc->chan) {
> +			dev_err(nandc->dev,
> +				"failed to request slave channel\n");
> +			return -ENODEV;
> +		}
> +	} else {
> +		nandc->reg_read_buf =
> +			dmam_alloc_coherent(nandc->dev, MAX_REG_RD *
> +					    sizeof(*nandc->reg_read_buf),
> +					    &nandc->reg_read_buf_phys,
> +					    GFP_KERNEL);
> +
> +		if (!nandc->reg_read_buf)
> +			return -ENOMEM;
> +
> +		nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
> +		if (!nandc->tx_chan) {
> +			dev_err(nandc->dev, "failed to request tx channel\n");
> +			return -ENODEV;
> +		}
> +
> +		nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
> +		if (!nandc->rx_chan) {
> +			dev_err(nandc->dev, "failed to request rx channel\n");
> +			return -ENODEV;
> +		}
> +
> +		nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
> +		if (!nandc->cmd_chan) {
> +			dev_err(nandc->dev, "failed to request cmd channel\n");
> +			return -ENODEV;
> +		}
>  	}
>  
>  	INIT_LIST_HEAD(&nandc->desc_list);
> @@ -1978,7 +2022,19 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>  
>  static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
>  {
> -	dma_release_channel(nandc->chan);
> +	if (nandc->dma_bam_enabled) {
> +		if (nandc->tx_chan)
> +			dma_release_channel(nandc->tx_chan);
> +
> +		if (nandc->rx_chan)
> +			dma_release_channel(nandc->rx_chan);
> +
> +		if (nandc->cmd_chan)
> +			dma_release_channel(nandc->cmd_chan);
> +	} else {
> +		if (nandc->chan)
> +			dma_release_channel(nandc->chan);
> +	}
>  }
>  
>  /* one time setup of a few nand controller registers */
> @@ -2063,16 +2119,20 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
>  	struct device_node *np = nandc->dev->of_node;
>  	int ret;
>  
> -	ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
> -	if (ret) {
> -		dev_err(nandc->dev, "command CRCI unspecified\n");
> -		return ret;
> -	}
> +	if (!nandc->dma_bam_enabled) {

 instead, can we simply do if (is_bam) return; here ?

Regards,
 Sricharan

-- 
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Re: [PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources

[Sricharan R]

Hi Abhishek,

On 6/29/2017 12:45 PM, Abhishek Sahu wrote:
> 1. The QPIC NAND uses 3 BAM channels: command, data tx and
>    data rx while EBI2 NAND uses only single ADM channel.
> 
> 2. The EBI2 NAND uses normal register read buffer since this
>    buffer will be remapped with dma_map_sg. The QPIC NAND will give
>    register read buffer in command descriptor and the command
>    descriptor will be mapped with dma_map_sg so the register buffer
>    should be DMA coherent.
> 
> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>  .../devicetree/bindings/mtd/qcom_nandc.txt         |  25 +++--
>  drivers/mtd/nand/qcom_nandc.c                      | 106 ++++++++++++++++-----
>  2 files changed, 99 insertions(+), 32 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 5d0f7ae..87b9a56 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -9,15 +9,17 @@ Required properties:
>  - clock-names:		must contain "core" for the core clock and "aon" for the
>  			always on clock
>  - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
> -			controller node and the channel number to be used for
> -			NAND. Refer to dma.txt and qcom_adm.txt for more details
> -- dma-names:		must be "rxtx"
> -- qcom,cmd-crci:	must contain the ADM command type CRCI block instance
> -			number specified for the NAND controller on the given
> -			platform
> -- qcom,data-crci:	must contain the ADM data type CRCI block instance
> -			number specified for the NAND controller on the given
> -			platform
> +			or BAM DMA controller node and the channel number to
> +			be used for NAND. Refer to dma.txt, qcom_adm.txt(ADM)
> +			and qcom/bam_dma.txt(BAM) for more details
> +- dma-names:		"rxtx" - ADM
> +			"tx", "rx", "cmd" - BAM
> +- qcom,cmd-crci:	Only required for ADM DMA. must contain the ADM command
> +			type CRCI block instance number specified for the NAND
> +			controller on the given platform.
> +- qcom,data-crci:	Only required for ADM DMA. must contain the ADM data
> +			type CRCI block instance number specified for the NAND
> +			controller on the given platform.
>  - #address-cells:	<1> - subnodes give the chip-select number
>  - #size-cells:		<0>
>  
> @@ -95,6 +97,11 @@ nand@79b0000 {
>  		<&gcc GCC_QPIC_AHB_CLK>;
>  	clock-names = "core", "aon";
>  
> +	dmas = <&qpicbam 0>,
> +		<&qpicbam 1>,
> +		<&qpicbam 2>;
> +	dma-names = "tx", "rx", "cmd";
> +
>  	#address-cells = <1>;
>  	#size-cells = <0>;
>  
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index f55f728..520add9 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -226,6 +226,7 @@ struct nandc_regs {
>   *				by upper layers directly
>   * @buf_size/count/start:	markers for chip->read_buf/write_buf functions
>   * @reg_read_buf:		local buffer for reading back registers via DMA
> + * @reg_read_buf_phys:		contains dma address for register read buffer
>   * @reg_read_pos:		marker for data read in reg_read_buf
>   *
>   * @regs:			a contiguous chunk of memory for DMA register
> @@ -249,9 +250,19 @@ struct qcom_nand_controller {
>  	struct clk *core_clk;
>  	struct clk *aon_clk;
>  
> -	struct dma_chan *chan;
> -	unsigned int cmd_crci;
> -	unsigned int data_crci;
> +	union {
> +		struct {
> +			struct dma_chan *tx_chan;
> +			struct dma_chan *rx_chan;
> +			struct dma_chan *cmd_chan;
> +		};
> +		struct {
> +			struct dma_chan *chan;
> +			unsigned int cmd_crci;
> +			unsigned int data_crci;
> +		};
> +	};
> +
>  	struct list_head desc_list;
>  
>  	u8		*data_buffer;
> @@ -261,6 +272,7 @@ struct qcom_nand_controller {
>  	int		buf_start;
>  
>  	__le32 *reg_read_buf;
> +	dma_addr_t reg_read_buf_phys;
>  	int reg_read_pos;
>  
>  	struct nandc_regs *regs;
> @@ -1956,16 +1968,48 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>  	if (!nandc->regs)
>  		return -ENOMEM;
>  
> -	nandc->reg_read_buf = devm_kzalloc(nandc->dev,
> -				MAX_REG_RD * sizeof(*nandc->reg_read_buf),
> -				GFP_KERNEL);
> -	if (!nandc->reg_read_buf)
> -		return -ENOMEM;
>  
> -	nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> -	if (!nandc->chan) {
> -		dev_err(nandc->dev, "failed to request slave channel\n");
> -		return -ENODEV;
> +	if (!nandc->dma_bam_enabled) {
> +		nandc->reg_read_buf =
> +			devm_kzalloc(nandc->dev, MAX_REG_RD *
> +				     sizeof(*nandc->reg_read_buf), GFP_KERNEL);
> +
> +		if (!nandc->reg_read_buf)
> +			return -ENOMEM;
> +
> +		nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> +		if (!nandc->chan) {
> +			dev_err(nandc->dev,
> +				"failed to request slave channel\n");
> +			return -ENODEV;
> +		}
> +	} else {
> +		nandc->reg_read_buf =
> +			dmam_alloc_coherent(nandc->dev, MAX_REG_RD *
> +					    sizeof(*nandc->reg_read_buf),
> +					    &nandc->reg_read_buf_phys,
> +					    GFP_KERNEL);
> +

 I think as Archit has commented, do not see a reason for this to be
 alloc_coherent change here.

Regards,
 Sricharan

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Re: [PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources

[Sricharan R]

Hi Abhishek,

On 6/29/2017 12:45 PM, Abhishek Sahu wrote:
> 1. The QPIC NAND uses 3 BAM channels: command, data tx and
>    data rx while EBI2 NAND uses only single ADM channel.
> 
> 2. The EBI2 NAND uses normal register read buffer since this
>    buffer will be remapped with dma_map_sg. The QPIC NAND will give
>    register read buffer in command descriptor and the command
>    descriptor will be mapped with dma_map_sg so the register buffer
>    should be DMA coherent.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>  .../devicetree/bindings/mtd/qcom_nandc.txt         |  25 +++--
>  drivers/mtd/nand/qcom_nandc.c                      | 106 ++++++++++++++++-----
>  2 files changed, 99 insertions(+), 32 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 5d0f7ae..87b9a56 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -9,15 +9,17 @@ Required properties:
>  - clock-names:		must contain "core" for the core clock and "aon" for the
>  			always on clock
>  - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
> -			controller node and the channel number to be used for
> -			NAND. Refer to dma.txt and qcom_adm.txt for more details
> -- dma-names:		must be "rxtx"
> -- qcom,cmd-crci:	must contain the ADM command type CRCI block instance
> -			number specified for the NAND controller on the given
> -			platform
> -- qcom,data-crci:	must contain the ADM data type CRCI block instance
> -			number specified for the NAND controller on the given
> -			platform
> +			or BAM DMA controller node and the channel number to
> +			be used for NAND. Refer to dma.txt, qcom_adm.txt(ADM)
> +			and qcom/bam_dma.txt(BAM) for more details
> +- dma-names:		"rxtx" - ADM
> +			"tx", "rx", "cmd" - BAM
> +- qcom,cmd-crci:	Only required for ADM DMA. must contain the ADM command
> +			type CRCI block instance number specified for the NAND
> +			controller on the given platform.
> +- qcom,data-crci:	Only required for ADM DMA. must contain the ADM data
> +			type CRCI block instance number specified for the NAND
> +			controller on the given platform.
>  - #address-cells:	<1> - subnodes give the chip-select number
>  - #size-cells:		<0>
>  
> @@ -95,6 +97,11 @@ nand@79b0000 {
>  		<&gcc GCC_QPIC_AHB_CLK>;
>  	clock-names = "core", "aon";
>  
> +	dmas = <&qpicbam 0>,
> +		<&qpicbam 1>,
> +		<&qpicbam 2>;
> +	dma-names = "tx", "rx", "cmd";
> +
>  	#address-cells = <1>;
>  	#size-cells = <0>;
>  
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index f55f728..520add9 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -226,6 +226,7 @@ struct nandc_regs {
>   *				by upper layers directly
>   * @buf_size/count/start:	markers for chip->read_buf/write_buf functions
>   * @reg_read_buf:		local buffer for reading back registers via DMA
> + * @reg_read_buf_phys:		contains dma address for register read buffer
>   * @reg_read_pos:		marker for data read in reg_read_buf
>   *
>   * @regs:			a contiguous chunk of memory for DMA register
> @@ -249,9 +250,19 @@ struct qcom_nand_controller {
>  	struct clk *core_clk;
>  	struct clk *aon_clk;
>  
> -	struct dma_chan *chan;
> -	unsigned int cmd_crci;
> -	unsigned int data_crci;
> +	union {
> +		struct {
> +			struct dma_chan *tx_chan;
> +			struct dma_chan *rx_chan;
> +			struct dma_chan *cmd_chan;
> +		};
> +		struct {
> +			struct dma_chan *chan;
> +			unsigned int cmd_crci;
> +			unsigned int data_crci;
> +		};
> +	};
> +
>  	struct list_head desc_list;
>  
>  	u8		*data_buffer;
> @@ -261,6 +272,7 @@ struct qcom_nand_controller {
>  	int		buf_start;
>  
>  	__le32 *reg_read_buf;
> +	dma_addr_t reg_read_buf_phys;
>  	int reg_read_pos;
>  
>  	struct nandc_regs *regs;
> @@ -1956,16 +1968,48 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>  	if (!nandc->regs)
>  		return -ENOMEM;
>  
> -	nandc->reg_read_buf = devm_kzalloc(nandc->dev,
> -				MAX_REG_RD * sizeof(*nandc->reg_read_buf),
> -				GFP_KERNEL);
> -	if (!nandc->reg_read_buf)
> -		return -ENOMEM;
>  
> -	nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> -	if (!nandc->chan) {
> -		dev_err(nandc->dev, "failed to request slave channel\n");
> -		return -ENODEV;
> +	if (!nandc->dma_bam_enabled) {
> +		nandc->reg_read_buf =
> +			devm_kzalloc(nandc->dev, MAX_REG_RD *
> +				     sizeof(*nandc->reg_read_buf), GFP_KERNEL);
> +
> +		if (!nandc->reg_read_buf)
> +			return -ENOMEM;
> +
> +		nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
> +		if (!nandc->chan) {
> +			dev_err(nandc->dev,
> +				"failed to request slave channel\n");
> +			return -ENODEV;
> +		}
> +	} else {
> +		nandc->reg_read_buf =
> +			dmam_alloc_coherent(nandc->dev, MAX_REG_RD *
> +					    sizeof(*nandc->reg_read_buf),
> +					    &nandc->reg_read_buf_phys,
> +					    GFP_KERNEL);
> +

 I think as Archit has commented, do not see a reason for this to be
 alloc_coherent change here.

Regards,
 Sricharan

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[PATCH 06/14] qcom: mtd: nand: add bam dma descriptor handling

[Abhishek Sahu]

1. prepare_bam_async_desc is the function which will call
   all the DMA API’s. It will fetch the outstanding scatter gather
   list for passed channel and will do the DMA descriptor formation.
   The DMA flag is dependent upon the type of channel.

2. For ADM DMA, the descriptor is being formed for every DMA
   request so its sgl count will be always 1 while in BAM DMA, the
   clubbing of descriptor is being done to increase throughput.

3. ADM uses only one channel while in BAM, data descriptors
   will be submitted to tx channel (for write) or rx channel
   (for read) and all the registers read/write descriptors in
   command channel.

Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 drivers/mtd/nand/qcom_nandc.c | 119 ++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 114 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index f8d0bde..7042a65 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -206,14 +206,22 @@ struct bam_transaction {
  * This data type corresponds to the nand dma descriptor
  * @list - list for desc_info
  * @dir - DMA transfer direction
- * @sgl - sgl which will be used for single sgl dma descriptor
+ * @sgl - sgl which will be used for single sgl dma descriptor. Only used by ADM
+ * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
+ * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
  * @dma_desc - low level dma engine descriptor
  */
 struct desc_info {
 	struct list_head node;
 
 	enum dma_data_direction dir;
-	struct scatterlist sgl;
+	union {
+			struct scatterlist sgl;
+			struct {
+				struct scatterlist *bam_sgl;
+				int sgl_cnt;
+			};
+	};
 	struct dma_async_tx_descriptor *dma_desc;
 };
 
@@ -564,6 +572,68 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
 	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
 }
 
+/*
+ * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
+ * for BAM. This descriptor will be added in the NAND DMA descriptor queue
+ * which will be submitted to DMA engine.
+ */
+static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
+				  struct dma_chan *chan,
+				  unsigned long flags)
+{
+	struct desc_info *desc;
+	struct scatterlist *sgl;
+	unsigned int sgl_cnt;
+	struct bam_transaction *bam_txn = nandc->bam_txn;
+	enum dma_transfer_direction dir_eng;
+	struct dma_async_tx_descriptor *dma_desc;
+
+	desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+	if (!desc)
+		return -ENOMEM;
+
+	if (chan == nandc->cmd_chan) {
+		sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
+		sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
+		bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
+		dir_eng = DMA_MEM_TO_DEV;
+		desc->dir = DMA_TO_DEVICE;
+	} else if (chan == nandc->tx_chan) {
+		sgl = &bam_txn->data_sg[bam_txn->tx_sgl_start];
+		sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
+		bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
+		dir_eng = DMA_MEM_TO_DEV;
+		desc->dir = DMA_TO_DEVICE;
+	} else {
+		sgl = &bam_txn->data_sg[bam_txn->rx_sgl_start];
+		sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
+		bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
+		desc->dir = DMA_FROM_DEVICE;
+		dir_eng = DMA_DEV_TO_MEM;
+	}
+
+	sg_mark_end(sgl + sgl_cnt - 1);
+	dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
+
+	desc->sgl_cnt = sgl_cnt;
+	desc->bam_sgl = sgl;
+
+	dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
+					   flags);
+
+	if (!dma_desc) {
+		dev_err(nandc->dev, "failure in prep desc\n");
+		kfree(desc);
+		return -EINVAL;
+	}
+
+	desc->dma_desc = dma_desc;
+
+	list_add_tail(&desc->node, &nandc->desc_list);
+
+	return 0;
+}
+
 static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
 			 int reg_off, const void *vaddr, int size,
 			 bool flow_control)
@@ -891,12 +961,44 @@ static int submit_descs(struct qcom_nand_controller *nandc)
 {
 	struct desc_info *desc;
 	dma_cookie_t cookie = 0;
+	struct bam_transaction *bam_txn = nandc->bam_txn;
+	int r;
+
+	if (nandc->dma_bam_enabled) {
+		if (bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start) {
+			r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
+			if (r)
+				return r;
+		}
+
+		if (bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start) {
+			r = prepare_bam_async_desc(nandc, nandc->tx_chan,
+						   DMA_PREP_INTERRUPT);
+			if (r)
+				return r;
+		}
+
+		if (bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start) {
+			r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
+						   DMA_PREP_CMD);
+			if (r)
+				return r;
+		}
+	}
 
 	list_for_each_entry(desc, &nandc->desc_list, node)
 		cookie = dmaengine_submit(desc->dma_desc);
 
-	if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
-		return -ETIMEDOUT;
+	if (nandc->dma_bam_enabled) {
+		dma_async_issue_pending(nandc->tx_chan);
+		dma_async_issue_pending(nandc->rx_chan);
+
+		if (dma_sync_wait(nandc->cmd_chan, cookie) != DMA_COMPLETE)
+			return -ETIMEDOUT;
+	} else {
+		if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
+			return -ETIMEDOUT;
+	}
 
 	return 0;
 }
@@ -907,7 +1009,14 @@ static void free_descs(struct qcom_nand_controller *nandc)
 
 	list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
 		list_del(&desc->node);
-		dma_unmap_sg(nandc->dev, &desc->sgl, 1, desc->dir);
+
+		if (nandc->dma_bam_enabled)
+			dma_unmap_sg(nandc->dev, desc->bam_sgl,
+				     desc->sgl_cnt, desc->dir);
+		else
+			dma_unmap_sg(nandc->dev, &desc->sgl, 1,
+				     desc->dir);
+
 		kfree(desc);
 	}
 }
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[PATCH 06/14] qcom: mtd: nand: add bam dma descriptor handling

[Abhishek Sahu]

1. prepare_bam_async_desc is the function which will call
   all the DMA API’s. It will fetch the outstanding scatter gather
   list for passed channel and will do the DMA descriptor formation.
   The DMA flag is dependent upon the type of channel.

2. For ADM DMA, the descriptor is being formed for every DMA
   request so its sgl count will be always 1 while in BAM DMA, the
   clubbing of descriptor is being done to increase throughput.

3. ADM uses only one channel while in BAM, data descriptors
   will be submitted to tx channel (for write) or rx channel
   (for read) and all the registers read/write descriptors in
   command channel.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/mtd/nand/qcom_nandc.c | 119 ++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 114 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index f8d0bde..7042a65 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -206,14 +206,22 @@ struct bam_transaction {
  * This data type corresponds to the nand dma descriptor
  * @list - list for desc_info
  * @dir - DMA transfer direction
- * @sgl - sgl which will be used for single sgl dma descriptor
+ * @sgl - sgl which will be used for single sgl dma descriptor. Only used by ADM
+ * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
+ * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
  * @dma_desc - low level dma engine descriptor
  */
 struct desc_info {
 	struct list_head node;
 
 	enum dma_data_direction dir;
-	struct scatterlist sgl;
+	union {
+			struct scatterlist sgl;
+			struct {
+				struct scatterlist *bam_sgl;
+				int sgl_cnt;
+			};
+	};
 	struct dma_async_tx_descriptor *dma_desc;
 };
 
@@ -564,6 +572,68 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
 	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
 }
 
+/*
+ * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
+ * for BAM. This descriptor will be added in the NAND DMA descriptor queue
+ * which will be submitted to DMA engine.
+ */
+static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
+				  struct dma_chan *chan,
+				  unsigned long flags)
+{
+	struct desc_info *desc;
+	struct scatterlist *sgl;
+	unsigned int sgl_cnt;
+	struct bam_transaction *bam_txn = nandc->bam_txn;
+	enum dma_transfer_direction dir_eng;
+	struct dma_async_tx_descriptor *dma_desc;
+
+	desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+	if (!desc)
+		return -ENOMEM;
+
+	if (chan == nandc->cmd_chan) {
+		sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
+		sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
+		bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
+		dir_eng = DMA_MEM_TO_DEV;
+		desc->dir = DMA_TO_DEVICE;
+	} else if (chan == nandc->tx_chan) {
+		sgl = &bam_txn->data_sg[bam_txn->tx_sgl_start];
+		sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
+		bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
+		dir_eng = DMA_MEM_TO_DEV;
+		desc->dir = DMA_TO_DEVICE;
+	} else {
+		sgl = &bam_txn->data_sg[bam_txn->rx_sgl_start];
+		sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
+		bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
+		desc->dir = DMA_FROM_DEVICE;
+		dir_eng = DMA_DEV_TO_MEM;
+	}
+
+	sg_mark_end(sgl + sgl_cnt - 1);
+	dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
+
+	desc->sgl_cnt = sgl_cnt;
+	desc->bam_sgl = sgl;
+
+	dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
+					   flags);
+
+	if (!dma_desc) {
+		dev_err(nandc->dev, "failure in prep desc\n");
+		kfree(desc);
+		return -EINVAL;
+	}
+
+	desc->dma_desc = dma_desc;
+
+	list_add_tail(&desc->node, &nandc->desc_list);
+
+	return 0;
+}
+
 static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
 			 int reg_off, const void *vaddr, int size,
 			 bool flow_control)
@@ -891,12 +961,44 @@ static int submit_descs(struct qcom_nand_controller *nandc)
 {
 	struct desc_info *desc;
 	dma_cookie_t cookie = 0;
+	struct bam_transaction *bam_txn = nandc->bam_txn;
+	int r;
+
+	if (nandc->dma_bam_enabled) {
+		if (bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start) {
+			r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
+			if (r)
+				return r;
+		}
+
+		if (bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start) {
+			r = prepare_bam_async_desc(nandc, nandc->tx_chan,
+						   DMA_PREP_INTERRUPT);
+			if (r)
+				return r;
+		}
+
+		if (bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start) {
+			r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
+						   DMA_PREP_CMD);
+			if (r)
+				return r;
+		}
+	}
 
 	list_for_each_entry(desc, &nandc->desc_list, node)
 		cookie = dmaengine_submit(desc->dma_desc);
 
-	if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
-		return -ETIMEDOUT;
+	if (nandc->dma_bam_enabled) {
+		dma_async_issue_pending(nandc->tx_chan);
+		dma_async_issue_pending(nandc->rx_chan);
+
+		if (dma_sync_wait(nandc->cmd_chan, cookie) != DMA_COMPLETE)
+			return -ETIMEDOUT;
+	} else {
+		if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
+			return -ETIMEDOUT;
+	}
 
 	return 0;
 }
@@ -907,7 +1009,14 @@ static void free_descs(struct qcom_nand_controller *nandc)
 
 	list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
 		list_del(&desc->node);
-		dma_unmap_sg(nandc->dev, &desc->sgl, 1, desc->dir);
+
+		if (nandc->dma_bam_enabled)
+			dma_unmap_sg(nandc->dev, desc->bam_sgl,
+				     desc->sgl_cnt, desc->dir);
+		else
+			dma_unmap_sg(nandc->dev, &desc->sgl, 1,
+				     desc->dir);
+
 		kfree(desc);
 	}
 }
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 06/14] qcom: mtd: nand: add bam dma descriptor handling

[Archit Taneja]

On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
> 1. prepare_bam_async_desc is the function which will call
>     all the DMA API’s. It will fetch the outstanding scatter gather
>     list for passed channel and will do the DMA descriptor formation.
>     The DMA flag is dependent upon the type of channel.
> 
> 2. For ADM DMA, the descriptor is being formed for every DMA
>     request so its sgl count will be always 1 while in BAM DMA, the
>     clubbing of descriptor is being done to increase throughput.
> 
> 3. ADM uses only one channel while in BAM, data descriptors
>     will be submitted to tx channel (for write) or rx channel
>     (for read) and all the registers read/write descriptors in
>     command channel.
> 
> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>   drivers/mtd/nand/qcom_nandc.c | 119 ++++++++++++++++++++++++++++++++++++++++--
>   1 file changed, 114 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index f8d0bde..7042a65 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -206,14 +206,22 @@ struct bam_transaction {
>    * This data type corresponds to the nand dma descriptor
>    * @list - list for desc_info
>    * @dir - DMA transfer direction
> - * @sgl - sgl which will be used for single sgl dma descriptor
> + * @sgl - sgl which will be used for single sgl dma descriptor. Only used by ADM
> + * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
> + * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
>    * @dma_desc - low level dma engine descriptor
>    */
>   struct desc_info {
>   	struct list_head node;
>   
>   	enum dma_data_direction dir;
> -	struct scatterlist sgl;
> +	union {
> +			struct scatterlist sgl;

Can you make this adm_sgl instead for consistency? Also, please use only
two tabs instead of one here for indentation.

> +			struct {
> +				struct scatterlist *bam_sgl;
> +				int sgl_cnt;
> +			};
> +	};
>   	struct dma_async_tx_descriptor *dma_desc;
>   };
>   
> @@ -564,6 +572,68 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>   }
>   
> +/*
> + * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
> + * for BAM. This descriptor will be added in the NAND DMA descriptor queue
> + * which will be submitted to DMA engine.
> + */
> +static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
> +				  struct dma_chan *chan,
> +				  unsigned long flags)

 From what I gathered in patch #10, this would be called by
prep_dma_desc_data_bam() and prep_dma_desc_command(). Can you rename these
two to something like prep_bam_dma_desc_data() and prep_bam_dma_desc_cmd()


> +{
> +	struct desc_info *desc;
> +	struct scatterlist *sgl;
> +	unsigned int sgl_cnt;
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +	enum dma_transfer_direction dir_eng;
> +	struct dma_async_tx_descriptor *dma_desc;
> +
> +	desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> +	if (!desc)
> +		return -ENOMEM;
> +
> +	if (chan == nandc->cmd_chan) {
> +		sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
> +		sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
> +		bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
> +		dir_eng = DMA_MEM_TO_DEV;
> +		desc->dir = DMA_TO_DEVICE;
> +	} else if (chan == nandc->tx_chan) {
> +		sgl = &bam_txn->data_sg[bam_txn->tx_sgl_start];
> +		sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
> +		bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
> +		dir_eng = DMA_MEM_TO_DEV;
> +		desc->dir = DMA_TO_DEVICE;
> +	} else {
> +		sgl = &bam_txn->data_sg[bam_txn->rx_sgl_start];
> +		sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
> +		bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
> +		desc->dir = DMA_FROM_DEVICE;
> +		dir_eng = DMA_DEV_TO_MEM;
> +	}
> +
> +	sg_mark_end(sgl + sgl_cnt - 1);
> +	dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);

Is it safe to assume here that dma_map_sg won't return an error?

> +
> +	desc->sgl_cnt = sgl_cnt;
> +	desc->bam_sgl = sgl;
> +
> +	dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
> +					   flags);
> +
> +	if (!dma_desc) {
> +		dev_err(nandc->dev, "failure in prep desc\n");
> +		kfree(desc);
> +		return -EINVAL;
> +	}
> +
> +	desc->dma_desc = dma_desc;
> +
> +	list_add_tail(&desc->node, &nandc->desc_list);
> +
> +	return 0;
> +}
> +


>   static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
>   			 int reg_off, const void *vaddr, int size,
>   			 bool flow_control)

Could you rename this to prep_adm_dma_desc for consistency?

> @@ -891,12 +961,44 @@ static int submit_descs(struct qcom_nand_controller *nandc)
>   {
>   	struct desc_info *desc;
>   	dma_cookie_t cookie = 0;
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +	int r;
> +
> +	if (nandc->dma_bam_enabled) {
> +		if (bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start) {

Using '>' instead of '-' here should be more legible.

> +			r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
> +			if (r)
> +				return r;
> +		}
> +
> +		if (bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start) {
> +			r = prepare_bam_async_desc(nandc, nandc->tx_chan,
> +						   DMA_PREP_INTERRUPT);
> +			if (r)
> +				return r;
> +		}
> +
> +		if (bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start) {
> +			r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
> +						   DMA_PREP_CMD);
> +			if (r)
> +				return r;
> +		}
> +	}
>   
>   	list_for_each_entry(desc, &nandc->desc_list, node)
>   		cookie = dmaengine_submit(desc->dma_desc);
>   
> -	if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
> -		return -ETIMEDOUT;
> +	if (nandc->dma_bam_enabled) {
> +		dma_async_issue_pending(nandc->tx_chan);
> +		dma_async_issue_pending(nandc->rx_chan);
> +
> +		if (dma_sync_wait(nandc->cmd_chan, cookie) != DMA_COMPLETE)
> +			return -ETIMEDOUT;
> +	} else {
> +		if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
> +			return -ETIMEDOUT;
> +	}
>   
>   	return 0;
>   }
> @@ -907,7 +1009,14 @@ static void free_descs(struct qcom_nand_controller *nandc)
>   
>   	list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
>   		list_del(&desc->node);
> -		dma_unmap_sg(nandc->dev, &desc->sgl, 1, desc->dir);
> +
> +		if (nandc->dma_bam_enabled)
> +			dma_unmap_sg(nandc->dev, desc->bam_sgl,
> +				     desc->sgl_cnt, desc->dir);
> +		else
> +			dma_unmap_sg(nandc->dev, &desc->sgl, 1,
> +				     desc->dir);
> +
>   		kfree(desc);
>   	}
>   }
> 

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Re: [PATCH 06/14] qcom: mtd: nand: add bam dma descriptor handling

[Archit Taneja]

On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
> 1. prepare_bam_async_desc is the function which will call
>     all the DMA API’s. It will fetch the outstanding scatter gather
>     list for passed channel and will do the DMA descriptor formation.
>     The DMA flag is dependent upon the type of channel.
> 
> 2. For ADM DMA, the descriptor is being formed for every DMA
>     request so its sgl count will be always 1 while in BAM DMA, the
>     clubbing of descriptor is being done to increase throughput.
> 
> 3. ADM uses only one channel while in BAM, data descriptors
>     will be submitted to tx channel (for write) or rx channel
>     (for read) and all the registers read/write descriptors in
>     command channel.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>   drivers/mtd/nand/qcom_nandc.c | 119 ++++++++++++++++++++++++++++++++++++++++--
>   1 file changed, 114 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index f8d0bde..7042a65 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -206,14 +206,22 @@ struct bam_transaction {
>    * This data type corresponds to the nand dma descriptor
>    * @list - list for desc_info
>    * @dir - DMA transfer direction
> - * @sgl - sgl which will be used for single sgl dma descriptor
> + * @sgl - sgl which will be used for single sgl dma descriptor. Only used by ADM
> + * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
> + * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
>    * @dma_desc - low level dma engine descriptor
>    */
>   struct desc_info {
>   	struct list_head node;
>   
>   	enum dma_data_direction dir;
> -	struct scatterlist sgl;
> +	union {
> +			struct scatterlist sgl;

Can you make this adm_sgl instead for consistency? Also, please use only
two tabs instead of one here for indentation.

> +			struct {
> +				struct scatterlist *bam_sgl;
> +				int sgl_cnt;
> +			};
> +	};
>   	struct dma_async_tx_descriptor *dma_desc;
>   };
>   
> @@ -564,6 +572,68 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>   }
>   
> +/*
> + * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
> + * for BAM. This descriptor will be added in the NAND DMA descriptor queue
> + * which will be submitted to DMA engine.
> + */
> +static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
> +				  struct dma_chan *chan,
> +				  unsigned long flags)

 From what I gathered in patch #10, this would be called by
prep_dma_desc_data_bam() and prep_dma_desc_command(). Can you rename these
two to something like prep_bam_dma_desc_data() and prep_bam_dma_desc_cmd()


> +{
> +	struct desc_info *desc;
> +	struct scatterlist *sgl;
> +	unsigned int sgl_cnt;
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +	enum dma_transfer_direction dir_eng;
> +	struct dma_async_tx_descriptor *dma_desc;
> +
> +	desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> +	if (!desc)
> +		return -ENOMEM;
> +
> +	if (chan == nandc->cmd_chan) {
> +		sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
> +		sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
> +		bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
> +		dir_eng = DMA_MEM_TO_DEV;
> +		desc->dir = DMA_TO_DEVICE;
> +	} else if (chan == nandc->tx_chan) {
> +		sgl = &bam_txn->data_sg[bam_txn->tx_sgl_start];
> +		sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
> +		bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
> +		dir_eng = DMA_MEM_TO_DEV;
> +		desc->dir = DMA_TO_DEVICE;
> +	} else {
> +		sgl = &bam_txn->data_sg[bam_txn->rx_sgl_start];
> +		sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
> +		bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
> +		desc->dir = DMA_FROM_DEVICE;
> +		dir_eng = DMA_DEV_TO_MEM;
> +	}
> +
> +	sg_mark_end(sgl + sgl_cnt - 1);
> +	dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);

Is it safe to assume here that dma_map_sg won't return an error?

> +
> +	desc->sgl_cnt = sgl_cnt;
> +	desc->bam_sgl = sgl;
> +
> +	dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
> +					   flags);
> +
> +	if (!dma_desc) {
> +		dev_err(nandc->dev, "failure in prep desc\n");
> +		kfree(desc);
> +		return -EINVAL;
> +	}
> +
> +	desc->dma_desc = dma_desc;
> +
> +	list_add_tail(&desc->node, &nandc->desc_list);
> +
> +	return 0;
> +}
> +


>   static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
>   			 int reg_off, const void *vaddr, int size,
>   			 bool flow_control)

Could you rename this to prep_adm_dma_desc for consistency?

> @@ -891,12 +961,44 @@ static int submit_descs(struct qcom_nand_controller *nandc)
>   {
>   	struct desc_info *desc;
>   	dma_cookie_t cookie = 0;
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +	int r;
> +
> +	if (nandc->dma_bam_enabled) {
> +		if (bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start) {

Using '>' instead of '-' here should be more legible.

> +			r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
> +			if (r)
> +				return r;
> +		}
> +
> +		if (bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start) {
> +			r = prepare_bam_async_desc(nandc, nandc->tx_chan,
> +						   DMA_PREP_INTERRUPT);
> +			if (r)
> +				return r;
> +		}
> +
> +		if (bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start) {
> +			r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
> +						   DMA_PREP_CMD);
> +			if (r)
> +				return r;
> +		}
> +	}
>   
>   	list_for_each_entry(desc, &nandc->desc_list, node)
>   		cookie = dmaengine_submit(desc->dma_desc);
>   
> -	if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
> -		return -ETIMEDOUT;
> +	if (nandc->dma_bam_enabled) {
> +		dma_async_issue_pending(nandc->tx_chan);
> +		dma_async_issue_pending(nandc->rx_chan);
> +
> +		if (dma_sync_wait(nandc->cmd_chan, cookie) != DMA_COMPLETE)
> +			return -ETIMEDOUT;
> +	} else {
> +		if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
> +			return -ETIMEDOUT;
> +	}
>   
>   	return 0;
>   }
> @@ -907,7 +1009,14 @@ static void free_descs(struct qcom_nand_controller *nandc)
>   
>   	list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
>   		list_del(&desc->node);
> -		dma_unmap_sg(nandc->dev, &desc->sgl, 1, desc->dir);
> +
> +		if (nandc->dma_bam_enabled)
> +			dma_unmap_sg(nandc->dev, desc->bam_sgl,
> +				     desc->sgl_cnt, desc->dir);
> +		else
> +			dma_unmap_sg(nandc->dev, &desc->sgl, 1,
> +				     desc->dir);
> +
>   		kfree(desc);
>   	}
>   }
> 

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 06/14] qcom: mtd: nand: add bam dma descriptor handling

[Abhishek Sahu]

On 2017-07-04 11:40, Archit Taneja wrote:
> On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
>> 1. prepare_bam_async_desc is the function which will call
>>     all the DMA API’s. It will fetch the outstanding scatter gather
>>     list for passed channel and will do the DMA descriptor formation.
>>     The DMA flag is dependent upon the type of channel.
>> 
>> 2. For ADM DMA, the descriptor is being formed for every DMA
>>     request so its sgl count will be always 1 while in BAM DMA, the
>>     clubbing of descriptor is being done to increase throughput.
>> 
>> 3. ADM uses only one channel while in BAM, data descriptors
>>     will be submitted to tx channel (for write) or rx channel
>>     (for read) and all the registers read/write descriptors in
>>     command channel.
>> 
>> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>> ---
>>   drivers/mtd/nand/qcom_nandc.c | 119 
>> ++++++++++++++++++++++++++++++++++++++++--
>>   1 file changed, 114 insertions(+), 5 deletions(-)
>> 
>> diff --git a/drivers/mtd/nand/qcom_nandc.c 
>> b/drivers/mtd/nand/qcom_nandc.c
>> index f8d0bde..7042a65 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -206,14 +206,22 @@ struct bam_transaction {
>>    * This data type corresponds to the nand dma descriptor
>>    * @list - list for desc_info
>>    * @dir - DMA transfer direction
>> - * @sgl - sgl which will be used for single sgl dma descriptor
>> + * @sgl - sgl which will be used for single sgl dma descriptor. Only 
>> used by ADM
>> + * @bam_sgl - sgl which will be used for dma descriptor. Only used by 
>> BAM
>> + * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
>>    * @dma_desc - low level dma engine descriptor
>>    */
>>   struct desc_info {
>>   	struct list_head node;
>> 
>>   	enum dma_data_direction dir;
>> -	struct scatterlist sgl;
>> +	union {
>> +			struct scatterlist sgl;
> 
> Can you make this adm_sgl instead for consistency? Also, please use 
> only
> two tabs instead of one here for indentation.

  Sure. I will do the same in v2.

> 
>> +			struct {
>> +				struct scatterlist *bam_sgl;
>> +				int sgl_cnt;
>> +			};
>> +	};
>>   	struct dma_async_tx_descriptor *dma_desc;
>>   };
>> 
>> @@ -564,6 +572,68 @@ static void update_rw_regs(struct qcom_nand_host 
>> *host, int num_cw, bool read)
>>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>>   }
>> 
>> +/*
>> + * Maps the scatter gather list for DMA transfer and forms the DMA 
>> descriptor
>> + * for BAM. This descriptor will be added in the NAND DMA descriptor 
>> queue
>> + * which will be submitted to DMA engine.
>> + */
>> +static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
>> +				  struct dma_chan *chan,
>> +				  unsigned long flags)
> 
> From what I gathered in patch #10, this would be called by
> prep_dma_desc_data_bam() and prep_dma_desc_command(). Can you rename 
> these
> two to something like prep_bam_dma_desc_data() and 
> prep_bam_dma_desc_cmd()
> 

  Sure. I will do the same in v2.

> 
>> +{
>> +	struct desc_info *desc;
>> +	struct scatterlist *sgl;
>> +	unsigned int sgl_cnt;
>> +	struct bam_transaction *bam_txn = nandc->bam_txn;
>> +	enum dma_transfer_direction dir_eng;
>> +	struct dma_async_tx_descriptor *dma_desc;
>> +
>> +	desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>> +	if (!desc)
>> +		return -ENOMEM;
>> +
>> +	if (chan == nandc->cmd_chan) {
>> +		sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
>> +		sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
>> +		bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
>> +		dir_eng = DMA_MEM_TO_DEV;
>> +		desc->dir = DMA_TO_DEVICE;
>> +	} else if (chan == nandc->tx_chan) {
>> +		sgl = &bam_txn->data_sg[bam_txn->tx_sgl_start];
>> +		sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
>> +		bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
>> +		dir_eng = DMA_MEM_TO_DEV;
>> +		desc->dir = DMA_TO_DEVICE;
>> +	} else {
>> +		sgl = &bam_txn->data_sg[bam_txn->rx_sgl_start];
>> +		sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
>> +		bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
>> +		desc->dir = DMA_FROM_DEVICE;
>> +		dir_eng = DMA_DEV_TO_MEM;
>> +	}
>> +
>> +	sg_mark_end(sgl + sgl_cnt - 1);
>> +	dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
> 
> Is it safe to assume here that dma_map_sg won't return an error?
> 

  We need to check for error. I will fix this in v2.

>> +
>> +	desc->sgl_cnt = sgl_cnt;
>> +	desc->bam_sgl = sgl;
>> +
>> +	dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
>> +					   flags);
>> +
>> +	if (!dma_desc) {
>> +		dev_err(nandc->dev, "failure in prep desc\n");
>> +		kfree(desc);
>> +		return -EINVAL;
>> +	}
>> +
>> +	desc->dma_desc = dma_desc;
>> +
>> +	list_add_tail(&desc->node, &nandc->desc_list);
>> +
>> +	return 0;
>> +}
>> +
> 
> 
>>   static int prep_dma_desc(struct qcom_nand_controller *nandc, bool 
>> read,
>>   			 int reg_off, const void *vaddr, int size,
>>   			 bool flow_control)
> 
> Could you rename this to prep_adm_dma_desc for consistency?
> 
>> @@ -891,12 +961,44 @@ static int submit_descs(struct 
>> qcom_nand_controller *nandc)
>>   {
>>   	struct desc_info *desc;
>>   	dma_cookie_t cookie = 0;
>> +	struct bam_transaction *bam_txn = nandc->bam_txn;
>> +	int r;
>> +
>> +	if (nandc->dma_bam_enabled) {
>> +		if (bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start) {
> 
> Using '>' instead of '-' here should be more legible.
> 

  Yes. I will use the same in v2.

>> +			r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
>> +			if (r)
>> +				return r;
>> +		}
>> +
>> +		if (bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start) {
>> +			r = prepare_bam_async_desc(nandc, nandc->tx_chan,
>> +						   DMA_PREP_INTERRUPT);
>> +			if (r)
>> +				return r;
>> +		}
>> +
>> +		if (bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start) {
>> +			r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
>> +						   DMA_PREP_CMD);
>> +			if (r)
>> +				return r;
>> +		}
>> +	}
>> 
>>   	list_for_each_entry(desc, &nandc->desc_list, node)
>>   		cookie = dmaengine_submit(desc->dma_desc);
>> 
>> -	if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
>> -		return -ETIMEDOUT;
>> +	if (nandc->dma_bam_enabled) {
>> +		dma_async_issue_pending(nandc->tx_chan);
>> +		dma_async_issue_pending(nandc->rx_chan);
>> +
>> +		if (dma_sync_wait(nandc->cmd_chan, cookie) != DMA_COMPLETE)
>> +			return -ETIMEDOUT;
>> +	} else {
>> +		if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
>> +			return -ETIMEDOUT;
>> +	}
>> 
>>   	return 0;
>>   }
>> @@ -907,7 +1009,14 @@ static void free_descs(struct 
>> qcom_nand_controller *nandc)
>> 
>>   	list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
>>   		list_del(&desc->node);
>> -		dma_unmap_sg(nandc->dev, &desc->sgl, 1, desc->dir);
>> +
>> +		if (nandc->dma_bam_enabled)
>> +			dma_unmap_sg(nandc->dev, desc->bam_sgl,
>> +				     desc->sgl_cnt, desc->dir);
>> +		else
>> +			dma_unmap_sg(nandc->dev, &desc->sgl, 1,
>> +				     desc->dir);
>> +
>>   		kfree(desc);
>>   	}
>>   }
>> 

-- 
Abhishek Sahu
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Re: [PATCH 06/14] qcom: mtd: nand: add bam dma descriptor handling

[Abhishek Sahu]

On 2017-07-04 11:40, Archit Taneja wrote:
> On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
>> 1. prepare_bam_async_desc is the function which will call
>>     all the DMA API’s. It will fetch the outstanding scatter gather
>>     list for passed channel and will do the DMA descriptor formation.
>>     The DMA flag is dependent upon the type of channel.
>> 
>> 2. For ADM DMA, the descriptor is being formed for every DMA
>>     request so its sgl count will be always 1 while in BAM DMA, the
>>     clubbing of descriptor is being done to increase throughput.
>> 
>> 3. ADM uses only one channel while in BAM, data descriptors
>>     will be submitted to tx channel (for write) or rx channel
>>     (for read) and all the registers read/write descriptors in
>>     command channel.
>> 
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> ---
>>   drivers/mtd/nand/qcom_nandc.c | 119 
>> ++++++++++++++++++++++++++++++++++++++++--
>>   1 file changed, 114 insertions(+), 5 deletions(-)
>> 
>> diff --git a/drivers/mtd/nand/qcom_nandc.c 
>> b/drivers/mtd/nand/qcom_nandc.c
>> index f8d0bde..7042a65 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -206,14 +206,22 @@ struct bam_transaction {
>>    * This data type corresponds to the nand dma descriptor
>>    * @list - list for desc_info
>>    * @dir - DMA transfer direction
>> - * @sgl - sgl which will be used for single sgl dma descriptor
>> + * @sgl - sgl which will be used for single sgl dma descriptor. Only 
>> used by ADM
>> + * @bam_sgl - sgl which will be used for dma descriptor. Only used by 
>> BAM
>> + * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
>>    * @dma_desc - low level dma engine descriptor
>>    */
>>   struct desc_info {
>>   	struct list_head node;
>> 
>>   	enum dma_data_direction dir;
>> -	struct scatterlist sgl;
>> +	union {
>> +			struct scatterlist sgl;
> 
> Can you make this adm_sgl instead for consistency? Also, please use 
> only
> two tabs instead of one here for indentation.

  Sure. I will do the same in v2.

> 
>> +			struct {
>> +				struct scatterlist *bam_sgl;
>> +				int sgl_cnt;
>> +			};
>> +	};
>>   	struct dma_async_tx_descriptor *dma_desc;
>>   };
>> 
>> @@ -564,6 +572,68 @@ static void update_rw_regs(struct qcom_nand_host 
>> *host, int num_cw, bool read)
>>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>>   }
>> 
>> +/*
>> + * Maps the scatter gather list for DMA transfer and forms the DMA 
>> descriptor
>> + * for BAM. This descriptor will be added in the NAND DMA descriptor 
>> queue
>> + * which will be submitted to DMA engine.
>> + */
>> +static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
>> +				  struct dma_chan *chan,
>> +				  unsigned long flags)
> 
> From what I gathered in patch #10, this would be called by
> prep_dma_desc_data_bam() and prep_dma_desc_command(). Can you rename 
> these
> two to something like prep_bam_dma_desc_data() and 
> prep_bam_dma_desc_cmd()
> 

  Sure. I will do the same in v2.

> 
>> +{
>> +	struct desc_info *desc;
>> +	struct scatterlist *sgl;
>> +	unsigned int sgl_cnt;
>> +	struct bam_transaction *bam_txn = nandc->bam_txn;
>> +	enum dma_transfer_direction dir_eng;
>> +	struct dma_async_tx_descriptor *dma_desc;
>> +
>> +	desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>> +	if (!desc)
>> +		return -ENOMEM;
>> +
>> +	if (chan == nandc->cmd_chan) {
>> +		sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
>> +		sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
>> +		bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
>> +		dir_eng = DMA_MEM_TO_DEV;
>> +		desc->dir = DMA_TO_DEVICE;
>> +	} else if (chan == nandc->tx_chan) {
>> +		sgl = &bam_txn->data_sg[bam_txn->tx_sgl_start];
>> +		sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
>> +		bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
>> +		dir_eng = DMA_MEM_TO_DEV;
>> +		desc->dir = DMA_TO_DEVICE;
>> +	} else {
>> +		sgl = &bam_txn->data_sg[bam_txn->rx_sgl_start];
>> +		sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
>> +		bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
>> +		desc->dir = DMA_FROM_DEVICE;
>> +		dir_eng = DMA_DEV_TO_MEM;
>> +	}
>> +
>> +	sg_mark_end(sgl + sgl_cnt - 1);
>> +	dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
> 
> Is it safe to assume here that dma_map_sg won't return an error?
> 

  We need to check for error. I will fix this in v2.

>> +
>> +	desc->sgl_cnt = sgl_cnt;
>> +	desc->bam_sgl = sgl;
>> +
>> +	dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
>> +					   flags);
>> +
>> +	if (!dma_desc) {
>> +		dev_err(nandc->dev, "failure in prep desc\n");
>> +		kfree(desc);
>> +		return -EINVAL;
>> +	}
>> +
>> +	desc->dma_desc = dma_desc;
>> +
>> +	list_add_tail(&desc->node, &nandc->desc_list);
>> +
>> +	return 0;
>> +}
>> +
> 
> 
>>   static int prep_dma_desc(struct qcom_nand_controller *nandc, bool 
>> read,
>>   			 int reg_off, const void *vaddr, int size,
>>   			 bool flow_control)
> 
> Could you rename this to prep_adm_dma_desc for consistency?
> 
>> @@ -891,12 +961,44 @@ static int submit_descs(struct 
>> qcom_nand_controller *nandc)
>>   {
>>   	struct desc_info *desc;
>>   	dma_cookie_t cookie = 0;
>> +	struct bam_transaction *bam_txn = nandc->bam_txn;
>> +	int r;
>> +
>> +	if (nandc->dma_bam_enabled) {
>> +		if (bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start) {
> 
> Using '>' instead of '-' here should be more legible.
> 

  Yes. I will use the same in v2.

>> +			r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
>> +			if (r)
>> +				return r;
>> +		}
>> +
>> +		if (bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start) {
>> +			r = prepare_bam_async_desc(nandc, nandc->tx_chan,
>> +						   DMA_PREP_INTERRUPT);
>> +			if (r)
>> +				return r;
>> +		}
>> +
>> +		if (bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start) {
>> +			r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
>> +						   DMA_PREP_CMD);
>> +			if (r)
>> +				return r;
>> +		}
>> +	}
>> 
>>   	list_for_each_entry(desc, &nandc->desc_list, node)
>>   		cookie = dmaengine_submit(desc->dma_desc);
>> 
>> -	if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
>> -		return -ETIMEDOUT;
>> +	if (nandc->dma_bam_enabled) {
>> +		dma_async_issue_pending(nandc->tx_chan);
>> +		dma_async_issue_pending(nandc->rx_chan);
>> +
>> +		if (dma_sync_wait(nandc->cmd_chan, cookie) != DMA_COMPLETE)
>> +			return -ETIMEDOUT;
>> +	} else {
>> +		if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
>> +			return -ETIMEDOUT;
>> +	}
>> 
>>   	return 0;
>>   }
>> @@ -907,7 +1009,14 @@ static void free_descs(struct 
>> qcom_nand_controller *nandc)
>> 
>>   	list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
>>   		list_del(&desc->node);
>> -		dma_unmap_sg(nandc->dev, &desc->sgl, 1, desc->dir);
>> +
>> +		if (nandc->dma_bam_enabled)
>> +			dma_unmap_sg(nandc->dev, desc->bam_sgl,
>> +				     desc->sgl_cnt, desc->dir);
>> +		else
>> +			dma_unmap_sg(nandc->dev, &desc->sgl, 1,
>> +				     desc->dir);
>> +
>>   		kfree(desc);
>>   	}
>>   }
>> 

-- 
Abhishek Sahu

[PATCH 09/14] qcom: mtd: nand: BAM support for read page

[Abhishek Sahu]

1. The BAM mode requires few registers configuration before each
   NAND page read and codeword read which is different from ADM
   so add the helper functions which will be called in BAM mode
   only.

2. The NAND page read handling of BAM is different from ADM so
   call the appropriate helper functions

Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 drivers/mtd/nand/qcom_nandc.c | 63 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 62 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 8e7dc9e..17766af 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -870,6 +870,35 @@ static void config_cw_read(struct qcom_nand_controller *nandc)
 }
 
 /*
+ * Helpers to prepare DMA descriptors for configuring registers
+ * before reading a NAND page with BAM.
+ */
+static void config_bam_page_read(struct qcom_nand_controller *nandc)
+{
+	write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
+	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
+	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
+	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
+	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
+		      NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
+}
+
+/*
+ * Helpers to prepare DMA descriptors for configuring registers
+ * before reading each codeword in NAND page with BAM.
+ */
+static void config_bam_cw_read(struct qcom_nand_controller *nandc)
+{
+	write_reg_dma(nandc, NAND_READ_LOCATION_0, 2, 0);
+	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
+	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
+
+	read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
+	read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
+		     NAND_BAM_NEXT_SGL);
+}
+
+/*
  * helpers to prepare dma descriptors used to configure registers needed for
  * writing a codeword/step in a page
  */
@@ -1398,6 +1427,9 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
 	struct nand_ecc_ctrl *ecc = &chip->ecc;
 	int i, ret;
 
+	if (nandc->dma_bam_enabled)
+		config_bam_page_read(nandc);
+
 	/* queue cmd descs for each codeword */
 	for (i = 0; i < ecc->steps; i++) {
 		int data_size, oob_size;
@@ -1411,7 +1443,36 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
 			oob_size = host->ecc_bytes_hw + host->spare_bytes;
 		}
 
-		config_cw_read(nandc);
+		if (nandc->dma_bam_enabled) {
+			if (data_buf && oob_buf) {
+				nandc_set_reg(nandc, NAND_READ_LOCATION_0,
+					      (0 << READ_LOCATION_OFFSET) |
+					      (data_size <<
+					      READ_LOCATION_SIZE) |
+					      (0 << READ_LOCATION_LAST));
+				nandc_set_reg(nandc, NAND_READ_LOCATION_1,
+					      (data_size <<
+					      READ_LOCATION_OFFSET) |
+					      (oob_size << READ_LOCATION_SIZE) |
+					      (1 << READ_LOCATION_LAST));
+			} else if (data_buf) {
+				nandc_set_reg(nandc, NAND_READ_LOCATION_0,
+					      (0 << READ_LOCATION_OFFSET) |
+					      (data_size <<
+					      READ_LOCATION_SIZE) |
+					      (1 << READ_LOCATION_LAST));
+			} else {
+				nandc_set_reg(nandc, NAND_READ_LOCATION_0,
+					      (data_size <<
+					      READ_LOCATION_OFFSET) |
+					      (oob_size << READ_LOCATION_SIZE) |
+					      (1 << READ_LOCATION_LAST));
+			}
+
+			config_bam_cw_read(nandc);
+		} else {
+			config_cw_read(nandc);
+		}
 
 		if (data_buf)
 			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
-- 
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[PATCH 09/14] qcom: mtd: nand: BAM support for read page

[Abhishek Sahu]

1. The BAM mode requires few registers configuration before each
   NAND page read and codeword read which is different from ADM
   so add the helper functions which will be called in BAM mode
   only.

2. The NAND page read handling of BAM is different from ADM so
   call the appropriate helper functions

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/mtd/nand/qcom_nandc.c | 63 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 62 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 8e7dc9e..17766af 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -870,6 +870,35 @@ static void config_cw_read(struct qcom_nand_controller *nandc)
 }
 
 /*
+ * Helpers to prepare DMA descriptors for configuring registers
+ * before reading a NAND page with BAM.
+ */
+static void config_bam_page_read(struct qcom_nand_controller *nandc)
+{
+	write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
+	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
+	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
+	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
+	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
+		      NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
+}
+
+/*
+ * Helpers to prepare DMA descriptors for configuring registers
+ * before reading each codeword in NAND page with BAM.
+ */
+static void config_bam_cw_read(struct qcom_nand_controller *nandc)
+{
+	write_reg_dma(nandc, NAND_READ_LOCATION_0, 2, 0);
+	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
+	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
+
+	read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
+	read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
+		     NAND_BAM_NEXT_SGL);
+}
+
+/*
  * helpers to prepare dma descriptors used to configure registers needed for
  * writing a codeword/step in a page
  */
@@ -1398,6 +1427,9 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
 	struct nand_ecc_ctrl *ecc = &chip->ecc;
 	int i, ret;
 
+	if (nandc->dma_bam_enabled)
+		config_bam_page_read(nandc);
+
 	/* queue cmd descs for each codeword */
 	for (i = 0; i < ecc->steps; i++) {
 		int data_size, oob_size;
@@ -1411,7 +1443,36 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
 			oob_size = host->ecc_bytes_hw + host->spare_bytes;
 		}
 
-		config_cw_read(nandc);
+		if (nandc->dma_bam_enabled) {
+			if (data_buf && oob_buf) {
+				nandc_set_reg(nandc, NAND_READ_LOCATION_0,
+					      (0 << READ_LOCATION_OFFSET) |
+					      (data_size <<
+					      READ_LOCATION_SIZE) |
+					      (0 << READ_LOCATION_LAST));
+				nandc_set_reg(nandc, NAND_READ_LOCATION_1,
+					      (data_size <<
+					      READ_LOCATION_OFFSET) |
+					      (oob_size << READ_LOCATION_SIZE) |
+					      (1 << READ_LOCATION_LAST));
+			} else if (data_buf) {
+				nandc_set_reg(nandc, NAND_READ_LOCATION_0,
+					      (0 << READ_LOCATION_OFFSET) |
+					      (data_size <<
+					      READ_LOCATION_SIZE) |
+					      (1 << READ_LOCATION_LAST));
+			} else {
+				nandc_set_reg(nandc, NAND_READ_LOCATION_0,
+					      (data_size <<
+					      READ_LOCATION_OFFSET) |
+					      (oob_size << READ_LOCATION_SIZE) |
+					      (1 << READ_LOCATION_LAST));
+			}
+
+			config_bam_cw_read(nandc);
+		} else {
+			config_cw_read(nandc);
+		}
 
 		if (data_buf)
 			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
-- 
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Re: [PATCH 09/14] qcom: mtd: nand: BAM support for read page

[Archit Taneja]

On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
> 1. The BAM mode requires few registers configuration before each
>     NAND page read and codeword read which is different from ADM
>     so add the helper functions which will be called in BAM mode
>     only.
> 
> 2. The NAND page read handling of BAM is different from ADM so
>     call the appropriate helper functions
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>   drivers/mtd/nand/qcom_nandc.c | 63 ++++++++++++++++++++++++++++++++++++++++++-
>   1 file changed, 62 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 8e7dc9e..17766af 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -870,6 +870,35 @@ static void config_cw_read(struct qcom_nand_controller *nandc)
>   }
>   
>   /*
> + * Helpers to prepare DMA descriptors for configuring registers
> + * before reading a NAND page with BAM.
> + */
> +static void config_bam_page_read(struct qcom_nand_controller *nandc)
> +{
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
> +	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> +	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
> +	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
> +	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
> +		      NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
> +}
> +
> +/*
> + * Helpers to prepare DMA descriptors for configuring registers
> + * before reading each codeword in NAND page with BAM.
> + */

If I understood right, EBI2 nand required us to load all the registers
configured in config_cw_read() for every codeword, and for BAM, the
registers configured in config_bam_page_read() just needs to be done once,
and the registers in config_bam_cw_read()  need to be reloaded for every
codeword?

Could you please clarify this better in the commit message and comments? Also,
I still see config_cw_read() being used for QPIC nand in nandc_param() and
copy_last_cw()?

Also, I think these should be called config_qpic_page_read() and
config_qpic_cw_read() since it seems more of a property of the NAND controller
rather than the underlying DMA engine. If so, config_cw_read() can be called
config_cw_ebi2_read(). Please correct me if I'm wrong somewhere.

> +static void config_bam_cw_read(struct qcom_nand_controller *nandc)
> +{
> +	write_reg_dma(nandc, NAND_READ_LOCATION_0, 2, 0);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
> +
> +	read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
> +	read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
> +		     NAND_BAM_NEXT_SGL);
> +}
> +
> +/*
>    * helpers to prepare dma descriptors used to configure registers needed for
>    * writing a codeword/step in a page
>    */
> @@ -1398,6 +1427,9 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
>   	struct nand_ecc_ctrl *ecc = &chip->ecc;
>   	int i, ret;
>   
> +	if (nandc->dma_bam_enabled)
> +		config_bam_page_read(nandc);
> +
>   	/* queue cmd descs for each codeword */
>   	for (i = 0; i < ecc->steps; i++) {
>   		int data_size, oob_size;
> @@ -1411,7 +1443,36 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
>   			oob_size = host->ecc_bytes_hw + host->spare_bytes;
>   		}
>   
> -		config_cw_read(nandc);
> +		if (nandc->dma_bam_enabled) {
> +			if (data_buf && oob_buf) {
> +				nandc_set_reg(nandc, NAND_READ_LOCATION_0,
> +					      (0 << READ_LOCATION_OFFSET) |
> +					      (data_size <<
> +					      READ_LOCATION_SIZE) |
> +					      (0 << READ_LOCATION_LAST));
> +				nandc_set_reg(nandc, NAND_READ_LOCATION_1,
> +					      (data_size <<
> +					      READ_LOCATION_OFFSET) |
> +					      (oob_size << READ_LOCATION_SIZE) |
> +					      (1 << READ_LOCATION_LAST));
> +			} else if (data_buf) {
> +				nandc_set_reg(nandc, NAND_READ_LOCATION_0,
> +					      (0 << READ_LOCATION_OFFSET) |
> +					      (data_size <<
> +					      READ_LOCATION_SIZE) |
> +					      (1 << READ_LOCATION_LAST));
> +			} else {
> +				nandc_set_reg(nandc, NAND_READ_LOCATION_0,
> +					      (data_size <<
> +					      READ_LOCATION_OFFSET) |
> +					      (oob_size << READ_LOCATION_SIZE) |
> +					      (1 << READ_LOCATION_LAST));
> +			}

Could we put the READ_LOCATION_x register configuration into a small helper?
This is probably a matter of taste, but you could consider configuring like this.
Maybe something similar for patch #11 for raw page reads.

	if (data_buf && oob_buf) {
		r0_off = 0;
		r0_size = r1_off = data_size;
		r1_size = oob_size;
		r0_last = 0;
		r1_last = 1;
	} else if (data_buf) {
		rl0_off = 0;
		rl0_size = data_size;
		rl0_last = 1;
	} else {
		rl0_off = data_size;
		rl0_size = oob_size;
		rl0_last = 1;
	}

	nandc_set_reg(nandc, NAND_READ_LOCATION_0,
		      (rl0_off << READ_LOCATION_OFFSET) |
		      (rl0_size << READ_LOCATION_SIZE) |
		      (rl0_last << READ_LOCATION_LAST));
	if (rl1_last)
		/* program LOCATION_1 register */

Thanks,
Archit

> +
> +			config_bam_cw_read(nandc);
> +		} else {
> +			config_cw_read(nandc);
> +		}
>   
>   		if (data_buf)
>   			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
> 

-- 
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a Linux Foundation Collaborative Project

Re: [PATCH 09/14] qcom: mtd: nand: BAM support for read page

[Sricharan R]

Hi,

On 7/4/2017 3:10 PM, Archit Taneja wrote:
> 
> 
> On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
>> 1. The BAM mode requires few registers configuration before each
>>     NAND page read and codeword read which is different from ADM
>>     so add the helper functions which will be called in BAM mode
>>     only.
>>
>> 2. The NAND page read handling of BAM is different from ADM so
>>     call the appropriate helper functions
>>
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> ---
>>   drivers/mtd/nand/qcom_nandc.c | 63 ++++++++++++++++++++++++++++++++++++++++++-
>>   1 file changed, 62 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
>> index 8e7dc9e..17766af 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -870,6 +870,35 @@ static void config_cw_read(struct qcom_nand_controller *nandc)
>>   }
>>     /*
>> + * Helpers to prepare DMA descriptors for configuring registers
>> + * before reading a NAND page with BAM.
>> + */
>> +static void config_bam_page_read(struct qcom_nand_controller *nandc)
>> +{
>> +    write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
>> +    write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> +    write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>> +    write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
>> +    write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
>> +              NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
>> +}
>> +
>> +/*
>> + * Helpers to prepare DMA descriptors for configuring registers
>> + * before reading each codeword in NAND page with BAM.
>> + */
> 
> If I understood right, EBI2 nand required us to load all the registers
> configured in config_cw_read() for every codeword, and for BAM, the
> registers configured in config_bam_page_read() just needs to be done once,
> and the registers in config_bam_cw_read()  need to be reloaded for every
> codeword?
> 
> Could you please clarify this better in the commit message and comments? Also,
> I still see config_cw_read() being used for QPIC nand in nandc_param() and
> copy_last_cw()?
> 
> Also, I think these should be called config_qpic_page_read() and
> config_qpic_cw_read() since it seems more of a property of the NAND controller
> rather than the underlying DMA engine. If so, config_cw_read() can be called
> config_cw_ebi2_read(). Please correct me if I'm wrong somewhere.
> 

 Even here as well, if we have different function pointers for config_bam_cw_read
 and config_cw_read for bam, adm, we can still share code with helpers and have
 only the difference populated in to those functions, reducing the if (bam_dma_enabled)
 checks.

Regards,
 Sricharan



>> +static void config_bam_cw_read(struct qcom_nand_controller *nandc)
>> +{
>> +    write_reg_dma(nandc, NAND_READ_LOCATION_0, 2, 0);
>> +    write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
>> +    write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>> +
>> +    read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
>> +    read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
>> +             NAND_BAM_NEXT_SGL);
>> +}
>> +
>> +/*
>>    * helpers to prepare dma descriptors used to configure registers needed for
>>    * writing a codeword/step in a page
>>    */
>> @@ -1398,6 +1427,9 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
>>       struct nand_ecc_ctrl *ecc = &chip->ecc;
>>       int i, ret;
>>   +    if (nandc->dma_bam_enabled)
>> +        config_bam_page_read(nandc);
>> +
>>       /* queue cmd descs for each codeword */
>>       for (i = 0; i < ecc->steps; i++) {
>>           int data_size, oob_size;
>> @@ -1411,7 +1443,36 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
>>               oob_size = host->ecc_bytes_hw + host->spare_bytes;
>>           }
>>   -        config_cw_read(nandc);
>> +        if (nandc->dma_bam_enabled) {
>> +            if (data_buf && oob_buf) {
>> +                nandc_set_reg(nandc, NAND_READ_LOCATION_0,
>> +                          (0 << READ_LOCATION_OFFSET) |
>> +                          (data_size <<
>> +                          READ_LOCATION_SIZE) |
>> +                          (0 << READ_LOCATION_LAST));
>> +                nandc_set_reg(nandc, NAND_READ_LOCATION_1,
>> +                          (data_size <<
>> +                          READ_LOCATION_OFFSET) |
>> +                          (oob_size << READ_LOCATION_SIZE) |
>> +                          (1 << READ_LOCATION_LAST));
>> +            } else if (data_buf) {
>> +                nandc_set_reg(nandc, NAND_READ_LOCATION_0,
>> +                          (0 << READ_LOCATION_OFFSET) |
>> +                          (data_size <<
>> +                          READ_LOCATION_SIZE) |
>> +                          (1 << READ_LOCATION_LAST));
>> +            } else {
>> +                nandc_set_reg(nandc, NAND_READ_LOCATION_0,
>> +                          (data_size <<
>> +                          READ_LOCATION_OFFSET) |
>> +                          (oob_size << READ_LOCATION_SIZE) |
>> +                          (1 << READ_LOCATION_LAST));
>> +            }
> 
> Could we put the READ_LOCATION_x register configuration into a small helper?
> This is probably a matter of taste, but you could consider configuring like this.
> Maybe something similar for patch #11 for raw page reads.
> 
>     if (data_buf && oob_buf) {
>         r0_off = 0;
>         r0_size = r1_off = data_size;
>         r1_size = oob_size;
>         r0_last = 0;
>         r1_last = 1;
>     } else if (data_buf) {
>         rl0_off = 0;
>         rl0_size = data_size;
>         rl0_last = 1;
>     } else {
>         rl0_off = data_size;
>         rl0_size = oob_size;
>         rl0_last = 1;
>     }
> 
>     nandc_set_reg(nandc, NAND_READ_LOCATION_0,
>               (rl0_off << READ_LOCATION_OFFSET) |
>               (rl0_size << READ_LOCATION_SIZE) |
>               (rl0_last << READ_LOCATION_LAST));
>     if (rl1_last)
>         /* program LOCATION_1 register */
> 
> Thanks,
> Archit
> 
>> +
>> +            config_bam_cw_read(nandc);
>> +        } else {
>> +            config_cw_read(nandc);
>> +        }
>>             if (data_buf)
>>               read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
>>
> 

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Re: [PATCH 09/14] qcom: mtd: nand: BAM support for read page

[Abhishek Sahu]

On 2017-07-04 15:10, Archit Taneja wrote:
> On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
>> 1. The BAM mode requires few registers configuration before each
>>     NAND page read and codeword read which is different from ADM
>>     so add the helper functions which will be called in BAM mode
>>     only.
>> 
>> 2. The NAND page read handling of BAM is different from ADM so
>>     call the appropriate helper functions
>> 
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> ---
>>   drivers/mtd/nand/qcom_nandc.c | 63 
>> ++++++++++++++++++++++++++++++++++++++++++-
>>   1 file changed, 62 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/mtd/nand/qcom_nandc.c 
>> b/drivers/mtd/nand/qcom_nandc.c
>> index 8e7dc9e..17766af 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -870,6 +870,35 @@ static void config_cw_read(struct 
>> qcom_nand_controller *nandc)
>>   }
>> 
>>   /*
>> + * Helpers to prepare DMA descriptors for configuring registers
>> + * before reading a NAND page with BAM.
>> + */
>> +static void config_bam_page_read(struct qcom_nand_controller *nandc)
>> +{
>> +	write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
>> +	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> +	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>> +	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
>> +	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
>> +		      NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
>> +}
>> +
>> +/*
>> + * Helpers to prepare DMA descriptors for configuring registers
>> + * before reading each codeword in NAND page with BAM.
>> + */
> 
> If I understood right, EBI2 nand required us to load all the registers
> configured in config_cw_read() for every codeword, and for BAM, the
> registers configured in config_bam_page_read() just needs to be done 
> once,
> and the registers in config_bam_cw_read()  need to be reloaded for 
> every
> codeword?
> 
> Could you please clarify this better in the commit message and 
> comments? Also,
> I still see config_cw_read() being used for QPIC nand in nandc_param() 
> and
> copy_last_cw()?
> 
> Also, I think these should be called config_qpic_page_read() and
> config_qpic_cw_read() since it seems more of a property of the NAND 
> controller
> rather than the underlying DMA engine. If so, config_cw_read() can be 
> called
> config_cw_ebi2_read(). Please correct me if I'm wrong somewhere.
> 

  I did some code reorganization in v2 in this area and now, we don't
  have do different things for EBI2 and QPIC for read.

>> +static void config_bam_cw_read(struct qcom_nand_controller *nandc)
>> +{
>> +	write_reg_dma(nandc, NAND_READ_LOCATION_0, 2, 0);
>> +	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
>> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>> +
>> +	read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
>> +	read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
>> +		     NAND_BAM_NEXT_SGL);
>> +}
>> +
>> +/*
>>    * helpers to prepare dma descriptors used to configure registers 
>> needed for
>>    * writing a codeword/step in a page
>>    */
>> @@ -1398,6 +1427,9 @@ static int read_page_ecc(struct qcom_nand_host 
>> *host, u8 *data_buf,
>>   	struct nand_ecc_ctrl *ecc = &chip->ecc;
>>   	int i, ret;
>> 
>> +	if (nandc->dma_bam_enabled)
>> +		config_bam_page_read(nandc);
>> +
>>   	/* queue cmd descs for each codeword */
>>   	for (i = 0; i < ecc->steps; i++) {
>>   		int data_size, oob_size;
>> @@ -1411,7 +1443,36 @@ static int read_page_ecc(struct qcom_nand_host 
>> *host, u8 *data_buf,
>>   			oob_size = host->ecc_bytes_hw + host->spare_bytes;
>>   		}
>> 
>> -		config_cw_read(nandc);
>> +		if (nandc->dma_bam_enabled) {
>> +			if (data_buf && oob_buf) {
>> +				nandc_set_reg(nandc, NAND_READ_LOCATION_0,
>> +					      (0 << READ_LOCATION_OFFSET) |
>> +					      (data_size <<
>> +					      READ_LOCATION_SIZE) |
>> +					      (0 << READ_LOCATION_LAST));
>> +				nandc_set_reg(nandc, NAND_READ_LOCATION_1,
>> +					      (data_size <<
>> +					      READ_LOCATION_OFFSET) |
>> +					      (oob_size << READ_LOCATION_SIZE) |
>> +					      (1 << READ_LOCATION_LAST));
>> +			} else if (data_buf) {
>> +				nandc_set_reg(nandc, NAND_READ_LOCATION_0,
>> +					      (0 << READ_LOCATION_OFFSET) |
>> +					      (data_size <<
>> +					      READ_LOCATION_SIZE) |
>> +					      (1 << READ_LOCATION_LAST));
>> +			} else {
>> +				nandc_set_reg(nandc, NAND_READ_LOCATION_0,
>> +					      (data_size <<
>> +					      READ_LOCATION_OFFSET) |
>> +					      (oob_size << READ_LOCATION_SIZE) |
>> +					      (1 << READ_LOCATION_LAST));
>> +			}
> 
> Could we put the READ_LOCATION_x register configuration into a small 
> helper?
> This is probably a matter of taste, but you could consider configuring
> like this.
> Maybe something similar for patch #11 for raw page reads.
> 

  I will use macro for assigning READ LOCATION registers in v2,
  which makes the code cleaner. If required, I will use helpers
  also.

> 	if (data_buf && oob_buf) {
> 		r0_off = 0;
> 		r0_size = r1_off = data_size;
> 		r1_size = oob_size;
> 		r0_last = 0;
> 		r1_last = 1;
> 	} else if (data_buf) {
> 		rl0_off = 0;
> 		rl0_size = data_size;
> 		rl0_last = 1;
> 	} else {
> 		rl0_off = data_size;
> 		rl0_size = oob_size;
> 		rl0_last = 1;
> 	}
> 
> 	nandc_set_reg(nandc, NAND_READ_LOCATION_0,
> 		      (rl0_off << READ_LOCATION_OFFSET) |
> 		      (rl0_size << READ_LOCATION_SIZE) |
> 		      (rl0_last << READ_LOCATION_LAST));
> 	if (rl1_last)
> 		/* program LOCATION_1 register */
> 
> Thanks,
> Archit
> 
>> +
>> +			config_bam_cw_read(nandc);
>> +		} else {
>> +			config_cw_read(nandc);
>> +		}
>> 
>>   		if (data_buf)
>>   			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
>> 

-- 
Abhishek Sahu

[PATCH 13/14] qcom: mtd: nand: support for QPIC version 1.5.0

[Abhishek Sahu]

The current QCOM NAND driver only supports version 1.4.0
QCOM QPIC NAND controller. This patch adds the support for
version 1.5.0 which contains some of the registers at
different offsets. The driver data contains the register offset
field which is being initialized with its crossponding register
offsets array. A new compatible string has been added for
version 1.5.0 in BAM mode which uses version 1.5.0 register
offsets.

Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 .../devicetree/bindings/mtd/qcom_nandc.txt         | 44 ++++++++++++++++++
 drivers/mtd/nand/qcom_nandc.c                      | 54 ++++++++++++++++++++--
 2 files changed, 95 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index 87b9a56..11e2da2 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -4,6 +4,8 @@ Required properties:
 - compatible:		must be one of the following:
 	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
 	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
+	* "qcom,qpic-nandc-v1.5.0" - QPIC NAND v1.5.0 which uses BAM DMA like IPQ8074.
+
 - reg:			MMIO address range
 - clocks:		must contain core clock and always on clock
 - clock-names:		must contain "core" for the core clock and "aon" for the
@@ -130,3 +132,45 @@ nand@79b0000 {
 		};
 	};
 };
+
+nand@79b0000 {
+	compatible = "qcom,qpic-nandc-v1.5.0";
+	reg = <0x79B0000 0x1000>;
+
+	clocks = <&gcc GCC_QPIC_CLK>,
+		<&gcc GCC_QPIC_AHB_CLK>;
+	clock-names = "core", "aon";
+
+	dmas = <&qpicbam 0>,
+		<&qpicbam 1>,
+		<&qpicbam 2>;
+	dma-names = "tx", "rx", "cmd";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@0 {
+		compatible = "qcom,nandcs";
+		reg = <0>;
+
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "boot-nand";
+				reg = <0 0x58a0000>;
+			};
+
+			partition@58a0000 {
+				label = "fs-nand";
+				reg = <0x58a0000 0x4000000>;
+			};
+		};
+	};
+};
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 24750e6..641e85d 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -430,15 +430,18 @@ struct qcom_nand_host {
  * This data type corresponds to the nand driver data which will be used at
  * driver probe time
  * @ecc_modes - ecc mode for nand
+ * @regs_offsets - contains the register offsets array pointer.
  * @dma_bam_enabled - whether this driver is using bam
  */
 struct qcom_nand_driver_data {
 	u32 ecc_modes;
+	const u32 *regs_offsets;
 	bool dma_bam_enabled;
 };
 
 /* Mapping table which contains the actual register offsets */
-static const u32 regs_offsets[] = {
+/* NAND controller Version 1.4.0 mapping table */
+static const u32 regs_offsets_v1_4_0[] = {
 	[NAND_FLASH_CMD] = 0x00,
 	[NAND_ADDR0] = 0x04,
 	[NAND_ADDR1] = 0x08,
@@ -471,6 +474,40 @@ struct qcom_nand_driver_data {
 	[NAND_READ_LOCATION_3] = 0xf2c,
 };
 
+/* NAND controller Version 1.5.0 mapping table */
+static const u32 regs_offsets_v1_5_0[] = {
+	[NAND_FLASH_CMD] = 0x00,
+	[NAND_ADDR0] = 0x04,
+	[NAND_ADDR1] = 0x08,
+	[NAND_FLASH_CHIP_SELECT] = 0x0c,
+	[NAND_EXEC_CMD] = 0x10,
+	[NAND_FLASH_STATUS] = 0x14,
+	[NAND_BUFFER_STATUS] = 0x18,
+	[NAND_DEV0_CFG0] = 0x20,
+	[NAND_DEV0_CFG1] = 0x24,
+	[NAND_DEV0_ECC_CFG] = 0x28,
+	[NAND_DEV1_ECC_CFG] = 0x2c,
+	[NAND_DEV1_CFG0] = 0x30,
+	[NAND_DEV1_CFG1] = 0x34,
+	[NAND_READ_ID] = 0x40,
+	[NAND_READ_STATUS] = 0x44,
+	[NAND_DEV_CMD0] = 0x70a0,
+	[NAND_DEV_CMD1] = 0x70a4,
+	[NAND_DEV_CMD2] = 0x70a8,
+	[NAND_DEV_CMD_VLD] = 0x70ac,
+	[SFLASHC_BURST_CFG] = 0xe0,
+	[NAND_ERASED_CW_DETECT_CFG] = 0xe8,
+	[NAND_ERASED_CW_DETECT_STATUS] = 0xec,
+	[NAND_EBI2_ECC_BUF_CFG] = 0xf0,
+	[FLASH_BUF_ACC] = 0x100,
+	[NAND_CTRL] = 0xf00,
+	[NAND_VERSION] = 0x4f08,
+	[NAND_READ_LOCATION_0] = 0xf20,
+	[NAND_READ_LOCATION_1] = 0xf24,
+	[NAND_READ_LOCATION_2] = 0xf28,
+	[NAND_READ_LOCATION_3] = 0xf2c,
+};
+
 /* Frees the BAM transaction memory */
 static void free_bam_transaction(struct qcom_nand_controller *nandc)
 {
@@ -2832,7 +2869,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 
 	nandc->ecc_modes = driver_data->ecc_modes;
 	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
-	nandc->regs_offsets = regs_offsets;
+	nandc->regs_offsets = driver_data->regs_offsets;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	nandc->base = devm_ioremap_resource(dev, res);
@@ -2902,16 +2939,24 @@ static int qcom_nandc_remove(struct platform_device *pdev)
 	return 0;
 }
 
-
 static const struct qcom_nand_driver_data ebi2_nandc_data = {
 	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
 	.dma_bam_enabled = false,
+	.regs_offsets = regs_offsets_v1_4_0,
 };
 
 static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
 	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
 	.dma_bam_enabled = true,
+	.regs_offsets = regs_offsets_v1_4_0,
+};
+
+static const struct qcom_nand_driver_data qpic_nandc_v1_5_0_data = {
+	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
+	.dma_bam_enabled = true,
+	.regs_offsets = regs_offsets_v1_5_0,
 };
+
 /*
  * data will hold a struct pointer containing more differences once we support
  * more controller variants
@@ -2923,6 +2968,9 @@ static int qcom_nandc_remove(struct platform_device *pdev)
 	{	.compatible = "qcom,qpic-nandc-v1.4.0",
 		.data = (void *)&qpic_nandc_v1_4_0_data,
 	},
+	{	.compatible = "qcom,qpic-nandc-v1.5.0",
+		.data = (void *)&qpic_nandc_v1_5_0_data,
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

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[PATCH 13/14] qcom: mtd: nand: support for QPIC version 1.5.0

[Abhishek Sahu]

The current QCOM NAND driver only supports version 1.4.0
QCOM QPIC NAND controller. This patch adds the support for
version 1.5.0 which contains some of the registers at
different offsets. The driver data contains the register offset
field which is being initialized with its crossponding register
offsets array. A new compatible string has been added for
version 1.5.0 in BAM mode which uses version 1.5.0 register
offsets.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 .../devicetree/bindings/mtd/qcom_nandc.txt         | 44 ++++++++++++++++++
 drivers/mtd/nand/qcom_nandc.c                      | 54 ++++++++++++++++++++--
 2 files changed, 95 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index 87b9a56..11e2da2 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -4,6 +4,8 @@ Required properties:
 - compatible:		must be one of the following:
 	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
 	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
+	* "qcom,qpic-nandc-v1.5.0" - QPIC NAND v1.5.0 which uses BAM DMA like IPQ8074.
+
 - reg:			MMIO address range
 - clocks:		must contain core clock and always on clock
 - clock-names:		must contain "core" for the core clock and "aon" for the
@@ -130,3 +132,45 @@ nand@79b0000 {
 		};
 	};
 };
+
+nand@79b0000 {
+	compatible = "qcom,qpic-nandc-v1.5.0";
+	reg = <0x79B0000 0x1000>;
+
+	clocks = <&gcc GCC_QPIC_CLK>,
+		<&gcc GCC_QPIC_AHB_CLK>;
+	clock-names = "core", "aon";
+
+	dmas = <&qpicbam 0>,
+		<&qpicbam 1>,
+		<&qpicbam 2>;
+	dma-names = "tx", "rx", "cmd";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@0 {
+		compatible = "qcom,nandcs";
+		reg = <0>;
+
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "boot-nand";
+				reg = <0 0x58a0000>;
+			};
+
+			partition@58a0000 {
+				label = "fs-nand";
+				reg = <0x58a0000 0x4000000>;
+			};
+		};
+	};
+};
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 24750e6..641e85d 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -430,15 +430,18 @@ struct qcom_nand_host {
  * This data type corresponds to the nand driver data which will be used at
  * driver probe time
  * @ecc_modes - ecc mode for nand
+ * @regs_offsets - contains the register offsets array pointer.
  * @dma_bam_enabled - whether this driver is using bam
  */
 struct qcom_nand_driver_data {
 	u32 ecc_modes;
+	const u32 *regs_offsets;
 	bool dma_bam_enabled;
 };
 
 /* Mapping table which contains the actual register offsets */
-static const u32 regs_offsets[] = {
+/* NAND controller Version 1.4.0 mapping table */
+static const u32 regs_offsets_v1_4_0[] = {
 	[NAND_FLASH_CMD] = 0x00,
 	[NAND_ADDR0] = 0x04,
 	[NAND_ADDR1] = 0x08,
@@ -471,6 +474,40 @@ struct qcom_nand_driver_data {
 	[NAND_READ_LOCATION_3] = 0xf2c,
 };
 
+/* NAND controller Version 1.5.0 mapping table */
+static const u32 regs_offsets_v1_5_0[] = {
+	[NAND_FLASH_CMD] = 0x00,
+	[NAND_ADDR0] = 0x04,
+	[NAND_ADDR1] = 0x08,
+	[NAND_FLASH_CHIP_SELECT] = 0x0c,
+	[NAND_EXEC_CMD] = 0x10,
+	[NAND_FLASH_STATUS] = 0x14,
+	[NAND_BUFFER_STATUS] = 0x18,
+	[NAND_DEV0_CFG0] = 0x20,
+	[NAND_DEV0_CFG1] = 0x24,
+	[NAND_DEV0_ECC_CFG] = 0x28,
+	[NAND_DEV1_ECC_CFG] = 0x2c,
+	[NAND_DEV1_CFG0] = 0x30,
+	[NAND_DEV1_CFG1] = 0x34,
+	[NAND_READ_ID] = 0x40,
+	[NAND_READ_STATUS] = 0x44,
+	[NAND_DEV_CMD0] = 0x70a0,
+	[NAND_DEV_CMD1] = 0x70a4,
+	[NAND_DEV_CMD2] = 0x70a8,
+	[NAND_DEV_CMD_VLD] = 0x70ac,
+	[SFLASHC_BURST_CFG] = 0xe0,
+	[NAND_ERASED_CW_DETECT_CFG] = 0xe8,
+	[NAND_ERASED_CW_DETECT_STATUS] = 0xec,
+	[NAND_EBI2_ECC_BUF_CFG] = 0xf0,
+	[FLASH_BUF_ACC] = 0x100,
+	[NAND_CTRL] = 0xf00,
+	[NAND_VERSION] = 0x4f08,
+	[NAND_READ_LOCATION_0] = 0xf20,
+	[NAND_READ_LOCATION_1] = 0xf24,
+	[NAND_READ_LOCATION_2] = 0xf28,
+	[NAND_READ_LOCATION_3] = 0xf2c,
+};
+
 /* Frees the BAM transaction memory */
 static void free_bam_transaction(struct qcom_nand_controller *nandc)
 {
@@ -2832,7 +2869,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 
 	nandc->ecc_modes = driver_data->ecc_modes;
 	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
-	nandc->regs_offsets = regs_offsets;
+	nandc->regs_offsets = driver_data->regs_offsets;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	nandc->base = devm_ioremap_resource(dev, res);
@@ -2902,16 +2939,24 @@ static int qcom_nandc_remove(struct platform_device *pdev)
 	return 0;
 }
 
-
 static const struct qcom_nand_driver_data ebi2_nandc_data = {
 	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
 	.dma_bam_enabled = false,
+	.regs_offsets = regs_offsets_v1_4_0,
 };
 
 static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
 	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
 	.dma_bam_enabled = true,
+	.regs_offsets = regs_offsets_v1_4_0,
+};
+
+static const struct qcom_nand_driver_data qpic_nandc_v1_5_0_data = {
+	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
+	.dma_bam_enabled = true,
+	.regs_offsets = regs_offsets_v1_5_0,
 };
+
 /*
  * data will hold a struct pointer containing more differences once we support
  * more controller variants
@@ -2923,6 +2968,9 @@ static int qcom_nandc_remove(struct platform_device *pdev)
 	{	.compatible = "qcom,qpic-nandc-v1.4.0",
 		.data = (void *)&qpic_nandc_v1_4_0_data,
 	},
+	{	.compatible = "qcom,qpic-nandc-v1.5.0",
+		.data = (void *)&qpic_nandc_v1_5_0_data,
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 13/14] qcom: mtd: nand: support for QPIC version 1.5.0

[Archit Taneja]

On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
> The current QCOM NAND driver only supports version 1.4.0
> QCOM QPIC NAND controller. This patch adds the support for
> version 1.5.0 which contains some of the registers at
> different offsets. The driver data contains the register offset
> field which is being initialized with its crossponding register

s/crossponding/corresponding

> offsets array. A new compatible string has been added for
> version 1.5.0 in BAM mode which uses version 1.5.0 register
> offsets.

Please split into 2 patches.

Thanks,
Archit

> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>   .../devicetree/bindings/mtd/qcom_nandc.txt         | 44 ++++++++++++++++++
>   drivers/mtd/nand/qcom_nandc.c                      | 54 ++++++++++++++++++++--
>   2 files changed, 95 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 87b9a56..11e2da2 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -4,6 +4,8 @@ Required properties:
>   - compatible:		must be one of the following:
>   	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
>   	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
> +	* "qcom,qpic-nandc-v1.5.0" - QPIC NAND v1.5.0 which uses BAM DMA like IPQ8074.
> +
>   - reg:			MMIO address range
>   - clocks:		must contain core clock and always on clock
>   - clock-names:		must contain "core" for the core clock and "aon" for the
> @@ -130,3 +132,45 @@ nand@79b0000 {
>   		};
>   	};
>   };
> +
> +nand@79b0000 {
> +	compatible = "qcom,qpic-nandc-v1.5.0";
> +	reg = <0x79B0000 0x1000>;
> +
> +	clocks = <&gcc GCC_QPIC_CLK>,
> +		<&gcc GCC_QPIC_AHB_CLK>;
> +	clock-names = "core", "aon";
> +
> +	dmas = <&qpicbam 0>,
> +		<&qpicbam 1>,
> +		<&qpicbam 2>;
> +	dma-names = "tx", "rx", "cmd";
> +
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	nandcs@0 {
> +		compatible = "qcom,nandcs";
> +		reg = <0>;
> +
> +		nand-ecc-strength = <4>;
> +		nand-ecc-step-size = <512>;
> +		nand-bus-width = <8>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				label = "boot-nand";
> +				reg = <0 0x58a0000>;
> +			};
> +
> +			partition@58a0000 {
> +				label = "fs-nand";
> +				reg = <0x58a0000 0x4000000>;
> +			};
> +		};
> +	};
> +};
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 24750e6..641e85d 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -430,15 +430,18 @@ struct qcom_nand_host {
>    * This data type corresponds to the nand driver data which will be used at
>    * driver probe time
>    * @ecc_modes - ecc mode for nand
> + * @regs_offsets - contains the register offsets array pointer.
>    * @dma_bam_enabled - whether this driver is using bam
>    */
>   struct qcom_nand_driver_data {
>   	u32 ecc_modes;
> +	const u32 *regs_offsets;
>   	bool dma_bam_enabled;
>   };
>   
>   /* Mapping table which contains the actual register offsets */
> -static const u32 regs_offsets[] = {
> +/* NAND controller Version 1.4.0 mapping table */
> +static const u32 regs_offsets_v1_4_0[] = {
>   	[NAND_FLASH_CMD] = 0x00,
>   	[NAND_ADDR0] = 0x04,
>   	[NAND_ADDR1] = 0x08,
> @@ -471,6 +474,40 @@ struct qcom_nand_driver_data {
>   	[NAND_READ_LOCATION_3] = 0xf2c,
>   };
>   
> +/* NAND controller Version 1.5.0 mapping table */
> +static const u32 regs_offsets_v1_5_0[] = {
> +	[NAND_FLASH_CMD] = 0x00,
> +	[NAND_ADDR0] = 0x04,
> +	[NAND_ADDR1] = 0x08,
> +	[NAND_FLASH_CHIP_SELECT] = 0x0c,
> +	[NAND_EXEC_CMD] = 0x10,
> +	[NAND_FLASH_STATUS] = 0x14,
> +	[NAND_BUFFER_STATUS] = 0x18,
> +	[NAND_DEV0_CFG0] = 0x20,
> +	[NAND_DEV0_CFG1] = 0x24,
> +	[NAND_DEV0_ECC_CFG] = 0x28,
> +	[NAND_DEV1_ECC_CFG] = 0x2c,
> +	[NAND_DEV1_CFG0] = 0x30,
> +	[NAND_DEV1_CFG1] = 0x34,
> +	[NAND_READ_ID] = 0x40,
> +	[NAND_READ_STATUS] = 0x44,
> +	[NAND_DEV_CMD0] = 0x70a0,
> +	[NAND_DEV_CMD1] = 0x70a4,
> +	[NAND_DEV_CMD2] = 0x70a8,
> +	[NAND_DEV_CMD_VLD] = 0x70ac,
> +	[SFLASHC_BURST_CFG] = 0xe0,
> +	[NAND_ERASED_CW_DETECT_CFG] = 0xe8,
> +	[NAND_ERASED_CW_DETECT_STATUS] = 0xec,
> +	[NAND_EBI2_ECC_BUF_CFG] = 0xf0,
> +	[FLASH_BUF_ACC] = 0x100,
> +	[NAND_CTRL] = 0xf00,
> +	[NAND_VERSION] = 0x4f08,
> +	[NAND_READ_LOCATION_0] = 0xf20,
> +	[NAND_READ_LOCATION_1] = 0xf24,
> +	[NAND_READ_LOCATION_2] = 0xf28,
> +	[NAND_READ_LOCATION_3] = 0xf2c,
> +};
> +
>   /* Frees the BAM transaction memory */
>   static void free_bam_transaction(struct qcom_nand_controller *nandc)
>   {
> @@ -2832,7 +2869,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>   
>   	nandc->ecc_modes = driver_data->ecc_modes;
>   	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
> -	nandc->regs_offsets = regs_offsets;
> +	nandc->regs_offsets = driver_data->regs_offsets;
>   
>   	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>   	nandc->base = devm_ioremap_resource(dev, res);
> @@ -2902,16 +2939,24 @@ static int qcom_nandc_remove(struct platform_device *pdev)
>   	return 0;
>   }
>   
> -
>   static const struct qcom_nand_driver_data ebi2_nandc_data = {
>   	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
>   	.dma_bam_enabled = false,
> +	.regs_offsets = regs_offsets_v1_4_0,
>   };
>   
>   static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
>   	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
>   	.dma_bam_enabled = true,
> +	.regs_offsets = regs_offsets_v1_4_0,
> +};
> +
> +static const struct qcom_nand_driver_data qpic_nandc_v1_5_0_data = {
> +	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
> +	.dma_bam_enabled = true,
> +	.regs_offsets = regs_offsets_v1_5_0,
>   };
> +
>   /*
>    * data will hold a struct pointer containing more differences once we support
>    * more controller variants
> @@ -2923,6 +2968,9 @@ static int qcom_nandc_remove(struct platform_device *pdev)
>   	{	.compatible = "qcom,qpic-nandc-v1.4.0",
>   		.data = (void *)&qpic_nandc_v1_4_0_data,
>   	},
> +	{	.compatible = "qcom,qpic-nandc-v1.5.0",
> +		.data = (void *)&qpic_nandc_v1_5_0_data,
> +	},
>   	{}
>   };
>   MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
> 

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 13/14] qcom: mtd: nand: support for QPIC version 1.5.0

[Abhishek Sahu]

On 2017-07-04 15:27, Archit Taneja wrote:
> On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
>> The current QCOM NAND driver only supports version 1.4.0
>> QCOM QPIC NAND controller. This patch adds the support for
>> version 1.5.0 which contains some of the registers at
>> different offsets. The driver data contains the register offset
>> field which is being initialized with its crossponding register
> 
> s/crossponding/corresponding
> 

  I Will fix this in v2.

>> offsets array. A new compatible string has been added for
>> version 1.5.0 in BAM mode which uses version 1.5.0 register
>> offsets.
> 
> Please split into 2 patches.
> 

  Sure. I will split it.

> Thanks,
> Archit
> 
>> 
>> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>> ---
>>   .../devicetree/bindings/mtd/qcom_nandc.txt         | 44 
>> ++++++++++++++++++
>>   drivers/mtd/nand/qcom_nandc.c                      | 54 
>> ++++++++++++++++++++--
>>   2 files changed, 95 insertions(+), 3 deletions(-)
>> 
>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt 
>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> index 87b9a56..11e2da2 100644
>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> @@ -4,6 +4,8 @@ Required properties:
>>   - compatible:		must be one of the following:
>>   	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
>>   	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA 
>> like IPQ4019.
>> +	* "qcom,qpic-nandc-v1.5.0" - QPIC NAND v1.5.0 which uses BAM DMA 
>> like IPQ8074.
>> +
>>   - reg:			MMIO address range
>>   - clocks:		must contain core clock and always on clock
>>   - clock-names:		must contain "core" for the core clock and "aon" for 
>> the
>> @@ -130,3 +132,45 @@ nand@79b0000 {
>>   		};
>>   	};
>>   };
>> +
>> +nand@79b0000 {
>> +	compatible = "qcom,qpic-nandc-v1.5.0";
>> +	reg = <0x79B0000 0x1000>;
>> +
>> +	clocks = <&gcc GCC_QPIC_CLK>,
>> +		<&gcc GCC_QPIC_AHB_CLK>;
>> +	clock-names = "core", "aon";
>> +
>> +	dmas = <&qpicbam 0>,
>> +		<&qpicbam 1>,
>> +		<&qpicbam 2>;
>> +	dma-names = "tx", "rx", "cmd";
>> +
>> +	#address-cells = <1>;
>> +	#size-cells = <0>;
>> +
>> +	nandcs@0 {
>> +		compatible = "qcom,nandcs";
>> +		reg = <0>;
>> +
>> +		nand-ecc-strength = <4>;
>> +		nand-ecc-step-size = <512>;
>> +		nand-bus-width = <8>;
>> +
>> +		partitions {
>> +			compatible = "fixed-partitions";
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +
>> +			partition@0 {
>> +				label = "boot-nand";
>> +				reg = <0 0x58a0000>;
>> +			};
>> +
>> +			partition@58a0000 {
>> +				label = "fs-nand";
>> +				reg = <0x58a0000 0x4000000>;
>> +			};
>> +		};
>> +	};
>> +};
>> diff --git a/drivers/mtd/nand/qcom_nandc.c 
>> b/drivers/mtd/nand/qcom_nandc.c
>> index 24750e6..641e85d 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -430,15 +430,18 @@ struct qcom_nand_host {
>>    * This data type corresponds to the nand driver data which will be 
>> used at
>>    * driver probe time
>>    * @ecc_modes - ecc mode for nand
>> + * @regs_offsets - contains the register offsets array pointer.
>>    * @dma_bam_enabled - whether this driver is using bam
>>    */
>>   struct qcom_nand_driver_data {
>>   	u32 ecc_modes;
>> +	const u32 *regs_offsets;
>>   	bool dma_bam_enabled;
>>   };
>> 
>>   /* Mapping table which contains the actual register offsets */
>> -static const u32 regs_offsets[] = {
>> +/* NAND controller Version 1.4.0 mapping table */
>> +static const u32 regs_offsets_v1_4_0[] = {
>>   	[NAND_FLASH_CMD] = 0x00,
>>   	[NAND_ADDR0] = 0x04,
>>   	[NAND_ADDR1] = 0x08,
>> @@ -471,6 +474,40 @@ struct qcom_nand_driver_data {
>>   	[NAND_READ_LOCATION_3] = 0xf2c,
>>   };
>> 
>> +/* NAND controller Version 1.5.0 mapping table */
>> +static const u32 regs_offsets_v1_5_0[] = {
>> +	[NAND_FLASH_CMD] = 0x00,
>> +	[NAND_ADDR0] = 0x04,
>> +	[NAND_ADDR1] = 0x08,
>> +	[NAND_FLASH_CHIP_SELECT] = 0x0c,
>> +	[NAND_EXEC_CMD] = 0x10,
>> +	[NAND_FLASH_STATUS] = 0x14,
>> +	[NAND_BUFFER_STATUS] = 0x18,
>> +	[NAND_DEV0_CFG0] = 0x20,
>> +	[NAND_DEV0_CFG1] = 0x24,
>> +	[NAND_DEV0_ECC_CFG] = 0x28,
>> +	[NAND_DEV1_ECC_CFG] = 0x2c,
>> +	[NAND_DEV1_CFG0] = 0x30,
>> +	[NAND_DEV1_CFG1] = 0x34,
>> +	[NAND_READ_ID] = 0x40,
>> +	[NAND_READ_STATUS] = 0x44,
>> +	[NAND_DEV_CMD0] = 0x70a0,
>> +	[NAND_DEV_CMD1] = 0x70a4,
>> +	[NAND_DEV_CMD2] = 0x70a8,
>> +	[NAND_DEV_CMD_VLD] = 0x70ac,
>> +	[SFLASHC_BURST_CFG] = 0xe0,
>> +	[NAND_ERASED_CW_DETECT_CFG] = 0xe8,
>> +	[NAND_ERASED_CW_DETECT_STATUS] = 0xec,
>> +	[NAND_EBI2_ECC_BUF_CFG] = 0xf0,
>> +	[FLASH_BUF_ACC] = 0x100,
>> +	[NAND_CTRL] = 0xf00,
>> +	[NAND_VERSION] = 0x4f08,
>> +	[NAND_READ_LOCATION_0] = 0xf20,
>> +	[NAND_READ_LOCATION_1] = 0xf24,
>> +	[NAND_READ_LOCATION_2] = 0xf28,
>> +	[NAND_READ_LOCATION_3] = 0xf2c,
>> +};
>> +
>>   /* Frees the BAM transaction memory */
>>   static void free_bam_transaction(struct qcom_nand_controller *nandc)
>>   {
>> @@ -2832,7 +2869,7 @@ static int qcom_nandc_probe(struct 
>> platform_device *pdev)
>> 
>>   	nandc->ecc_modes = driver_data->ecc_modes;
>>   	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
>> -	nandc->regs_offsets = regs_offsets;
>> +	nandc->regs_offsets = driver_data->regs_offsets;
>> 
>>   	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>   	nandc->base = devm_ioremap_resource(dev, res);
>> @@ -2902,16 +2939,24 @@ static int qcom_nandc_remove(struct 
>> platform_device *pdev)
>>   	return 0;
>>   }
>> 
>> -
>>   static const struct qcom_nand_driver_data ebi2_nandc_data = {
>>   	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
>>   	.dma_bam_enabled = false,
>> +	.regs_offsets = regs_offsets_v1_4_0,
>>   };
>> 
>>   static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
>>   	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
>>   	.dma_bam_enabled = true,
>> +	.regs_offsets = regs_offsets_v1_4_0,
>> +};
>> +
>> +static const struct qcom_nand_driver_data qpic_nandc_v1_5_0_data = {
>> +	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
>> +	.dma_bam_enabled = true,
>> +	.regs_offsets = regs_offsets_v1_5_0,
>>   };
>> +
>>   /*
>>    * data will hold a struct pointer containing more differences once 
>> we support
>>    * more controller variants
>> @@ -2923,6 +2968,9 @@ static int qcom_nandc_remove(struct 
>> platform_device *pdev)
>>   	{	.compatible = "qcom,qpic-nandc-v1.4.0",
>>   		.data = (void *)&qpic_nandc_v1_4_0_data,
>>   	},
>> +	{	.compatible = "qcom,qpic-nandc-v1.5.0",
>> +		.data = (void *)&qpic_nandc_v1_5_0_data,
>> +	},
>>   	{}
>>   };
>>   MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
>> 

-- 
Abhishek Sahu
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Re: [PATCH 13/14] qcom: mtd: nand: support for QPIC version 1.5.0

[Abhishek Sahu]

On 2017-07-04 15:27, Archit Taneja wrote:
> On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
>> The current QCOM NAND driver only supports version 1.4.0
>> QCOM QPIC NAND controller. This patch adds the support for
>> version 1.5.0 which contains some of the registers at
>> different offsets. The driver data contains the register offset
>> field which is being initialized with its crossponding register
> 
> s/crossponding/corresponding
> 

  I Will fix this in v2.

>> offsets array. A new compatible string has been added for
>> version 1.5.0 in BAM mode which uses version 1.5.0 register
>> offsets.
> 
> Please split into 2 patches.
> 

  Sure. I will split it.

> Thanks,
> Archit
> 
>> 
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> ---
>>   .../devicetree/bindings/mtd/qcom_nandc.txt         | 44 
>> ++++++++++++++++++
>>   drivers/mtd/nand/qcom_nandc.c                      | 54 
>> ++++++++++++++++++++--
>>   2 files changed, 95 insertions(+), 3 deletions(-)
>> 
>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt 
>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> index 87b9a56..11e2da2 100644
>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> @@ -4,6 +4,8 @@ Required properties:
>>   - compatible:		must be one of the following:
>>   	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
>>   	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA 
>> like IPQ4019.
>> +	* "qcom,qpic-nandc-v1.5.0" - QPIC NAND v1.5.0 which uses BAM DMA 
>> like IPQ8074.
>> +
>>   - reg:			MMIO address range
>>   - clocks:		must contain core clock and always on clock
>>   - clock-names:		must contain "core" for the core clock and "aon" for 
>> the
>> @@ -130,3 +132,45 @@ nand@79b0000 {
>>   		};
>>   	};
>>   };
>> +
>> +nand@79b0000 {
>> +	compatible = "qcom,qpic-nandc-v1.5.0";
>> +	reg = <0x79B0000 0x1000>;
>> +
>> +	clocks = <&gcc GCC_QPIC_CLK>,
>> +		<&gcc GCC_QPIC_AHB_CLK>;
>> +	clock-names = "core", "aon";
>> +
>> +	dmas = <&qpicbam 0>,
>> +		<&qpicbam 1>,
>> +		<&qpicbam 2>;
>> +	dma-names = "tx", "rx", "cmd";
>> +
>> +	#address-cells = <1>;
>> +	#size-cells = <0>;
>> +
>> +	nandcs@0 {
>> +		compatible = "qcom,nandcs";
>> +		reg = <0>;
>> +
>> +		nand-ecc-strength = <4>;
>> +		nand-ecc-step-size = <512>;
>> +		nand-bus-width = <8>;
>> +
>> +		partitions {
>> +			compatible = "fixed-partitions";
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +
>> +			partition@0 {
>> +				label = "boot-nand";
>> +				reg = <0 0x58a0000>;
>> +			};
>> +
>> +			partition@58a0000 {
>> +				label = "fs-nand";
>> +				reg = <0x58a0000 0x4000000>;
>> +			};
>> +		};
>> +	};
>> +};
>> diff --git a/drivers/mtd/nand/qcom_nandc.c 
>> b/drivers/mtd/nand/qcom_nandc.c
>> index 24750e6..641e85d 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -430,15 +430,18 @@ struct qcom_nand_host {
>>    * This data type corresponds to the nand driver data which will be 
>> used at
>>    * driver probe time
>>    * @ecc_modes - ecc mode for nand
>> + * @regs_offsets - contains the register offsets array pointer.
>>    * @dma_bam_enabled - whether this driver is using bam
>>    */
>>   struct qcom_nand_driver_data {
>>   	u32 ecc_modes;
>> +	const u32 *regs_offsets;
>>   	bool dma_bam_enabled;
>>   };
>> 
>>   /* Mapping table which contains the actual register offsets */
>> -static const u32 regs_offsets[] = {
>> +/* NAND controller Version 1.4.0 mapping table */
>> +static const u32 regs_offsets_v1_4_0[] = {
>>   	[NAND_FLASH_CMD] = 0x00,
>>   	[NAND_ADDR0] = 0x04,
>>   	[NAND_ADDR1] = 0x08,
>> @@ -471,6 +474,40 @@ struct qcom_nand_driver_data {
>>   	[NAND_READ_LOCATION_3] = 0xf2c,
>>   };
>> 
>> +/* NAND controller Version 1.5.0 mapping table */
>> +static const u32 regs_offsets_v1_5_0[] = {
>> +	[NAND_FLASH_CMD] = 0x00,
>> +	[NAND_ADDR0] = 0x04,
>> +	[NAND_ADDR1] = 0x08,
>> +	[NAND_FLASH_CHIP_SELECT] = 0x0c,
>> +	[NAND_EXEC_CMD] = 0x10,
>> +	[NAND_FLASH_STATUS] = 0x14,
>> +	[NAND_BUFFER_STATUS] = 0x18,
>> +	[NAND_DEV0_CFG0] = 0x20,
>> +	[NAND_DEV0_CFG1] = 0x24,
>> +	[NAND_DEV0_ECC_CFG] = 0x28,
>> +	[NAND_DEV1_ECC_CFG] = 0x2c,
>> +	[NAND_DEV1_CFG0] = 0x30,
>> +	[NAND_DEV1_CFG1] = 0x34,
>> +	[NAND_READ_ID] = 0x40,
>> +	[NAND_READ_STATUS] = 0x44,
>> +	[NAND_DEV_CMD0] = 0x70a0,
>> +	[NAND_DEV_CMD1] = 0x70a4,
>> +	[NAND_DEV_CMD2] = 0x70a8,
>> +	[NAND_DEV_CMD_VLD] = 0x70ac,
>> +	[SFLASHC_BURST_CFG] = 0xe0,
>> +	[NAND_ERASED_CW_DETECT_CFG] = 0xe8,
>> +	[NAND_ERASED_CW_DETECT_STATUS] = 0xec,
>> +	[NAND_EBI2_ECC_BUF_CFG] = 0xf0,
>> +	[FLASH_BUF_ACC] = 0x100,
>> +	[NAND_CTRL] = 0xf00,
>> +	[NAND_VERSION] = 0x4f08,
>> +	[NAND_READ_LOCATION_0] = 0xf20,
>> +	[NAND_READ_LOCATION_1] = 0xf24,
>> +	[NAND_READ_LOCATION_2] = 0xf28,
>> +	[NAND_READ_LOCATION_3] = 0xf2c,
>> +};
>> +
>>   /* Frees the BAM transaction memory */
>>   static void free_bam_transaction(struct qcom_nand_controller *nandc)
>>   {
>> @@ -2832,7 +2869,7 @@ static int qcom_nandc_probe(struct 
>> platform_device *pdev)
>> 
>>   	nandc->ecc_modes = driver_data->ecc_modes;
>>   	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
>> -	nandc->regs_offsets = regs_offsets;
>> +	nandc->regs_offsets = driver_data->regs_offsets;
>> 
>>   	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>   	nandc->base = devm_ioremap_resource(dev, res);
>> @@ -2902,16 +2939,24 @@ static int qcom_nandc_remove(struct 
>> platform_device *pdev)
>>   	return 0;
>>   }
>> 
>> -
>>   static const struct qcom_nand_driver_data ebi2_nandc_data = {
>>   	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
>>   	.dma_bam_enabled = false,
>> +	.regs_offsets = regs_offsets_v1_4_0,
>>   };
>> 
>>   static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
>>   	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
>>   	.dma_bam_enabled = true,
>> +	.regs_offsets = regs_offsets_v1_4_0,
>> +};
>> +
>> +static const struct qcom_nand_driver_data qpic_nandc_v1_5_0_data = {
>> +	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
>> +	.dma_bam_enabled = true,
>> +	.regs_offsets = regs_offsets_v1_5_0,
>>   };
>> +
>>   /*
>>    * data will hold a struct pointer containing more differences once 
>> we support
>>    * more controller variants
>> @@ -2923,6 +2968,9 @@ static int qcom_nandc_remove(struct 
>> platform_device *pdev)
>>   	{	.compatible = "qcom,qpic-nandc-v1.4.0",
>>   		.data = (void *)&qpic_nandc_v1_4_0_data,
>>   	},
>> +	{	.compatible = "qcom,qpic-nandc-v1.5.0",
>> +		.data = (void *)&qpic_nandc_v1_5_0_data,
>> +	},
>>   	{}
>>   };
>>   MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
>> 

-- 
Abhishek Sahu

[PATCH 07/14] qcom: mtd: nand: support for passing flags in transfer functions

[Abhishek Sahu]

The BAM has multiple flags to control the transfer. This patch
adds flags parameter in register and data transfer functions and
modifies all these function call with appropriate flags.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/mtd/nand/qcom_nandc.c | 114 ++++++++++++++++++++++++------------------
 1 file changed, 65 insertions(+), 49 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 7042a65..65c9059 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -170,6 +170,14 @@
 #define	ECC_BCH_4BIT	BIT(2)
 #define	ECC_BCH_8BIT	BIT(3)
 
+/* Flags used for BAM DMA desc preparation*/
+/* Don't set the EOT in current tx sgl */
+#define NAND_BAM_NO_EOT			(0x0001)
+/* Set the NWD flag in current sgl */
+#define NAND_BAM_NWD			(0x0002)
+/* Finish writing in the current sgl and start writing in another sgl */
+#define NAND_BAM_NEXT_SGL		(0x0004)
+
 #define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
 #define QPIC_PER_CW_MAX_CMD_SGL		(32)
 #define QPIC_PER_CW_MAX_DATA_SGL	(8)
@@ -712,7 +720,7 @@ static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
  * @num_regs:		number of registers to read
  */
 static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
-			int num_regs)
+			int num_regs, unsigned int flags)
 {
 	bool flow_control = false;
 	void *vaddr;
@@ -736,7 +744,7 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
  * @num_regs:		number of registers to write
  */
 static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
-			 int num_regs)
+			 int num_regs, unsigned int flags)
 {
 	bool flow_control = false;
 	struct nandc_regs *regs = nandc->regs;
@@ -748,6 +756,9 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
 	if (first == NAND_FLASH_CMD)
 		flow_control = true;
 
+	if (first == NAND_EXEC_CMD)
+		flags |= NAND_BAM_NWD;
+
 	if (first == NAND_DEV_CMD1_RESTORE)
 		first = NAND_DEV_CMD1;
 
@@ -768,7 +779,7 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
  * @size:		DMA transaction size in bytes
  */
 static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
-			 const u8 *vaddr, int size)
+			 const u8 *vaddr, int size, unsigned int flags)
 {
 	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
 }
@@ -782,7 +793,7 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
  * @size:		DMA transaction size in bytes
  */
 static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
-			  const u8 *vaddr, int size)
+			  const u8 *vaddr, int size, unsigned int flags)
 {
 	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
 }
@@ -793,14 +804,16 @@ static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
  */
 static void config_cw_read(struct qcom_nand_controller *nandc)
 {
-	write_reg_dma(nandc, NAND_FLASH_CMD, 3);
-	write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
-	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
+	write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
+	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
+	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
 
-	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
+	write_reg_dma(nandc, NAND_EXEC_CMD, 1,
+		      NAND_BAM_NWD | NAND_BAM_NEXT_SGL);
 
-	read_reg_dma(nandc, NAND_FLASH_STATUS, 2);
-	read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1);
+	read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
+	read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
+		     NAND_BAM_NEXT_SGL);
 }
 
 /*
@@ -809,19 +822,20 @@ static void config_cw_read(struct qcom_nand_controller *nandc)
  */
 static void config_cw_write_pre(struct qcom_nand_controller *nandc)
 {
-	write_reg_dma(nandc, NAND_FLASH_CMD, 3);
-	write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
-	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
+	write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
+	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
+	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
+		      NAND_BAM_NEXT_SGL);
 }
 
 static void config_cw_write_post(struct qcom_nand_controller *nandc)
 {
-	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
+	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
 
-	read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
+	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
 
-	write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
-	write_reg_dma(nandc, NAND_READ_STATUS, 1);
+	write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
+	write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
 }
 
 /*
@@ -869,8 +883,8 @@ static int nandc_param(struct qcom_nand_host *host)
 	nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
 	nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
 
-	write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1);
-	write_reg_dma(nandc, NAND_DEV_CMD1, 1);
+	write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
+	write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
 
 	nandc->buf_count = 512;
 	memset(nandc->data_buffer, 0xff, nandc->buf_count);
@@ -878,11 +892,11 @@ static int nandc_param(struct qcom_nand_host *host)
 	config_cw_read(nandc);
 
 	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
-		      nandc->buf_count);
+		      nandc->buf_count, 0);
 
 	/* restore CMD1 and VLD regs */
-	write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1);
-	write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1);
+	write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0);
+	write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL);
 
 	return 0;
 }
@@ -904,14 +918,14 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
 	nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
 	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
 
-	write_reg_dma(nandc, NAND_FLASH_CMD, 3);
-	write_reg_dma(nandc, NAND_DEV0_CFG0, 2);
-	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
+	write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
+	write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
+	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
 
-	read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
+	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
 
-	write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
-	write_reg_dma(nandc, NAND_READ_STATUS, 1);
+	write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
+	write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
 
 	return 0;
 }
@@ -931,10 +945,10 @@ static int read_id(struct qcom_nand_host *host, int column)
 	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
 	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
 
-	write_reg_dma(nandc, NAND_FLASH_CMD, 4);
-	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
+	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
+	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
 
-	read_reg_dma(nandc, NAND_READ_ID, 1);
+	read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
 
 	return 0;
 }
@@ -948,10 +962,10 @@ static int reset(struct qcom_nand_host *host)
 	nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
 	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
 
-	write_reg_dma(nandc, NAND_FLASH_CMD, 1);
-	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
+	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
+	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
 
-	read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
+	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
 
 	return 0;
 }
@@ -1344,7 +1358,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
 
 		if (data_buf)
 			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
-				      data_size);
+				      data_size, 0);
 
 		/*
 		 * when ecc is enabled, the controller doesn't read the real
@@ -1360,7 +1374,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
 				*oob_buf++ = 0xff;
 
 			read_data_dma(nandc, FLASH_BUF_ACC + data_size,
-				      oob_buf, oob_size);
+				      oob_buf, oob_size, 0);
 		}
 
 		if (data_buf)
@@ -1402,7 +1416,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
 
 	config_cw_read(nandc);
 
-	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size);
+	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
 
 	ret = submit_descs(nandc);
 	if (ret)
@@ -1470,19 +1484,19 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
 
 		config_cw_read(nandc);
 
-		read_data_dma(nandc, reg_off, data_buf, data_size1);
+		read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
 		reg_off += data_size1;
 		data_buf += data_size1;
 
-		read_data_dma(nandc, reg_off, oob_buf, oob_size1);
+		read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
 		reg_off += oob_size1;
 		oob_buf += oob_size1;
 
-		read_data_dma(nandc, reg_off, data_buf, data_size2);
+		read_data_dma(nandc, reg_off, data_buf, data_size2, 0);
 		reg_off += data_size2;
 		data_buf += data_size2;
 
-		read_data_dma(nandc, reg_off, oob_buf, oob_size2);
+		read_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
 		oob_buf += oob_size2;
 	}
 
@@ -1549,7 +1563,8 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 
 		config_cw_write_pre(nandc);
 
-		write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size);
+		write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
+			       i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);
 
 		/*
 		 * when ECC is enabled, we don't really need to write anything
@@ -1562,7 +1577,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 			oob_buf += host->bbm_size;
 
 			write_data_dma(nandc, FLASH_BUF_ACC + data_size,
-				       oob_buf, oob_size);
+				       oob_buf, oob_size, 0);
 		}
 
 		config_cw_write_post(nandc);
@@ -1618,19 +1633,19 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
 
 		config_cw_write_pre(nandc);
 
-		write_data_dma(nandc, reg_off, data_buf, data_size1);
+		write_data_dma(nandc, reg_off, data_buf, data_size1, 0);
 		reg_off += data_size1;
 		data_buf += data_size1;
 
-		write_data_dma(nandc, reg_off, oob_buf, oob_size1);
+		write_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
 		reg_off += oob_size1;
 		oob_buf += oob_size1;
 
-		write_data_dma(nandc, reg_off, data_buf, data_size2);
+		write_data_dma(nandc, reg_off, data_buf, data_size2, 0);
 		reg_off += data_size2;
 		data_buf += data_size2;
 
-		write_data_dma(nandc, reg_off, oob_buf, oob_size2);
+		write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
 		oob_buf += oob_size2;
 
 		config_cw_write_post(nandc);
@@ -1685,7 +1700,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 
 	config_cw_write_pre(nandc);
 	write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
-		       data_size + oob_size);
+		       data_size + oob_size, 0);
 	config_cw_write_post(nandc);
 
 	ret = submit_descs(nandc);
@@ -1769,7 +1784,8 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
 	update_rw_regs(host, 1, false);
 
 	config_cw_write_pre(nandc);
-	write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, host->cw_size);
+	write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
+		       host->cw_size, 0);
 	config_cw_write_post(nandc);
 
 	ret = submit_descs(nandc);
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 07/14] qcom: mtd: nand: support for passing flags in transfer functions

[Marek Vasut]

On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
> The BAM has multiple flags to control the transfer. This patch
> adds flags parameter in register and data transfer functions and
> modifies all these function call with appropriate flags.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>  drivers/mtd/nand/qcom_nandc.c | 114 ++++++++++++++++++++++++------------------
>  1 file changed, 65 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 7042a65..65c9059 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -170,6 +170,14 @@
>  #define	ECC_BCH_4BIT	BIT(2)
>  #define	ECC_BCH_8BIT	BIT(3)
>  
> +/* Flags used for BAM DMA desc preparation*/
> +/* Don't set the EOT in current tx sgl */
> +#define NAND_BAM_NO_EOT			(0x0001)

No parenthesis around constants . Also, this looks like you can use
BIT() macro.

> +/* Set the NWD flag in current sgl */
> +#define NAND_BAM_NWD			(0x0002)
> +/* Finish writing in the current sgl and start writing in another sgl */
> +#define NAND_BAM_NEXT_SGL		(0x0004)
> +
>  #define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
>  #define QPIC_PER_CW_MAX_CMD_SGL		(32)
>  #define QPIC_PER_CW_MAX_DATA_SGL	(8)
> @@ -712,7 +720,7 @@ static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
>   * @num_regs:		number of registers to read
>   */
>  static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
> -			int num_regs)
> +			int num_regs, unsigned int flags)
>  {
>  	bool flow_control = false;
>  	void *vaddr;
> @@ -736,7 +744,7 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
>   * @num_regs:		number of registers to write
>   */
>  static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
> -			 int num_regs)
> +			 int num_regs, unsigned int flags)
>  {
>  	bool flow_control = false;
>  	struct nandc_regs *regs = nandc->regs;
> @@ -748,6 +756,9 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>  	if (first == NAND_FLASH_CMD)
>  		flow_control = true;
>  
> +	if (first == NAND_EXEC_CMD)
> +		flags |= NAND_BAM_NWD;
> +
>  	if (first == NAND_DEV_CMD1_RESTORE)
>  		first = NAND_DEV_CMD1;
>  
> @@ -768,7 +779,7 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>   * @size:		DMA transaction size in bytes
>   */
>  static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> -			 const u8 *vaddr, int size)
> +			 const u8 *vaddr, int size, unsigned int flags)
>  {
>  	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
>  }
> @@ -782,7 +793,7 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>   * @size:		DMA transaction size in bytes
>   */
>  static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> -			  const u8 *vaddr, int size)
> +			  const u8 *vaddr, int size, unsigned int flags)
>  {
>  	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
>  }
> @@ -793,14 +804,16 @@ static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>   */
>  static void config_cw_read(struct qcom_nand_controller *nandc)
>  {
> -	write_reg_dma(nandc, NAND_FLASH_CMD, 3);
> -	write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
> -	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
> +	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> +	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>  
> -	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1,
> +		      NAND_BAM_NWD | NAND_BAM_NEXT_SGL);
>  
> -	read_reg_dma(nandc, NAND_FLASH_STATUS, 2);
> -	read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1);
> +	read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
> +	read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
> +		     NAND_BAM_NEXT_SGL);
>  }
>  
>  /*
> @@ -809,19 +822,20 @@ static void config_cw_read(struct qcom_nand_controller *nandc)
>   */
>  static void config_cw_write_pre(struct qcom_nand_controller *nandc)
>  {
> -	write_reg_dma(nandc, NAND_FLASH_CMD, 3);
> -	write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
> -	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
> +	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> +	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
> +		      NAND_BAM_NEXT_SGL);
>  }
>  
>  static void config_cw_write_post(struct qcom_nand_controller *nandc)
>  {
> -	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>  
> -	read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> +	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
>  
> -	write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> -	write_reg_dma(nandc, NAND_READ_STATUS, 1);
> +	write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
> +	write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
>  }
>  
>  /*
> @@ -869,8 +883,8 @@ static int nandc_param(struct qcom_nand_host *host)
>  	nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
>  	nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
>  
> -	write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1);
> -	write_reg_dma(nandc, NAND_DEV_CMD1, 1);
> +	write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
> +	write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
>  
>  	nandc->buf_count = 512;
>  	memset(nandc->data_buffer, 0xff, nandc->buf_count);
> @@ -878,11 +892,11 @@ static int nandc_param(struct qcom_nand_host *host)
>  	config_cw_read(nandc);
>  
>  	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
> -		      nandc->buf_count);
> +		      nandc->buf_count, 0);
>  
>  	/* restore CMD1 and VLD regs */
> -	write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1);
> -	write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1);
> +	write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0);
> +	write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL);
>  
>  	return 0;
>  }
> @@ -904,14 +918,14 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
>  	nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
>  	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
>  
> -	write_reg_dma(nandc, NAND_FLASH_CMD, 3);
> -	write_reg_dma(nandc, NAND_DEV0_CFG0, 2);
> -	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
> +	write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>  
> -	read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> +	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
>  
> -	write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> -	write_reg_dma(nandc, NAND_READ_STATUS, 1);
> +	write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
> +	write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
>  
>  	return 0;
>  }
> @@ -931,10 +945,10 @@ static int read_id(struct qcom_nand_host *host, int column)
>  	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
>  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>  
> -	write_reg_dma(nandc, NAND_FLASH_CMD, 4);
> -	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>  
> -	read_reg_dma(nandc, NAND_READ_ID, 1);
> +	read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
>  
>  	return 0;
>  }
> @@ -948,10 +962,10 @@ static int reset(struct qcom_nand_host *host)
>  	nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
>  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>  
> -	write_reg_dma(nandc, NAND_FLASH_CMD, 1);
> -	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>  
> -	read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> +	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
>  
>  	return 0;
>  }
> @@ -1344,7 +1358,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
>  
>  		if (data_buf)
>  			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
> -				      data_size);
> +				      data_size, 0);
>  
>  		/*
>  		 * when ecc is enabled, the controller doesn't read the real
> @@ -1360,7 +1374,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
>  				*oob_buf++ = 0xff;
>  
>  			read_data_dma(nandc, FLASH_BUF_ACC + data_size,
> -				      oob_buf, oob_size);
> +				      oob_buf, oob_size, 0);
>  		}
>  
>  		if (data_buf)
> @@ -1402,7 +1416,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
>  
>  	config_cw_read(nandc);
>  
> -	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size);
> +	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
>  
>  	ret = submit_descs(nandc);
>  	if (ret)
> @@ -1470,19 +1484,19 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
>  
>  		config_cw_read(nandc);
>  
> -		read_data_dma(nandc, reg_off, data_buf, data_size1);
> +		read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
>  		reg_off += data_size1;
>  		data_buf += data_size1;
>  
> -		read_data_dma(nandc, reg_off, oob_buf, oob_size1);
> +		read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
>  		reg_off += oob_size1;
>  		oob_buf += oob_size1;
>  
> -		read_data_dma(nandc, reg_off, data_buf, data_size2);
> +		read_data_dma(nandc, reg_off, data_buf, data_size2, 0);
>  		reg_off += data_size2;
>  		data_buf += data_size2;
>  
> -		read_data_dma(nandc, reg_off, oob_buf, oob_size2);
> +		read_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
>  		oob_buf += oob_size2;
>  	}
>  
> @@ -1549,7 +1563,8 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>  
>  		config_cw_write_pre(nandc);
>  
> -		write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size);
> +		write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
> +			       i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);
>  
>  		/*
>  		 * when ECC is enabled, we don't really need to write anything
> @@ -1562,7 +1577,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>  			oob_buf += host->bbm_size;
>  
>  			write_data_dma(nandc, FLASH_BUF_ACC + data_size,
> -				       oob_buf, oob_size);
> +				       oob_buf, oob_size, 0);
>  		}
>  
>  		config_cw_write_post(nandc);
> @@ -1618,19 +1633,19 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
>  
>  		config_cw_write_pre(nandc);
>  
> -		write_data_dma(nandc, reg_off, data_buf, data_size1);
> +		write_data_dma(nandc, reg_off, data_buf, data_size1, 0);
>  		reg_off += data_size1;
>  		data_buf += data_size1;
>  
> -		write_data_dma(nandc, reg_off, oob_buf, oob_size1);
> +		write_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
>  		reg_off += oob_size1;
>  		oob_buf += oob_size1;
>  
> -		write_data_dma(nandc, reg_off, data_buf, data_size2);
> +		write_data_dma(nandc, reg_off, data_buf, data_size2, 0);
>  		reg_off += data_size2;
>  		data_buf += data_size2;
>  
> -		write_data_dma(nandc, reg_off, oob_buf, oob_size2);
> +		write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
>  		oob_buf += oob_size2;
>  
>  		config_cw_write_post(nandc);
> @@ -1685,7 +1700,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
>  
>  	config_cw_write_pre(nandc);
>  	write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
> -		       data_size + oob_size);
> +		       data_size + oob_size, 0);
>  	config_cw_write_post(nandc);
>  
>  	ret = submit_descs(nandc);
> @@ -1769,7 +1784,8 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
>  	update_rw_regs(host, 1, false);
>  
>  	config_cw_write_pre(nandc);
> -	write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, host->cw_size);
> +	write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
> +		       host->cw_size, 0);
>  	config_cw_write_post(nandc);
>  
>  	ret = submit_descs(nandc);
> 


-- 
Best regards,
Marek Vasut

Re: [PATCH 07/14] qcom: mtd: nand: support for passing flags in transfer functions

[Archit Taneja]

On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
> The BAM has multiple flags to control the transfer. This patch
> adds flags parameter in register and data transfer functions and
> modifies all these function call with appropriate flags.
> 
> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>   drivers/mtd/nand/qcom_nandc.c | 114 ++++++++++++++++++++++++------------------
>   1 file changed, 65 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 7042a65..65c9059 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -170,6 +170,14 @@
>   #define	ECC_BCH_4BIT	BIT(2)
>   #define	ECC_BCH_8BIT	BIT(3)
>   
> +/* Flags used for BAM DMA desc preparation*/
> +/* Don't set the EOT in current tx sgl */
> +#define NAND_BAM_NO_EOT			(0x0001)
> +/* Set the NWD flag in current sgl */
> +#define NAND_BAM_NWD			(0x0002)
> +/* Finish writing in the current sgl and start writing in another sgl */
> +#define NAND_BAM_NEXT_SGL		(0x0004)
> +
>   #define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
>   #define QPIC_PER_CW_MAX_CMD_SGL		(32)
>   #define QPIC_PER_CW_MAX_DATA_SGL	(8)
> @@ -712,7 +720,7 @@ static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
>    * @num_regs:		number of registers to read
>    */
>   static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
> -			int num_regs)
> +			int num_regs, unsigned int flags)
>   {
>   	bool flow_control = false;
>   	void *vaddr;
> @@ -736,7 +744,7 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
>    * @num_regs:		number of registers to write
>    */
>   static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
> -			 int num_regs)
> +			 int num_regs, unsigned int flags)

Adding flags to read_reg_dma and write_reg_dma is making things a bit messy. I can't
think of a better way to share the code either, though.

One thing we could consider doing is something like below. I don't know if it would
make things more legible.

union nand_dma_props {
	bool adm_flow_control;
	unsigned int bam_flags;
};

config_cw_read()
{
	union nand_dma_props dma_props;
	...
	...

	if (is_bam)
		dma_props.bam_flags = NAND_BAM_NWD;
	else
		dma_props.adm_flow_control = false;

	write_reg_dma(nandc, NAND_EXEC_CMD, 1, &dma_props);
	...
	...
}

Thanks,
Archit

>   {
>   	bool flow_control = false;
>   	struct nandc_regs *regs = nandc->regs;
> @@ -748,6 +756,9 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>   	if (first == NAND_FLASH_CMD)
>   		flow_control = true;
>   
> +	if (first == NAND_EXEC_CMD)
> +		flags |= NAND_BAM_NWD;
> +
>   	if (first == NAND_DEV_CMD1_RESTORE)
>   		first = NAND_DEV_CMD1;
>   
> @@ -768,7 +779,7 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>    * @size:		DMA transaction size in bytes
>    */
>   static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> -			 const u8 *vaddr, int size)
> +			 const u8 *vaddr, int size, unsigned int flags)
>   {
>   	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
>   }
> @@ -782,7 +793,7 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>    * @size:		DMA transaction size in bytes
>    */
>   static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> -			  const u8 *vaddr, int size)
> +			  const u8 *vaddr, int size, unsigned int flags)
>   {
>   	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
>   }
> @@ -793,14 +804,16 @@ static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>    */
>   static void config_cw_read(struct qcom_nand_controller *nandc)
>   {
> -	write_reg_dma(nandc, NAND_FLASH_CMD, 3);
> -	write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
> -	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
> +	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> +	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>   
> -	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1,
> +		      NAND_BAM_NWD | NAND_BAM_NEXT_SGL);
>   
> -	read_reg_dma(nandc, NAND_FLASH_STATUS, 2);
> -	read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1);
> +	read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
> +	read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
> +		     NAND_BAM_NEXT_SGL);
>   }
>   
>   /*
> @@ -809,19 +822,20 @@ static void config_cw_read(struct qcom_nand_controller *nandc)
>    */
>   static void config_cw_write_pre(struct qcom_nand_controller *nandc)
>   {
> -	write_reg_dma(nandc, NAND_FLASH_CMD, 3);
> -	write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
> -	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
> +	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> +	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
> +		      NAND_BAM_NEXT_SGL);
>   }
>   
>   static void config_cw_write_post(struct qcom_nand_controller *nandc)
>   {
> -	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>   
> -	read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> +	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
>   
> -	write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> -	write_reg_dma(nandc, NAND_READ_STATUS, 1);
> +	write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
> +	write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
>   }
>   
>   /*
> @@ -869,8 +883,8 @@ static int nandc_param(struct qcom_nand_host *host)
>   	nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
>   	nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
>   
> -	write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1);
> -	write_reg_dma(nandc, NAND_DEV_CMD1, 1);
> +	write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
> +	write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
>   
>   	nandc->buf_count = 512;
>   	memset(nandc->data_buffer, 0xff, nandc->buf_count);
> @@ -878,11 +892,11 @@ static int nandc_param(struct qcom_nand_host *host)
>   	config_cw_read(nandc);
>   
>   	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
> -		      nandc->buf_count);
> +		      nandc->buf_count, 0);
>   
>   	/* restore CMD1 and VLD regs */
> -	write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1);
> -	write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1);
> +	write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0);
> +	write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL);
>   
>   	return 0;
>   }
> @@ -904,14 +918,14 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
>   	nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
>   	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
>   
> -	write_reg_dma(nandc, NAND_FLASH_CMD, 3);
> -	write_reg_dma(nandc, NAND_DEV0_CFG0, 2);
> -	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
> +	write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>   
> -	read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> +	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
>   
> -	write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> -	write_reg_dma(nandc, NAND_READ_STATUS, 1);
> +	write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
> +	write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
>   
>   	return 0;
>   }
> @@ -931,10 +945,10 @@ static int read_id(struct qcom_nand_host *host, int column)
>   	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>   
> -	write_reg_dma(nandc, NAND_FLASH_CMD, 4);
> -	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>   
> -	read_reg_dma(nandc, NAND_READ_ID, 1);
> +	read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
>   
>   	return 0;
>   }
> @@ -948,10 +962,10 @@ static int reset(struct qcom_nand_host *host)
>   	nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>   
> -	write_reg_dma(nandc, NAND_FLASH_CMD, 1);
> -	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>   
> -	read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> +	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
>   
>   	return 0;
>   }
> @@ -1344,7 +1358,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
>   
>   		if (data_buf)
>   			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
> -				      data_size);
> +				      data_size, 0);
>   
>   		/*
>   		 * when ecc is enabled, the controller doesn't read the real
> @@ -1360,7 +1374,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
>   				*oob_buf++ = 0xff;
>   
>   			read_data_dma(nandc, FLASH_BUF_ACC + data_size,
> -				      oob_buf, oob_size);
> +				      oob_buf, oob_size, 0);
>   		}
>   
>   		if (data_buf)
> @@ -1402,7 +1416,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
>   
>   	config_cw_read(nandc);
>   
> -	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size);
> +	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
>   
>   	ret = submit_descs(nandc);
>   	if (ret)
> @@ -1470,19 +1484,19 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
>   
>   		config_cw_read(nandc);
>   
> -		read_data_dma(nandc, reg_off, data_buf, data_size1);
> +		read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
>   		reg_off += data_size1;
>   		data_buf += data_size1;
>   
> -		read_data_dma(nandc, reg_off, oob_buf, oob_size1);
> +		read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
>   		reg_off += oob_size1;
>   		oob_buf += oob_size1;
>   
> -		read_data_dma(nandc, reg_off, data_buf, data_size2);
> +		read_data_dma(nandc, reg_off, data_buf, data_size2, 0);
>   		reg_off += data_size2;
>   		data_buf += data_size2;
>   
> -		read_data_dma(nandc, reg_off, oob_buf, oob_size2);
> +		read_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
>   		oob_buf += oob_size2;
>   	}
>   
> @@ -1549,7 +1563,8 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>   
>   		config_cw_write_pre(nandc);
>   
> -		write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size);
> +		write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
> +			       i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);
>   
>   		/*
>   		 * when ECC is enabled, we don't really need to write anything
> @@ -1562,7 +1577,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>   			oob_buf += host->bbm_size;
>   
>   			write_data_dma(nandc, FLASH_BUF_ACC + data_size,
> -				       oob_buf, oob_size);
> +				       oob_buf, oob_size, 0);
>   		}
>   
>   		config_cw_write_post(nandc);
> @@ -1618,19 +1633,19 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
>   
>   		config_cw_write_pre(nandc);
>   
> -		write_data_dma(nandc, reg_off, data_buf, data_size1);
> +		write_data_dma(nandc, reg_off, data_buf, data_size1, 0);
>   		reg_off += data_size1;
>   		data_buf += data_size1;
>   
> -		write_data_dma(nandc, reg_off, oob_buf, oob_size1);
> +		write_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
>   		reg_off += oob_size1;
>   		oob_buf += oob_size1;
>   
> -		write_data_dma(nandc, reg_off, data_buf, data_size2);
> +		write_data_dma(nandc, reg_off, data_buf, data_size2, 0);
>   		reg_off += data_size2;
>   		data_buf += data_size2;
>   
> -		write_data_dma(nandc, reg_off, oob_buf, oob_size2);
> +		write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
>   		oob_buf += oob_size2;
>   
>   		config_cw_write_post(nandc);
> @@ -1685,7 +1700,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
>   
>   	config_cw_write_pre(nandc);
>   	write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
> -		       data_size + oob_size);
> +		       data_size + oob_size, 0);
>   	config_cw_write_post(nandc);
>   
>   	ret = submit_descs(nandc);
> @@ -1769,7 +1784,8 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
>   	update_rw_regs(host, 1, false);
>   
>   	config_cw_write_pre(nandc);
> -	write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, host->cw_size);
> +	write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
> +		       host->cw_size, 0);
>   	config_cw_write_post(nandc);
>   
>   	ret = submit_descs(nandc);
> 

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Re: [PATCH 07/14] qcom: mtd: nand: support for passing flags in transfer functions

[Archit Taneja]

On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
> The BAM has multiple flags to control the transfer. This patch
> adds flags parameter in register and data transfer functions and
> modifies all these function call with appropriate flags.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>   drivers/mtd/nand/qcom_nandc.c | 114 ++++++++++++++++++++++++------------------
>   1 file changed, 65 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 7042a65..65c9059 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -170,6 +170,14 @@
>   #define	ECC_BCH_4BIT	BIT(2)
>   #define	ECC_BCH_8BIT	BIT(3)
>   
> +/* Flags used for BAM DMA desc preparation*/
> +/* Don't set the EOT in current tx sgl */
> +#define NAND_BAM_NO_EOT			(0x0001)
> +/* Set the NWD flag in current sgl */
> +#define NAND_BAM_NWD			(0x0002)
> +/* Finish writing in the current sgl and start writing in another sgl */
> +#define NAND_BAM_NEXT_SGL		(0x0004)
> +
>   #define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
>   #define QPIC_PER_CW_MAX_CMD_SGL		(32)
>   #define QPIC_PER_CW_MAX_DATA_SGL	(8)
> @@ -712,7 +720,7 @@ static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
>    * @num_regs:		number of registers to read
>    */
>   static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
> -			int num_regs)
> +			int num_regs, unsigned int flags)
>   {
>   	bool flow_control = false;
>   	void *vaddr;
> @@ -736,7 +744,7 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
>    * @num_regs:		number of registers to write
>    */
>   static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
> -			 int num_regs)
> +			 int num_regs, unsigned int flags)

Adding flags to read_reg_dma and write_reg_dma is making things a bit messy. I can't
think of a better way to share the code either, though.

One thing we could consider doing is something like below. I don't know if it would
make things more legible.

union nand_dma_props {
	bool adm_flow_control;
	unsigned int bam_flags;
};

config_cw_read()
{
	union nand_dma_props dma_props;
	...
	...

	if (is_bam)
		dma_props.bam_flags = NAND_BAM_NWD;
	else
		dma_props.adm_flow_control = false;

	write_reg_dma(nandc, NAND_EXEC_CMD, 1, &dma_props);
	...
	...
}

Thanks,
Archit

>   {
>   	bool flow_control = false;
>   	struct nandc_regs *regs = nandc->regs;
> @@ -748,6 +756,9 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>   	if (first == NAND_FLASH_CMD)
>   		flow_control = true;
>   
> +	if (first == NAND_EXEC_CMD)
> +		flags |= NAND_BAM_NWD;
> +
>   	if (first == NAND_DEV_CMD1_RESTORE)
>   		first = NAND_DEV_CMD1;
>   
> @@ -768,7 +779,7 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>    * @size:		DMA transaction size in bytes
>    */
>   static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> -			 const u8 *vaddr, int size)
> +			 const u8 *vaddr, int size, unsigned int flags)
>   {
>   	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
>   }
> @@ -782,7 +793,7 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>    * @size:		DMA transaction size in bytes
>    */
>   static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> -			  const u8 *vaddr, int size)
> +			  const u8 *vaddr, int size, unsigned int flags)
>   {
>   	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
>   }
> @@ -793,14 +804,16 @@ static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>    */
>   static void config_cw_read(struct qcom_nand_controller *nandc)
>   {
> -	write_reg_dma(nandc, NAND_FLASH_CMD, 3);
> -	write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
> -	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
> +	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> +	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>   
> -	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1,
> +		      NAND_BAM_NWD | NAND_BAM_NEXT_SGL);
>   
> -	read_reg_dma(nandc, NAND_FLASH_STATUS, 2);
> -	read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1);
> +	read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
> +	read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
> +		     NAND_BAM_NEXT_SGL);
>   }
>   
>   /*
> @@ -809,19 +822,20 @@ static void config_cw_read(struct qcom_nand_controller *nandc)
>    */
>   static void config_cw_write_pre(struct qcom_nand_controller *nandc)
>   {
> -	write_reg_dma(nandc, NAND_FLASH_CMD, 3);
> -	write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
> -	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
> +	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> +	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
> +		      NAND_BAM_NEXT_SGL);
>   }
>   
>   static void config_cw_write_post(struct qcom_nand_controller *nandc)
>   {
> -	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>   
> -	read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> +	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
>   
> -	write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> -	write_reg_dma(nandc, NAND_READ_STATUS, 1);
> +	write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
> +	write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
>   }
>   
>   /*
> @@ -869,8 +883,8 @@ static int nandc_param(struct qcom_nand_host *host)
>   	nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
>   	nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
>   
> -	write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1);
> -	write_reg_dma(nandc, NAND_DEV_CMD1, 1);
> +	write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
> +	write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
>   
>   	nandc->buf_count = 512;
>   	memset(nandc->data_buffer, 0xff, nandc->buf_count);
> @@ -878,11 +892,11 @@ static int nandc_param(struct qcom_nand_host *host)
>   	config_cw_read(nandc);
>   
>   	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
> -		      nandc->buf_count);
> +		      nandc->buf_count, 0);
>   
>   	/* restore CMD1 and VLD regs */
> -	write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1);
> -	write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1);
> +	write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0);
> +	write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL);
>   
>   	return 0;
>   }
> @@ -904,14 +918,14 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
>   	nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
>   	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
>   
> -	write_reg_dma(nandc, NAND_FLASH_CMD, 3);
> -	write_reg_dma(nandc, NAND_DEV0_CFG0, 2);
> -	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
> +	write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>   
> -	read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> +	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
>   
> -	write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> -	write_reg_dma(nandc, NAND_READ_STATUS, 1);
> +	write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
> +	write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
>   
>   	return 0;
>   }
> @@ -931,10 +945,10 @@ static int read_id(struct qcom_nand_host *host, int column)
>   	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>   
> -	write_reg_dma(nandc, NAND_FLASH_CMD, 4);
> -	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>   
> -	read_reg_dma(nandc, NAND_READ_ID, 1);
> +	read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
>   
>   	return 0;
>   }
> @@ -948,10 +962,10 @@ static int reset(struct qcom_nand_host *host)
>   	nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>   
> -	write_reg_dma(nandc, NAND_FLASH_CMD, 1);
> -	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
> +	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
> +	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>   
> -	read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
> +	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
>   
>   	return 0;
>   }
> @@ -1344,7 +1358,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
>   
>   		if (data_buf)
>   			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
> -				      data_size);
> +				      data_size, 0);
>   
>   		/*
>   		 * when ecc is enabled, the controller doesn't read the real
> @@ -1360,7 +1374,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
>   				*oob_buf++ = 0xff;
>   
>   			read_data_dma(nandc, FLASH_BUF_ACC + data_size,
> -				      oob_buf, oob_size);
> +				      oob_buf, oob_size, 0);
>   		}
>   
>   		if (data_buf)
> @@ -1402,7 +1416,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
>   
>   	config_cw_read(nandc);
>   
> -	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size);
> +	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
>   
>   	ret = submit_descs(nandc);
>   	if (ret)
> @@ -1470,19 +1484,19 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
>   
>   		config_cw_read(nandc);
>   
> -		read_data_dma(nandc, reg_off, data_buf, data_size1);
> +		read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
>   		reg_off += data_size1;
>   		data_buf += data_size1;
>   
> -		read_data_dma(nandc, reg_off, oob_buf, oob_size1);
> +		read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
>   		reg_off += oob_size1;
>   		oob_buf += oob_size1;
>   
> -		read_data_dma(nandc, reg_off, data_buf, data_size2);
> +		read_data_dma(nandc, reg_off, data_buf, data_size2, 0);
>   		reg_off += data_size2;
>   		data_buf += data_size2;
>   
> -		read_data_dma(nandc, reg_off, oob_buf, oob_size2);
> +		read_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
>   		oob_buf += oob_size2;
>   	}
>   
> @@ -1549,7 +1563,8 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>   
>   		config_cw_write_pre(nandc);
>   
> -		write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size);
> +		write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
> +			       i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);
>   
>   		/*
>   		 * when ECC is enabled, we don't really need to write anything
> @@ -1562,7 +1577,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>   			oob_buf += host->bbm_size;
>   
>   			write_data_dma(nandc, FLASH_BUF_ACC + data_size,
> -				       oob_buf, oob_size);
> +				       oob_buf, oob_size, 0);
>   		}
>   
>   		config_cw_write_post(nandc);
> @@ -1618,19 +1633,19 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
>   
>   		config_cw_write_pre(nandc);
>   
> -		write_data_dma(nandc, reg_off, data_buf, data_size1);
> +		write_data_dma(nandc, reg_off, data_buf, data_size1, 0);
>   		reg_off += data_size1;
>   		data_buf += data_size1;
>   
> -		write_data_dma(nandc, reg_off, oob_buf, oob_size1);
> +		write_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
>   		reg_off += oob_size1;
>   		oob_buf += oob_size1;
>   
> -		write_data_dma(nandc, reg_off, data_buf, data_size2);
> +		write_data_dma(nandc, reg_off, data_buf, data_size2, 0);
>   		reg_off += data_size2;
>   		data_buf += data_size2;
>   
> -		write_data_dma(nandc, reg_off, oob_buf, oob_size2);
> +		write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
>   		oob_buf += oob_size2;
>   
>   		config_cw_write_post(nandc);
> @@ -1685,7 +1700,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
>   
>   	config_cw_write_pre(nandc);
>   	write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
> -		       data_size + oob_size);
> +		       data_size + oob_size, 0);
>   	config_cw_write_post(nandc);
>   
>   	ret = submit_descs(nandc);
> @@ -1769,7 +1784,8 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
>   	update_rw_regs(host, 1, false);
>   
>   	config_cw_write_pre(nandc);
> -	write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, host->cw_size);
> +	write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
> +		       host->cw_size, 0);
>   	config_cw_write_post(nandc);
>   
>   	ret = submit_descs(nandc);
> 

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a Linux Foundation Collaborative Project

Re: [PATCH 07/14] qcom: mtd: nand: support for passing flags in transfer functions

[Sricharan R]

Hi,

On 7/4/2017 12:19 PM, Archit Taneja wrote:
> 
> 
> On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
>> The BAM has multiple flags to control the transfer. This patch
>> adds flags parameter in register and data transfer functions and
>> modifies all these function call with appropriate flags.
>>
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> ---
>>   drivers/mtd/nand/qcom_nandc.c | 114 ++++++++++++++++++++++++------------------
>>   1 file changed, 65 insertions(+), 49 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
>> index 7042a65..65c9059 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -170,6 +170,14 @@
>>   #define    ECC_BCH_4BIT    BIT(2)
>>   #define    ECC_BCH_8BIT    BIT(3)
>>   +/* Flags used for BAM DMA desc preparation*/
>> +/* Don't set the EOT in current tx sgl */
>> +#define NAND_BAM_NO_EOT            (0x0001)
>> +/* Set the NWD flag in current sgl */
>> +#define NAND_BAM_NWD            (0x0002)
>> +/* Finish writing in the current sgl and start writing in another sgl */
>> +#define NAND_BAM_NEXT_SGL        (0x0004)
>> +
>>   #define QPIC_PER_CW_MAX_CMD_ELEMENTS    (32)
>>   #define QPIC_PER_CW_MAX_CMD_SGL        (32)
>>   #define QPIC_PER_CW_MAX_DATA_SGL    (8)
>> @@ -712,7 +720,7 @@ static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
>>    * @num_regs:        number of registers to read
>>    */
>>   static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
>> -            int num_regs)
>> +            int num_regs, unsigned int flags)
>>   {
>>       bool flow_control = false;
>>       void *vaddr;
>> @@ -736,7 +744,7 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
>>    * @num_regs:        number of registers to write
>>    */
>>   static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>> -             int num_regs)
>> +             int num_regs, unsigned int flags)
> 
> Adding flags to read_reg_dma and write_reg_dma is making things a bit messy. I can't
> think of a better way to share the code either, though.
> 
> One thing we could consider doing is something like below. I don't know if it would
> make things more legible.
> 
> union nand_dma_props {
>     bool adm_flow_control;
>     unsigned int bam_flags;
> };
> 
> config_cw_read()
> {
>     union nand_dma_props dma_props;
>     ...
>     ...
> 
>     if (is_bam)
>         dma_props.bam_flags = NAND_BAM_NWD;
>     else
>         dma_props.adm_flow_control = false;
> 
>     write_reg_dma(nandc, NAND_EXEC_CMD, 1, &dma_props);
>     ...
>     ...
> }

 Right, with this , i think we can have two different indirections for functions like,
 prep_dma_desc_command and prep_dma_desc. That will help to reduce the bam_dma_enabled
 checks.

Regards,
 Sricharan

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Re: [PATCH 07/14] qcom: mtd: nand: support for passing flags in transfer functions

[Abhishek Sahu]

On 2017-07-10 19:40, Sricharan R wrote:
> Hi,
> 
> On 7/4/2017 12:19 PM, Archit Taneja wrote:
>> 
>> 
>> On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
>>> The BAM has multiple flags to control the transfer. This patch
>>> adds flags parameter in register and data transfer functions and
>>> modifies all these function call with appropriate flags.
>>> 
>>> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>>> ---
>>>   drivers/mtd/nand/qcom_nandc.c | 114
>>> ++++++++++++++++++++++++------------------
>>>   1 file changed, 65 insertions(+), 49 deletions(-)
>>> 
>>> diff --git a/drivers/mtd/nand/qcom_nandc.c
>>> b/drivers/mtd/nand/qcom_nandc.c
>>> index 7042a65..65c9059 100644
>>> --- a/drivers/mtd/nand/qcom_nandc.c
>>> +++ b/drivers/mtd/nand/qcom_nandc.c
>>> @@ -170,6 +170,14 @@
>>>   #define    ECC_BCH_4BIT    BIT(2)
>>>   #define    ECC_BCH_8BIT    BIT(3)
>>>   +/* Flags used for BAM DMA desc preparation*/
>>> +/* Don't set the EOT in current tx sgl */
>>> +#define NAND_BAM_NO_EOT            (0x0001)
>>> +/* Set the NWD flag in current sgl */
>>> +#define NAND_BAM_NWD            (0x0002)
>>> +/* Finish writing in the current sgl and start writing in another 
>>> sgl */
>>> +#define NAND_BAM_NEXT_SGL        (0x0004)
>>> +
>>>   #define QPIC_PER_CW_MAX_CMD_ELEMENTS    (32)
>>>   #define QPIC_PER_CW_MAX_CMD_SGL        (32)
>>>   #define QPIC_PER_CW_MAX_DATA_SGL    (8)

  I will remove the braces and use the bit macros.

>>> @@ -712,7 +720,7 @@ static int prep_dma_desc(struct 
>>> qcom_nand_controller
>>> *nandc, bool read,
>>>    * @num_regs:        number of registers to read
>>>    */
>>>   static int read_reg_dma(struct qcom_nand_controller *nandc, int 
>>> first,
>>> -            int num_regs)
>>> +            int num_regs, unsigned int flags)
>>>   {
>>>       bool flow_control = false;
>>>       void *vaddr;
>>> @@ -736,7 +744,7 @@ static int read_reg_dma(struct 
>>> qcom_nand_controller
>>> *nandc, int first,
>>>    * @num_regs:        number of registers to write
>>>    */
>>>   static int write_reg_dma(struct qcom_nand_controller *nandc, int 
>>> first,
>>> -             int num_regs)
>>> +             int num_regs, unsigned int flags)
>> 
>> Adding flags to read_reg_dma and write_reg_dma is making things a bit
>> messy. I can't
>> think of a better way to share the code either, though.
>> 
>> One thing we could consider doing is something like below. I don't 
>> know if
>> it would
>> make things more legible.
>> 
>> union nand_dma_props {
>>     bool adm_flow_control;
>>     unsigned int bam_flags;
>> };
>> 
>> config_cw_read()
>> {
>>     union nand_dma_props dma_props;
>>     ...
>>     ...
>> 
>>     if (is_bam)
>>         dma_props.bam_flags = NAND_BAM_NWD;
>>     else
>>         dma_props.adm_flow_control = false;
>> 
>>     write_reg_dma(nandc, NAND_EXEC_CMD, 1, &dma_props);
>>     ...
>>     ...
>> }

  The flags for each write_reg_dma and read_reg_dma will be different.
  Normally, for all the API's which uses flags
  (like dmaengine_prep_slave_sg), we are passing the flags directly.
  this union won't help us making this code more readable.

> 
>  Right, with this , i think we can have two different indirections for
> functions like,
>  prep_dma_desc_command and prep_dma_desc. That will help to reduce the
> bam_dma_enabled
>  checks.

  Since common code changes are intermixed with bam_dma_enabled check
  so taking function pointer won't help much in making code more 
readable.

  anyway, I will analyze the final code for v2 and will check the
  possibility of using function pointers.

> 
> Regards,
>  Sricharan

-- 
Abhishek Sahu
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Re: [PATCH 07/14] qcom: mtd: nand: support for passing flags in transfer functions

[Abhishek Sahu]

On 2017-07-10 19:40, Sricharan R wrote:
> Hi,
> 
> On 7/4/2017 12:19 PM, Archit Taneja wrote:
>> 
>> 
>> On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
>>> The BAM has multiple flags to control the transfer. This patch
>>> adds flags parameter in register and data transfer functions and
>>> modifies all these function call with appropriate flags.
>>> 
>>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>>> ---
>>>   drivers/mtd/nand/qcom_nandc.c | 114
>>> ++++++++++++++++++++++++------------------
>>>   1 file changed, 65 insertions(+), 49 deletions(-)
>>> 
>>> diff --git a/drivers/mtd/nand/qcom_nandc.c
>>> b/drivers/mtd/nand/qcom_nandc.c
>>> index 7042a65..65c9059 100644
>>> --- a/drivers/mtd/nand/qcom_nandc.c
>>> +++ b/drivers/mtd/nand/qcom_nandc.c
>>> @@ -170,6 +170,14 @@
>>>   #define    ECC_BCH_4BIT    BIT(2)
>>>   #define    ECC_BCH_8BIT    BIT(3)
>>>   +/* Flags used for BAM DMA desc preparation*/
>>> +/* Don't set the EOT in current tx sgl */
>>> +#define NAND_BAM_NO_EOT            (0x0001)
>>> +/* Set the NWD flag in current sgl */
>>> +#define NAND_BAM_NWD            (0x0002)
>>> +/* Finish writing in the current sgl and start writing in another 
>>> sgl */
>>> +#define NAND_BAM_NEXT_SGL        (0x0004)
>>> +
>>>   #define QPIC_PER_CW_MAX_CMD_ELEMENTS    (32)
>>>   #define QPIC_PER_CW_MAX_CMD_SGL        (32)
>>>   #define QPIC_PER_CW_MAX_DATA_SGL    (8)

  I will remove the braces and use the bit macros.

>>> @@ -712,7 +720,7 @@ static int prep_dma_desc(struct 
>>> qcom_nand_controller
>>> *nandc, bool read,
>>>    * @num_regs:        number of registers to read
>>>    */
>>>   static int read_reg_dma(struct qcom_nand_controller *nandc, int 
>>> first,
>>> -            int num_regs)
>>> +            int num_regs, unsigned int flags)
>>>   {
>>>       bool flow_control = false;
>>>       void *vaddr;
>>> @@ -736,7 +744,7 @@ static int read_reg_dma(struct 
>>> qcom_nand_controller
>>> *nandc, int first,
>>>    * @num_regs:        number of registers to write
>>>    */
>>>   static int write_reg_dma(struct qcom_nand_controller *nandc, int 
>>> first,
>>> -             int num_regs)
>>> +             int num_regs, unsigned int flags)
>> 
>> Adding flags to read_reg_dma and write_reg_dma is making things a bit
>> messy. I can't
>> think of a better way to share the code either, though.
>> 
>> One thing we could consider doing is something like below. I don't 
>> know if
>> it would
>> make things more legible.
>> 
>> union nand_dma_props {
>>     bool adm_flow_control;
>>     unsigned int bam_flags;
>> };
>> 
>> config_cw_read()
>> {
>>     union nand_dma_props dma_props;
>>     ...
>>     ...
>> 
>>     if (is_bam)
>>         dma_props.bam_flags = NAND_BAM_NWD;
>>     else
>>         dma_props.adm_flow_control = false;
>> 
>>     write_reg_dma(nandc, NAND_EXEC_CMD, 1, &dma_props);
>>     ...
>>     ...
>> }

  The flags for each write_reg_dma and read_reg_dma will be different.
  Normally, for all the API's which uses flags
  (like dmaengine_prep_slave_sg), we are passing the flags directly.
  this union won't help us making this code more readable.

> 
>  Right, with this , i think we can have two different indirections for
> functions like,
>  prep_dma_desc_command and prep_dma_desc. That will help to reduce the
> bam_dma_enabled
>  checks.

  Since common code changes are intermixed with bam_dma_enabled check
  so taking function pointer won't help much in making code more 
readable.

  anyway, I will analyze the final code for v2 and will check the
  possibility of using function pointers.

> 
> Regards,
>  Sricharan

-- 
Abhishek Sahu

[PATCH 08/14] qcom: mtd: nand: Add support for additional CSRs

[Abhishek Sahu]

1. NAND_READ_LOCATION: provides the offset in page for
   reading in BAM DMA mode

2. NAND_ERASED_CW_DETECT_CFG: contains the status for erased
   code words

3. NAND_BUFFER_STATUS: contains the status for ECC

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/mtd/nand/qcom_nandc.c | 67 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 66 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 65c9059..8e7dc9e 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -54,6 +54,8 @@
 #define	NAND_VERSION			0xf08
 #define	NAND_READ_LOCATION_0		0xf20
 #define	NAND_READ_LOCATION_1		0xf24
+#define	NAND_READ_LOCATION_2		0xf28
+#define	NAND_READ_LOCATION_3		0xf2c
 
 /* dummy register offsets, used by write_reg_dma */
 #define	NAND_DEV_CMD1_RESTORE		0xdead
@@ -132,6 +134,11 @@
 #define	ERASED_PAGE			(PAGE_ALL_ERASED | PAGE_ERASED)
 #define	ERASED_CW			(CODEWORD_ALL_ERASED | CODEWORD_ERASED)
 
+/* NAND_READ_LOCATION_n bits */
+#define READ_LOCATION_OFFSET		0
+#define READ_LOCATION_SIZE		16
+#define READ_LOCATION_LAST		31
+
 /* Version Mask */
 #define	NAND_VERSION_MAJOR_MASK		0xf0000000
 #define	NAND_VERSION_MAJOR_SHIFT	28
@@ -177,6 +184,11 @@
 #define NAND_BAM_NWD			(0x0002)
 /* Finish writing in the current sgl and start writing in another sgl */
 #define NAND_BAM_NEXT_SGL		(0x0004)
+/*
+ * Erased codeword status is being used two times in single transfer so this
+ * flag will determine the current value of erased codeword status register
+ */
+#define NAND_ERASED_CW_SET		(0x0008)
 
 #define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
 #define QPIC_PER_CW_MAX_CMD_SGL		(32)
@@ -258,6 +270,13 @@ struct nandc_regs {
 	__le32 orig_vld;
 
 	__le32 ecc_buf_cfg;
+	__le32 read_location0;
+	__le32 read_location1;
+	__le32 read_location2;
+	__le32 read_location3;
+
+	__le32 erased_cw_detect_cfg_clr;
+	__le32 erased_cw_detect_cfg_set;
 };
 
 /*
@@ -504,6 +523,16 @@ static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
 		return &regs->orig_vld;
 	case NAND_EBI2_ECC_BUF_CFG:
 		return &regs->ecc_buf_cfg;
+	case NAND_BUFFER_STATUS:
+		return &regs->clrreadstatus;
+	case NAND_READ_LOCATION_0:
+		return &regs->read_location0;
+	case NAND_READ_LOCATION_1:
+		return &regs->read_location1;
+	case NAND_READ_LOCATION_2:
+		return &regs->read_location2;
+	case NAND_READ_LOCATION_3:
+		return &regs->read_location3;
 	default:
 		return NULL;
 	}
@@ -545,7 +574,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
 {
 	struct nand_chip *chip = &host->chip;
 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
-	u32 cmd, cfg0, cfg1, ecc_bch_cfg;
+	u32 cmd, cfg0, cfg1, ecc_bch_cfg, read_location0;
 
 	if (read) {
 		if (host->use_ecc)
@@ -562,12 +591,20 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
 
 		cfg1 = host->cfg1;
 		ecc_bch_cfg = host->ecc_bch_cfg;
+		if (read)
+			read_location0 = (0 << READ_LOCATION_OFFSET) |
+				(host->cw_data << READ_LOCATION_SIZE) |
+				(1 << READ_LOCATION_LAST);
 	} else {
 		cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) |
 				(num_cw - 1) << CW_PER_PAGE;
 
 		cfg1 = host->cfg1_raw;
 		ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
+		if (read)
+			read_location0 = (0 << READ_LOCATION_OFFSET) |
+				(host->cw_size << READ_LOCATION_SIZE) |
+				(1 << READ_LOCATION_LAST);
 	}
 
 	nandc_set_reg(nandc, NAND_FLASH_CMD, cmd);
@@ -578,6 +615,9 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
 	nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
 	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
 	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
+
+	if (read)
+		nandc_set_reg(nandc, NAND_READ_LOCATION_0, read_location0);
 }
 
 /*
@@ -756,6 +796,13 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
 	if (first == NAND_FLASH_CMD)
 		flow_control = true;
 
+	if (first == NAND_ERASED_CW_DETECT_CFG) {
+		if (flags & NAND_ERASED_CW_SET)
+			vaddr = &regs->erased_cw_detect_cfg_set;
+		else
+			vaddr = &regs->erased_cw_detect_cfg_clr;
+	}
+
 	if (first == NAND_EXEC_CMD)
 		flags |= NAND_BAM_NWD;
 
@@ -808,6 +855,12 @@ static void config_cw_read(struct qcom_nand_controller *nandc)
 	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
 	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
 
+	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
+	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, NAND_ERASED_CW_SET);
+	if (nandc->dma_bam_enabled)
+		write_reg_dma(nandc, NAND_READ_LOCATION_0, 1,
+			      NAND_BAM_NEXT_SGL);
+
 	write_reg_dma(nandc, NAND_EXEC_CMD, 1,
 		      NAND_BAM_NWD | NAND_BAM_NEXT_SGL);
 
@@ -882,6 +935,10 @@ static int nandc_param(struct qcom_nand_host *host)
 
 	nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
 	nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
+	nandc_set_reg(nandc, NAND_READ_LOCATION_0,
+		      (0 << READ_LOCATION_OFFSET) |
+		      (512 << READ_LOCATION_SIZE) |
+		      (1 << READ_LOCATION_LAST));
 
 	write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
 	write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
@@ -1413,6 +1470,10 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
 
 	set_address(host, host->cw_size * (ecc->steps - 1), page);
 	update_rw_regs(host, 1, true);
+	nandc_set_reg(nandc, NAND_READ_LOCATION_0,
+		      (0 << READ_LOCATION_OFFSET) |
+		      (size << READ_LOCATION_SIZE) |
+		      (1 << READ_LOCATION_LAST));
 
 	config_cw_read(nandc);
 
@@ -2147,6 +2208,10 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
 
 	host->clrflashstatus = FS_READY_BSY_N;
 	host->clrreadstatus = 0xc0;
+	nandc->regs->erased_cw_detect_cfg_clr =
+		cpu_to_le32(CLR_ERASED_PAGE_DET);
+	nandc->regs->erased_cw_detect_cfg_set =
+		cpu_to_le32(SET_ERASED_PAGE_DET);
 
 	dev_dbg(nandc->dev,
 		"cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 08/14] qcom: mtd: nand: Add support for additional CSRs

[Archit Taneja]

On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
> 1. NAND_READ_LOCATION: provides the offset in page for
>     reading in BAM DMA mode
> 
> 2. NAND_ERASED_CW_DETECT_CFG: contains the status for erased
>     code words
> 
> 3. NAND_BUFFER_STATUS: contains the status for ECC
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>   drivers/mtd/nand/qcom_nandc.c | 67 ++++++++++++++++++++++++++++++++++++++++++-
>   1 file changed, 66 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 65c9059..8e7dc9e 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -54,6 +54,8 @@
>   #define	NAND_VERSION			0xf08
>   #define	NAND_READ_LOCATION_0		0xf20
>   #define	NAND_READ_LOCATION_1		0xf24
> +#define	NAND_READ_LOCATION_2		0xf28
> +#define	NAND_READ_LOCATION_3		0xf2c
>   
>   /* dummy register offsets, used by write_reg_dma */
>   #define	NAND_DEV_CMD1_RESTORE		0xdead
> @@ -132,6 +134,11 @@
>   #define	ERASED_PAGE			(PAGE_ALL_ERASED | PAGE_ERASED)
>   #define	ERASED_CW			(CODEWORD_ALL_ERASED | CODEWORD_ERASED)
>   
> +/* NAND_READ_LOCATION_n bits */
> +#define READ_LOCATION_OFFSET		0
> +#define READ_LOCATION_SIZE		16
> +#define READ_LOCATION_LAST		31
> +
>   /* Version Mask */
>   #define	NAND_VERSION_MAJOR_MASK		0xf0000000
>   #define	NAND_VERSION_MAJOR_SHIFT	28
> @@ -177,6 +184,11 @@
>   #define NAND_BAM_NWD			(0x0002)
>   /* Finish writing in the current sgl and start writing in another sgl */
>   #define NAND_BAM_NEXT_SGL		(0x0004)
> +/*
> + * Erased codeword status is being used two times in single transfer so this
> + * flag will determine the current value of erased codeword status register
> + */
> +#define NAND_ERASED_CW_SET		(0x0008)
>   
>   #define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
>   #define QPIC_PER_CW_MAX_CMD_SGL		(32)
> @@ -258,6 +270,13 @@ struct nandc_regs {
>   	__le32 orig_vld;
>   
>   	__le32 ecc_buf_cfg;
> +	__le32 read_location0;
> +	__le32 read_location1;
> +	__le32 read_location2;
> +	__le32 read_location3;
> +
> +	__le32 erased_cw_detect_cfg_clr;
> +	__le32 erased_cw_detect_cfg_set;
>   };
>   
>   /*
> @@ -504,6 +523,16 @@ static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
>   		return &regs->orig_vld;
>   	case NAND_EBI2_ECC_BUF_CFG:
>   		return &regs->ecc_buf_cfg;
> +	case NAND_BUFFER_STATUS:
> +		return &regs->clrreadstatus;
> +	case NAND_READ_LOCATION_0:
> +		return &regs->read_location0;
> +	case NAND_READ_LOCATION_1:
> +		return &regs->read_location1;
> +	case NAND_READ_LOCATION_2:
> +		return &regs->read_location2;
> +	case NAND_READ_LOCATION_3:
> +		return &regs->read_location3;
>   	default:
>   		return NULL;
>   	}
> @@ -545,7 +574,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
>   {
>   	struct nand_chip *chip = &host->chip;
>   	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> -	u32 cmd, cfg0, cfg1, ecc_bch_cfg;
> +	u32 cmd, cfg0, cfg1, ecc_bch_cfg, read_location0;
>   
>   	if (read) {
>   		if (host->use_ecc)
> @@ -562,12 +591,20 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
>   
>   		cfg1 = host->cfg1;
>   		ecc_bch_cfg = host->ecc_bch_cfg;
> +		if (read)
> +			read_location0 = (0 << READ_LOCATION_OFFSET) |
> +				(host->cw_data << READ_LOCATION_SIZE) |
> +				(1 << READ_LOCATION_LAST);
>   	} else {
>   		cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) |
>   				(num_cw - 1) << CW_PER_PAGE;
>   
>   		cfg1 = host->cfg1_raw;
>   		ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
> +		if (read)
> +			read_location0 = (0 << READ_LOCATION_OFFSET) |
> +				(host->cw_size << READ_LOCATION_SIZE) |
> +				(1 << READ_LOCATION_LAST);
>   	}
>   
>   	nandc_set_reg(nandc, NAND_FLASH_CMD, cmd);
> @@ -578,6 +615,9 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
>   	nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
>   	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
> +
> +	if (read)
> +		nandc_set_reg(nandc, NAND_READ_LOCATION_0, read_location0);
>   }
>   
>   /*
> @@ -756,6 +796,13 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>   	if (first == NAND_FLASH_CMD)
>   		flow_control = true;
>   
> +	if (first == NAND_ERASED_CW_DETECT_CFG) {
> +		if (flags & NAND_ERASED_CW_SET)
> +			vaddr = &regs->erased_cw_detect_cfg_set;
> +		else
> +			vaddr = &regs->erased_cw_detect_cfg_clr;
> +	}
> +
>   	if (first == NAND_EXEC_CMD)
>   		flags |= NAND_BAM_NWD;
>   
> @@ -808,6 +855,12 @@ static void config_cw_read(struct qcom_nand_controller *nandc)
>   	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>   	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>   
> +	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
> +	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, NAND_ERASED_CW_SET);
> +	if (nandc->dma_bam_enabled)
> +		write_reg_dma(nandc, NAND_READ_LOCATION_0, 1,
> +			      NAND_BAM_NEXT_SGL);
> +
>   	write_reg_dma(nandc, NAND_EXEC_CMD, 1,
>   		      NAND_BAM_NWD | NAND_BAM_NEXT_SGL);
>   
> @@ -882,6 +935,10 @@ static int nandc_param(struct qcom_nand_host *host)
>   
>   	nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
>   	nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
> +	nandc_set_reg(nandc, NAND_READ_LOCATION_0,
> +		      (0 << READ_LOCATION_OFFSET) |
> +		      (512 << READ_LOCATION_SIZE) |
> +		      (1 << READ_LOCATION_LAST));
>   
>   	write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
>   	write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
> @@ -1413,6 +1470,10 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
>   
>   	set_address(host, host->cw_size * (ecc->steps - 1), page);
>   	update_rw_regs(host, 1, true);
> +	nandc_set_reg(nandc, NAND_READ_LOCATION_0,
> +		      (0 << READ_LOCATION_OFFSET) |
> +		      (size << READ_LOCATION_SIZE) |
> +		      (1 << READ_LOCATION_LAST));
>   
>   	config_cw_read(nandc);
>   
> @@ -2147,6 +2208,10 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
>   
>   	host->clrflashstatus = FS_READY_BSY_N;
>   	host->clrreadstatus = 0xc0;
> +	nandc->regs->erased_cw_detect_cfg_clr =
> +		cpu_to_le32(CLR_ERASED_PAGE_DET);
> +	nandc->regs->erased_cw_detect_cfg_set =
> +		cpu_to_le32(SET_ERASED_PAGE_DET);
>   

Can these 2 be put in qcom_nand_host like done for other registers?

Thanks,
Archit

>   	dev_dbg(nandc->dev,
>   		"cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
> 

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 08/14] qcom: mtd: nand: Add support for additional CSRs

[Abhishek Sahu]

On 2017-07-04 12:24, Archit Taneja wrote:
> On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
>> 1. NAND_READ_LOCATION: provides the offset in page for
>>     reading in BAM DMA mode
>> 
>> 2. NAND_ERASED_CW_DETECT_CFG: contains the status for erased
>>     code words
>> 
>> 3. NAND_BUFFER_STATUS: contains the status for ECC
>> 
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> ---
>>   drivers/mtd/nand/qcom_nandc.c | 67 
>> ++++++++++++++++++++++++++++++++++++++++++-
>>   1 file changed, 66 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/mtd/nand/qcom_nandc.c 
>> b/drivers/mtd/nand/qcom_nandc.c
>> index 65c9059..8e7dc9e 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -54,6 +54,8 @@
>>   #define	NAND_VERSION			0xf08
>>   #define	NAND_READ_LOCATION_0		0xf20
>>   #define	NAND_READ_LOCATION_1		0xf24
>> +#define	NAND_READ_LOCATION_2		0xf28
>> +#define	NAND_READ_LOCATION_3		0xf2c
>> 
>>   /* dummy register offsets, used by write_reg_dma */
>>   #define	NAND_DEV_CMD1_RESTORE		0xdead
>> @@ -132,6 +134,11 @@
>>   #define	ERASED_PAGE			(PAGE_ALL_ERASED | PAGE_ERASED)
>>   #define	ERASED_CW			(CODEWORD_ALL_ERASED | CODEWORD_ERASED)
>> 
>> +/* NAND_READ_LOCATION_n bits */
>> +#define READ_LOCATION_OFFSET		0
>> +#define READ_LOCATION_SIZE		16
>> +#define READ_LOCATION_LAST		31
>> +
>>   /* Version Mask */
>>   #define	NAND_VERSION_MAJOR_MASK		0xf0000000
>>   #define	NAND_VERSION_MAJOR_SHIFT	28
>> @@ -177,6 +184,11 @@
>>   #define NAND_BAM_NWD			(0x0002)
>>   /* Finish writing in the current sgl and start writing in another 
>> sgl */
>>   #define NAND_BAM_NEXT_SGL		(0x0004)
>> +/*
>> + * Erased codeword status is being used two times in single transfer 
>> so this
>> + * flag will determine the current value of erased codeword status 
>> register
>> + */
>> +#define NAND_ERASED_CW_SET		(0x0008)
>> 
>>   #define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
>>   #define QPIC_PER_CW_MAX_CMD_SGL		(32)
>> @@ -258,6 +270,13 @@ struct nandc_regs {
>>   	__le32 orig_vld;
>> 
>>   	__le32 ecc_buf_cfg;
>> +	__le32 read_location0;
>> +	__le32 read_location1;
>> +	__le32 read_location2;
>> +	__le32 read_location3;
>> +
>> +	__le32 erased_cw_detect_cfg_clr;
>> +	__le32 erased_cw_detect_cfg_set;
>>   };
>> 
>>   /*
>> @@ -504,6 +523,16 @@ static __le32 *offset_to_nandc_reg(struct 
>> nandc_regs *regs, int offset)
>>   		return &regs->orig_vld;
>>   	case NAND_EBI2_ECC_BUF_CFG:
>>   		return &regs->ecc_buf_cfg;
>> +	case NAND_BUFFER_STATUS:
>> +		return &regs->clrreadstatus;
>> +	case NAND_READ_LOCATION_0:
>> +		return &regs->read_location0;
>> +	case NAND_READ_LOCATION_1:
>> +		return &regs->read_location1;
>> +	case NAND_READ_LOCATION_2:
>> +		return &regs->read_location2;
>> +	case NAND_READ_LOCATION_3:
>> +		return &regs->read_location3;
>>   	default:
>>   		return NULL;
>>   	}
>> @@ -545,7 +574,7 @@ static void update_rw_regs(struct qcom_nand_host 
>> *host, int num_cw, bool read)
>>   {
>>   	struct nand_chip *chip = &host->chip;
>>   	struct qcom_nand_controller *nandc = 
>> get_qcom_nand_controller(chip);
>> -	u32 cmd, cfg0, cfg1, ecc_bch_cfg;
>> +	u32 cmd, cfg0, cfg1, ecc_bch_cfg, read_location0;
>> 
>>   	if (read) {
>>   		if (host->use_ecc)
>> @@ -562,12 +591,20 @@ static void update_rw_regs(struct qcom_nand_host 
>> *host, int num_cw, bool read)
>> 
>>   		cfg1 = host->cfg1;
>>   		ecc_bch_cfg = host->ecc_bch_cfg;
>> +		if (read)
>> +			read_location0 = (0 << READ_LOCATION_OFFSET) |
>> +				(host->cw_data << READ_LOCATION_SIZE) |
>> +				(1 << READ_LOCATION_LAST);
>>   	} else {
>>   		cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) |
>>   				(num_cw - 1) << CW_PER_PAGE;
>> 
>>   		cfg1 = host->cfg1_raw;
>>   		ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
>> +		if (read)
>> +			read_location0 = (0 << READ_LOCATION_OFFSET) |
>> +				(host->cw_size << READ_LOCATION_SIZE) |
>> +				(1 << READ_LOCATION_LAST);
>>   	}
>> 
>>   	nandc_set_reg(nandc, NAND_FLASH_CMD, cmd);
>> @@ -578,6 +615,9 @@ static void update_rw_regs(struct qcom_nand_host 
>> *host, int num_cw, bool read)
>>   	nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
>>   	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
>>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>> +
>> +	if (read)
>> +		nandc_set_reg(nandc, NAND_READ_LOCATION_0, read_location0);
>>   }
>> 
>>   /*
>> @@ -756,6 +796,13 @@ static int write_reg_dma(struct 
>> qcom_nand_controller *nandc, int first,
>>   	if (first == NAND_FLASH_CMD)
>>   		flow_control = true;
>> 
>> +	if (first == NAND_ERASED_CW_DETECT_CFG) {
>> +		if (flags & NAND_ERASED_CW_SET)
>> +			vaddr = &regs->erased_cw_detect_cfg_set;
>> +		else
>> +			vaddr = &regs->erased_cw_detect_cfg_clr;
>> +	}
>> +
>>   	if (first == NAND_EXEC_CMD)
>>   		flags |= NAND_BAM_NWD;
>> 
>> @@ -808,6 +855,12 @@ static void config_cw_read(struct 
>> qcom_nand_controller *nandc)
>>   	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>>   	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>> 
>> +	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
>> +	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 
>> NAND_ERASED_CW_SET);
>> +	if (nandc->dma_bam_enabled)
>> +		write_reg_dma(nandc, NAND_READ_LOCATION_0, 1,
>> +			      NAND_BAM_NEXT_SGL);
>> +
>>   	write_reg_dma(nandc, NAND_EXEC_CMD, 1,
>>   		      NAND_BAM_NWD | NAND_BAM_NEXT_SGL);
>> 
>> @@ -882,6 +935,10 @@ static int nandc_param(struct qcom_nand_host 
>> *host)
>> 
>>   	nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
>>   	nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
>> +	nandc_set_reg(nandc, NAND_READ_LOCATION_0,
>> +		      (0 << READ_LOCATION_OFFSET) |
>> +		      (512 << READ_LOCATION_SIZE) |
>> +		      (1 << READ_LOCATION_LAST));
>> 
>>   	write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
>>   	write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
>> @@ -1413,6 +1470,10 @@ static int copy_last_cw(struct qcom_nand_host 
>> *host, int page)
>> 
>>   	set_address(host, host->cw_size * (ecc->steps - 1), page);
>>   	update_rw_regs(host, 1, true);
>> +	nandc_set_reg(nandc, NAND_READ_LOCATION_0,
>> +		      (0 << READ_LOCATION_OFFSET) |
>> +		      (size << READ_LOCATION_SIZE) |
>> +		      (1 << READ_LOCATION_LAST));
>> 
>>   	config_cw_read(nandc);
>> 
>> @@ -2147,6 +2208,10 @@ static int qcom_nand_host_setup(struct 
>> qcom_nand_host *host)
>> 
>>   	host->clrflashstatus = FS_READY_BSY_N;
>>   	host->clrreadstatus = 0xc0;
>> +	nandc->regs->erased_cw_detect_cfg_clr =
>> +		cpu_to_le32(CLR_ERASED_PAGE_DET);
>> +	nandc->regs->erased_cw_detect_cfg_set =
>> +		cpu_to_le32(SET_ERASED_PAGE_DET);
>> 
> 
> Can these 2 be put in qcom_nand_host like done for other registers?
> 

  For, All the other registers, the register is being used only once
  in per codeword read/write and its values changes for different
  operations but the erased codeword register is being used twice in
  the same codeword which we can't differentiate in nandc_set_reg.

  Also, the values for this will be fixed and it will never change
  so its better to assign directly in nandc->regs.

> Thanks,
> Archit
> 
>>   	dev_dbg(nandc->dev,
>>   		"cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data 
>> %d strength %d parity_bytes %d steps %d\n",
>> 

-- 
Abhishek Sahu

[PATCH 10/14] qcom: mtd: nand: support for QPIC Page read/write

[Abhishek Sahu]

1. Add the function for command descriptor preparation which
   will be used only by BAM DMA and it will form the DMA descriptors
   containing command elements.

2. Add the data descriptor preparation function which will be used
   only by BAM DMA for forming the data SGL’s.

3. Add clear BAM transaction and call it before every new request

4. Check DMA mode for ADM or BAM and call the appropriate
   descriptor formation function.

5. Enable the BAM in NAND_CTRL.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/mtd/nand/qcom_nandc.c | 190 +++++++++++++++++++++++++++++++++++++++---
 1 file changed, 180 insertions(+), 10 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 17766af..4c6e594 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -156,6 +156,8 @@
 #define	FETCH_ID			0xb
 #define	RESET_DEVICE			0xd
 
+/* NAND_CTRL bits */
+#define	BAM_MODE_EN			BIT(0)
 /*
  * the NAND controller performs reads/writes with ECC in 516 byte chunks.
  * the driver calls the chunks 'step' or 'codeword' interchangeably
@@ -190,6 +192,14 @@
  */
 #define NAND_ERASED_CW_SET		(0x0008)
 
+/* Returns the dma address for reg read buffer */
+#define REG_BUF_DMA_ADDR(chip, vaddr) \
+	((chip)->reg_read_buf_phys + \
+	((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
+
+/* Returns the NAND register physical address */
+#define NAND_REG_PHYS(chip, offset) ((chip)->base_phys + (offset))
+
 #define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
 #define QPIC_PER_CW_MAX_CMD_SGL		(32)
 #define QPIC_PER_CW_MAX_DATA_SGL	(8)
@@ -287,7 +297,8 @@ struct nandc_regs {
  *				controller
  * @dev:			parent device
  * @base:			MMIO base
- * @base_dma:			physical base address of controller registers
+ * @base_phys:			physical base address of controller registers
+ * @base_dma:			dma base address of controller registers
  * @core_clk:			controller clock
  * @aon_clk:			another controller clock
  *
@@ -323,6 +334,7 @@ struct qcom_nand_controller {
 	struct device *dev;
 
 	void __iomem *base;
+	phys_addr_t base_phys;
 	dma_addr_t base_dma;
 
 	struct clk *core_clk;
@@ -467,6 +479,29 @@ static void free_bam_transaction(struct qcom_nand_controller *nandc)
 	return bam_txn;
 }
 
+/* Clears the BAM transaction indexes */
+static void clear_bam_transaction(struct qcom_nand_controller *nandc)
+{
+	struct bam_transaction *bam_txn = nandc->bam_txn;
+
+	if (!nandc->dma_bam_enabled)
+		return;
+
+	bam_txn->bam_ce_pos = 0;
+	bam_txn->bam_ce_start = 0;
+	bam_txn->cmd_sgl_pos = 0;
+	bam_txn->cmd_sgl_start = 0;
+	bam_txn->tx_sgl_pos = 0;
+	bam_txn->tx_sgl_start = 0;
+	bam_txn->rx_sgl_pos = 0;
+	bam_txn->rx_sgl_start = 0;
+
+	sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
+		      QPIC_PER_CW_MAX_CMD_SGL);
+	sg_init_table(bam_txn->data_sg, nandc->max_cwperpage *
+		      QPIC_PER_CW_MAX_DATA_SGL);
+}
+
 static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
 {
 	return container_of(chip, struct qcom_nand_host, chip);
@@ -682,6 +717,102 @@ static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
 	return 0;
 }
 
+/*
+ * Prepares the command descriptor for BAM DMA which will be used for NAND
+ * register reads and writes. The command descriptor requires the command
+ * to be formed in command element type so this function uses the command
+ * element from bam transaction ce array and fills the same with required
+ * data. A single SGL can contain multiple command elements so
+ * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
+ * after the current command element.
+ */
+static int prep_dma_desc_command(struct qcom_nand_controller *nandc, bool read,
+				 int reg_off, const void *vaddr,
+				 int size, unsigned int flags)
+{
+	int bam_ce_size;
+	int i, ret;
+	struct bam_cmd_element *bam_ce_buffer;
+	struct bam_transaction *bam_txn = nandc->bam_txn;
+
+	bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
+
+	/* fill the command desc */
+	for (i = 0; i < size; i++) {
+		if (read)
+			bam_prep_ce(&bam_ce_buffer[i],
+				    NAND_REG_PHYS(nandc, reg_off + 4 * i),
+				    BAM_READ_COMMAND,
+				    REG_BUF_DMA_ADDR(nandc,
+						     (__le32 *)vaddr + i));
+		else
+			bam_prep_ce_le32(&bam_ce_buffer[i],
+					 NAND_REG_PHYS(nandc, reg_off + 4 * i),
+					 BAM_WRITE_COMMAND,
+					 *((__le32 *)vaddr + i));
+	}
+
+	bam_txn->bam_ce_pos += size;
+
+	/* use the separate sgl after this command */
+	if (flags & NAND_BAM_NEXT_SGL) {
+		bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
+		bam_ce_size = (bam_txn->bam_ce_pos -
+				bam_txn->bam_ce_start) *
+				sizeof(struct bam_cmd_element);
+		sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
+			   bam_ce_buffer, bam_ce_size);
+		bam_txn->cmd_sgl_pos++;
+		bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
+
+		if (flags & NAND_BAM_NWD) {
+			ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
+						     DMA_PREP_FENCE |
+						     DMA_PREP_CMD);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Prepares the data descriptor for BAM DMA which will be used for NAND
+ * data reads and writes.
+ */
+static int prep_dma_desc_data_bam(struct qcom_nand_controller *nandc, bool read,
+				  int reg_off, const void *vaddr,
+				  int size, unsigned int flags)
+{
+	int ret;
+	struct bam_transaction *bam_txn = nandc->bam_txn;
+
+	if (read) {
+		sg_set_buf(&bam_txn->data_sg[bam_txn->rx_sgl_pos],
+			   vaddr, size);
+		bam_txn->rx_sgl_pos++;
+	} else {
+		sg_set_buf(&bam_txn->data_sg[bam_txn->tx_sgl_pos],
+			   vaddr, size);
+		bam_txn->tx_sgl_pos++;
+
+		/*
+		 * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
+		 * is not set, form the DMA descriptor
+		 */
+		if (!(flags & NAND_BAM_NO_EOT)) {
+			ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
+						     DMA_PREP_INTERRUPT);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
+/* Prepares the dma descriptor for adm dma engine */
 static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
 			 int reg_off, const void *vaddr, int size,
 			 bool flow_control)
@@ -764,16 +895,19 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
 {
 	bool flow_control = false;
 	void *vaddr;
-	int size;
 
 	if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
 		flow_control = true;
 
-	size = num_regs * sizeof(u32);
 	vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
 	nandc->reg_read_pos += num_regs;
 
-	return prep_dma_desc(nandc, true, first, vaddr, size, flow_control);
+	if (nandc->dma_bam_enabled)
+		return prep_dma_desc_command(nandc, true, first, vaddr,
+					     num_regs, flags);
+
+	return prep_dma_desc(nandc, true, first, vaddr, num_regs * sizeof(u32),
+			     flow_control);
 }
 
 /*
@@ -789,7 +923,6 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
 	bool flow_control = false;
 	struct nandc_regs *regs = nandc->regs;
 	void *vaddr;
-	int size;
 
 	vaddr = offset_to_nandc_reg(regs, first);
 
@@ -812,9 +945,12 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
 	if (first == NAND_DEV_CMD_VLD_RESTORE)
 		first = NAND_DEV_CMD_VLD;
 
-	size = num_regs * sizeof(u32);
+	if (nandc->dma_bam_enabled)
+		return prep_dma_desc_command(nandc, false, first, vaddr,
+					     num_regs, flags);
 
-	return prep_dma_desc(nandc, false, first, vaddr, size, flow_control);
+	return prep_dma_desc(nandc, false, first, vaddr, num_regs * sizeof(u32),
+			     flow_control);
 }
 
 /*
@@ -828,6 +964,10 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
 static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
 			 const u8 *vaddr, int size, unsigned int flags)
 {
+	if (nandc->dma_bam_enabled)
+		return prep_dma_desc_data_bam(nandc, true, reg_off, vaddr, size,
+					      flags);
+
 	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
 }
 
@@ -842,6 +982,10 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
 static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
 			  const u8 *vaddr, int size, unsigned int flags)
 {
+	if (nandc->dma_bam_enabled)
+		return prep_dma_desc_data_bam(nandc, false, reg_off, vaddr,
+					      size, flags);
+
 	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
 }
 
@@ -931,6 +1075,8 @@ static int nandc_param(struct qcom_nand_host *host)
 	struct nand_chip *chip = &host->chip;
 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
 
+	clear_bam_transaction(nandc);
+
 	/*
 	 * NAND_CMD_PARAM is called before we know much about the FLASH chip
 	 * in use. we configure the controller to perform a raw read of 512
@@ -993,6 +1139,8 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
 	struct nand_chip *chip = &host->chip;
 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
 
+	clear_bam_transaction(nandc);
+
 	nandc_set_reg(nandc, NAND_FLASH_CMD,
 		      BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
 	nandc_set_reg(nandc, NAND_ADDR0, page_addr);
@@ -1025,10 +1173,13 @@ static int read_id(struct qcom_nand_host *host, int column)
 	if (column == -1)
 		return 0;
 
+	clear_bam_transaction(nandc);
+
 	nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
 	nandc_set_reg(nandc, NAND_ADDR0, column);
 	nandc_set_reg(nandc, NAND_ADDR1, 0);
-	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
+		      nandc->dma_bam_enabled ? 0 : DM_EN);
 	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
 
 	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
@@ -1045,6 +1196,8 @@ static int reset(struct qcom_nand_host *host)
 	struct nand_chip *chip = &host->chip;
 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
 
+	clear_bam_transaction(nandc);
+
 	nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
 	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
 
@@ -1561,6 +1714,7 @@ static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 	data_buf = buf;
 	oob_buf = oob_required ? chip->oob_poi : NULL;
 
+	clear_bam_transaction(nandc);
 	ret = read_page_ecc(host, data_buf, oob_buf);
 	if (ret) {
 		dev_err(nandc->dev, "failure to read page\n");
@@ -1585,6 +1739,8 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
 	oob_buf = chip->oob_poi;
 
 	host->use_ecc = false;
+
+	clear_bam_transaction(nandc);
 	update_rw_regs(host, ecc->steps, true);
 
 	for (i = 0; i < ecc->steps; i++) {
@@ -1641,6 +1797,7 @@ static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 	int ret;
 
 	clear_read_regs(nandc);
+	clear_bam_transaction(nandc);
 
 	host->use_ecc = true;
 	set_address(host, 0, page);
@@ -1664,6 +1821,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 	int i, ret;
 
 	clear_read_regs(nandc);
+	clear_bam_transaction(nandc);
 
 	data_buf = (u8 *)buf;
 	oob_buf = chip->oob_poi;
@@ -1729,6 +1887,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
 	int i, ret;
 
 	clear_read_regs(nandc);
+	clear_bam_transaction(nandc);
 
 	data_buf = (u8 *)buf;
 	oob_buf = chip->oob_poi;
@@ -1803,6 +1962,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 
 	host->use_ecc = true;
 
+	clear_bam_transaction(nandc);
 	ret = copy_last_cw(host, page);
 	if (ret)
 		return ret;
@@ -1860,6 +2020,7 @@ static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs)
 	 */
 	host->use_ecc = false;
 
+	clear_bam_transaction(nandc);
 	ret = copy_last_cw(host, page);
 	if (ret)
 		goto err;
@@ -1890,6 +2051,7 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
 	int page, ret, status = 0;
 
 	clear_read_regs(nandc);
+	clear_bam_transaction(nandc);
 
 	/*
 	 * to mark the BBM as bad, we flash the entire last codeword with 0s.
@@ -2396,11 +2558,18 @@ static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
 /* one time setup of a few nand controller registers */
 static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
 {
+	u32 nand_ctrl;
+
 	/* kill onenand */
 	nandc_write(nandc, SFLASHC_BURST_CFG, 0);
 
-	/* enable ADM DMA */
-	nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+	/* enable ADM or BAM DMA */
+	if (!nandc->dma_bam_enabled) {
+		nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
+	} else {
+		nand_ctrl = nandc_read(nandc, NAND_CTRL);
+		nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
+	}
 
 	/* save the original values of these registers */
 	nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
@@ -2592,6 +2761,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 	if (IS_ERR(nandc->base))
 		return PTR_ERR(nandc->base);
 
+	nandc->base_phys = res->start;
 	nandc->base_dma = phys_to_dma(dev, (phys_addr_t)res->start);
 
 	nandc->core_clk = devm_clk_get(dev, "core");
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 10/14] qcom: mtd: nand: support for QPIC Page read/write

[Archit Taneja]

On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
> 1. Add the function for command descriptor preparation which
>     will be used only by BAM DMA and it will form the DMA descriptors
>     containing command elements.
> 
> 2. Add the data descriptor preparation function which will be used
>     only by BAM DMA for forming the data SGL’s.
> 
> 3. Add clear BAM transaction and call it before every new request
> 
> 4. Check DMA mode for ADM or BAM and call the appropriate
>     descriptor formation function.
> 
> 5. Enable the BAM in NAND_CTRL.
> 
> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>   drivers/mtd/nand/qcom_nandc.c | 190 +++++++++++++++++++++++++++++++++++++++---
>   1 file changed, 180 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 17766af..4c6e594 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -156,6 +156,8 @@
>   #define	FETCH_ID			0xb
>   #define	RESET_DEVICE			0xd
>   
> +/* NAND_CTRL bits */
> +#define	BAM_MODE_EN			BIT(0)
>   /*
>    * the NAND controller performs reads/writes with ECC in 516 byte chunks.
>    * the driver calls the chunks 'step' or 'codeword' interchangeably
> @@ -190,6 +192,14 @@
>    */
>   #define NAND_ERASED_CW_SET		(0x0008)
>   
> +/* Returns the dma address for reg read buffer */
> +#define REG_BUF_DMA_ADDR(chip, vaddr) \
> +	((chip)->reg_read_buf_phys + \
> +	((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
> +
> +/* Returns the NAND register physical address */
> +#define NAND_REG_PHYS(chip, offset) ((chip)->base_phys + (offset))
> +
>   #define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
>   #define QPIC_PER_CW_MAX_CMD_SGL		(32)
>   #define QPIC_PER_CW_MAX_DATA_SGL	(8)
> @@ -287,7 +297,8 @@ struct nandc_regs {
>    *				controller
>    * @dev:			parent device
>    * @base:			MMIO base
> - * @base_dma:			physical base address of controller registers
> + * @base_phys:			physical base address of controller registers
> + * @base_dma:			dma base address of controller registers
>    * @core_clk:			controller clock
>    * @aon_clk:			another controller clock
>    *
> @@ -323,6 +334,7 @@ struct qcom_nand_controller {
>   	struct device *dev;
>   
>   	void __iomem *base;
> +	phys_addr_t base_phys;
>   	dma_addr_t base_dma;
>   
>   	struct clk *core_clk;
> @@ -467,6 +479,29 @@ static void free_bam_transaction(struct qcom_nand_controller *nandc)
>   	return bam_txn;
>   }
>   
> +/* Clears the BAM transaction indexes */
> +static void clear_bam_transaction(struct qcom_nand_controller *nandc)
> +{
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> +	if (!nandc->dma_bam_enabled)
> +		return;
> +
> +	bam_txn->bam_ce_pos = 0;
> +	bam_txn->bam_ce_start = 0;
> +	bam_txn->cmd_sgl_pos = 0;
> +	bam_txn->cmd_sgl_start = 0;
> +	bam_txn->tx_sgl_pos = 0;
> +	bam_txn->tx_sgl_start = 0;
> +	bam_txn->rx_sgl_pos = 0;
> +	bam_txn->rx_sgl_start = 0;
> +
> +	sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
> +		      QPIC_PER_CW_MAX_CMD_SGL);
> +	sg_init_table(bam_txn->data_sg, nandc->max_cwperpage *
> +		      QPIC_PER_CW_MAX_DATA_SGL);
> +}
> +
>   static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>   {
>   	return container_of(chip, struct qcom_nand_host, chip);
> @@ -682,6 +717,102 @@ static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
>   	return 0;
>   }
>   
> +/*
> + * Prepares the command descriptor for BAM DMA which will be used for NAND
> + * register reads and writes. The command descriptor requires the command
> + * to be formed in command element type so this function uses the command
> + * element from bam transaction ce array and fills the same with required
> + * data. A single SGL can contain multiple command elements so
> + * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
> + * after the current command element.
> + */
> +static int prep_dma_desc_command(struct qcom_nand_controller *nandc, bool read,
> +				 int reg_off, const void *vaddr,
> +				 int size, unsigned int flags)
> +{
> +	int bam_ce_size;
> +	int i, ret;
> +	struct bam_cmd_element *bam_ce_buffer;
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> +	bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
> +
> +	/* fill the command desc */
> +	for (i = 0; i < size; i++) {
> +		if (read)
> +			bam_prep_ce(&bam_ce_buffer[i],
> +				    NAND_REG_PHYS(nandc, reg_off + 4 * i),
> +				    BAM_READ_COMMAND,
> +				    REG_BUF_DMA_ADDR(nandc,
> +						     (__le32 *)vaddr + i));
> +		else
> +			bam_prep_ce_le32(&bam_ce_buffer[i],
> +					 NAND_REG_PHYS(nandc, reg_off + 4 * i),
> +					 BAM_WRITE_COMMAND,
> +					 *((__le32 *)vaddr + i));
> +	}
> +
> +	bam_txn->bam_ce_pos += size;
> +
> +	/* use the separate sgl after this command */
> +	if (flags & NAND_BAM_NEXT_SGL) {
> +		bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
> +		bam_ce_size = (bam_txn->bam_ce_pos -
> +				bam_txn->bam_ce_start) *
> +				sizeof(struct bam_cmd_element);
> +		sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
> +			   bam_ce_buffer, bam_ce_size);
> +		bam_txn->cmd_sgl_pos++;
> +		bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
> +
> +		if (flags & NAND_BAM_NWD) {
> +			ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
> +						     DMA_PREP_FENCE |
> +						     DMA_PREP_CMD);
> +			if (ret)
> +				return ret;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +/*
> + * Prepares the data descriptor for BAM DMA which will be used for NAND
> + * data reads and writes.
> + */
> +static int prep_dma_desc_data_bam(struct qcom_nand_controller *nandc, bool read,
> +				  int reg_off, const void *vaddr,
> +				  int size, unsigned int flags)
> +{
> +	int ret;
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> +	if (read) {
> +		sg_set_buf(&bam_txn->data_sg[bam_txn->rx_sgl_pos],
> +			   vaddr, size);
> +		bam_txn->rx_sgl_pos++;
> +	} else {
> +		sg_set_buf(&bam_txn->data_sg[bam_txn->tx_sgl_pos],
> +			   vaddr, size);
> +		bam_txn->tx_sgl_pos++;
> +
> +		/*
> +		 * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
> +		 * is not set, form the DMA descriptor
> +		 */
> +		if (!(flags & NAND_BAM_NO_EOT)) {
> +			ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
> +						     DMA_PREP_INTERRUPT);
> +			if (ret)
> +				return ret;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +/* Prepares the dma descriptor for adm dma engine */
>   static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
>   			 int reg_off, const void *vaddr, int size,
>   			 bool flow_control)
> @@ -764,16 +895,19 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
>   {
>   	bool flow_control = false;
>   	void *vaddr;
> -	int size;
>   
>   	if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
>   		flow_control = true;
>   
> -	size = num_regs * sizeof(u32);
>   	vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
>   	nandc->reg_read_pos += num_regs;
>   
> -	return prep_dma_desc(nandc, true, first, vaddr, size, flow_control);
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_command(nandc, true, first, vaddr,
> +					     num_regs, flags);
> +
> +	return prep_dma_desc(nandc, true, first, vaddr, num_regs * sizeof(u32),
> +			     flow_control);
>   }
>   
>   /*
> @@ -789,7 +923,6 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>   	bool flow_control = false;
>   	struct nandc_regs *regs = nandc->regs;
>   	void *vaddr;
> -	int size;
>   
>   	vaddr = offset_to_nandc_reg(regs, first);
>   
> @@ -812,9 +945,12 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>   	if (first == NAND_DEV_CMD_VLD_RESTORE)
>   		first = NAND_DEV_CMD_VLD;
>   
> -	size = num_regs * sizeof(u32);
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_command(nandc, false, first, vaddr,
> +					     num_regs, flags);
>   
> -	return prep_dma_desc(nandc, false, first, vaddr, size, flow_control);
> +	return prep_dma_desc(nandc, false, first, vaddr, num_regs * sizeof(u32),
> +			     flow_control);
>   }
>   
>   /*
> @@ -828,6 +964,10 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>   static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>   			 const u8 *vaddr, int size, unsigned int flags)
>   {
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_data_bam(nandc, true, reg_off, vaddr, size,
> +					      flags);
> +
>   	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
>   }
>   
> @@ -842,6 +982,10 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>   static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>   			  const u8 *vaddr, int size, unsigned int flags)
>   {
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_data_bam(nandc, false, reg_off, vaddr,
> +					      size, flags);
> +
>   	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
>   }
>   
> @@ -931,6 +1075,8 @@ static int nandc_param(struct qcom_nand_host *host)
>   	struct nand_chip *chip = &host->chip;
>   	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>   
> +	clear_bam_transaction(nandc);

For all the commands that go through chip->cmdfunc, can we move
clear_bam_transaction() calls to pre_command()?

Thanks,
Archit

>   	/*
>   	 * NAND_CMD_PARAM is called before we know much about the FLASH chip
>   	 * in use. we configure the controller to perform a raw read of 512
> @@ -993,6 +1139,8 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
>   	struct nand_chip *chip = &host->chip;
>   	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>   
> +	clear_bam_transaction(nandc);
> +
>   	nandc_set_reg(nandc, NAND_FLASH_CMD,
>   		      BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
>   	nandc_set_reg(nandc, NAND_ADDR0, page_addr);
> @@ -1025,10 +1173,13 @@ static int read_id(struct qcom_nand_host *host, int column)
>   	if (column == -1)
>   		return 0;
>   
> +	clear_bam_transaction(nandc);
> +
>   	nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
>   	nandc_set_reg(nandc, NAND_ADDR0, column);
>   	nandc_set_reg(nandc, NAND_ADDR1, 0);
> -	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
> +	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
> +		      nandc->dma_bam_enabled ? 0 : DM_EN);
>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>   
>   	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
> @@ -1045,6 +1196,8 @@ static int reset(struct qcom_nand_host *host)
>   	struct nand_chip *chip = &host->chip;
>   	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>   
> +	clear_bam_transaction(nandc);
> +
>   	nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>   
> @@ -1561,6 +1714,7 @@ static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
>   	data_buf = buf;
>   	oob_buf = oob_required ? chip->oob_poi : NULL;
>   
> +	clear_bam_transaction(nandc);
>   	ret = read_page_ecc(host, data_buf, oob_buf);
>   	if (ret) {
>   		dev_err(nandc->dev, "failure to read page\n");
> @@ -1585,6 +1739,8 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
>   	oob_buf = chip->oob_poi;
>   
>   	host->use_ecc = false;
> +
> +	clear_bam_transaction(nandc);
>   	update_rw_regs(host, ecc->steps, true);
>   
>   	for (i = 0; i < ecc->steps; i++) {
> @@ -1641,6 +1797,7 @@ static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
>   	int ret;
>   
>   	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>   
>   	host->use_ecc = true;
>   	set_address(host, 0, page);
> @@ -1664,6 +1821,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>   	int i, ret;
>   
>   	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>   
>   	data_buf = (u8 *)buf;
>   	oob_buf = chip->oob_poi;
> @@ -1729,6 +1887,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
>   	int i, ret;
>   
>   	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>   
>   	data_buf = (u8 *)buf;
>   	oob_buf = chip->oob_poi;
> @@ -1803,6 +1962,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
>   
>   	host->use_ecc = true;
>   
> +	clear_bam_transaction(nandc);
>   	ret = copy_last_cw(host, page);
>   	if (ret)
>   		return ret;
> @@ -1860,6 +2020,7 @@ static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs)
>   	 */
>   	host->use_ecc = false;
>   
> +	clear_bam_transaction(nandc);
>   	ret = copy_last_cw(host, page);
>   	if (ret)
>   		goto err;
> @@ -1890,6 +2051,7 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
>   	int page, ret, status = 0;
>   
>   	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>   
>   	/*
>   	 * to mark the BBM as bad, we flash the entire last codeword with 0s.
> @@ -2396,11 +2558,18 @@ static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
>   /* one time setup of a few nand controller registers */
>   static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
>   {
> +	u32 nand_ctrl;
> +
>   	/* kill onenand */
>   	nandc_write(nandc, SFLASHC_BURST_CFG, 0);
>   
> -	/* enable ADM DMA */
> -	nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
> +	/* enable ADM or BAM DMA */
> +	if (!nandc->dma_bam_enabled) {
> +		nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
> +	} else {
> +		nand_ctrl = nandc_read(nandc, NAND_CTRL);
> +		nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
> +	}
>   
>   	/* save the original values of these registers */
>   	nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
> @@ -2592,6 +2761,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>   	if (IS_ERR(nandc->base))
>   		return PTR_ERR(nandc->base);
>   
> +	nandc->base_phys = res->start;
>   	nandc->base_dma = phys_to_dma(dev, (phys_addr_t)res->start);
>   
>   	nandc->core_clk = devm_clk_get(dev, "core");
> 

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Re: [PATCH 10/14] qcom: mtd: nand: support for QPIC Page read/write

[Archit Taneja]

On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
> 1. Add the function for command descriptor preparation which
>     will be used only by BAM DMA and it will form the DMA descriptors
>     containing command elements.
> 
> 2. Add the data descriptor preparation function which will be used
>     only by BAM DMA for forming the data SGL’s.
> 
> 3. Add clear BAM transaction and call it before every new request
> 
> 4. Check DMA mode for ADM or BAM and call the appropriate
>     descriptor formation function.
> 
> 5. Enable the BAM in NAND_CTRL.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>   drivers/mtd/nand/qcom_nandc.c | 190 +++++++++++++++++++++++++++++++++++++++---
>   1 file changed, 180 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 17766af..4c6e594 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -156,6 +156,8 @@
>   #define	FETCH_ID			0xb
>   #define	RESET_DEVICE			0xd
>   
> +/* NAND_CTRL bits */
> +#define	BAM_MODE_EN			BIT(0)
>   /*
>    * the NAND controller performs reads/writes with ECC in 516 byte chunks.
>    * the driver calls the chunks 'step' or 'codeword' interchangeably
> @@ -190,6 +192,14 @@
>    */
>   #define NAND_ERASED_CW_SET		(0x0008)
>   
> +/* Returns the dma address for reg read buffer */
> +#define REG_BUF_DMA_ADDR(chip, vaddr) \
> +	((chip)->reg_read_buf_phys + \
> +	((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
> +
> +/* Returns the NAND register physical address */
> +#define NAND_REG_PHYS(chip, offset) ((chip)->base_phys + (offset))
> +
>   #define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
>   #define QPIC_PER_CW_MAX_CMD_SGL		(32)
>   #define QPIC_PER_CW_MAX_DATA_SGL	(8)
> @@ -287,7 +297,8 @@ struct nandc_regs {
>    *				controller
>    * @dev:			parent device
>    * @base:			MMIO base
> - * @base_dma:			physical base address of controller registers
> + * @base_phys:			physical base address of controller registers
> + * @base_dma:			dma base address of controller registers
>    * @core_clk:			controller clock
>    * @aon_clk:			another controller clock
>    *
> @@ -323,6 +334,7 @@ struct qcom_nand_controller {
>   	struct device *dev;
>   
>   	void __iomem *base;
> +	phys_addr_t base_phys;
>   	dma_addr_t base_dma;
>   
>   	struct clk *core_clk;
> @@ -467,6 +479,29 @@ static void free_bam_transaction(struct qcom_nand_controller *nandc)
>   	return bam_txn;
>   }
>   
> +/* Clears the BAM transaction indexes */
> +static void clear_bam_transaction(struct qcom_nand_controller *nandc)
> +{
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> +	if (!nandc->dma_bam_enabled)
> +		return;
> +
> +	bam_txn->bam_ce_pos = 0;
> +	bam_txn->bam_ce_start = 0;
> +	bam_txn->cmd_sgl_pos = 0;
> +	bam_txn->cmd_sgl_start = 0;
> +	bam_txn->tx_sgl_pos = 0;
> +	bam_txn->tx_sgl_start = 0;
> +	bam_txn->rx_sgl_pos = 0;
> +	bam_txn->rx_sgl_start = 0;
> +
> +	sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
> +		      QPIC_PER_CW_MAX_CMD_SGL);
> +	sg_init_table(bam_txn->data_sg, nandc->max_cwperpage *
> +		      QPIC_PER_CW_MAX_DATA_SGL);
> +}
> +
>   static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>   {
>   	return container_of(chip, struct qcom_nand_host, chip);
> @@ -682,6 +717,102 @@ static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
>   	return 0;
>   }
>   
> +/*
> + * Prepares the command descriptor for BAM DMA which will be used for NAND
> + * register reads and writes. The command descriptor requires the command
> + * to be formed in command element type so this function uses the command
> + * element from bam transaction ce array and fills the same with required
> + * data. A single SGL can contain multiple command elements so
> + * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
> + * after the current command element.
> + */
> +static int prep_dma_desc_command(struct qcom_nand_controller *nandc, bool read,
> +				 int reg_off, const void *vaddr,
> +				 int size, unsigned int flags)
> +{
> +	int bam_ce_size;
> +	int i, ret;
> +	struct bam_cmd_element *bam_ce_buffer;
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> +	bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
> +
> +	/* fill the command desc */
> +	for (i = 0; i < size; i++) {
> +		if (read)
> +			bam_prep_ce(&bam_ce_buffer[i],
> +				    NAND_REG_PHYS(nandc, reg_off + 4 * i),
> +				    BAM_READ_COMMAND,
> +				    REG_BUF_DMA_ADDR(nandc,
> +						     (__le32 *)vaddr + i));
> +		else
> +			bam_prep_ce_le32(&bam_ce_buffer[i],
> +					 NAND_REG_PHYS(nandc, reg_off + 4 * i),
> +					 BAM_WRITE_COMMAND,
> +					 *((__le32 *)vaddr + i));
> +	}
> +
> +	bam_txn->bam_ce_pos += size;
> +
> +	/* use the separate sgl after this command */
> +	if (flags & NAND_BAM_NEXT_SGL) {
> +		bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
> +		bam_ce_size = (bam_txn->bam_ce_pos -
> +				bam_txn->bam_ce_start) *
> +				sizeof(struct bam_cmd_element);
> +		sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
> +			   bam_ce_buffer, bam_ce_size);
> +		bam_txn->cmd_sgl_pos++;
> +		bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
> +
> +		if (flags & NAND_BAM_NWD) {
> +			ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
> +						     DMA_PREP_FENCE |
> +						     DMA_PREP_CMD);
> +			if (ret)
> +				return ret;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +/*
> + * Prepares the data descriptor for BAM DMA which will be used for NAND
> + * data reads and writes.
> + */
> +static int prep_dma_desc_data_bam(struct qcom_nand_controller *nandc, bool read,
> +				  int reg_off, const void *vaddr,
> +				  int size, unsigned int flags)
> +{
> +	int ret;
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> +	if (read) {
> +		sg_set_buf(&bam_txn->data_sg[bam_txn->rx_sgl_pos],
> +			   vaddr, size);
> +		bam_txn->rx_sgl_pos++;
> +	} else {
> +		sg_set_buf(&bam_txn->data_sg[bam_txn->tx_sgl_pos],
> +			   vaddr, size);
> +		bam_txn->tx_sgl_pos++;
> +
> +		/*
> +		 * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
> +		 * is not set, form the DMA descriptor
> +		 */
> +		if (!(flags & NAND_BAM_NO_EOT)) {
> +			ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
> +						     DMA_PREP_INTERRUPT);
> +			if (ret)
> +				return ret;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +/* Prepares the dma descriptor for adm dma engine */
>   static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
>   			 int reg_off, const void *vaddr, int size,
>   			 bool flow_control)
> @@ -764,16 +895,19 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
>   {
>   	bool flow_control = false;
>   	void *vaddr;
> -	int size;
>   
>   	if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
>   		flow_control = true;
>   
> -	size = num_regs * sizeof(u32);
>   	vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
>   	nandc->reg_read_pos += num_regs;
>   
> -	return prep_dma_desc(nandc, true, first, vaddr, size, flow_control);
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_command(nandc, true, first, vaddr,
> +					     num_regs, flags);
> +
> +	return prep_dma_desc(nandc, true, first, vaddr, num_regs * sizeof(u32),
> +			     flow_control);
>   }
>   
>   /*
> @@ -789,7 +923,6 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>   	bool flow_control = false;
>   	struct nandc_regs *regs = nandc->regs;
>   	void *vaddr;
> -	int size;
>   
>   	vaddr = offset_to_nandc_reg(regs, first);
>   
> @@ -812,9 +945,12 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>   	if (first == NAND_DEV_CMD_VLD_RESTORE)
>   		first = NAND_DEV_CMD_VLD;
>   
> -	size = num_regs * sizeof(u32);
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_command(nandc, false, first, vaddr,
> +					     num_regs, flags);
>   
> -	return prep_dma_desc(nandc, false, first, vaddr, size, flow_control);
> +	return prep_dma_desc(nandc, false, first, vaddr, num_regs * sizeof(u32),
> +			     flow_control);
>   }
>   
>   /*
> @@ -828,6 +964,10 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>   static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>   			 const u8 *vaddr, int size, unsigned int flags)
>   {
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_data_bam(nandc, true, reg_off, vaddr, size,
> +					      flags);
> +
>   	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
>   }
>   
> @@ -842,6 +982,10 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>   static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>   			  const u8 *vaddr, int size, unsigned int flags)
>   {
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_data_bam(nandc, false, reg_off, vaddr,
> +					      size, flags);
> +
>   	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
>   }
>   
> @@ -931,6 +1075,8 @@ static int nandc_param(struct qcom_nand_host *host)
>   	struct nand_chip *chip = &host->chip;
>   	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>   
> +	clear_bam_transaction(nandc);

For all the commands that go through chip->cmdfunc, can we move
clear_bam_transaction() calls to pre_command()?

Thanks,
Archit

>   	/*
>   	 * NAND_CMD_PARAM is called before we know much about the FLASH chip
>   	 * in use. we configure the controller to perform a raw read of 512
> @@ -993,6 +1139,8 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
>   	struct nand_chip *chip = &host->chip;
>   	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>   
> +	clear_bam_transaction(nandc);
> +
>   	nandc_set_reg(nandc, NAND_FLASH_CMD,
>   		      BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
>   	nandc_set_reg(nandc, NAND_ADDR0, page_addr);
> @@ -1025,10 +1173,13 @@ static int read_id(struct qcom_nand_host *host, int column)
>   	if (column == -1)
>   		return 0;
>   
> +	clear_bam_transaction(nandc);
> +
>   	nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
>   	nandc_set_reg(nandc, NAND_ADDR0, column);
>   	nandc_set_reg(nandc, NAND_ADDR1, 0);
> -	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
> +	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
> +		      nandc->dma_bam_enabled ? 0 : DM_EN);
>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>   
>   	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
> @@ -1045,6 +1196,8 @@ static int reset(struct qcom_nand_host *host)
>   	struct nand_chip *chip = &host->chip;
>   	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>   
> +	clear_bam_transaction(nandc);
> +
>   	nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>   
> @@ -1561,6 +1714,7 @@ static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
>   	data_buf = buf;
>   	oob_buf = oob_required ? chip->oob_poi : NULL;
>   
> +	clear_bam_transaction(nandc);
>   	ret = read_page_ecc(host, data_buf, oob_buf);
>   	if (ret) {
>   		dev_err(nandc->dev, "failure to read page\n");
> @@ -1585,6 +1739,8 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
>   	oob_buf = chip->oob_poi;
>   
>   	host->use_ecc = false;
> +
> +	clear_bam_transaction(nandc);
>   	update_rw_regs(host, ecc->steps, true);
>   
>   	for (i = 0; i < ecc->steps; i++) {
> @@ -1641,6 +1797,7 @@ static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
>   	int ret;
>   
>   	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>   
>   	host->use_ecc = true;
>   	set_address(host, 0, page);
> @@ -1664,6 +1821,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>   	int i, ret;
>   
>   	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>   
>   	data_buf = (u8 *)buf;
>   	oob_buf = chip->oob_poi;
> @@ -1729,6 +1887,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
>   	int i, ret;
>   
>   	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>   
>   	data_buf = (u8 *)buf;
>   	oob_buf = chip->oob_poi;
> @@ -1803,6 +1962,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
>   
>   	host->use_ecc = true;
>   
> +	clear_bam_transaction(nandc);
>   	ret = copy_last_cw(host, page);
>   	if (ret)
>   		return ret;
> @@ -1860,6 +2020,7 @@ static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs)
>   	 */
>   	host->use_ecc = false;
>   
> +	clear_bam_transaction(nandc);
>   	ret = copy_last_cw(host, page);
>   	if (ret)
>   		goto err;
> @@ -1890,6 +2051,7 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
>   	int page, ret, status = 0;
>   
>   	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>   
>   	/*
>   	 * to mark the BBM as bad, we flash the entire last codeword with 0s.
> @@ -2396,11 +2558,18 @@ static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
>   /* one time setup of a few nand controller registers */
>   static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
>   {
> +	u32 nand_ctrl;
> +
>   	/* kill onenand */
>   	nandc_write(nandc, SFLASHC_BURST_CFG, 0);
>   
> -	/* enable ADM DMA */
> -	nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
> +	/* enable ADM or BAM DMA */
> +	if (!nandc->dma_bam_enabled) {
> +		nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
> +	} else {
> +		nand_ctrl = nandc_read(nandc, NAND_CTRL);
> +		nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
> +	}
>   
>   	/* save the original values of these registers */
>   	nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
> @@ -2592,6 +2761,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>   	if (IS_ERR(nandc->base))
>   		return PTR_ERR(nandc->base);
>   
> +	nandc->base_phys = res->start;
>   	nandc->base_dma = phys_to_dma(dev, (phys_addr_t)res->start);
>   
>   	nandc->core_clk = devm_clk_get(dev, "core");
> 

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 10/14] qcom: mtd: nand: support for QPIC Page read/write

[Abhishek Sahu]

On 2017-07-04 15:14, Archit Taneja wrote:
> On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
>> 1. Add the function for command descriptor preparation which
>>     will be used only by BAM DMA and it will form the DMA descriptors
>>     containing command elements.
>> 
>> 2. Add the data descriptor preparation function which will be used
>>     only by BAM DMA for forming the data SGL’s.
>> 
>> 3. Add clear BAM transaction and call it before every new request
>> 
>> 4. Check DMA mode for ADM or BAM and call the appropriate
>>     descriptor formation function.
>> 
>> 5. Enable the BAM in NAND_CTRL.
>> 
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> ---
>>   drivers/mtd/nand/qcom_nandc.c | 190 
>> +++++++++++++++++++++++++++++++++++++++---
>>   1 file changed, 180 insertions(+), 10 deletions(-)
>> 
>> diff --git a/drivers/mtd/nand/qcom_nandc.c 
>> b/drivers/mtd/nand/qcom_nandc.c
>> index 17766af..4c6e594 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -156,6 +156,8 @@
>>   #define	FETCH_ID			0xb
>>   #define	RESET_DEVICE			0xd
>> 
>> +/* NAND_CTRL bits */
>> +#define	BAM_MODE_EN			BIT(0)
>>   /*
>>    * the NAND controller performs reads/writes with ECC in 516 byte 
>> chunks.
>>    * the driver calls the chunks 'step' or 'codeword' interchangeably
>> @@ -190,6 +192,14 @@
>>    */
>>   #define NAND_ERASED_CW_SET		(0x0008)
>> 
>> +/* Returns the dma address for reg read buffer */
>> +#define REG_BUF_DMA_ADDR(chip, vaddr) \
>> +	((chip)->reg_read_buf_phys + \
>> +	((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
>> +
>> +/* Returns the NAND register physical address */
>> +#define NAND_REG_PHYS(chip, offset) ((chip)->base_phys + (offset))
>> +
>>   #define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
>>   #define QPIC_PER_CW_MAX_CMD_SGL		(32)
>>   #define QPIC_PER_CW_MAX_DATA_SGL	(8)
>> @@ -287,7 +297,8 @@ struct nandc_regs {
>>    *				controller
>>    * @dev:			parent device
>>    * @base:			MMIO base
>> - * @base_dma:			physical base address of controller registers
>> + * @base_phys:			physical base address of controller registers
>> + * @base_dma:			dma base address of controller registers
>>    * @core_clk:			controller clock
>>    * @aon_clk:			another controller clock
>>    *
>> @@ -323,6 +334,7 @@ struct qcom_nand_controller {
>>   	struct device *dev;
>> 
>>   	void __iomem *base;
>> +	phys_addr_t base_phys;
>>   	dma_addr_t base_dma;
>> 
>>   	struct clk *core_clk;
>> @@ -467,6 +479,29 @@ static void free_bam_transaction(struct 
>> qcom_nand_controller *nandc)
>>   	return bam_txn;
>>   }
>> 
>> +/* Clears the BAM transaction indexes */
>> +static void clear_bam_transaction(struct qcom_nand_controller *nandc)
>> +{
>> +	struct bam_transaction *bam_txn = nandc->bam_txn;
>> +
>> +	if (!nandc->dma_bam_enabled)
>> +		return;
>> +
>> +	bam_txn->bam_ce_pos = 0;
>> +	bam_txn->bam_ce_start = 0;
>> +	bam_txn->cmd_sgl_pos = 0;
>> +	bam_txn->cmd_sgl_start = 0;
>> +	bam_txn->tx_sgl_pos = 0;
>> +	bam_txn->tx_sgl_start = 0;
>> +	bam_txn->rx_sgl_pos = 0;
>> +	bam_txn->rx_sgl_start = 0;
>> +
>> +	sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
>> +		      QPIC_PER_CW_MAX_CMD_SGL);
>> +	sg_init_table(bam_txn->data_sg, nandc->max_cwperpage *
>> +		      QPIC_PER_CW_MAX_DATA_SGL);
>> +}
>> +
>>   static inline struct qcom_nand_host *to_qcom_nand_host(struct 
>> nand_chip *chip)
>>   {
>>   	return container_of(chip, struct qcom_nand_host, chip);
>> @@ -682,6 +717,102 @@ static int prepare_bam_async_desc(struct 
>> qcom_nand_controller *nandc,
>>   	return 0;
>>   }
>> 
>> +/*
>> + * Prepares the command descriptor for BAM DMA which will be used for 
>> NAND
>> + * register reads and writes. The command descriptor requires the 
>> command
>> + * to be formed in command element type so this function uses the 
>> command
>> + * element from bam transaction ce array and fills the same with 
>> required
>> + * data. A single SGL can contain multiple command elements so
>> + * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
>> + * after the current command element.
>> + */
>> +static int prep_dma_desc_command(struct qcom_nand_controller *nandc, 
>> bool read,
>> +				 int reg_off, const void *vaddr,
>> +				 int size, unsigned int flags)
>> +{
>> +	int bam_ce_size;
>> +	int i, ret;
>> +	struct bam_cmd_element *bam_ce_buffer;
>> +	struct bam_transaction *bam_txn = nandc->bam_txn;
>> +
>> +	bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
>> +
>> +	/* fill the command desc */
>> +	for (i = 0; i < size; i++) {
>> +		if (read)
>> +			bam_prep_ce(&bam_ce_buffer[i],
>> +				    NAND_REG_PHYS(nandc, reg_off + 4 * i),
>> +				    BAM_READ_COMMAND,
>> +				    REG_BUF_DMA_ADDR(nandc,
>> +						     (__le32 *)vaddr + i));
>> +		else
>> +			bam_prep_ce_le32(&bam_ce_buffer[i],
>> +					 NAND_REG_PHYS(nandc, reg_off + 4 * i),
>> +					 BAM_WRITE_COMMAND,
>> +					 *((__le32 *)vaddr + i));
>> +	}
>> +
>> +	bam_txn->bam_ce_pos += size;
>> +
>> +	/* use the separate sgl after this command */
>> +	if (flags & NAND_BAM_NEXT_SGL) {
>> +		bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
>> +		bam_ce_size = (bam_txn->bam_ce_pos -
>> +				bam_txn->bam_ce_start) *
>> +				sizeof(struct bam_cmd_element);
>> +		sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
>> +			   bam_ce_buffer, bam_ce_size);
>> +		bam_txn->cmd_sgl_pos++;
>> +		bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
>> +
>> +		if (flags & NAND_BAM_NWD) {
>> +			ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
>> +						     DMA_PREP_FENCE |
>> +						     DMA_PREP_CMD);
>> +			if (ret)
>> +				return ret;
>> +		}
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +/*
>> + * Prepares the data descriptor for BAM DMA which will be used for 
>> NAND
>> + * data reads and writes.
>> + */
>> +static int prep_dma_desc_data_bam(struct qcom_nand_controller *nandc, 
>> bool read,
>> +				  int reg_off, const void *vaddr,
>> +				  int size, unsigned int flags)
>> +{
>> +	int ret;
>> +	struct bam_transaction *bam_txn = nandc->bam_txn;
>> +
>> +	if (read) {
>> +		sg_set_buf(&bam_txn->data_sg[bam_txn->rx_sgl_pos],
>> +			   vaddr, size);
>> +		bam_txn->rx_sgl_pos++;
>> +	} else {
>> +		sg_set_buf(&bam_txn->data_sg[bam_txn->tx_sgl_pos],
>> +			   vaddr, size);
>> +		bam_txn->tx_sgl_pos++;
>> +
>> +		/*
>> +		 * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
>> +		 * is not set, form the DMA descriptor
>> +		 */
>> +		if (!(flags & NAND_BAM_NO_EOT)) {
>> +			ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
>> +						     DMA_PREP_INTERRUPT);
>> +			if (ret)
>> +				return ret;
>> +		}
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +/* Prepares the dma descriptor for adm dma engine */
>>   static int prep_dma_desc(struct qcom_nand_controller *nandc, bool 
>> read,
>>   			 int reg_off, const void *vaddr, int size,
>>   			 bool flow_control)
>> @@ -764,16 +895,19 @@ static int read_reg_dma(struct 
>> qcom_nand_controller *nandc, int first,
>>   {
>>   	bool flow_control = false;
>>   	void *vaddr;
>> -	int size;
>> 
>>   	if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
>>   		flow_control = true;
>> 
>> -	size = num_regs * sizeof(u32);
>>   	vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
>>   	nandc->reg_read_pos += num_regs;
>> 
>> -	return prep_dma_desc(nandc, true, first, vaddr, size, flow_control);
>> +	if (nandc->dma_bam_enabled)
>> +		return prep_dma_desc_command(nandc, true, first, vaddr,
>> +					     num_regs, flags);
>> +
>> +	return prep_dma_desc(nandc, true, first, vaddr, num_regs * 
>> sizeof(u32),
>> +			     flow_control);
>>   }
>> 
>>   /*
>> @@ -789,7 +923,6 @@ static int write_reg_dma(struct 
>> qcom_nand_controller *nandc, int first,
>>   	bool flow_control = false;
>>   	struct nandc_regs *regs = nandc->regs;
>>   	void *vaddr;
>> -	int size;
>> 
>>   	vaddr = offset_to_nandc_reg(regs, first);
>> 
>> @@ -812,9 +945,12 @@ static int write_reg_dma(struct 
>> qcom_nand_controller *nandc, int first,
>>   	if (first == NAND_DEV_CMD_VLD_RESTORE)
>>   		first = NAND_DEV_CMD_VLD;
>> 
>> -	size = num_regs * sizeof(u32);
>> +	if (nandc->dma_bam_enabled)
>> +		return prep_dma_desc_command(nandc, false, first, vaddr,
>> +					     num_regs, flags);
>> 
>> -	return prep_dma_desc(nandc, false, first, vaddr, size, 
>> flow_control);
>> +	return prep_dma_desc(nandc, false, first, vaddr, num_regs * 
>> sizeof(u32),
>> +			     flow_control);
>>   }
>> 
>>   /*
>> @@ -828,6 +964,10 @@ static int write_reg_dma(struct 
>> qcom_nand_controller *nandc, int first,
>>   static int read_data_dma(struct qcom_nand_controller *nandc, int 
>> reg_off,
>>   			 const u8 *vaddr, int size, unsigned int flags)
>>   {
>> +	if (nandc->dma_bam_enabled)
>> +		return prep_dma_desc_data_bam(nandc, true, reg_off, vaddr, size,
>> +					      flags);
>> +
>>   	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
>>   }
>> 
>> @@ -842,6 +982,10 @@ static int read_data_dma(struct 
>> qcom_nand_controller *nandc, int reg_off,
>>   static int write_data_dma(struct qcom_nand_controller *nandc, int 
>> reg_off,
>>   			  const u8 *vaddr, int size, unsigned int flags)
>>   {
>> +	if (nandc->dma_bam_enabled)
>> +		return prep_dma_desc_data_bam(nandc, false, reg_off, vaddr,
>> +					      size, flags);
>> +
>>   	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
>>   }
>> 
>> @@ -931,6 +1075,8 @@ static int nandc_param(struct qcom_nand_host 
>> *host)
>>   	struct nand_chip *chip = &host->chip;
>>   	struct qcom_nand_controller *nandc = 
>> get_qcom_nand_controller(chip);
>> 
>> +	clear_bam_transaction(nandc);
> 
> For all the commands that go through chip->cmdfunc, can we move
> clear_bam_transaction() calls to pre_command()?
> 

  Sure. I will move this in pre_command.

> Thanks,
> Archit
> 
>>   	/*
>>   	 * NAND_CMD_PARAM is called before we know much about the FLASH 
>> chip
>>   	 * in use. we configure the controller to perform a raw read of 512
>> @@ -993,6 +1139,8 @@ static int erase_block(struct qcom_nand_host 
>> *host, int page_addr)
>>   	struct nand_chip *chip = &host->chip;
>>   	struct qcom_nand_controller *nandc = 
>> get_qcom_nand_controller(chip);
>> 
>> +	clear_bam_transaction(nandc);
>> +
>>   	nandc_set_reg(nandc, NAND_FLASH_CMD,
>>   		      BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
>>   	nandc_set_reg(nandc, NAND_ADDR0, page_addr);
>> @@ -1025,10 +1173,13 @@ static int read_id(struct qcom_nand_host 
>> *host, int column)
>>   	if (column == -1)
>>   		return 0;
>> 
>> +	clear_bam_transaction(nandc);
>> +
>>   	nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
>>   	nandc_set_reg(nandc, NAND_ADDR0, column);
>>   	nandc_set_reg(nandc, NAND_ADDR1, 0);
>> -	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
>> +	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
>> +		      nandc->dma_bam_enabled ? 0 : DM_EN);
>>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>> 
>>   	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
>> @@ -1045,6 +1196,8 @@ static int reset(struct qcom_nand_host *host)
>>   	struct nand_chip *chip = &host->chip;
>>   	struct qcom_nand_controller *nandc = 
>> get_qcom_nand_controller(chip);
>> 
>> +	clear_bam_transaction(nandc);
>> +
>>   	nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
>>   	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>> 
>> @@ -1561,6 +1714,7 @@ static int qcom_nandc_read_page(struct mtd_info 
>> *mtd, struct nand_chip *chip,
>>   	data_buf = buf;
>>   	oob_buf = oob_required ? chip->oob_poi : NULL;
>> 
>> +	clear_bam_transaction(nandc);
>>   	ret = read_page_ecc(host, data_buf, oob_buf);
>>   	if (ret) {
>>   		dev_err(nandc->dev, "failure to read page\n");
>> @@ -1585,6 +1739,8 @@ static int qcom_nandc_read_page_raw(struct 
>> mtd_info *mtd,
>>   	oob_buf = chip->oob_poi;
>> 
>>   	host->use_ecc = false;
>> +
>> +	clear_bam_transaction(nandc);
>>   	update_rw_regs(host, ecc->steps, true);
>> 
>>   	for (i = 0; i < ecc->steps; i++) {
>> @@ -1641,6 +1797,7 @@ static int qcom_nandc_read_oob(struct mtd_info 
>> *mtd, struct nand_chip *chip,
>>   	int ret;
>> 
>>   	clear_read_regs(nandc);
>> +	clear_bam_transaction(nandc);
>> 
>>   	host->use_ecc = true;
>>   	set_address(host, 0, page);
>> @@ -1664,6 +1821,7 @@ static int qcom_nandc_write_page(struct mtd_info 
>> *mtd, struct nand_chip *chip,
>>   	int i, ret;
>> 
>>   	clear_read_regs(nandc);
>> +	clear_bam_transaction(nandc);
>> 
>>   	data_buf = (u8 *)buf;
>>   	oob_buf = chip->oob_poi;
>> @@ -1729,6 +1887,7 @@ static int qcom_nandc_write_page_raw(struct 
>> mtd_info *mtd,
>>   	int i, ret;
>> 
>>   	clear_read_regs(nandc);
>> +	clear_bam_transaction(nandc);
>> 
>>   	data_buf = (u8 *)buf;
>>   	oob_buf = chip->oob_poi;
>> @@ -1803,6 +1962,7 @@ static int qcom_nandc_write_oob(struct mtd_info 
>> *mtd, struct nand_chip *chip,
>> 
>>   	host->use_ecc = true;
>> 
>> +	clear_bam_transaction(nandc);
>>   	ret = copy_last_cw(host, page);
>>   	if (ret)
>>   		return ret;
>> @@ -1860,6 +2020,7 @@ static int qcom_nandc_block_bad(struct mtd_info 
>> *mtd, loff_t ofs)
>>   	 */
>>   	host->use_ecc = false;
>> 
>> +	clear_bam_transaction(nandc);
>>   	ret = copy_last_cw(host, page);
>>   	if (ret)
>>   		goto err;
>> @@ -1890,6 +2051,7 @@ static int qcom_nandc_block_markbad(struct 
>> mtd_info *mtd, loff_t ofs)
>>   	int page, ret, status = 0;
>> 
>>   	clear_read_regs(nandc);
>> +	clear_bam_transaction(nandc);
>> 
>>   	/*
>>   	 * to mark the BBM as bad, we flash the entire last codeword with 
>> 0s.
>> @@ -2396,11 +2558,18 @@ static void qcom_nandc_unalloc(struct 
>> qcom_nand_controller *nandc)
>>   /* one time setup of a few nand controller registers */
>>   static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
>>   {
>> +	u32 nand_ctrl;
>> +
>>   	/* kill onenand */
>>   	nandc_write(nandc, SFLASHC_BURST_CFG, 0);
>> 
>> -	/* enable ADM DMA */
>> -	nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
>> +	/* enable ADM or BAM DMA */
>> +	if (!nandc->dma_bam_enabled) {
>> +		nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
>> +	} else {
>> +		nand_ctrl = nandc_read(nandc, NAND_CTRL);
>> +		nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
>> +	}
>> 
>>   	/* save the original values of these registers */
>>   	nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
>> @@ -2592,6 +2761,7 @@ static int qcom_nandc_probe(struct 
>> platform_device *pdev)
>>   	if (IS_ERR(nandc->base))
>>   		return PTR_ERR(nandc->base);
>> 
>> +	nandc->base_phys = res->start;
>>   	nandc->base_dma = phys_to_dma(dev, (phys_addr_t)res->start);
>> 
>>   	nandc->core_clk = devm_clk_get(dev, "core");
>> 

-- 
Abhishek Sahu

Re: [PATCH 10/14] qcom: mtd: nand: support for QPIC Page read/write

[Sricharan R]

On 6/29/2017 12:46 PM, Abhishek Sahu wrote:
> 1. Add the function for command descriptor preparation which
>    will be used only by BAM DMA and it will form the DMA descriptors
>    containing command elements.
> 
> 2. Add the data descriptor preparation function which will be used
>    only by BAM DMA for forming the data SGL’s.
> 
> 3. Add clear BAM transaction and call it before every new request
> 
> 4. Check DMA mode for ADM or BAM and call the appropriate
>    descriptor formation function.
> 
> 5. Enable the BAM in NAND_CTRL.
> 

Should this patch be patch #8 and then add other support ?

Regards,
 Sricharan


> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>  drivers/mtd/nand/qcom_nandc.c | 190 +++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 180 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 17766af..4c6e594 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -156,6 +156,8 @@
>  #define	FETCH_ID			0xb
>  #define	RESET_DEVICE			0xd
>  
> +/* NAND_CTRL bits */
> +#define	BAM_MODE_EN			BIT(0)
>  /*
>   * the NAND controller performs reads/writes with ECC in 516 byte chunks.
>   * the driver calls the chunks 'step' or 'codeword' interchangeably
> @@ -190,6 +192,14 @@
>   */
>  #define NAND_ERASED_CW_SET		(0x0008)
>  
> +/* Returns the dma address for reg read buffer */
> +#define REG_BUF_DMA_ADDR(chip, vaddr) \
> +	((chip)->reg_read_buf_phys + \
> +	((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
> +
> +/* Returns the NAND register physical address */
> +#define NAND_REG_PHYS(chip, offset) ((chip)->base_phys + (offset))
> +
>  #define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
>  #define QPIC_PER_CW_MAX_CMD_SGL		(32)
>  #define QPIC_PER_CW_MAX_DATA_SGL	(8)
> @@ -287,7 +297,8 @@ struct nandc_regs {
>   *				controller
>   * @dev:			parent device
>   * @base:			MMIO base
> - * @base_dma:			physical base address of controller registers
> + * @base_phys:			physical base address of controller registers
> + * @base_dma:			dma base address of controller registers
>   * @core_clk:			controller clock
>   * @aon_clk:			another controller clock
>   *
> @@ -323,6 +334,7 @@ struct qcom_nand_controller {
>  	struct device *dev;
>  
>  	void __iomem *base;
> +	phys_addr_t base_phys;
>  	dma_addr_t base_dma;
>  
>  	struct clk *core_clk;
> @@ -467,6 +479,29 @@ static void free_bam_transaction(struct qcom_nand_controller *nandc)
>  	return bam_txn;
>  }
>  
> +/* Clears the BAM transaction indexes */
> +static void clear_bam_transaction(struct qcom_nand_controller *nandc)
> +{
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> +	if (!nandc->dma_bam_enabled)
> +		return;
> +
> +	bam_txn->bam_ce_pos = 0;
> +	bam_txn->bam_ce_start = 0;
> +	bam_txn->cmd_sgl_pos = 0;
> +	bam_txn->cmd_sgl_start = 0;
> +	bam_txn->tx_sgl_pos = 0;
> +	bam_txn->tx_sgl_start = 0;
> +	bam_txn->rx_sgl_pos = 0;
> +	bam_txn->rx_sgl_start = 0;
> +
> +	sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
> +		      QPIC_PER_CW_MAX_CMD_SGL);
> +	sg_init_table(bam_txn->data_sg, nandc->max_cwperpage *
> +		      QPIC_PER_CW_MAX_DATA_SGL);
> +}
> +
>  static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>  {
>  	return container_of(chip, struct qcom_nand_host, chip);
> @@ -682,6 +717,102 @@ static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
>  	return 0;
>  }
>  
> +/*
> + * Prepares the command descriptor for BAM DMA which will be used for NAND
> + * register reads and writes. The command descriptor requires the command
> + * to be formed in command element type so this function uses the command
> + * element from bam transaction ce array and fills the same with required
> + * data. A single SGL can contain multiple command elements so
> + * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
> + * after the current command element.
> + */
> +static int prep_dma_desc_command(struct qcom_nand_controller *nandc, bool read,
> +				 int reg_off, const void *vaddr,
> +				 int size, unsigned int flags)
> +{
> +	int bam_ce_size;
> +	int i, ret;
> +	struct bam_cmd_element *bam_ce_buffer;
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> +	bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
> +
> +	/* fill the command desc */
> +	for (i = 0; i < size; i++) {
> +		if (read)
> +			bam_prep_ce(&bam_ce_buffer[i],
> +				    NAND_REG_PHYS(nandc, reg_off + 4 * i),
> +				    BAM_READ_COMMAND,
> +				    REG_BUF_DMA_ADDR(nandc,
> +						     (__le32 *)vaddr + i));
> +		else
> +			bam_prep_ce_le32(&bam_ce_buffer[i],
> +					 NAND_REG_PHYS(nandc, reg_off + 4 * i),
> +					 BAM_WRITE_COMMAND,
> +					 *((__le32 *)vaddr + i));
> +	}
> +
> +	bam_txn->bam_ce_pos += size;
> +
> +	/* use the separate sgl after this command */
> +	if (flags & NAND_BAM_NEXT_SGL) {
> +		bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
> +		bam_ce_size = (bam_txn->bam_ce_pos -
> +				bam_txn->bam_ce_start) *
> +				sizeof(struct bam_cmd_element);
> +		sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
> +			   bam_ce_buffer, bam_ce_size);
> +		bam_txn->cmd_sgl_pos++;
> +		bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
> +
> +		if (flags & NAND_BAM_NWD) {
> +			ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
> +						     DMA_PREP_FENCE |
> +						     DMA_PREP_CMD);
> +			if (ret)
> +				return ret;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +/*
> + * Prepares the data descriptor for BAM DMA which will be used for NAND
> + * data reads and writes.
> + */
> +static int prep_dma_desc_data_bam(struct qcom_nand_controller *nandc, bool read,
> +				  int reg_off, const void *vaddr,
> +				  int size, unsigned int flags)
> +{
> +	int ret;
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> +	if (read) {
> +		sg_set_buf(&bam_txn->data_sg[bam_txn->rx_sgl_pos],
> +			   vaddr, size);
> +		bam_txn->rx_sgl_pos++;
> +	} else {
> +		sg_set_buf(&bam_txn->data_sg[bam_txn->tx_sgl_pos],
> +			   vaddr, size);
> +		bam_txn->tx_sgl_pos++;
> +
> +		/*
> +		 * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
> +		 * is not set, form the DMA descriptor
> +		 */
> +		if (!(flags & NAND_BAM_NO_EOT)) {
> +			ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
> +						     DMA_PREP_INTERRUPT);
> +			if (ret)
> +				return ret;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +/* Prepares the dma descriptor for adm dma engine */
>  static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
>  			 int reg_off, const void *vaddr, int size,
>  			 bool flow_control)
> @@ -764,16 +895,19 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
>  {
>  	bool flow_control = false;
>  	void *vaddr;
> -	int size;
>  
>  	if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
>  		flow_control = true;
>  
> -	size = num_regs * sizeof(u32);
>  	vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
>  	nandc->reg_read_pos += num_regs;
>  
> -	return prep_dma_desc(nandc, true, first, vaddr, size, flow_control);
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_command(nandc, true, first, vaddr,
> +					     num_regs, flags);
> +
> +	return prep_dma_desc(nandc, true, first, vaddr, num_regs * sizeof(u32),
> +			     flow_control);
>  }
>  
>  /*
> @@ -789,7 +923,6 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>  	bool flow_control = false;
>  	struct nandc_regs *regs = nandc->regs;
>  	void *vaddr;
> -	int size;
>  
>  	vaddr = offset_to_nandc_reg(regs, first);
>  
> @@ -812,9 +945,12 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>  	if (first == NAND_DEV_CMD_VLD_RESTORE)
>  		first = NAND_DEV_CMD_VLD;
>  
> -	size = num_regs * sizeof(u32);
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_command(nandc, false, first, vaddr,
> +					     num_regs, flags);
>  
> -	return prep_dma_desc(nandc, false, first, vaddr, size, flow_control);
> +	return prep_dma_desc(nandc, false, first, vaddr, num_regs * sizeof(u32),
> +			     flow_control);
>  }
>  
>  /*
> @@ -828,6 +964,10 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>  static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>  			 const u8 *vaddr, int size, unsigned int flags)
>  {
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_data_bam(nandc, true, reg_off, vaddr, size,
> +					      flags);
> +
>  	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
>  }
>  
> @@ -842,6 +982,10 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>  static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>  			  const u8 *vaddr, int size, unsigned int flags)
>  {
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_data_bam(nandc, false, reg_off, vaddr,
> +					      size, flags);
> +
>  	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
>  }
>  
> @@ -931,6 +1075,8 @@ static int nandc_param(struct qcom_nand_host *host)
>  	struct nand_chip *chip = &host->chip;
>  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>  
> +	clear_bam_transaction(nandc);
> +
>  	/*
>  	 * NAND_CMD_PARAM is called before we know much about the FLASH chip
>  	 * in use. we configure the controller to perform a raw read of 512
> @@ -993,6 +1139,8 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
>  	struct nand_chip *chip = &host->chip;
>  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>  
> +	clear_bam_transaction(nandc);
> +
>  	nandc_set_reg(nandc, NAND_FLASH_CMD,
>  		      BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
>  	nandc_set_reg(nandc, NAND_ADDR0, page_addr);
> @@ -1025,10 +1173,13 @@ static int read_id(struct qcom_nand_host *host, int column)
>  	if (column == -1)
>  		return 0;
>  
> +	clear_bam_transaction(nandc);
> +
>  	nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
>  	nandc_set_reg(nandc, NAND_ADDR0, column);
>  	nandc_set_reg(nandc, NAND_ADDR1, 0);
> -	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
> +	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
> +		      nandc->dma_bam_enabled ? 0 : DM_EN);
>  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>  
>  	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
> @@ -1045,6 +1196,8 @@ static int reset(struct qcom_nand_host *host)
>  	struct nand_chip *chip = &host->chip;
>  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>  
> +	clear_bam_transaction(nandc);
> +
>  	nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
>  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>  
> @@ -1561,6 +1714,7 @@ static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
>  	data_buf = buf;
>  	oob_buf = oob_required ? chip->oob_poi : NULL;
>  
> +	clear_bam_transaction(nandc);
>  	ret = read_page_ecc(host, data_buf, oob_buf);
>  	if (ret) {
>  		dev_err(nandc->dev, "failure to read page\n");
> @@ -1585,6 +1739,8 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
>  	oob_buf = chip->oob_poi;
>  
>  	host->use_ecc = false;
> +
> +	clear_bam_transaction(nandc);
>  	update_rw_regs(host, ecc->steps, true);
>  
>  	for (i = 0; i < ecc->steps; i++) {
> @@ -1641,6 +1797,7 @@ static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
>  	int ret;
>  
>  	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>  
>  	host->use_ecc = true;
>  	set_address(host, 0, page);
> @@ -1664,6 +1821,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>  	int i, ret;
>  
>  	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>  
>  	data_buf = (u8 *)buf;
>  	oob_buf = chip->oob_poi;
> @@ -1729,6 +1887,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
>  	int i, ret;
>  
>  	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>  
>  	data_buf = (u8 *)buf;
>  	oob_buf = chip->oob_poi;
> @@ -1803,6 +1962,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
>  
>  	host->use_ecc = true;
>  
> +	clear_bam_transaction(nandc);
>  	ret = copy_last_cw(host, page);
>  	if (ret)
>  		return ret;
> @@ -1860,6 +2020,7 @@ static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs)
>  	 */
>  	host->use_ecc = false;
>  
> +	clear_bam_transaction(nandc);
>  	ret = copy_last_cw(host, page);
>  	if (ret)
>  		goto err;
> @@ -1890,6 +2051,7 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
>  	int page, ret, status = 0;
>  
>  	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>  
>  	/*
>  	 * to mark the BBM as bad, we flash the entire last codeword with 0s.
> @@ -2396,11 +2558,18 @@ static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
>  /* one time setup of a few nand controller registers */
>  static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
>  {
> +	u32 nand_ctrl;
> +
>  	/* kill onenand */
>  	nandc_write(nandc, SFLASHC_BURST_CFG, 0);
>  
> -	/* enable ADM DMA */
> -	nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
> +	/* enable ADM or BAM DMA */
> +	if (!nandc->dma_bam_enabled) {
> +		nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
> +	} else {
> +		nand_ctrl = nandc_read(nandc, NAND_CTRL);
> +		nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
> +	}
>  
>  	/* save the original values of these registers */
>  	nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
> @@ -2592,6 +2761,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>  	if (IS_ERR(nandc->base))
>  		return PTR_ERR(nandc->base);
>  
> +	nandc->base_phys = res->start;
>  	nandc->base_dma = phys_to_dma(dev, (phys_addr_t)res->start);
>  
>  	nandc->core_clk = devm_clk_get(dev, "core");
> 

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Re: [PATCH 10/14] qcom: mtd: nand: support for QPIC Page read/write

[Sricharan R]

On 6/29/2017 12:46 PM, Abhishek Sahu wrote:
> 1. Add the function for command descriptor preparation which
>    will be used only by BAM DMA and it will form the DMA descriptors
>    containing command elements.
> 
> 2. Add the data descriptor preparation function which will be used
>    only by BAM DMA for forming the data SGL’s.
> 
> 3. Add clear BAM transaction and call it before every new request
> 
> 4. Check DMA mode for ADM or BAM and call the appropriate
>    descriptor formation function.
> 
> 5. Enable the BAM in NAND_CTRL.
> 

Should this patch be patch #8 and then add other support ?

Regards,
 Sricharan


> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>  drivers/mtd/nand/qcom_nandc.c | 190 +++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 180 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 17766af..4c6e594 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -156,6 +156,8 @@
>  #define	FETCH_ID			0xb
>  #define	RESET_DEVICE			0xd
>  
> +/* NAND_CTRL bits */
> +#define	BAM_MODE_EN			BIT(0)
>  /*
>   * the NAND controller performs reads/writes with ECC in 516 byte chunks.
>   * the driver calls the chunks 'step' or 'codeword' interchangeably
> @@ -190,6 +192,14 @@
>   */
>  #define NAND_ERASED_CW_SET		(0x0008)
>  
> +/* Returns the dma address for reg read buffer */
> +#define REG_BUF_DMA_ADDR(chip, vaddr) \
> +	((chip)->reg_read_buf_phys + \
> +	((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
> +
> +/* Returns the NAND register physical address */
> +#define NAND_REG_PHYS(chip, offset) ((chip)->base_phys + (offset))
> +
>  #define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
>  #define QPIC_PER_CW_MAX_CMD_SGL		(32)
>  #define QPIC_PER_CW_MAX_DATA_SGL	(8)
> @@ -287,7 +297,8 @@ struct nandc_regs {
>   *				controller
>   * @dev:			parent device
>   * @base:			MMIO base
> - * @base_dma:			physical base address of controller registers
> + * @base_phys:			physical base address of controller registers
> + * @base_dma:			dma base address of controller registers
>   * @core_clk:			controller clock
>   * @aon_clk:			another controller clock
>   *
> @@ -323,6 +334,7 @@ struct qcom_nand_controller {
>  	struct device *dev;
>  
>  	void __iomem *base;
> +	phys_addr_t base_phys;
>  	dma_addr_t base_dma;
>  
>  	struct clk *core_clk;
> @@ -467,6 +479,29 @@ static void free_bam_transaction(struct qcom_nand_controller *nandc)
>  	return bam_txn;
>  }
>  
> +/* Clears the BAM transaction indexes */
> +static void clear_bam_transaction(struct qcom_nand_controller *nandc)
> +{
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> +	if (!nandc->dma_bam_enabled)
> +		return;
> +
> +	bam_txn->bam_ce_pos = 0;
> +	bam_txn->bam_ce_start = 0;
> +	bam_txn->cmd_sgl_pos = 0;
> +	bam_txn->cmd_sgl_start = 0;
> +	bam_txn->tx_sgl_pos = 0;
> +	bam_txn->tx_sgl_start = 0;
> +	bam_txn->rx_sgl_pos = 0;
> +	bam_txn->rx_sgl_start = 0;
> +
> +	sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
> +		      QPIC_PER_CW_MAX_CMD_SGL);
> +	sg_init_table(bam_txn->data_sg, nandc->max_cwperpage *
> +		      QPIC_PER_CW_MAX_DATA_SGL);
> +}
> +
>  static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>  {
>  	return container_of(chip, struct qcom_nand_host, chip);
> @@ -682,6 +717,102 @@ static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
>  	return 0;
>  }
>  
> +/*
> + * Prepares the command descriptor for BAM DMA which will be used for NAND
> + * register reads and writes. The command descriptor requires the command
> + * to be formed in command element type so this function uses the command
> + * element from bam transaction ce array and fills the same with required
> + * data. A single SGL can contain multiple command elements so
> + * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
> + * after the current command element.
> + */
> +static int prep_dma_desc_command(struct qcom_nand_controller *nandc, bool read,
> +				 int reg_off, const void *vaddr,
> +				 int size, unsigned int flags)
> +{
> +	int bam_ce_size;
> +	int i, ret;
> +	struct bam_cmd_element *bam_ce_buffer;
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> +	bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
> +
> +	/* fill the command desc */
> +	for (i = 0; i < size; i++) {
> +		if (read)
> +			bam_prep_ce(&bam_ce_buffer[i],
> +				    NAND_REG_PHYS(nandc, reg_off + 4 * i),
> +				    BAM_READ_COMMAND,
> +				    REG_BUF_DMA_ADDR(nandc,
> +						     (__le32 *)vaddr + i));
> +		else
> +			bam_prep_ce_le32(&bam_ce_buffer[i],
> +					 NAND_REG_PHYS(nandc, reg_off + 4 * i),
> +					 BAM_WRITE_COMMAND,
> +					 *((__le32 *)vaddr + i));
> +	}
> +
> +	bam_txn->bam_ce_pos += size;
> +
> +	/* use the separate sgl after this command */
> +	if (flags & NAND_BAM_NEXT_SGL) {
> +		bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
> +		bam_ce_size = (bam_txn->bam_ce_pos -
> +				bam_txn->bam_ce_start) *
> +				sizeof(struct bam_cmd_element);
> +		sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
> +			   bam_ce_buffer, bam_ce_size);
> +		bam_txn->cmd_sgl_pos++;
> +		bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
> +
> +		if (flags & NAND_BAM_NWD) {
> +			ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
> +						     DMA_PREP_FENCE |
> +						     DMA_PREP_CMD);
> +			if (ret)
> +				return ret;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +/*
> + * Prepares the data descriptor for BAM DMA which will be used for NAND
> + * data reads and writes.
> + */
> +static int prep_dma_desc_data_bam(struct qcom_nand_controller *nandc, bool read,
> +				  int reg_off, const void *vaddr,
> +				  int size, unsigned int flags)
> +{
> +	int ret;
> +	struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> +	if (read) {
> +		sg_set_buf(&bam_txn->data_sg[bam_txn->rx_sgl_pos],
> +			   vaddr, size);
> +		bam_txn->rx_sgl_pos++;
> +	} else {
> +		sg_set_buf(&bam_txn->data_sg[bam_txn->tx_sgl_pos],
> +			   vaddr, size);
> +		bam_txn->tx_sgl_pos++;
> +
> +		/*
> +		 * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
> +		 * is not set, form the DMA descriptor
> +		 */
> +		if (!(flags & NAND_BAM_NO_EOT)) {
> +			ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
> +						     DMA_PREP_INTERRUPT);
> +			if (ret)
> +				return ret;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +/* Prepares the dma descriptor for adm dma engine */
>  static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
>  			 int reg_off, const void *vaddr, int size,
>  			 bool flow_control)
> @@ -764,16 +895,19 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
>  {
>  	bool flow_control = false;
>  	void *vaddr;
> -	int size;
>  
>  	if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
>  		flow_control = true;
>  
> -	size = num_regs * sizeof(u32);
>  	vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
>  	nandc->reg_read_pos += num_regs;
>  
> -	return prep_dma_desc(nandc, true, first, vaddr, size, flow_control);
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_command(nandc, true, first, vaddr,
> +					     num_regs, flags);
> +
> +	return prep_dma_desc(nandc, true, first, vaddr, num_regs * sizeof(u32),
> +			     flow_control);
>  }
>  
>  /*
> @@ -789,7 +923,6 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>  	bool flow_control = false;
>  	struct nandc_regs *regs = nandc->regs;
>  	void *vaddr;
> -	int size;
>  
>  	vaddr = offset_to_nandc_reg(regs, first);
>  
> @@ -812,9 +945,12 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>  	if (first == NAND_DEV_CMD_VLD_RESTORE)
>  		first = NAND_DEV_CMD_VLD;
>  
> -	size = num_regs * sizeof(u32);
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_command(nandc, false, first, vaddr,
> +					     num_regs, flags);
>  
> -	return prep_dma_desc(nandc, false, first, vaddr, size, flow_control);
> +	return prep_dma_desc(nandc, false, first, vaddr, num_regs * sizeof(u32),
> +			     flow_control);
>  }
>  
>  /*
> @@ -828,6 +964,10 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>  static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>  			 const u8 *vaddr, int size, unsigned int flags)
>  {
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_data_bam(nandc, true, reg_off, vaddr, size,
> +					      flags);
> +
>  	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
>  }
>  
> @@ -842,6 +982,10 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>  static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>  			  const u8 *vaddr, int size, unsigned int flags)
>  {
> +	if (nandc->dma_bam_enabled)
> +		return prep_dma_desc_data_bam(nandc, false, reg_off, vaddr,
> +					      size, flags);
> +
>  	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
>  }
>  
> @@ -931,6 +1075,8 @@ static int nandc_param(struct qcom_nand_host *host)
>  	struct nand_chip *chip = &host->chip;
>  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>  
> +	clear_bam_transaction(nandc);
> +
>  	/*
>  	 * NAND_CMD_PARAM is called before we know much about the FLASH chip
>  	 * in use. we configure the controller to perform a raw read of 512
> @@ -993,6 +1139,8 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
>  	struct nand_chip *chip = &host->chip;
>  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>  
> +	clear_bam_transaction(nandc);
> +
>  	nandc_set_reg(nandc, NAND_FLASH_CMD,
>  		      BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
>  	nandc_set_reg(nandc, NAND_ADDR0, page_addr);
> @@ -1025,10 +1173,13 @@ static int read_id(struct qcom_nand_host *host, int column)
>  	if (column == -1)
>  		return 0;
>  
> +	clear_bam_transaction(nandc);
> +
>  	nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
>  	nandc_set_reg(nandc, NAND_ADDR0, column);
>  	nandc_set_reg(nandc, NAND_ADDR1, 0);
> -	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
> +	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
> +		      nandc->dma_bam_enabled ? 0 : DM_EN);
>  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>  
>  	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
> @@ -1045,6 +1196,8 @@ static int reset(struct qcom_nand_host *host)
>  	struct nand_chip *chip = &host->chip;
>  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>  
> +	clear_bam_transaction(nandc);
> +
>  	nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
>  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>  
> @@ -1561,6 +1714,7 @@ static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
>  	data_buf = buf;
>  	oob_buf = oob_required ? chip->oob_poi : NULL;
>  
> +	clear_bam_transaction(nandc);
>  	ret = read_page_ecc(host, data_buf, oob_buf);
>  	if (ret) {
>  		dev_err(nandc->dev, "failure to read page\n");
> @@ -1585,6 +1739,8 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
>  	oob_buf = chip->oob_poi;
>  
>  	host->use_ecc = false;
> +
> +	clear_bam_transaction(nandc);
>  	update_rw_regs(host, ecc->steps, true);
>  
>  	for (i = 0; i < ecc->steps; i++) {
> @@ -1641,6 +1797,7 @@ static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
>  	int ret;
>  
>  	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>  
>  	host->use_ecc = true;
>  	set_address(host, 0, page);
> @@ -1664,6 +1821,7 @@ static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>  	int i, ret;
>  
>  	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>  
>  	data_buf = (u8 *)buf;
>  	oob_buf = chip->oob_poi;
> @@ -1729,6 +1887,7 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
>  	int i, ret;
>  
>  	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>  
>  	data_buf = (u8 *)buf;
>  	oob_buf = chip->oob_poi;
> @@ -1803,6 +1962,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
>  
>  	host->use_ecc = true;
>  
> +	clear_bam_transaction(nandc);
>  	ret = copy_last_cw(host, page);
>  	if (ret)
>  		return ret;
> @@ -1860,6 +2020,7 @@ static int qcom_nandc_block_bad(struct mtd_info *mtd, loff_t ofs)
>  	 */
>  	host->use_ecc = false;
>  
> +	clear_bam_transaction(nandc);
>  	ret = copy_last_cw(host, page);
>  	if (ret)
>  		goto err;
> @@ -1890,6 +2051,7 @@ static int qcom_nandc_block_markbad(struct mtd_info *mtd, loff_t ofs)
>  	int page, ret, status = 0;
>  
>  	clear_read_regs(nandc);
> +	clear_bam_transaction(nandc);
>  
>  	/*
>  	 * to mark the BBM as bad, we flash the entire last codeword with 0s.
> @@ -2396,11 +2558,18 @@ static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
>  /* one time setup of a few nand controller registers */
>  static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
>  {
> +	u32 nand_ctrl;
> +
>  	/* kill onenand */
>  	nandc_write(nandc, SFLASHC_BURST_CFG, 0);
>  
> -	/* enable ADM DMA */
> -	nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
> +	/* enable ADM or BAM DMA */
> +	if (!nandc->dma_bam_enabled) {
> +		nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
> +	} else {
> +		nand_ctrl = nandc_read(nandc, NAND_CTRL);
> +		nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
> +	}
>  
>  	/* save the original values of these registers */
>  	nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
> @@ -2592,6 +2761,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>  	if (IS_ERR(nandc->base))
>  		return PTR_ERR(nandc->base);
>  
> +	nandc->base_phys = res->start;
>  	nandc->base_dma = phys_to_dma(dev, (phys_addr_t)res->start);
>  
>  	nandc->core_clk = devm_clk_get(dev, "core");
> 

-- 
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Re: [PATCH 10/14] qcom: mtd: nand: support for QPIC Page read/write

[Abhishek Sahu]

On 2017-07-10 19:48, Sricharan R wrote:
> On 6/29/2017 12:46 PM, Abhishek Sahu wrote:
>> 1. Add the function for command descriptor preparation which
>>    will be used only by BAM DMA and it will form the DMA descriptors
>>    containing command elements.
>> 
>> 2. Add the data descriptor preparation function which will be used
>>    only by BAM DMA for forming the data SGL’s.
>> 
>> 3. Add clear BAM transaction and call it before every new request
>> 
>> 4. Check DMA mode for ADM or BAM and call the appropriate
>>    descriptor formation function.
>> 
>> 5. Enable the BAM in NAND_CTRL.
>> 
> 
> Should this patch be patch #8 and then add other support ?
> 

  The original plan was to add other these function and
  finally enable the operation but it was generating the
  unused functions warnings that's why I need to club all
  these together in the last patch. anyway, I will check
  once again and will reorder if possible.

> Regards,
>  Sricharan
> 
> 
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> ---
>>  drivers/mtd/nand/qcom_nandc.c | 190
>> +++++++++++++++++++++++++++++++++++++++---
>>  1 file changed, 180 insertions(+), 10 deletions(-)
>> 
>> diff --git a/drivers/mtd/nand/qcom_nandc.c 
>> b/drivers/mtd/nand/qcom_nandc.c
>> index 17766af..4c6e594 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -156,6 +156,8 @@
>>  #define	FETCH_ID			0xb
>>  #define	RESET_DEVICE			0xd
>> 
>> +/* NAND_CTRL bits */
>> +#define	BAM_MODE_EN			BIT(0)
>>  /*
>>   * the NAND controller performs reads/writes with ECC in 516 byte 
>> chunks.
>>   * the driver calls the chunks 'step' or 'codeword' interchangeably
>> @@ -190,6 +192,14 @@
>>   */
>>  #define NAND_ERASED_CW_SET		(0x0008)
>> 
>> +/* Returns the dma address for reg read buffer */
>> +#define REG_BUF_DMA_ADDR(chip, vaddr) \
>> +	((chip)->reg_read_buf_phys + \
>> +	((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
>> +
>> +/* Returns the NAND register physical address */
>> +#define NAND_REG_PHYS(chip, offset) ((chip)->base_phys + (offset))
>> +
>>  #define QPIC_PER_CW_MAX_CMD_ELEMENTS	(32)
>>  #define QPIC_PER_CW_MAX_CMD_SGL		(32)
>>  #define QPIC_PER_CW_MAX_DATA_SGL	(8)
>> @@ -287,7 +297,8 @@ struct nandc_regs {
>>   *				controller
>>   * @dev:			parent device
>>   * @base:			MMIO base
>> - * @base_dma:			physical base address of controller registers
>> + * @base_phys:			physical base address of controller registers
>> + * @base_dma:			dma base address of controller registers
>>   * @core_clk:			controller clock
>>   * @aon_clk:			another controller clock
>>   *
>> @@ -323,6 +334,7 @@ struct qcom_nand_controller {
>>  	struct device *dev;
>> 
>>  	void __iomem *base;
>> +	phys_addr_t base_phys;
>>  	dma_addr_t base_dma;
>> 
>>  	struct clk *core_clk;
>> @@ -467,6 +479,29 @@ static void free_bam_transaction(struct
>> qcom_nand_controller *nandc)
>>  	return bam_txn;
>>  }
>> 
>> +/* Clears the BAM transaction indexes */
>> +static void clear_bam_transaction(struct qcom_nand_controller *nandc)
>> +{
>> +	struct bam_transaction *bam_txn = nandc->bam_txn;
>> +
>> +	if (!nandc->dma_bam_enabled)
>> +		return;
>> +
>> +	bam_txn->bam_ce_pos = 0;
>> +	bam_txn->bam_ce_start = 0;
>> +	bam_txn->cmd_sgl_pos = 0;
>> +	bam_txn->cmd_sgl_start = 0;
>> +	bam_txn->tx_sgl_pos = 0;
>> +	bam_txn->tx_sgl_start = 0;
>> +	bam_txn->rx_sgl_pos = 0;
>> +	bam_txn->rx_sgl_start = 0;
>> +
>> +	sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
>> +		      QPIC_PER_CW_MAX_CMD_SGL);
>> +	sg_init_table(bam_txn->data_sg, nandc->max_cwperpage *
>> +		      QPIC_PER_CW_MAX_DATA_SGL);
>> +}
>> +
>>  static inline struct qcom_nand_host *to_qcom_nand_host(struct 
>> nand_chip
>> *chip)
>>  {
>>  	return container_of(chip, struct qcom_nand_host, chip);
>> @@ -682,6 +717,102 @@ static int prepare_bam_async_desc(struct
>> qcom_nand_controller *nandc,
>>  	return 0;
>>  }
>> 
>> +/*
>> + * Prepares the command descriptor for BAM DMA which will be used for
>> NAND
>> + * register reads and writes. The command descriptor requires the 
>> command
>> + * to be formed in command element type so this function uses the 
>> command
>> + * element from bam transaction ce array and fills the same with 
>> required
>> + * data. A single SGL can contain multiple command elements so
>> + * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
>> + * after the current command element.
>> + */
>> +static int prep_dma_desc_command(struct qcom_nand_controller *nandc, 
>> bool
>> read,
>> +				 int reg_off, const void *vaddr,
>> +				 int size, unsigned int flags)
>> +{
>> +	int bam_ce_size;
>> +	int i, ret;
>> +	struct bam_cmd_element *bam_ce_buffer;
>> +	struct bam_transaction *bam_txn = nandc->bam_txn;
>> +
>> +	bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
>> +
>> +	/* fill the command desc */
>> +	for (i = 0; i < size; i++) {
>> +		if (read)
>> +			bam_prep_ce(&bam_ce_buffer[i],
>> +				    NAND_REG_PHYS(nandc, reg_off + 4 * i),
>> +				    BAM_READ_COMMAND,
>> +				    REG_BUF_DMA_ADDR(nandc,
>> +						     (__le32 *)vaddr + i));
>> +		else
>> +			bam_prep_ce_le32(&bam_ce_buffer[i],
>> +					 NAND_REG_PHYS(nandc, reg_off + 4 * i),
>> +					 BAM_WRITE_COMMAND,
>> +					 *((__le32 *)vaddr + i));
>> +	}
>> +
>> +	bam_txn->bam_ce_pos += size;
>> +
>> +	/* use the separate sgl after this command */
>> +	if (flags & NAND_BAM_NEXT_SGL) {
>> +		bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
>> +		bam_ce_size = (bam_txn->bam_ce_pos -
>> +				bam_txn->bam_ce_start) *
>> +				sizeof(struct bam_cmd_element);
>> +		sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
>> +			   bam_ce_buffer, bam_ce_size);
>> +		bam_txn->cmd_sgl_pos++;
>> +		bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
>> +
>> +		if (flags & NAND_BAM_NWD) {
>> +			ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
>> +						     DMA_PREP_FENCE |
>> +						     DMA_PREP_CMD);
>> +			if (ret)
>> +				return ret;
>> +		}
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +/*
>> + * Prepares the data descriptor for BAM DMA which will be used for 
>> NAND
>> + * data reads and writes.
>> + */
>> +static int prep_dma_desc_data_bam(struct qcom_nand_controller *nandc,
>> bool read,
>> +				  int reg_off, const void *vaddr,
>> +				  int size, unsigned int flags)
>> +{
>> +	int ret;
>> +	struct bam_transaction *bam_txn = nandc->bam_txn;
>> +
>> +	if (read) {
>> +		sg_set_buf(&bam_txn->data_sg[bam_txn->rx_sgl_pos],
>> +			   vaddr, size);
>> +		bam_txn->rx_sgl_pos++;
>> +	} else {
>> +		sg_set_buf(&bam_txn->data_sg[bam_txn->tx_sgl_pos],
>> +			   vaddr, size);
>> +		bam_txn->tx_sgl_pos++;
>> +
>> +		/*
>> +		 * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
>> +		 * is not set, form the DMA descriptor
>> +		 */
>> +		if (!(flags & NAND_BAM_NO_EOT)) {
>> +			ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
>> +						     DMA_PREP_INTERRUPT);
>> +			if (ret)
>> +				return ret;
>> +		}
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +/* Prepares the dma descriptor for adm dma engine */
>>  static int prep_dma_desc(struct qcom_nand_controller *nandc, bool 
>> read,
>>  			 int reg_off, const void *vaddr, int size,
>>  			 bool flow_control)
>> @@ -764,16 +895,19 @@ static int read_reg_dma(struct 
>> qcom_nand_controller
>> *nandc, int first,
>>  {
>>  	bool flow_control = false;
>>  	void *vaddr;
>> -	int size;
>> 
>>  	if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
>>  		flow_control = true;
>> 
>> -	size = num_regs * sizeof(u32);
>>  	vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
>>  	nandc->reg_read_pos += num_regs;
>> 
>> -	return prep_dma_desc(nandc, true, first, vaddr, size, flow_control);
>> +	if (nandc->dma_bam_enabled)
>> +		return prep_dma_desc_command(nandc, true, first, vaddr,
>> +					     num_regs, flags);
>> +
>> +	return prep_dma_desc(nandc, true, first, vaddr, num_regs * 
>> sizeof(u32),
>> +			     flow_control);
>>  }
>> 
>>  /*
>> @@ -789,7 +923,6 @@ static int write_reg_dma(struct 
>> qcom_nand_controller
>> *nandc, int first,
>>  	bool flow_control = false;
>>  	struct nandc_regs *regs = nandc->regs;
>>  	void *vaddr;
>> -	int size;
>> 
>>  	vaddr = offset_to_nandc_reg(regs, first);
>> 
>> @@ -812,9 +945,12 @@ static int write_reg_dma(struct 
>> qcom_nand_controller
>> *nandc, int first,
>>  	if (first == NAND_DEV_CMD_VLD_RESTORE)
>>  		first = NAND_DEV_CMD_VLD;
>> 
>> -	size = num_regs * sizeof(u32);
>> +	if (nandc->dma_bam_enabled)
>> +		return prep_dma_desc_command(nandc, false, first, vaddr,
>> +					     num_regs, flags);
>> 
>> -	return prep_dma_desc(nandc, false, first, vaddr, size, 
>> flow_control);
>> +	return prep_dma_desc(nandc, false, first, vaddr, num_regs * 
>> sizeof(u32),
>> +			     flow_control);
>>  }
>> 
>>  /*
>> @@ -828,6 +964,10 @@ static int write_reg_dma(struct 
>> qcom_nand_controller
>> *nandc, int first,
>>  static int read_data_dma(struct qcom_nand_controller *nandc, int 
>> reg_off,
>>  			 const u8 *vaddr, int size, unsigned int flags)
>>  {
>> +	if (nandc->dma_bam_enabled)
>> +		return prep_dma_desc_data_bam(nandc, true, reg_off, vaddr, size,
>> +					      flags);
>> +
>>  	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
>>  }
>> 
>> @@ -842,6 +982,10 @@ static int read_data_dma(struct 
>> qcom_nand_controller
>> *nandc, int reg_off,
>>  static int write_data_dma(struct qcom_nand_controller *nandc, int
>> reg_off,
>>  			  const u8 *vaddr, int size, unsigned int flags)
>>  {
>> +	if (nandc->dma_bam_enabled)
>> +		return prep_dma_desc_data_bam(nandc, false, reg_off, vaddr,
>> +					      size, flags);
>> +
>>  	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
>>  }
>> 
>> @@ -931,6 +1075,8 @@ static int nandc_param(struct qcom_nand_host 
>> *host)
>>  	struct nand_chip *chip = &host->chip;
>>  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> 
>> +	clear_bam_transaction(nandc);
>> +
>>  	/*
>>  	 * NAND_CMD_PARAM is called before we know much about the FLASH chip
>>  	 * in use. we configure the controller to perform a raw read of 512
>> @@ -993,6 +1139,8 @@ static int erase_block(struct qcom_nand_host 
>> *host,
>> int page_addr)
>>  	struct nand_chip *chip = &host->chip;
>>  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> 
>> +	clear_bam_transaction(nandc);
>> +
>>  	nandc_set_reg(nandc, NAND_FLASH_CMD,
>>  		      BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
>>  	nandc_set_reg(nandc, NAND_ADDR0, page_addr);
>> @@ -1025,10 +1173,13 @@ static int read_id(struct qcom_nand_host 
>> *host,
>> int column)
>>  	if (column == -1)
>>  		return 0;
>> 
>> +	clear_bam_transaction(nandc);
>> +
>>  	nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
>>  	nandc_set_reg(nandc, NAND_ADDR0, column);
>>  	nandc_set_reg(nandc, NAND_ADDR1, 0);
>> -	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
>> +	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
>> +		      nandc->dma_bam_enabled ? 0 : DM_EN);
>>  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>> 
>>  	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
>> @@ -1045,6 +1196,8 @@ static int reset(struct qcom_nand_host *host)
>>  	struct nand_chip *chip = &host->chip;
>>  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> 
>> +	clear_bam_transaction(nandc);
>> +
>>  	nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
>>  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>> 
>> @@ -1561,6 +1714,7 @@ static int qcom_nandc_read_page(struct mtd_info
>> *mtd, struct nand_chip *chip,
>>  	data_buf = buf;
>>  	oob_buf = oob_required ? chip->oob_poi : NULL;
>> 
>> +	clear_bam_transaction(nandc);
>>  	ret = read_page_ecc(host, data_buf, oob_buf);
>>  	if (ret) {
>>  		dev_err(nandc->dev, "failure to read page\n");
>> @@ -1585,6 +1739,8 @@ static int qcom_nandc_read_page_raw(struct 
>> mtd_info
>> *mtd,
>>  	oob_buf = chip->oob_poi;
>> 
>>  	host->use_ecc = false;
>> +
>> +	clear_bam_transaction(nandc);
>>  	update_rw_regs(host, ecc->steps, true);
>> 
>>  	for (i = 0; i < ecc->steps; i++) {
>> @@ -1641,6 +1797,7 @@ static int qcom_nandc_read_oob(struct mtd_info 
>> *mtd,
>> struct nand_chip *chip,
>>  	int ret;
>> 
>>  	clear_read_regs(nandc);
>> +	clear_bam_transaction(nandc);
>> 
>>  	host->use_ecc = true;
>>  	set_address(host, 0, page);
>> @@ -1664,6 +1821,7 @@ static int qcom_nandc_write_page(struct mtd_info
>> *mtd, struct nand_chip *chip,
>>  	int i, ret;
>> 
>>  	clear_read_regs(nandc);
>> +	clear_bam_transaction(nandc);
>> 
>>  	data_buf = (u8 *)buf;
>>  	oob_buf = chip->oob_poi;
>> @@ -1729,6 +1887,7 @@ static int qcom_nandc_write_page_raw(struct 
>> mtd_info
>> *mtd,
>>  	int i, ret;
>> 
>>  	clear_read_regs(nandc);
>> +	clear_bam_transaction(nandc);
>> 
>>  	data_buf = (u8 *)buf;
>>  	oob_buf = chip->oob_poi;
>> @@ -1803,6 +1962,7 @@ static int qcom_nandc_write_oob(struct mtd_info
>> *mtd, struct nand_chip *chip,
>> 
>>  	host->use_ecc = true;
>> 
>> +	clear_bam_transaction(nandc);
>>  	ret = copy_last_cw(host, page);
>>  	if (ret)
>>  		return ret;
>> @@ -1860,6 +2020,7 @@ static int qcom_nandc_block_bad(struct mtd_info
>> *mtd, loff_t ofs)
>>  	 */
>>  	host->use_ecc = false;
>> 
>> +	clear_bam_transaction(nandc);
>>  	ret = copy_last_cw(host, page);
>>  	if (ret)
>>  		goto err;
>> @@ -1890,6 +2051,7 @@ static int qcom_nandc_block_markbad(struct 
>> mtd_info
>> *mtd, loff_t ofs)
>>  	int page, ret, status = 0;
>> 
>>  	clear_read_regs(nandc);
>> +	clear_bam_transaction(nandc);
>> 
>>  	/*
>>  	 * to mark the BBM as bad, we flash the entire last codeword with 
>> 0s.
>> @@ -2396,11 +2558,18 @@ static void qcom_nandc_unalloc(struct
>> qcom_nand_controller *nandc)
>>  /* one time setup of a few nand controller registers */
>>  static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
>>  {
>> +	u32 nand_ctrl;
>> +
>>  	/* kill onenand */
>>  	nandc_write(nandc, SFLASHC_BURST_CFG, 0);
>> 
>> -	/* enable ADM DMA */
>> -	nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
>> +	/* enable ADM or BAM DMA */
>> +	if (!nandc->dma_bam_enabled) {
>> +		nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
>> +	} else {
>> +		nand_ctrl = nandc_read(nandc, NAND_CTRL);
>> +		nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
>> +	}
>> 
>>  	/* save the original values of these registers */
>>  	nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
>> @@ -2592,6 +2761,7 @@ static int qcom_nandc_probe(struct 
>> platform_device
>> *pdev)
>>  	if (IS_ERR(nandc->base))
>>  		return PTR_ERR(nandc->base);
>> 
>> +	nandc->base_phys = res->start;
>>  	nandc->base_dma = phys_to_dma(dev, (phys_addr_t)res->start);
>> 
>>  	nandc->core_clk = devm_clk_get(dev, "core");
>> 

-- 
Abhishek Sahu

[PATCH 11/14] qcom: mtd: nand: BAM raw read and write support

[Abhishek Sahu]

1. BAM uses READ_LOCATION registers to copy data from offset
   into data buffer.

2. BAM requires EOT flag should be set only for the last data
   write in a codeword.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/mtd/nand/qcom_nandc.c | 46 ++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 41 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 4c6e594..6d749b6 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -1033,7 +1033,7 @@ static void config_bam_page_read(struct qcom_nand_controller *nandc)
  */
 static void config_bam_cw_read(struct qcom_nand_controller *nandc)
 {
-	write_reg_dma(nandc, NAND_READ_LOCATION_0, 2, 0);
+	write_reg_dma(nandc, NAND_READ_LOCATION_0, 4, 0);
 	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
 	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
 
@@ -1734,6 +1734,7 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
 	u8 *data_buf, *oob_buf;
 	struct nand_ecc_ctrl *ecc = &chip->ecc;
 	int i, ret;
+	int read_location;
 
 	data_buf = buf;
 	oob_buf = chip->oob_poi;
@@ -1743,6 +1744,9 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
 	clear_bam_transaction(nandc);
 	update_rw_regs(host, ecc->steps, true);
 
+	if (nandc->dma_bam_enabled)
+		config_bam_page_read(nandc);
+
 	for (i = 0; i < ecc->steps; i++) {
 		int data_size1, data_size2, oob_size1, oob_size2;
 		int reg_off = FLASH_BUF_ACC;
@@ -1760,7 +1764,35 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
 			oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
 		}
 
-		config_cw_read(nandc);
+		if (nandc->dma_bam_enabled) {
+			read_location = 0;
+			nandc_set_reg(nandc, NAND_READ_LOCATION_0,
+				      (read_location << READ_LOCATION_OFFSET) |
+				      (data_size1 << READ_LOCATION_SIZE) |
+				      (0 << READ_LOCATION_LAST));
+			read_location += data_size1;
+
+			nandc_set_reg(nandc, NAND_READ_LOCATION_1,
+				      (read_location << READ_LOCATION_OFFSET) |
+				      (oob_size1 << READ_LOCATION_SIZE) |
+				      (0 << READ_LOCATION_LAST));
+			read_location += oob_size1;
+
+			nandc_set_reg(nandc, NAND_READ_LOCATION_2,
+				      (read_location << READ_LOCATION_OFFSET) |
+				      (data_size2 << READ_LOCATION_SIZE) |
+				      (0 << READ_LOCATION_LAST));
+			read_location += data_size2;
+
+			nandc_set_reg(nandc, NAND_READ_LOCATION_3,
+				      (read_location << READ_LOCATION_OFFSET) |
+				      (oob_size2 << READ_LOCATION_SIZE) |
+				      (1 << READ_LOCATION_LAST));
+
+			config_bam_cw_read(nandc);
+		} else {
+			config_cw_read(nandc);
+		}
 
 		read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
 		reg_off += data_size1;
@@ -1914,15 +1946,18 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
 
 		config_cw_write_pre(nandc);
 
-		write_data_dma(nandc, reg_off, data_buf, data_size1, 0);
+		write_data_dma(nandc, reg_off, data_buf, data_size1,
+			       NAND_BAM_NO_EOT);
 		reg_off += data_size1;
 		data_buf += data_size1;
 
-		write_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
+		write_data_dma(nandc, reg_off, oob_buf, oob_size1,
+			       NAND_BAM_NO_EOT);
 		reg_off += oob_size1;
 		oob_buf += oob_size1;
 
-		write_data_dma(nandc, reg_off, data_buf, data_size2, 0);
+		write_data_dma(nandc, reg_off, data_buf, data_size2,
+			       NAND_BAM_NO_EOT);
 		reg_off += data_size2;
 		data_buf += data_size2;
 
@@ -1968,6 +2003,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 		return ret;
 
 	clear_read_regs(nandc);
+	clear_bam_transaction(nandc);
 
 	/* calculate the data and oob size for the last codeword/step */
 	data_size = ecc->size - ((ecc->steps - 1) << 2);
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 12/14] qcom: mtd: nand: change register offset defines with enums

[Abhishek Sahu]

The current driver defines the register offset with preprocessor
macro which is defined crossponding to NAND controller version
1.4.0. This patch changes these macro with enumeration. It also
adds mapping array which contains controller register offsets for
each register offset enumeration. This mapping array will be
referenced before each register read and writes, where the register
offset enumeration is being replaced with actual register offsets.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/mtd/nand/qcom_nandc.c | 136 +++++++++++++++++++++++++++---------------
 1 file changed, 89 insertions(+), 47 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 6d749b6..24750e6 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -24,43 +24,6 @@
 #include <linux/delay.h>
 #include <linux/dma/qcom_bam_dma.h>
 
-/* NANDc reg offsets */
-#define	NAND_FLASH_CMD			0x00
-#define	NAND_ADDR0			0x04
-#define	NAND_ADDR1			0x08
-#define	NAND_FLASH_CHIP_SELECT		0x0c
-#define	NAND_EXEC_CMD			0x10
-#define	NAND_FLASH_STATUS		0x14
-#define	NAND_BUFFER_STATUS		0x18
-#define	NAND_DEV0_CFG0			0x20
-#define	NAND_DEV0_CFG1			0x24
-#define	NAND_DEV0_ECC_CFG		0x28
-#define	NAND_DEV1_ECC_CFG		0x2c
-#define	NAND_DEV1_CFG0			0x30
-#define	NAND_DEV1_CFG1			0x34
-#define	NAND_READ_ID			0x40
-#define	NAND_READ_STATUS		0x44
-#define	NAND_DEV_CMD0			0xa0
-#define	NAND_DEV_CMD1			0xa4
-#define	NAND_DEV_CMD2			0xa8
-#define	NAND_DEV_CMD_VLD		0xac
-#define	SFLASHC_BURST_CFG		0xe0
-#define	NAND_ERASED_CW_DETECT_CFG	0xe8
-#define	NAND_ERASED_CW_DETECT_STATUS	0xec
-#define	NAND_EBI2_ECC_BUF_CFG		0xf0
-#define	FLASH_BUF_ACC			0x100
-
-#define	NAND_CTRL			0xf00
-#define	NAND_VERSION			0xf08
-#define	NAND_READ_LOCATION_0		0xf20
-#define	NAND_READ_LOCATION_1		0xf24
-#define	NAND_READ_LOCATION_2		0xf28
-#define	NAND_READ_LOCATION_3		0xf2c
-
-/* dummy register offsets, used by write_reg_dma */
-#define	NAND_DEV_CMD1_RESTORE		0xdead
-#define	NAND_DEV_CMD_VLD_RESTORE	0xbeef
-
 /* NAND_FLASH_CMD bits */
 #define	PAGE_ACC			BIT(4)
 #define	LAST_PAGE			BIT(5)
@@ -204,6 +167,44 @@
 #define QPIC_PER_CW_MAX_CMD_SGL		(32)
 #define QPIC_PER_CW_MAX_DATA_SGL	(8)
 
+/* NANDc reg offsets enumeration */
+enum {
+	NAND_FLASH_CMD,
+	NAND_ADDR0,
+	NAND_ADDR1,
+	NAND_FLASH_CHIP_SELECT,
+	NAND_EXEC_CMD,
+	NAND_FLASH_STATUS,
+	NAND_BUFFER_STATUS,
+	NAND_DEV0_CFG0,
+	NAND_DEV0_CFG1,
+	NAND_DEV0_ECC_CFG,
+	NAND_DEV1_ECC_CFG,
+	NAND_DEV1_CFG0,
+	NAND_DEV1_CFG1,
+	NAND_READ_ID,
+	NAND_READ_STATUS,
+	NAND_DEV_CMD0,
+	NAND_DEV_CMD1,
+	NAND_DEV_CMD2,
+	NAND_DEV_CMD_VLD,
+	SFLASHC_BURST_CFG,
+	NAND_ERASED_CW_DETECT_CFG,
+	NAND_ERASED_CW_DETECT_STATUS,
+	NAND_EBI2_ECC_BUF_CFG,
+	FLASH_BUF_ACC,
+	NAND_CTRL,
+	NAND_VERSION,
+	NAND_READ_LOCATION_0,
+	NAND_READ_LOCATION_1,
+	NAND_READ_LOCATION_2,
+	NAND_READ_LOCATION_3,
+
+	/* dummy register offsets, used by write_reg_dma */
+	NAND_DEV_CMD1_RESTORE,
+	NAND_DEV_CMD_VLD_RESTORE,
+};
+
 /*
  * This data type corresponds to the BAM transaction which will be used for all
  * NAND transfers.
@@ -326,6 +327,7 @@ struct nandc_regs {
  *				bam dma
  * @max_cwperpage:		maximum qpic codeword required. calcualted
  *				from all nand device pagesize
+ * @regs_offsets:		register offset mapping array
  */
 struct qcom_nand_controller {
 	struct nand_hw_control controller;
@@ -371,6 +373,7 @@ struct qcom_nand_controller {
 
 	u32 cmd1, vld;
 	u32 ecc_modes;
+	const u32 *regs_offsets;
 };
 
 /*
@@ -434,6 +437,40 @@ struct qcom_nand_driver_data {
 	bool dma_bam_enabled;
 };
 
+/* Mapping table which contains the actual register offsets */
+static const u32 regs_offsets[] = {
+	[NAND_FLASH_CMD] = 0x00,
+	[NAND_ADDR0] = 0x04,
+	[NAND_ADDR1] = 0x08,
+	[NAND_FLASH_CHIP_SELECT] = 0x0c,
+	[NAND_EXEC_CMD] = 0x10,
+	[NAND_FLASH_STATUS] = 0x14,
+	[NAND_BUFFER_STATUS] = 0x18,
+	[NAND_DEV0_CFG0] = 0x20,
+	[NAND_DEV0_CFG1] = 0x24,
+	[NAND_DEV0_ECC_CFG] = 0x28,
+	[NAND_DEV1_ECC_CFG] = 0x2c,
+	[NAND_DEV1_CFG0] = 0x30,
+	[NAND_DEV1_CFG1] = 0x34,
+	[NAND_READ_ID] = 0x40,
+	[NAND_READ_STATUS] = 0x44,
+	[NAND_DEV_CMD0] = 0xa0,
+	[NAND_DEV_CMD1] = 0xa4,
+	[NAND_DEV_CMD2] = 0xa8,
+	[NAND_DEV_CMD_VLD] = 0xac,
+	[SFLASHC_BURST_CFG] = 0xe0,
+	[NAND_ERASED_CW_DETECT_CFG] = 0xe8,
+	[NAND_ERASED_CW_DETECT_STATUS] = 0xec,
+	[NAND_EBI2_ECC_BUF_CFG] = 0xf0,
+	[FLASH_BUF_ACC] = 0x100,
+	[NAND_CTRL] = 0xf00,
+	[NAND_VERSION] = 0xf08,
+	[NAND_READ_LOCATION_0] = 0xf20,
+	[NAND_READ_LOCATION_1] = 0xf24,
+	[NAND_READ_LOCATION_2] = 0xf28,
+	[NAND_READ_LOCATION_3] = 0xf2c,
+};
+
 /* Frees the BAM transaction memory */
 static void free_bam_transaction(struct qcom_nand_controller *nandc)
 {
@@ -516,13 +553,13 @@ static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
 
 static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
 {
-	return ioread32(nandc->base + offset);
+	return ioread32(nandc->base + nandc->regs_offsets[offset]);
 }
 
 static inline void nandc_write(struct qcom_nand_controller *nandc, int offset,
 			       u32 val)
 {
-	iowrite32(val, nandc->base + offset);
+	iowrite32(val, nandc->base + nandc->regs_offsets[offset]);
 }
 
 static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
@@ -903,11 +940,12 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
 	nandc->reg_read_pos += num_regs;
 
 	if (nandc->dma_bam_enabled)
-		return prep_dma_desc_command(nandc, true, first, vaddr,
+		return prep_dma_desc_command(nandc, true,
+					     nandc->regs_offsets[first], vaddr,
 					     num_regs, flags);
 
-	return prep_dma_desc(nandc, true, first, vaddr, num_regs * sizeof(u32),
-			     flow_control);
+	return prep_dma_desc(nandc, true, nandc->regs_offsets[first], vaddr,
+			     num_regs * sizeof(u32), flow_control);
 }
 
 /*
@@ -946,11 +984,12 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
 		first = NAND_DEV_CMD_VLD;
 
 	if (nandc->dma_bam_enabled)
-		return prep_dma_desc_command(nandc, false, first, vaddr,
+		return prep_dma_desc_command(nandc, false,
+					     nandc->regs_offsets[first], vaddr,
 					     num_regs, flags);
 
-	return prep_dma_desc(nandc, false, first, vaddr, num_regs * sizeof(u32),
-			     flow_control);
+	return prep_dma_desc(nandc, false, nandc->regs_offsets[first], vaddr,
+			     num_regs * sizeof(u32), flow_control);
 }
 
 /*
@@ -968,7 +1007,8 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
 		return prep_dma_desc_data_bam(nandc, true, reg_off, vaddr, size,
 					      flags);
 
-	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
+	return prep_dma_desc(nandc, true, nandc->regs_offsets[FLASH_BUF_ACC] +
+			     reg_off - FLASH_BUF_ACC, vaddr, size, false);
 }
 
 /*
@@ -986,7 +1026,8 @@ static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
 		return prep_dma_desc_data_bam(nandc, false, reg_off, vaddr,
 					      size, flags);
 
-	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
+	return prep_dma_desc(nandc, false, nandc->regs_offsets[FLASH_BUF_ACC] +
+			     reg_off - FLASH_BUF_ACC, vaddr, size, false);
 }
 
 /*
@@ -2791,6 +2832,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 
 	nandc->ecc_modes = driver_data->ecc_modes;
 	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
+	nandc->regs_offsets = regs_offsets;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	nandc->base = devm_ioremap_resource(dev, res);
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 12/14] qcom: mtd: nand: change register offset defines with enums

[Archit Taneja]

On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
> The current driver defines the register offset with preprocessor
> macro which is defined crossponding to NAND controller version
> 1.4.0. This patch changes these macro with enumeration. It also
> adds mapping array which contains controller register offsets for
> each register offset enumeration. This mapping array will be
> referenced before each register read and writes, where the register
> offset enumeration is being replaced with actual register offsets.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>   drivers/mtd/nand/qcom_nandc.c | 136 +++++++++++++++++++++++++++---------------
>   1 file changed, 89 insertions(+), 47 deletions(-)
> 
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 6d749b6..24750e6 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -24,43 +24,6 @@
>   #include <linux/delay.h>
>   #include <linux/dma/qcom_bam_dma.h>
>   
> -/* NANDc reg offsets */
> -#define	NAND_FLASH_CMD			0x00
> -#define	NAND_ADDR0			0x04
> -#define	NAND_ADDR1			0x08
> -#define	NAND_FLASH_CHIP_SELECT		0x0c
> -#define	NAND_EXEC_CMD			0x10
> -#define	NAND_FLASH_STATUS		0x14
> -#define	NAND_BUFFER_STATUS		0x18
> -#define	NAND_DEV0_CFG0			0x20
> -#define	NAND_DEV0_CFG1			0x24
> -#define	NAND_DEV0_ECC_CFG		0x28
> -#define	NAND_DEV1_ECC_CFG		0x2c
> -#define	NAND_DEV1_CFG0			0x30
> -#define	NAND_DEV1_CFG1			0x34
> -#define	NAND_READ_ID			0x40
> -#define	NAND_READ_STATUS		0x44
> -#define	NAND_DEV_CMD0			0xa0
> -#define	NAND_DEV_CMD1			0xa4
> -#define	NAND_DEV_CMD2			0xa8
> -#define	NAND_DEV_CMD_VLD		0xac
> -#define	SFLASHC_BURST_CFG		0xe0
> -#define	NAND_ERASED_CW_DETECT_CFG	0xe8
> -#define	NAND_ERASED_CW_DETECT_STATUS	0xec
> -#define	NAND_EBI2_ECC_BUF_CFG		0xf0
> -#define	FLASH_BUF_ACC			0x100
> -
> -#define	NAND_CTRL			0xf00
> -#define	NAND_VERSION			0xf08
> -#define	NAND_READ_LOCATION_0		0xf20
> -#define	NAND_READ_LOCATION_1		0xf24
> -#define	NAND_READ_LOCATION_2		0xf28
> -#define	NAND_READ_LOCATION_3		0xf2c
> -
> -/* dummy register offsets, used by write_reg_dma */
> -#define	NAND_DEV_CMD1_RESTORE		0xdead
> -#define	NAND_DEV_CMD_VLD_RESTORE	0xbeef
> -
>   /* NAND_FLASH_CMD bits */
>   #define	PAGE_ACC			BIT(4)
>   #define	LAST_PAGE			BIT(5)
> @@ -204,6 +167,44 @@
>   #define QPIC_PER_CW_MAX_CMD_SGL		(32)
>   #define QPIC_PER_CW_MAX_DATA_SGL	(8)
>   
> +/* NANDc reg offsets enumeration */
> +enum {
> +	NAND_FLASH_CMD,
> +	NAND_ADDR0,
> +	NAND_ADDR1,
> +	NAND_FLASH_CHIP_SELECT,
> +	NAND_EXEC_CMD,
> +	NAND_FLASH_STATUS,
> +	NAND_BUFFER_STATUS,
> +	NAND_DEV0_CFG0,
> +	NAND_DEV0_CFG1,
> +	NAND_DEV0_ECC_CFG,
> +	NAND_DEV1_ECC_CFG,
> +	NAND_DEV1_CFG0,
> +	NAND_DEV1_CFG1,
> +	NAND_READ_ID,
> +	NAND_READ_STATUS,
> +	NAND_DEV_CMD0,
> +	NAND_DEV_CMD1,
> +	NAND_DEV_CMD2,
> +	NAND_DEV_CMD_VLD,
> +	SFLASHC_BURST_CFG,
> +	NAND_ERASED_CW_DETECT_CFG,
> +	NAND_ERASED_CW_DETECT_STATUS,
> +	NAND_EBI2_ECC_BUF_CFG,
> +	FLASH_BUF_ACC,
> +	NAND_CTRL,
> +	NAND_VERSION,
> +	NAND_READ_LOCATION_0,
> +	NAND_READ_LOCATION_1,
> +	NAND_READ_LOCATION_2,
> +	NAND_READ_LOCATION_3,
> +
> +	/* dummy register offsets, used by write_reg_dma */
> +	NAND_DEV_CMD1_RESTORE,
> +	NAND_DEV_CMD_VLD_RESTORE,
> +};
> +
>   /*
>    * This data type corresponds to the BAM transaction which will be used for all
>    * NAND transfers.
> @@ -326,6 +327,7 @@ struct nandc_regs {
>    *				bam dma
>    * @max_cwperpage:		maximum qpic codeword required. calcualted
>    *				from all nand device pagesize
> + * @regs_offsets:		register offset mapping array
>    */
>   struct qcom_nand_controller {
>   	struct nand_hw_control controller;
> @@ -371,6 +373,7 @@ struct qcom_nand_controller {
>   
>   	u32 cmd1, vld;
>   	u32 ecc_modes;
> +	const u32 *regs_offsets;

minor quirk:

s/regs_offsets/reg_offsets

>   };
>   
>   /*
> @@ -434,6 +437,40 @@ struct qcom_nand_driver_data {
>   	bool dma_bam_enabled;
>   };
>   
> +/* Mapping table which contains the actual register offsets */
> +static const u32 regs_offsets[] = {
> +	[NAND_FLASH_CMD] = 0x00,
> +	[NAND_ADDR0] = 0x04,
> +	[NAND_ADDR1] = 0x08,
> +	[NAND_FLASH_CHIP_SELECT] = 0x0c,
> +	[NAND_EXEC_CMD] = 0x10,
> +	[NAND_FLASH_STATUS] = 0x14,
> +	[NAND_BUFFER_STATUS] = 0x18,
> +	[NAND_DEV0_CFG0] = 0x20,
> +	[NAND_DEV0_CFG1] = 0x24,
> +	[NAND_DEV0_ECC_CFG] = 0x28,
> +	[NAND_DEV1_ECC_CFG] = 0x2c,
> +	[NAND_DEV1_CFG0] = 0x30,
> +	[NAND_DEV1_CFG1] = 0x34,
> +	[NAND_READ_ID] = 0x40,
> +	[NAND_READ_STATUS] = 0x44,
> +	[NAND_DEV_CMD0] = 0xa0,
> +	[NAND_DEV_CMD1] = 0xa4,
> +	[NAND_DEV_CMD2] = 0xa8,
> +	[NAND_DEV_CMD_VLD] = 0xac,
> +	[SFLASHC_BURST_CFG] = 0xe0,
> +	[NAND_ERASED_CW_DETECT_CFG] = 0xe8,
> +	[NAND_ERASED_CW_DETECT_STATUS] = 0xec,
> +	[NAND_EBI2_ECC_BUF_CFG] = 0xf0,
> +	[FLASH_BUF_ACC] = 0x100,
> +	[NAND_CTRL] = 0xf00,
> +	[NAND_VERSION] = 0xf08,
> +	[NAND_READ_LOCATION_0] = 0xf20,
> +	[NAND_READ_LOCATION_1] = 0xf24,
> +	[NAND_READ_LOCATION_2] = 0xf28,
> +	[NAND_READ_LOCATION_3] = 0xf2c,
> +};
> +
>   /* Frees the BAM transaction memory */
>   static void free_bam_transaction(struct qcom_nand_controller *nandc)
>   {
> @@ -516,13 +553,13 @@ static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>   
>   static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
>   {
> -	return ioread32(nandc->base + offset);
> +	return ioread32(nandc->base + nandc->regs_offsets[offset]);
>   }
>   
>   static inline void nandc_write(struct qcom_nand_controller *nandc, int offset,
>   			       u32 val)
>   {
> -	iowrite32(val, nandc->base + offset);
> +	iowrite32(val, nandc->base + nandc->regs_offsets[offset]);
>   }
>   
>   static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
> @@ -903,11 +940,12 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
>   	nandc->reg_read_pos += num_regs;
>   
>   	if (nandc->dma_bam_enabled)
> -		return prep_dma_desc_command(nandc, true, first, vaddr,
> +		return prep_dma_desc_command(nandc, true,
> +					     nandc->regs_offsets[first], vaddr,
>   					     num_regs, flags);
>   
> -	return prep_dma_desc(nandc, true, first, vaddr, num_regs * sizeof(u32),
> -			     flow_control);
> +	return prep_dma_desc(nandc, true, nandc->regs_offsets[first], vaddr,
> +			     num_regs * sizeof(u32), flow_control);
>   }
>   
>   /*
> @@ -946,11 +984,12 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>   		first = NAND_DEV_CMD_VLD;
>   
>   	if (nandc->dma_bam_enabled)
> -		return prep_dma_desc_command(nandc, false, first, vaddr,
> +		return prep_dma_desc_command(nandc, false,
> +					     nandc->regs_offsets[first], vaddr,
>   					     num_regs, flags);
>   
> -	return prep_dma_desc(nandc, false, first, vaddr, num_regs * sizeof(u32),
> -			     flow_control);
> +	return prep_dma_desc(nandc, false, nandc->regs_offsets[first], vaddr,
> +			     num_regs * sizeof(u32), flow_control);
>   }
>   
>   /*
> @@ -968,7 +1007,8 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>   		return prep_dma_desc_data_bam(nandc, true, reg_off, vaddr, size,
>   					      flags);
>   
> -	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
> +	return prep_dma_desc(nandc, true, nandc->regs_offsets[FLASH_BUF_ACC] +
> +			     reg_off - FLASH_BUF_ACC, vaddr, size, false);

This doesn't make sense. The integer corresponding to FLASH_BUF_ACC enum constant shouldn't be
involved in any calculations.

It would be better to pass the correct param to reg_off in all the call sites to read_data_dma()
and write_data_dma()

Looks good otherwise.

Archit

>   }
>   
>   /*
> @@ -986,7 +1026,8 @@ static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>   		return prep_dma_desc_data_bam(nandc, false, reg_off, vaddr,
>   					      size, flags);
>   
> -	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
> +	return prep_dma_desc(nandc, false, nandc->regs_offsets[FLASH_BUF_ACC] +
> +			     reg_off - FLASH_BUF_ACC, vaddr, size, false);
>   }
>   
>   /*
> @@ -2791,6 +2832,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>   
>   	nandc->ecc_modes = driver_data->ecc_modes;
>   	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
> +	nandc->regs_offsets = regs_offsets;
>   
>   	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>   	nandc->base = devm_ioremap_resource(dev, res);
> 

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 12/14] qcom: mtd: nand: change register offset defines with enums

[Abhishek Sahu]

On 2017-07-04 15:25, Archit Taneja wrote:
> On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
>> The current driver defines the register offset with preprocessor
>> macro which is defined crossponding to NAND controller version
>> 1.4.0. This patch changes these macro with enumeration. It also
>> adds mapping array which contains controller register offsets for
>> each register offset enumeration. This mapping array will be
>> referenced before each register read and writes, where the register
>> offset enumeration is being replaced with actual register offsets.
>> 
>> Signed-off-by: Abhishek Sahu <absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>> ---
>>   drivers/mtd/nand/qcom_nandc.c | 136 
>> +++++++++++++++++++++++++++---------------
>>   1 file changed, 89 insertions(+), 47 deletions(-)
>> 
>> diff --git a/drivers/mtd/nand/qcom_nandc.c 
>> b/drivers/mtd/nand/qcom_nandc.c
>> index 6d749b6..24750e6 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -24,43 +24,6 @@
>>   #include <linux/delay.h>
>>   #include <linux/dma/qcom_bam_dma.h>
>> 
>> -/* NANDc reg offsets */
>> -#define	NAND_FLASH_CMD			0x00
>> -#define	NAND_ADDR0			0x04
>> -#define	NAND_ADDR1			0x08
>> -#define	NAND_FLASH_CHIP_SELECT		0x0c
>> -#define	NAND_EXEC_CMD			0x10
>> -#define	NAND_FLASH_STATUS		0x14
>> -#define	NAND_BUFFER_STATUS		0x18
>> -#define	NAND_DEV0_CFG0			0x20
>> -#define	NAND_DEV0_CFG1			0x24
>> -#define	NAND_DEV0_ECC_CFG		0x28
>> -#define	NAND_DEV1_ECC_CFG		0x2c
>> -#define	NAND_DEV1_CFG0			0x30
>> -#define	NAND_DEV1_CFG1			0x34
>> -#define	NAND_READ_ID			0x40
>> -#define	NAND_READ_STATUS		0x44
>> -#define	NAND_DEV_CMD0			0xa0
>> -#define	NAND_DEV_CMD1			0xa4
>> -#define	NAND_DEV_CMD2			0xa8
>> -#define	NAND_DEV_CMD_VLD		0xac
>> -#define	SFLASHC_BURST_CFG		0xe0
>> -#define	NAND_ERASED_CW_DETECT_CFG	0xe8
>> -#define	NAND_ERASED_CW_DETECT_STATUS	0xec
>> -#define	NAND_EBI2_ECC_BUF_CFG		0xf0
>> -#define	FLASH_BUF_ACC			0x100
>> -
>> -#define	NAND_CTRL			0xf00
>> -#define	NAND_VERSION			0xf08
>> -#define	NAND_READ_LOCATION_0		0xf20
>> -#define	NAND_READ_LOCATION_1		0xf24
>> -#define	NAND_READ_LOCATION_2		0xf28
>> -#define	NAND_READ_LOCATION_3		0xf2c
>> -
>> -/* dummy register offsets, used by write_reg_dma */
>> -#define	NAND_DEV_CMD1_RESTORE		0xdead
>> -#define	NAND_DEV_CMD_VLD_RESTORE	0xbeef
>> -
>>   /* NAND_FLASH_CMD bits */
>>   #define	PAGE_ACC			BIT(4)
>>   #define	LAST_PAGE			BIT(5)
>> @@ -204,6 +167,44 @@
>>   #define QPIC_PER_CW_MAX_CMD_SGL		(32)
>>   #define QPIC_PER_CW_MAX_DATA_SGL	(8)
>> 
>> +/* NANDc reg offsets enumeration */
>> +enum {
>> +	NAND_FLASH_CMD,
>> +	NAND_ADDR0,
>> +	NAND_ADDR1,
>> +	NAND_FLASH_CHIP_SELECT,
>> +	NAND_EXEC_CMD,
>> +	NAND_FLASH_STATUS,
>> +	NAND_BUFFER_STATUS,
>> +	NAND_DEV0_CFG0,
>> +	NAND_DEV0_CFG1,
>> +	NAND_DEV0_ECC_CFG,
>> +	NAND_DEV1_ECC_CFG,
>> +	NAND_DEV1_CFG0,
>> +	NAND_DEV1_CFG1,
>> +	NAND_READ_ID,
>> +	NAND_READ_STATUS,
>> +	NAND_DEV_CMD0,
>> +	NAND_DEV_CMD1,
>> +	NAND_DEV_CMD2,
>> +	NAND_DEV_CMD_VLD,
>> +	SFLASHC_BURST_CFG,
>> +	NAND_ERASED_CW_DETECT_CFG,
>> +	NAND_ERASED_CW_DETECT_STATUS,
>> +	NAND_EBI2_ECC_BUF_CFG,
>> +	FLASH_BUF_ACC,
>> +	NAND_CTRL,
>> +	NAND_VERSION,
>> +	NAND_READ_LOCATION_0,
>> +	NAND_READ_LOCATION_1,
>> +	NAND_READ_LOCATION_2,
>> +	NAND_READ_LOCATION_3,
>> +
>> +	/* dummy register offsets, used by write_reg_dma */
>> +	NAND_DEV_CMD1_RESTORE,
>> +	NAND_DEV_CMD_VLD_RESTORE,
>> +};
>> +
>>   /*
>>    * This data type corresponds to the BAM transaction which will be 
>> used for all
>>    * NAND transfers.
>> @@ -326,6 +327,7 @@ struct nandc_regs {
>>    *				bam dma
>>    * @max_cwperpage:		maximum qpic codeword required. calcualted
>>    *				from all nand device pagesize
>> + * @regs_offsets:		register offset mapping array
>>    */
>>   struct qcom_nand_controller {
>>   	struct nand_hw_control controller;
>> @@ -371,6 +373,7 @@ struct qcom_nand_controller {
>> 
>>   	u32 cmd1, vld;
>>   	u32 ecc_modes;
>> +	const u32 *regs_offsets;
> 
> minor quirk:
> 
> s/regs_offsets/reg_offsets
> 

  Sure. I will fix this in v2.

>>   };
>> 
>>   /*
>> @@ -434,6 +437,40 @@ struct qcom_nand_driver_data {
>>   	bool dma_bam_enabled;
>>   };
>> 
>> +/* Mapping table which contains the actual register offsets */
>> +static const u32 regs_offsets[] = {
>> +	[NAND_FLASH_CMD] = 0x00,
>> +	[NAND_ADDR0] = 0x04,
>> +	[NAND_ADDR1] = 0x08,
>> +	[NAND_FLASH_CHIP_SELECT] = 0x0c,
>> +	[NAND_EXEC_CMD] = 0x10,
>> +	[NAND_FLASH_STATUS] = 0x14,
>> +	[NAND_BUFFER_STATUS] = 0x18,
>> +	[NAND_DEV0_CFG0] = 0x20,
>> +	[NAND_DEV0_CFG1] = 0x24,
>> +	[NAND_DEV0_ECC_CFG] = 0x28,
>> +	[NAND_DEV1_ECC_CFG] = 0x2c,
>> +	[NAND_DEV1_CFG0] = 0x30,
>> +	[NAND_DEV1_CFG1] = 0x34,
>> +	[NAND_READ_ID] = 0x40,
>> +	[NAND_READ_STATUS] = 0x44,
>> +	[NAND_DEV_CMD0] = 0xa0,
>> +	[NAND_DEV_CMD1] = 0xa4,
>> +	[NAND_DEV_CMD2] = 0xa8,
>> +	[NAND_DEV_CMD_VLD] = 0xac,
>> +	[SFLASHC_BURST_CFG] = 0xe0,
>> +	[NAND_ERASED_CW_DETECT_CFG] = 0xe8,
>> +	[NAND_ERASED_CW_DETECT_STATUS] = 0xec,
>> +	[NAND_EBI2_ECC_BUF_CFG] = 0xf0,
>> +	[FLASH_BUF_ACC] = 0x100,
>> +	[NAND_CTRL] = 0xf00,
>> +	[NAND_VERSION] = 0xf08,
>> +	[NAND_READ_LOCATION_0] = 0xf20,
>> +	[NAND_READ_LOCATION_1] = 0xf24,
>> +	[NAND_READ_LOCATION_2] = 0xf28,
>> +	[NAND_READ_LOCATION_3] = 0xf2c,
>> +};
>> +
>>   /* Frees the BAM transaction memory */
>>   static void free_bam_transaction(struct qcom_nand_controller *nandc)
>>   {
>> @@ -516,13 +553,13 @@ static inline struct qcom_nand_host 
>> *to_qcom_nand_host(struct nand_chip *chip)
>> 
>>   static inline u32 nandc_read(struct qcom_nand_controller *nandc, int 
>> offset)
>>   {
>> -	return ioread32(nandc->base + offset);
>> +	return ioread32(nandc->base + nandc->regs_offsets[offset]);
>>   }
>> 
>>   static inline void nandc_write(struct qcom_nand_controller *nandc, 
>> int offset,
>>   			       u32 val)
>>   {
>> -	iowrite32(val, nandc->base + offset);
>> +	iowrite32(val, nandc->base + nandc->regs_offsets[offset]);
>>   }
>> 
>>   static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int 
>> offset)
>> @@ -903,11 +940,12 @@ static int read_reg_dma(struct 
>> qcom_nand_controller *nandc, int first,
>>   	nandc->reg_read_pos += num_regs;
>> 
>>   	if (nandc->dma_bam_enabled)
>> -		return prep_dma_desc_command(nandc, true, first, vaddr,
>> +		return prep_dma_desc_command(nandc, true,
>> +					     nandc->regs_offsets[first], vaddr,
>>   					     num_regs, flags);
>> 
>> -	return prep_dma_desc(nandc, true, first, vaddr, num_regs * 
>> sizeof(u32),
>> -			     flow_control);
>> +	return prep_dma_desc(nandc, true, nandc->regs_offsets[first], vaddr,
>> +			     num_regs * sizeof(u32), flow_control);
>>   }
>> 
>>   /*
>> @@ -946,11 +984,12 @@ static int write_reg_dma(struct 
>> qcom_nand_controller *nandc, int first,
>>   		first = NAND_DEV_CMD_VLD;
>> 
>>   	if (nandc->dma_bam_enabled)
>> -		return prep_dma_desc_command(nandc, false, first, vaddr,
>> +		return prep_dma_desc_command(nandc, false,
>> +					     nandc->regs_offsets[first], vaddr,
>>   					     num_regs, flags);
>> 
>> -	return prep_dma_desc(nandc, false, first, vaddr, num_regs * 
>> sizeof(u32),
>> -			     flow_control);
>> +	return prep_dma_desc(nandc, false, nandc->regs_offsets[first], 
>> vaddr,
>> +			     num_regs * sizeof(u32), flow_control);
>>   }
>> 
>>   /*
>> @@ -968,7 +1007,8 @@ static int read_data_dma(struct 
>> qcom_nand_controller *nandc, int reg_off,
>>   		return prep_dma_desc_data_bam(nandc, true, reg_off, vaddr, size,
>>   					      flags);
>> 
>> -	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
>> +	return prep_dma_desc(nandc, true, nandc->regs_offsets[FLASH_BUF_ACC] 
>> +
>> +			     reg_off - FLASH_BUF_ACC, vaddr, size, false);
> 
> This doesn't make sense. The integer corresponding to FLASH_BUF_ACC
> enum constant shouldn't be
> involved in any calculations.
> 
> It would be better to pass the correct param to reg_off in all the
> call sites to read_data_dma()
> and write_data_dma()
> 

  Yes. I will do the same in v2.

> Looks good otherwise.
> 
> Archit
> 
>>   }
>> 
>>   /*
>> @@ -986,7 +1026,8 @@ static int write_data_dma(struct 
>> qcom_nand_controller *nandc, int reg_off,
>>   		return prep_dma_desc_data_bam(nandc, false, reg_off, vaddr,
>>   					      size, flags);
>> 
>> -	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
>> +	return prep_dma_desc(nandc, false, 
>> nandc->regs_offsets[FLASH_BUF_ACC] +
>> +			     reg_off - FLASH_BUF_ACC, vaddr, size, false);
>>   }
>> 
>>   /*
>> @@ -2791,6 +2832,7 @@ static int qcom_nandc_probe(struct 
>> platform_device *pdev)
>> 
>>   	nandc->ecc_modes = driver_data->ecc_modes;
>>   	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
>> +	nandc->regs_offsets = regs_offsets;
>> 
>>   	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>   	nandc->base = devm_ioremap_resource(dev, res);
>> 

-- 
Abhishek Sahu
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Re: [PATCH 12/14] qcom: mtd: nand: change register offset defines with enums

[Abhishek Sahu]

On 2017-07-04 15:25, Archit Taneja wrote:
> On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
>> The current driver defines the register offset with preprocessor
>> macro which is defined crossponding to NAND controller version
>> 1.4.0. This patch changes these macro with enumeration. It also
>> adds mapping array which contains controller register offsets for
>> each register offset enumeration. This mapping array will be
>> referenced before each register read and writes, where the register
>> offset enumeration is being replaced with actual register offsets.
>> 
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> ---
>>   drivers/mtd/nand/qcom_nandc.c | 136 
>> +++++++++++++++++++++++++++---------------
>>   1 file changed, 89 insertions(+), 47 deletions(-)
>> 
>> diff --git a/drivers/mtd/nand/qcom_nandc.c 
>> b/drivers/mtd/nand/qcom_nandc.c
>> index 6d749b6..24750e6 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -24,43 +24,6 @@
>>   #include <linux/delay.h>
>>   #include <linux/dma/qcom_bam_dma.h>
>> 
>> -/* NANDc reg offsets */
>> -#define	NAND_FLASH_CMD			0x00
>> -#define	NAND_ADDR0			0x04
>> -#define	NAND_ADDR1			0x08
>> -#define	NAND_FLASH_CHIP_SELECT		0x0c
>> -#define	NAND_EXEC_CMD			0x10
>> -#define	NAND_FLASH_STATUS		0x14
>> -#define	NAND_BUFFER_STATUS		0x18
>> -#define	NAND_DEV0_CFG0			0x20
>> -#define	NAND_DEV0_CFG1			0x24
>> -#define	NAND_DEV0_ECC_CFG		0x28
>> -#define	NAND_DEV1_ECC_CFG		0x2c
>> -#define	NAND_DEV1_CFG0			0x30
>> -#define	NAND_DEV1_CFG1			0x34
>> -#define	NAND_READ_ID			0x40
>> -#define	NAND_READ_STATUS		0x44
>> -#define	NAND_DEV_CMD0			0xa0
>> -#define	NAND_DEV_CMD1			0xa4
>> -#define	NAND_DEV_CMD2			0xa8
>> -#define	NAND_DEV_CMD_VLD		0xac
>> -#define	SFLASHC_BURST_CFG		0xe0
>> -#define	NAND_ERASED_CW_DETECT_CFG	0xe8
>> -#define	NAND_ERASED_CW_DETECT_STATUS	0xec
>> -#define	NAND_EBI2_ECC_BUF_CFG		0xf0
>> -#define	FLASH_BUF_ACC			0x100
>> -
>> -#define	NAND_CTRL			0xf00
>> -#define	NAND_VERSION			0xf08
>> -#define	NAND_READ_LOCATION_0		0xf20
>> -#define	NAND_READ_LOCATION_1		0xf24
>> -#define	NAND_READ_LOCATION_2		0xf28
>> -#define	NAND_READ_LOCATION_3		0xf2c
>> -
>> -/* dummy register offsets, used by write_reg_dma */
>> -#define	NAND_DEV_CMD1_RESTORE		0xdead
>> -#define	NAND_DEV_CMD_VLD_RESTORE	0xbeef
>> -
>>   /* NAND_FLASH_CMD bits */
>>   #define	PAGE_ACC			BIT(4)
>>   #define	LAST_PAGE			BIT(5)
>> @@ -204,6 +167,44 @@
>>   #define QPIC_PER_CW_MAX_CMD_SGL		(32)
>>   #define QPIC_PER_CW_MAX_DATA_SGL	(8)
>> 
>> +/* NANDc reg offsets enumeration */
>> +enum {
>> +	NAND_FLASH_CMD,
>> +	NAND_ADDR0,
>> +	NAND_ADDR1,
>> +	NAND_FLASH_CHIP_SELECT,
>> +	NAND_EXEC_CMD,
>> +	NAND_FLASH_STATUS,
>> +	NAND_BUFFER_STATUS,
>> +	NAND_DEV0_CFG0,
>> +	NAND_DEV0_CFG1,
>> +	NAND_DEV0_ECC_CFG,
>> +	NAND_DEV1_ECC_CFG,
>> +	NAND_DEV1_CFG0,
>> +	NAND_DEV1_CFG1,
>> +	NAND_READ_ID,
>> +	NAND_READ_STATUS,
>> +	NAND_DEV_CMD0,
>> +	NAND_DEV_CMD1,
>> +	NAND_DEV_CMD2,
>> +	NAND_DEV_CMD_VLD,
>> +	SFLASHC_BURST_CFG,
>> +	NAND_ERASED_CW_DETECT_CFG,
>> +	NAND_ERASED_CW_DETECT_STATUS,
>> +	NAND_EBI2_ECC_BUF_CFG,
>> +	FLASH_BUF_ACC,
>> +	NAND_CTRL,
>> +	NAND_VERSION,
>> +	NAND_READ_LOCATION_0,
>> +	NAND_READ_LOCATION_1,
>> +	NAND_READ_LOCATION_2,
>> +	NAND_READ_LOCATION_3,
>> +
>> +	/* dummy register offsets, used by write_reg_dma */
>> +	NAND_DEV_CMD1_RESTORE,
>> +	NAND_DEV_CMD_VLD_RESTORE,
>> +};
>> +
>>   /*
>>    * This data type corresponds to the BAM transaction which will be 
>> used for all
>>    * NAND transfers.
>> @@ -326,6 +327,7 @@ struct nandc_regs {
>>    *				bam dma
>>    * @max_cwperpage:		maximum qpic codeword required. calcualted
>>    *				from all nand device pagesize
>> + * @regs_offsets:		register offset mapping array
>>    */
>>   struct qcom_nand_controller {
>>   	struct nand_hw_control controller;
>> @@ -371,6 +373,7 @@ struct qcom_nand_controller {
>> 
>>   	u32 cmd1, vld;
>>   	u32 ecc_modes;
>> +	const u32 *regs_offsets;
> 
> minor quirk:
> 
> s/regs_offsets/reg_offsets
> 

  Sure. I will fix this in v2.

>>   };
>> 
>>   /*
>> @@ -434,6 +437,40 @@ struct qcom_nand_driver_data {
>>   	bool dma_bam_enabled;
>>   };
>> 
>> +/* Mapping table which contains the actual register offsets */
>> +static const u32 regs_offsets[] = {
>> +	[NAND_FLASH_CMD] = 0x00,
>> +	[NAND_ADDR0] = 0x04,
>> +	[NAND_ADDR1] = 0x08,
>> +	[NAND_FLASH_CHIP_SELECT] = 0x0c,
>> +	[NAND_EXEC_CMD] = 0x10,
>> +	[NAND_FLASH_STATUS] = 0x14,
>> +	[NAND_BUFFER_STATUS] = 0x18,
>> +	[NAND_DEV0_CFG0] = 0x20,
>> +	[NAND_DEV0_CFG1] = 0x24,
>> +	[NAND_DEV0_ECC_CFG] = 0x28,
>> +	[NAND_DEV1_ECC_CFG] = 0x2c,
>> +	[NAND_DEV1_CFG0] = 0x30,
>> +	[NAND_DEV1_CFG1] = 0x34,
>> +	[NAND_READ_ID] = 0x40,
>> +	[NAND_READ_STATUS] = 0x44,
>> +	[NAND_DEV_CMD0] = 0xa0,
>> +	[NAND_DEV_CMD1] = 0xa4,
>> +	[NAND_DEV_CMD2] = 0xa8,
>> +	[NAND_DEV_CMD_VLD] = 0xac,
>> +	[SFLASHC_BURST_CFG] = 0xe0,
>> +	[NAND_ERASED_CW_DETECT_CFG] = 0xe8,
>> +	[NAND_ERASED_CW_DETECT_STATUS] = 0xec,
>> +	[NAND_EBI2_ECC_BUF_CFG] = 0xf0,
>> +	[FLASH_BUF_ACC] = 0x100,
>> +	[NAND_CTRL] = 0xf00,
>> +	[NAND_VERSION] = 0xf08,
>> +	[NAND_READ_LOCATION_0] = 0xf20,
>> +	[NAND_READ_LOCATION_1] = 0xf24,
>> +	[NAND_READ_LOCATION_2] = 0xf28,
>> +	[NAND_READ_LOCATION_3] = 0xf2c,
>> +};
>> +
>>   /* Frees the BAM transaction memory */
>>   static void free_bam_transaction(struct qcom_nand_controller *nandc)
>>   {
>> @@ -516,13 +553,13 @@ static inline struct qcom_nand_host 
>> *to_qcom_nand_host(struct nand_chip *chip)
>> 
>>   static inline u32 nandc_read(struct qcom_nand_controller *nandc, int 
>> offset)
>>   {
>> -	return ioread32(nandc->base + offset);
>> +	return ioread32(nandc->base + nandc->regs_offsets[offset]);
>>   }
>> 
>>   static inline void nandc_write(struct qcom_nand_controller *nandc, 
>> int offset,
>>   			       u32 val)
>>   {
>> -	iowrite32(val, nandc->base + offset);
>> +	iowrite32(val, nandc->base + nandc->regs_offsets[offset]);
>>   }
>> 
>>   static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int 
>> offset)
>> @@ -903,11 +940,12 @@ static int read_reg_dma(struct 
>> qcom_nand_controller *nandc, int first,
>>   	nandc->reg_read_pos += num_regs;
>> 
>>   	if (nandc->dma_bam_enabled)
>> -		return prep_dma_desc_command(nandc, true, first, vaddr,
>> +		return prep_dma_desc_command(nandc, true,
>> +					     nandc->regs_offsets[first], vaddr,
>>   					     num_regs, flags);
>> 
>> -	return prep_dma_desc(nandc, true, first, vaddr, num_regs * 
>> sizeof(u32),
>> -			     flow_control);
>> +	return prep_dma_desc(nandc, true, nandc->regs_offsets[first], vaddr,
>> +			     num_regs * sizeof(u32), flow_control);
>>   }
>> 
>>   /*
>> @@ -946,11 +984,12 @@ static int write_reg_dma(struct 
>> qcom_nand_controller *nandc, int first,
>>   		first = NAND_DEV_CMD_VLD;
>> 
>>   	if (nandc->dma_bam_enabled)
>> -		return prep_dma_desc_command(nandc, false, first, vaddr,
>> +		return prep_dma_desc_command(nandc, false,
>> +					     nandc->regs_offsets[first], vaddr,
>>   					     num_regs, flags);
>> 
>> -	return prep_dma_desc(nandc, false, first, vaddr, num_regs * 
>> sizeof(u32),
>> -			     flow_control);
>> +	return prep_dma_desc(nandc, false, nandc->regs_offsets[first], 
>> vaddr,
>> +			     num_regs * sizeof(u32), flow_control);
>>   }
>> 
>>   /*
>> @@ -968,7 +1007,8 @@ static int read_data_dma(struct 
>> qcom_nand_controller *nandc, int reg_off,
>>   		return prep_dma_desc_data_bam(nandc, true, reg_off, vaddr, size,
>>   					      flags);
>> 
>> -	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
>> +	return prep_dma_desc(nandc, true, nandc->regs_offsets[FLASH_BUF_ACC] 
>> +
>> +			     reg_off - FLASH_BUF_ACC, vaddr, size, false);
> 
> This doesn't make sense. The integer corresponding to FLASH_BUF_ACC
> enum constant shouldn't be
> involved in any calculations.
> 
> It would be better to pass the correct param to reg_off in all the
> call sites to read_data_dma()
> and write_data_dma()
> 

  Yes. I will do the same in v2.

> Looks good otherwise.
> 
> Archit
> 
>>   }
>> 
>>   /*
>> @@ -986,7 +1026,8 @@ static int write_data_dma(struct 
>> qcom_nand_controller *nandc, int reg_off,
>>   		return prep_dma_desc_data_bam(nandc, false, reg_off, vaddr,
>>   					      size, flags);
>> 
>> -	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
>> +	return prep_dma_desc(nandc, false, 
>> nandc->regs_offsets[FLASH_BUF_ACC] +
>> +			     reg_off - FLASH_BUF_ACC, vaddr, size, false);
>>   }
>> 
>>   /*
>> @@ -2791,6 +2832,7 @@ static int qcom_nandc_probe(struct 
>> platform_device *pdev)
>> 
>>   	nandc->ecc_modes = driver_data->ecc_modes;
>>   	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
>> +	nandc->regs_offsets = regs_offsets;
>> 
>>   	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>   	nandc->base = devm_ioremap_resource(dev, res);
>> 

-- 
Abhishek Sahu

[PATCH 14/14] qcom: mtd: nand: programmed NAND_DEV_CMD_VLD register

[Abhishek Sahu]

The current driver is failing without complete bootchain in
BAM mode since NAND_DEV_CMD_VLD value is not valid. So
programmed the required value in NAND_DEV_CMD_VLD register.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/mtd/nand/qcom_nandc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 641e85d..260167b 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -121,6 +121,9 @@
 
 /* NAND_CTRL bits */
 #define	BAM_MODE_EN			BIT(0)
+
+/* Value for NAND_DEV_CMD_VLD */
+#define NAND_DEV_CMD_VLD_VAL		(0x1d)
 /*
  * the NAND controller performs reads/writes with ECC in 516 byte chunks.
  * the driver calls the chunks 'step' or 'codeword' interchangeably
@@ -2676,6 +2679,7 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
 
 	/* kill onenand */
 	nandc_write(nandc, SFLASHC_BURST_CFG, 0);
+	nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
 
 	/* enable ADM or BAM DMA */
 	if (!nandc->dma_bam_enabled) {
-- 
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