[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

To support sparse GPIO maps, pinctrl-msm client drivers can specify
that a given GPIO has a pin count of zero.  These GPIOs will be
considered "hidden".  Any attempt to claim the GPIO will fail, and they
will not be listed in debugfs.

However, when the driver probes, it calls gpiochip_add_data() which
wants to initialize the direction of all the GPIOs, even the ones that
are unavailable.  Therefore, msm_gpio_get_direction() checks to make
sure the pin is available.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 34 ++++++++++++++++++++++++++++++----
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 273badd..e915db4 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 	return 0;
 }
 
+/*
+ * Request a GPIO. If the number of pins for this GPIO group is zero,
+ * then assume that the GPIO is unavailable.
+ */
+static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
+{
+	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	const struct msm_pingroup *g;
+
+	g = &pctrl->soc->groups[offset];
+
+	return g->npins ? 0 : -ENODEV;
+}
+
 static const struct pinmux_ops msm_pinmux_ops = {
+	.request		= msm_request,
 	.get_functions_count	= msm_get_functions_count,
 	.get_function_name	= msm_get_function_name,
 	.get_function_groups	= msm_get_function_groups,
@@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 
 	g = &pctrl->soc->groups[offset];
 
+	/*
+	 * If the GPIO is unavailable, just return error.  This is necessary
+	 * because the GPIO layer tries to initialize the direction of all
+	 * the GPIOs, even the ones that are unavailable.
+	 */
+	if (!g->npins)
+		return -ENODEV;
+
 	val = readl(pctrl->regs + g->ctl_reg);
 
 	/* 0 = output, 1 = input */
@@ -494,6 +517,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 	};
 
 	g = &pctrl->soc->groups[offset];
+
+	/* If the GPIO group has no pins, then don't show it. */
+	if (!g->npins)
+		return;
+
 	ctl_reg = readl(pctrl->regs + g->ctl_reg);
 
 	is_out = !!(ctl_reg & BIT(g->oe_bit));
@@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 
 	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
-	seq_printf(s, " %s", pulls[pull]);
+	seq_printf(s, " %s\n", pulls[pull]);
 }
 
 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
@@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 	unsigned gpio = chip->base;
 	unsigned i;
 
-	for (i = 0; i < chip->ngpio; i++, gpio++) {
+	for (i = 0; i < chip->ngpio; i++, gpio++)
 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
-		seq_puts(s, "\n");
-	}
 }
 
 #else
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

To support sparse GPIO maps, pinctrl-msm client drivers can specify
that a given GPIO has a pin count of zero.  These GPIOs will be
considered "hidden".  Any attempt to claim the GPIO will fail, and they
will not be listed in debugfs.

However, when the driver probes, it calls gpiochip_add_data() which
wants to initialize the direction of all the GPIOs, even the ones that
are unavailable.  Therefore, msm_gpio_get_direction() checks to make
sure the pin is available.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 34 ++++++++++++++++++++++++++++++----
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 273badd..e915db4 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 	return 0;
 }
 
+/*
+ * Request a GPIO. If the number of pins for this GPIO group is zero,
+ * then assume that the GPIO is unavailable.
+ */
+static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
+{
+	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	const struct msm_pingroup *g;
+
+	g = &pctrl->soc->groups[offset];
+
+	return g->npins ? 0 : -ENODEV;
+}
+
 static const struct pinmux_ops msm_pinmux_ops = {
+	.request		= msm_request,
 	.get_functions_count	= msm_get_functions_count,
 	.get_function_name	= msm_get_function_name,
 	.get_function_groups	= msm_get_function_groups,
@@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 
 	g = &pctrl->soc->groups[offset];
 
+	/*
+	 * If the GPIO is unavailable, just return error.  This is necessary
+	 * because the GPIO layer tries to initialize the direction of all
+	 * the GPIOs, even the ones that are unavailable.
+	 */
+	if (!g->npins)
+		return -ENODEV;
+
 	val = readl(pctrl->regs + g->ctl_reg);
 
 	/* 0 = output, 1 = input */
@@ -494,6 +517,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 	};
 
 	g = &pctrl->soc->groups[offset];
+
+	/* If the GPIO group has no pins, then don't show it. */
+	if (!g->npins)
+		return;
+
 	ctl_reg = readl(pctrl->regs + g->ctl_reg);
 
 	is_out = !!(ctl_reg & BIT(g->oe_bit));
@@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 
 	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
-	seq_printf(s, " %s", pulls[pull]);
+	seq_printf(s, " %s\n", pulls[pull]);
 }
 
 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
@@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 	unsigned gpio = chip->base;
 	unsigned i;
 
-	for (i = 0; i < chip->ngpio; i++, gpio++) {
+	for (i = 0; i < chip->ngpio; i++, gpio++)
 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
-		seq_puts(s, "\n");
-	}
 }
 
 #else
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 2/2] [v2] pinctrl: qcom: qdf2xxx: expose only some GPIO pins

[Timur Tabi]

On Qualcomm Technologies QDF2xxx platforms, only a subset of the GPIOs
are actually available to the HLOS.  The others are blocked by the XPU,
and any attempt to access them will cause an XPU violation that halts
the system.

Instead, the ACPI table now lists only specific GPIOs that are exposed
externally as generic GPIO pins.  The full list of GPIOs is still
registered, but the pin count for the unavailable GPIOs is set to zero.
The pinctrl-msm driver will block those unavailable GPIOs from being
accessed.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 112 +++++++++++++++++++++------------
 1 file changed, 73 insertions(+), 39 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
index bb3ce5c..106e6c1 100644
--- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -43,68 +43,102 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
 	struct pinctrl_pin_desc *pins;
 	struct msm_pingroup *groups;
 	char (*names)[NAME_SIZE];
-	unsigned int i;
-	u32 num_gpios;
+	unsigned int i, num_gpios, max_gpios;
+	u32 *gpios;
 	int ret;
 
-	/* Query the number of GPIOs from ACPI */
-	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
+	/* The total number of GPIOs that exist */
+	ret = device_property_read_u32(&pdev->dev, "num-gpios", &max_gpios);
 	if (ret < 0) {
-		dev_warn(&pdev->dev, "missing num-gpios property\n");
+		dev_err(&pdev->dev, "missing num-gpios property\n");
 		return ret;
 	}
+	if (!max_gpios || max_gpios > MAX_GPIOS) {
+		dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
+		return -EINVAL;
+	}
 
-	if (!num_gpios || num_gpios > MAX_GPIOS) {
-		dev_warn(&pdev->dev, "invalid num-gpios property\n");
+	/* The number of GPIOs in the approved list */
+	num_gpios = ret = device_property_read_u32_array(&pdev->dev, "gpios",
+							 NULL, 0);
+	if (ret < 0) {
+		dev_err(&pdev->dev,
+			"missing or invalid 'gpios' property (ret=%i)\n", ret);
+		return ret;
+	}
+	if (ret == 0) {
+		dev_warn(&pdev->dev, "no GPIOs defined\n");
 		return -ENODEV;
 	}
 
-	pins = devm_kcalloc(&pdev->dev, num_gpios,
+	gpios = devm_kcalloc(&pdev->dev, num_gpios, sizeof(u32), GFP_KERNEL);
+	if (!gpios)
+		return -ENOMEM;
+
+	ret = device_property_read_u32_array(&pdev->dev, "gpios", gpios,
+					     num_gpios);
+	if (ret < 0) {
+		dev_err(&pdev->dev,
+			"could not read list of GPIOs (ret=%i)\n", ret);
+		return ret;
+	}
+
+	pins = devm_kcalloc(&pdev->dev, max_gpios,
 		sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
-	groups = devm_kcalloc(&pdev->dev, num_gpios,
+	groups = devm_kcalloc(&pdev->dev, max_gpios,
 		sizeof(struct msm_pingroup), GFP_KERNEL);
 	names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
 
 	if (!pins || !groups || !names)
 		return -ENOMEM;
 
-	for (i = 0; i < num_gpios; i++) {
-		snprintf(names[i], NAME_SIZE, "gpio%u", i);
-
+	/*
+	 * Initialize the array.  GPIOs not listed in the 'gpios' array
+	 * still need a number and a name, but nothing else.
+	 */
+	for (i = 0; i < max_gpios; i++) {
 		pins[i].number = i;
-		pins[i].name = names[i];
-
-		groups[i].npins = 1;
-		groups[i].name = names[i];
 		groups[i].pins = &pins[i].number;
+	}
 
-		groups[i].ctl_reg = 0x10000 * i;
-		groups[i].io_reg = 0x04 + 0x10000 * i;
-		groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
-		groups[i].intr_status_reg = 0x0c + 0x10000 * i;
-		groups[i].intr_target_reg = 0x08 + 0x10000 * i;
-
-		groups[i].mux_bit = 2;
-		groups[i].pull_bit = 0;
-		groups[i].drv_bit = 6;
-		groups[i].oe_bit = 9;
-		groups[i].in_bit = 0;
-		groups[i].out_bit = 1;
-		groups[i].intr_enable_bit = 0;
-		groups[i].intr_status_bit = 0;
-		groups[i].intr_target_bit = 5;
-		groups[i].intr_target_kpss_val = 1;
-		groups[i].intr_raw_status_bit = 4;
-		groups[i].intr_polarity_bit = 1;
-		groups[i].intr_detection_bit = 2;
-		groups[i].intr_detection_width = 2;
+	/* Populate the entries that are meant to be exposes as GPIOs. */
+	for (i = 0; i < num_gpios; i++) {
+		unsigned int gpio = gpios[i];
+
+		groups[gpio].npins = 1;
+		snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
+		pins[gpio].name = names[i];
+		groups[gpio].name = names[i];
+
+		groups[gpio].ctl_reg = 0x10000 * gpio;
+		groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
+		groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
+		groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
+		groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
+
+		groups[gpio].mux_bit = 2;
+		groups[gpio].pull_bit = 0;
+		groups[gpio].drv_bit = 6;
+		groups[gpio].oe_bit = 9;
+		groups[gpio].in_bit = 0;
+		groups[gpio].out_bit = 1;
+		groups[gpio].intr_enable_bit = 0;
+		groups[gpio].intr_status_bit = 0;
+		groups[gpio].intr_target_bit = 5;
+		groups[gpio].intr_target_kpss_val = 1;
+		groups[gpio].intr_raw_status_bit = 4;
+		groups[gpio].intr_polarity_bit = 1;
+		groups[gpio].intr_detection_bit = 2;
+		groups[gpio].intr_detection_width = 2;
 	}
 
+	devm_kfree(&pdev->dev, gpios);
+
 	qdf2xxx_pinctrl.pins = pins;
 	qdf2xxx_pinctrl.groups = groups;
-	qdf2xxx_pinctrl.npins = num_gpios;
-	qdf2xxx_pinctrl.ngroups = num_gpios;
-	qdf2xxx_pinctrl.ngpios = num_gpios;
+	qdf2xxx_pinctrl.npins = max_gpios;
+	qdf2xxx_pinctrl.ngroups = max_gpios;
+	qdf2xxx_pinctrl.ngpios = max_gpios;
 
 	return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
 }
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 2/2] [v2] pinctrl: qcom: qdf2xxx: expose only some GPIO pins

[Timur Tabi]

On Qualcomm Technologies QDF2xxx platforms, only a subset of the GPIOs
are actually available to the HLOS.  The others are blocked by the XPU,
and any attempt to access them will cause an XPU violation that halts
the system.

Instead, the ACPI table now lists only specific GPIOs that are exposed
externally as generic GPIO pins.  The full list of GPIOs is still
registered, but the pin count for the unavailable GPIOs is set to zero.
The pinctrl-msm driver will block those unavailable GPIOs from being
accessed.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 112 +++++++++++++++++++++------------
 1 file changed, 73 insertions(+), 39 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
index bb3ce5c..106e6c1 100644
--- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -43,68 +43,102 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
 	struct pinctrl_pin_desc *pins;
 	struct msm_pingroup *groups;
 	char (*names)[NAME_SIZE];
-	unsigned int i;
-	u32 num_gpios;
+	unsigned int i, num_gpios, max_gpios;
+	u32 *gpios;
 	int ret;
 
-	/* Query the number of GPIOs from ACPI */
-	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
+	/* The total number of GPIOs that exist */
+	ret = device_property_read_u32(&pdev->dev, "num-gpios", &max_gpios);
 	if (ret < 0) {
-		dev_warn(&pdev->dev, "missing num-gpios property\n");
+		dev_err(&pdev->dev, "missing num-gpios property\n");
 		return ret;
 	}
+	if (!max_gpios || max_gpios > MAX_GPIOS) {
+		dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
+		return -EINVAL;
+	}
 
-	if (!num_gpios || num_gpios > MAX_GPIOS) {
-		dev_warn(&pdev->dev, "invalid num-gpios property\n");
+	/* The number of GPIOs in the approved list */
+	num_gpios = ret = device_property_read_u32_array(&pdev->dev, "gpios",
+							 NULL, 0);
+	if (ret < 0) {
+		dev_err(&pdev->dev,
+			"missing or invalid 'gpios' property (ret=%i)\n", ret);
+		return ret;
+	}
+	if (ret == 0) {
+		dev_warn(&pdev->dev, "no GPIOs defined\n");
 		return -ENODEV;
 	}
 
-	pins = devm_kcalloc(&pdev->dev, num_gpios,
+	gpios = devm_kcalloc(&pdev->dev, num_gpios, sizeof(u32), GFP_KERNEL);
+	if (!gpios)
+		return -ENOMEM;
+
+	ret = device_property_read_u32_array(&pdev->dev, "gpios", gpios,
+					     num_gpios);
+	if (ret < 0) {
+		dev_err(&pdev->dev,
+			"could not read list of GPIOs (ret=%i)\n", ret);
+		return ret;
+	}
+
+	pins = devm_kcalloc(&pdev->dev, max_gpios,
 		sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
-	groups = devm_kcalloc(&pdev->dev, num_gpios,
+	groups = devm_kcalloc(&pdev->dev, max_gpios,
 		sizeof(struct msm_pingroup), GFP_KERNEL);
 	names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
 
 	if (!pins || !groups || !names)
 		return -ENOMEM;
 
-	for (i = 0; i < num_gpios; i++) {
-		snprintf(names[i], NAME_SIZE, "gpio%u", i);
-
+	/*
+	 * Initialize the array.  GPIOs not listed in the 'gpios' array
+	 * still need a number and a name, but nothing else.
+	 */
+	for (i = 0; i < max_gpios; i++) {
 		pins[i].number = i;
-		pins[i].name = names[i];
-
-		groups[i].npins = 1;
-		groups[i].name = names[i];
 		groups[i].pins = &pins[i].number;
+	}
 
-		groups[i].ctl_reg = 0x10000 * i;
-		groups[i].io_reg = 0x04 + 0x10000 * i;
-		groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
-		groups[i].intr_status_reg = 0x0c + 0x10000 * i;
-		groups[i].intr_target_reg = 0x08 + 0x10000 * i;
-
-		groups[i].mux_bit = 2;
-		groups[i].pull_bit = 0;
-		groups[i].drv_bit = 6;
-		groups[i].oe_bit = 9;
-		groups[i].in_bit = 0;
-		groups[i].out_bit = 1;
-		groups[i].intr_enable_bit = 0;
-		groups[i].intr_status_bit = 0;
-		groups[i].intr_target_bit = 5;
-		groups[i].intr_target_kpss_val = 1;
-		groups[i].intr_raw_status_bit = 4;
-		groups[i].intr_polarity_bit = 1;
-		groups[i].intr_detection_bit = 2;
-		groups[i].intr_detection_width = 2;
+	/* Populate the entries that are meant to be exposes as GPIOs. */
+	for (i = 0; i < num_gpios; i++) {
+		unsigned int gpio = gpios[i];
+
+		groups[gpio].npins = 1;
+		snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
+		pins[gpio].name = names[i];
+		groups[gpio].name = names[i];
+
+		groups[gpio].ctl_reg = 0x10000 * gpio;
+		groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
+		groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
+		groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
+		groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
+
+		groups[gpio].mux_bit = 2;
+		groups[gpio].pull_bit = 0;
+		groups[gpio].drv_bit = 6;
+		groups[gpio].oe_bit = 9;
+		groups[gpio].in_bit = 0;
+		groups[gpio].out_bit = 1;
+		groups[gpio].intr_enable_bit = 0;
+		groups[gpio].intr_status_bit = 0;
+		groups[gpio].intr_target_bit = 5;
+		groups[gpio].intr_target_kpss_val = 1;
+		groups[gpio].intr_raw_status_bit = 4;
+		groups[gpio].intr_polarity_bit = 1;
+		groups[gpio].intr_detection_bit = 2;
+		groups[gpio].intr_detection_width = 2;
 	}
 
+	devm_kfree(&pdev->dev, gpios);
+
 	qdf2xxx_pinctrl.pins = pins;
 	qdf2xxx_pinctrl.groups = groups;
-	qdf2xxx_pinctrl.npins = num_gpios;
-	qdf2xxx_pinctrl.ngroups = num_gpios;
-	qdf2xxx_pinctrl.ngpios = num_gpios;
+	qdf2xxx_pinctrl.npins = max_gpios;
+	qdf2xxx_pinctrl.ngroups = max_gpios;
+	qdf2xxx_pinctrl.ngpios = max_gpios;
 
 	return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
 }
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 2/2] [v2] pinctrl: qcom: qdf2xxx: expose only some GPIO pins

[Timur Tabi]

On Jun 29, 2017, at 8:42 PM, Timur Tabi wrote:

> On Qualcomm Technologies QDF2xxx platforms, only a subset of the GPIOs
> are actually available to the HLOS.  The others are blocked by the XPU,
> and any attempt to access them will cause an XPU violation that halts
> the system.
> 
> Instead, the ACPI table now lists only specific GPIOs that are exposed
> externally as generic GPIO pins.  The full list of GPIOs is still
> registered, but the pin count for the unavailable GPIOs is set to zero.
> The pinctrl-msm driver will block those unavailable GPIOs from being
> accessed.

Please do not apply this patchset just yet.  

We are considering assigning a new ACPI HID for this change, so that we don't accidentally cause XPU violations when someone uses an old kernel with new firmware.  However, with everyone on vacation this week, many of the stakeholders are not available for discussions.

I'm still interested in reviews on this patchset though.

[PATCH 2/2] [v2] pinctrl: qcom: qdf2xxx: expose only some GPIO pins

[Timur Tabi]

On Jun 29, 2017, at 8:42 PM, Timur Tabi wrote:

> On Qualcomm Technologies QDF2xxx platforms, only a subset of the GPIOs
> are actually available to the HLOS.  The others are blocked by the XPU,
> and any attempt to access them will cause an XPU violation that halts
> the system.
> 
> Instead, the ACPI table now lists only specific GPIOs that are exposed
> externally as generic GPIO pins.  The full list of GPIOs is still
> registered, but the pin count for the unavailable GPIOs is set to zero.
> The pinctrl-msm driver will block those unavailable GPIOs from being
> accessed.

Please do not apply this patchset just yet.  

We are considering assigning a new ACPI HID for this change, so that we don't accidentally cause XPU violations when someone uses an old kernel with new firmware.  However, with everyone on vacation this week, many of the stakeholders are not available for discussions.

I'm still interested in reviews on this patchset though.

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Stephen Boyd]

On 07/14, Timur Tabi wrote:
> On 07/14/2017 04:46 PM, Stephen Boyd wrote:
> >Right, the gpiolib core would need to be updated to request the
> >gpio in gpiochip_add_data() around the loop where it goes and
> >configures things. And it could ignore ones that it can't request
> >there.
> 
> __gpiod_request already calls chip->request(), so this would need to
> be a temporary request.  It seems a bit hackish, but I'll try it.

Yeah, request, configure, free, in a loop. Unless someone is
aware why we don't do that here.

> 
> BTW, I noticed that __gpiod_free() does this:
> 
> 	if (chip->free) {
> 		spin_unlock_irqrestore(&gpio_lock, flags);
> --->		might_sleep_if(chip->can_sleep);
> 		chip->free(chip, gpio_chip_hwgpio(desc));
> 		spin_lock_irqsave(&gpio_lock, flags);
> 
> 
> Should __gpiod_request() also call might_sleep_if()?
> 
> 	if (chip->request) {
> 		/* chip->request may sleep */
> 		spin_unlock_irqrestore(&gpio_lock, flags);
> ---> missing call to might_sleep_if() here?
> 		status = chip->request(chip, gpio_chip_hwgpio(desc));
> 		spin_lock_irqsave(&gpio_lock, flags);
> 

Probably. Except we would have caught it earlier when it was
requested?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Stephen Boyd]

On 07/14, Timur Tabi wrote:
> On 07/14/2017 04:46 PM, Stephen Boyd wrote:
> >Right, the gpiolib core would need to be updated to request the
> >gpio in gpiochip_add_data() around the loop where it goes and
> >configures things. And it could ignore ones that it can't request
> >there.
> 
> __gpiod_request already calls chip->request(), so this would need to
> be a temporary request.  It seems a bit hackish, but I'll try it.

Yeah, request, configure, free, in a loop. Unless someone is
aware why we don't do that here.

> 
> BTW, I noticed that __gpiod_free() does this:
> 
> 	if (chip->free) {
> 		spin_unlock_irqrestore(&gpio_lock, flags);
> --->		might_sleep_if(chip->can_sleep);
> 		chip->free(chip, gpio_chip_hwgpio(desc));
> 		spin_lock_irqsave(&gpio_lock, flags);
> 
> 
> Should __gpiod_request() also call might_sleep_if()?
> 
> 	if (chip->request) {
> 		/* chip->request may sleep */
> 		spin_unlock_irqrestore(&gpio_lock, flags);
> ---> missing call to might_sleep_if() here?
> 		status = chip->request(chip, gpio_chip_hwgpio(desc));
> 		spin_lock_irqsave(&gpio_lock, flags);
> 

Probably. Except we would have caught it earlier when it was
requested?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 04:46 PM, Stephen Boyd wrote:
> Right, the gpiolib core would need to be updated to request the
> gpio in gpiochip_add_data() around the loop where it goes and
> configures things. And it could ignore ones that it can't request
> there.

__gpiod_request already calls chip->request(), so this would need to be 
a temporary request.  It seems a bit hackish, but I'll try it.

BTW, I noticed that __gpiod_free() does this:

	if (chip->free) {
		spin_unlock_irqrestore(&gpio_lock, flags);
--->		might_sleep_if(chip->can_sleep);
		chip->free(chip, gpio_chip_hwgpio(desc));
		spin_lock_irqsave(&gpio_lock, flags);


Should __gpiod_request() also call might_sleep_if()?

	if (chip->request) {
		/* chip->request may sleep */
		spin_unlock_irqrestore(&gpio_lock, flags);
---> missing call to might_sleep_if() here?
		status = chip->request(chip, gpio_chip_hwgpio(desc));
		spin_lock_irqsave(&gpio_lock, flags);


-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 04:46 PM, Stephen Boyd wrote:
> Right, the gpiolib core would need to be updated to request the
> gpio in gpiochip_add_data() around the loop where it goes and
> configures things. And it could ignore ones that it can't request
> there.

__gpiod_request already calls chip->request(), so this would need to be 
a temporary request.  It seems a bit hackish, but I'll try it.

BTW, I noticed that __gpiod_free() does this:

	if (chip->free) {
		spin_unlock_irqrestore(&gpio_lock, flags);
--->		might_sleep_if(chip->can_sleep);
		chip->free(chip, gpio_chip_hwgpio(desc));
		spin_lock_irqsave(&gpio_lock, flags);


Should __gpiod_request() also call might_sleep_if()?

	if (chip->request) {
		/* chip->request may sleep */
		spin_unlock_irqrestore(&gpio_lock, flags);
---> missing call to might_sleep_if() here?
		status = chip->request(chip, gpio_chip_hwgpio(desc));
		spin_lock_irqsave(&gpio_lock, flags);


-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Stephen Boyd]

On 07/14, Timur Tabi wrote:
> On 07/14/2017 12:11 PM, Stephen Boyd wrote:
> >gpiochips also have a request() hook. Can we use that before
> >initializing direction to make sure the GPIO is accessible?
> 
> So I tried it, and it didn't work:
> 
> static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)
> {
> 	pr_info("%s:%u offset=%u\n", __func__, __LINE__, offset);
> 
> 	return 0;
> }
> 
> static struct gpio_chip msm_gpio_template = {
> 	.request          = msm_gpio_request,
> 	...
> 
> msm_gpio_request() is never called when the driver loads.  In fact,
> I can't figure out when it would be called.
> 

Right, the gpiolib core would need to be updated to request the
gpio in gpiochip_add_data() around the loop where it goes and
configures things. And it could ignore ones that it can't request
there.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Stephen Boyd]

On 07/14, Timur Tabi wrote:
> On 07/14/2017 12:11 PM, Stephen Boyd wrote:
> >gpiochips also have a request() hook. Can we use that before
> >initializing direction to make sure the GPIO is accessible?
> 
> So I tried it, and it didn't work:
> 
> static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)
> {
> 	pr_info("%s:%u offset=%u\n", __func__, __LINE__, offset);
> 
> 	return 0;
> }
> 
> static struct gpio_chip msm_gpio_template = {
> 	.request          = msm_gpio_request,
> 	...
> 
> msm_gpio_request() is never called when the driver loads.  In fact,
> I can't figure out when it would be called.
> 

Right, the gpiolib core would need to be updated to request the
gpio in gpiochip_add_data() around the loop where it goes and
configures things. And it could ignore ones that it can't request
there.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 12:11 PM, Stephen Boyd wrote:
> gpiochips also have a request() hook. Can we use that before
> initializing direction to make sure the GPIO is accessible?

So I tried it, and it didn't work:

static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
	pr_info("%s:%u offset=%u\n", __func__, __LINE__, offset);

	return 0;
}

static struct gpio_chip msm_gpio_template = {
	.request          = msm_gpio_request,
	...

msm_gpio_request() is never called when the driver loads.  In fact, I 
can't figure out when it would be called.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 12:11 PM, Stephen Boyd wrote:
> gpiochips also have a request() hook. Can we use that before
> initializing direction to make sure the GPIO is accessible?

So I tried it, and it didn't work:

static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
	pr_info("%s:%u offset=%u\n", __func__, __LINE__, offset);

	return 0;
}

static struct gpio_chip msm_gpio_template = {
	.request          = msm_gpio_request,
	...

msm_gpio_request() is never called when the driver loads.  In fact, I 
can't figure out when it would be called.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Bjorn Andersson]

On Fri 14 Jul 10:01 PDT 2017, Timur Tabi wrote:

> On 07/14/2017 11:44 AM, Bjorn Andersson wrote:
> > We would have to drop the "const" on the groups arrays of the other
> > platform in order to use this, but I don't have a better suggestion at
> > this time.
> 
> Why?  I don't modify any data in this patch, and I build just fine with
> these options enabled:
> 
> CONFIG_PINCTRL_MSM8916=y
> CONFIG_PINCTRL_MSM8994=y
> CONFIG_PINCTRL_MSM8996=y
> CONFIG_PINCTRL_QDF2XXX=m
> 

What I mean is that if we want to specify that any pin of those drivers
are locked down we would make npins = 0.

But as this is a system configuration thing this information would
preferably be injected in runtime (like you do), but the
soc_data->groups arrays are currently all const (see e.g.
msm8x74_groups), so we can't change npins in runtime.


But I think this is fine for now.

Regards,
Bjorn

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Bjorn Andersson]

On Fri 14 Jul 10:01 PDT 2017, Timur Tabi wrote:

> On 07/14/2017 11:44 AM, Bjorn Andersson wrote:
> > We would have to drop the "const" on the groups arrays of the other
> > platform in order to use this, but I don't have a better suggestion at
> > this time.
> 
> Why?  I don't modify any data in this patch, and I build just fine with
> these options enabled:
> 
> CONFIG_PINCTRL_MSM8916=y
> CONFIG_PINCTRL_MSM8994=y
> CONFIG_PINCTRL_MSM8996=y
> CONFIG_PINCTRL_QDF2XXX=m
> 

What I mean is that if we want to specify that any pin of those drivers
are locked down we would make npins = 0.

But as this is a system configuration thing this information would
preferably be injected in runtime (like you do), but the
soc_data->groups arrays are currently all const (see e.g.
msm8x74_groups), so we can't change npins in runtime.


But I think this is fine for now.

Regards,
Bjorn

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Bjorn Andersson]

On Fri 14 Jul 10:17 PDT 2017, Timur Tabi wrote:

> On 07/14/2017 12:11 PM, Stephen Boyd wrote:
> 
> > > +/*
> > > + * Request a GPIO. If the number of pins for this GPIO group is zero,
> > > + * then assume that the GPIO is unavailable.
> > > + */
> > > +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
> > 
> > These names are awful. Reminds me of the serial driver that has
> > functions like msm_reset(). But when in Rome this is how it goes
> > I suppose.
> 
> I can change it to msm_pinctrl_request().
> 

msm_pinmux_request()

Regards,
Bjorn

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Bjorn Andersson]

On Fri 14 Jul 10:17 PDT 2017, Timur Tabi wrote:

> On 07/14/2017 12:11 PM, Stephen Boyd wrote:
> 
> > > +/*
> > > + * Request a GPIO. If the number of pins for this GPIO group is zero,
> > > + * then assume that the GPIO is unavailable.
> > > + */
> > > +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
> > 
> > These names are awful. Reminds me of the serial driver that has
> > functions like msm_reset(). But when in Rome this is how it goes
> > I suppose.
> 
> I can change it to msm_pinctrl_request().
> 

msm_pinmux_request()

Regards,
Bjorn

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 12:11 PM, Stephen Boyd wrote:

>> +/*
>> + * Request a GPIO. If the number of pins for this GPIO group is zero,
>> + * then assume that the GPIO is unavailable.
>> + */
>> +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
> 
> These names are awful. Reminds me of the serial driver that has
> functions like msm_reset(). But when in Rome this is how it goes
> I suppose.

I can change it to msm_pinctrl_request().

>> @@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
>>   
>>   	g = &pctrl->soc->groups[offset];
>>   
>> +	/*
>> +	 * If the GPIO is unavailable, just return error.  This is necessary
>> +	 * because the GPIO layer tries to initialize the direction of all
>> +	 * the GPIOs, even the ones that are unavailable.
>> +	 */
>> +	if (!g->npins)
>> +		return -ENODEV;
>> +
> 
> gpiochips also have a request() hook. Can we use that before
> initializing direction to make sure the GPIO is accessible?

I'll try that.

>>   static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>> @@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>>   	unsigned gpio = chip->base;
>>   	unsigned i;
>>   
>> -	for (i = 0; i < chip->ngpio; i++, gpio++) {
>> +	for (i = 0; i < chip->ngpio; i++, gpio++)
>>   		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
>> -		seq_puts(s, "\n");
>> -	}
>>   }
> 
> Were these two hunks necessary? Looks like noise.

Yes, because otherwise there will be a whole bunch of blank lines for 
hidden GPIOs.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 12:11 PM, Stephen Boyd wrote:

>> +/*
>> + * Request a GPIO. If the number of pins for this GPIO group is zero,
>> + * then assume that the GPIO is unavailable.
>> + */
>> +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
> 
> These names are awful. Reminds me of the serial driver that has
> functions like msm_reset(). But when in Rome this is how it goes
> I suppose.

I can change it to msm_pinctrl_request().

>> @@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
>>   
>>   	g = &pctrl->soc->groups[offset];
>>   
>> +	/*
>> +	 * If the GPIO is unavailable, just return error.  This is necessary
>> +	 * because the GPIO layer tries to initialize the direction of all
>> +	 * the GPIOs, even the ones that are unavailable.
>> +	 */
>> +	if (!g->npins)
>> +		return -ENODEV;
>> +
> 
> gpiochips also have a request() hook. Can we use that before
> initializing direction to make sure the GPIO is accessible?

I'll try that.

>>   static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>> @@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>>   	unsigned gpio = chip->base;
>>   	unsigned i;
>>   
>> -	for (i = 0; i < chip->ngpio; i++, gpio++) {
>> +	for (i = 0; i < chip->ngpio; i++, gpio++)
>>   		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
>> -		seq_puts(s, "\n");
>> -	}
>>   }
> 
> Were these two hunks necessary? Looks like noise.

Yes, because otherwise there will be a whole bunch of blank lines for 
hidden GPIOs.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Stephen Boyd]

On 07/13, Timur Tabi wrote:
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index 273badd..e915db4 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
>  	return 0;
>  }
>  
> +/*
> + * Request a GPIO. If the number of pins for this GPIO group is zero,
> + * then assume that the GPIO is unavailable.
> + */
> +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)

These names are awful. Reminds me of the serial driver that has
functions like msm_reset(). But when in Rome this is how it goes
I suppose.

> +{
> +	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> +	const struct msm_pingroup *g;
> +
> +	g = &pctrl->soc->groups[offset];
> +
> +	return g->npins ? 0 : -ENODEV;
> +}
> +
>  static const struct pinmux_ops msm_pinmux_ops = {
> +	.request		= msm_request,
>  	.get_functions_count	= msm_get_functions_count,
>  	.get_function_name	= msm_get_function_name,
>  	.get_function_groups	= msm_get_function_groups,
> @@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
>  
>  	g = &pctrl->soc->groups[offset];
>  
> +	/*
> +	 * If the GPIO is unavailable, just return error.  This is necessary
> +	 * because the GPIO layer tries to initialize the direction of all
> +	 * the GPIOs, even the ones that are unavailable.
> +	 */
> +	if (!g->npins)
> +		return -ENODEV;
> +

gpiochips also have a request() hook. Can we use that before
initializing direction to make sure the GPIO is accessible?

>  	val = readl(pctrl->regs + g->ctl_reg);
>  
>  	/* 0 = output, 1 = input */
> @@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
>  
>  	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
>  	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
> -	seq_printf(s, " %s", pulls[pull]);
> +	seq_printf(s, " %s\n", pulls[pull]);
>  }
>  
>  static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
> @@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>  	unsigned gpio = chip->base;
>  	unsigned i;
>  
> -	for (i = 0; i < chip->ngpio; i++, gpio++) {
> +	for (i = 0; i < chip->ngpio; i++, gpio++)
>  		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
> -		seq_puts(s, "\n");
> -	}
>  }

Were these two hunks necessary? Looks like noise.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Stephen Boyd]

On 07/13, Timur Tabi wrote:
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index 273badd..e915db4 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
>  	return 0;
>  }
>  
> +/*
> + * Request a GPIO. If the number of pins for this GPIO group is zero,
> + * then assume that the GPIO is unavailable.
> + */
> +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)

These names are awful. Reminds me of the serial driver that has
functions like msm_reset(). But when in Rome this is how it goes
I suppose.

> +{
> +	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> +	const struct msm_pingroup *g;
> +
> +	g = &pctrl->soc->groups[offset];
> +
> +	return g->npins ? 0 : -ENODEV;
> +}
> +
>  static const struct pinmux_ops msm_pinmux_ops = {
> +	.request		= msm_request,
>  	.get_functions_count	= msm_get_functions_count,
>  	.get_function_name	= msm_get_function_name,
>  	.get_function_groups	= msm_get_function_groups,
> @@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
>  
>  	g = &pctrl->soc->groups[offset];
>  
> +	/*
> +	 * If the GPIO is unavailable, just return error.  This is necessary
> +	 * because the GPIO layer tries to initialize the direction of all
> +	 * the GPIOs, even the ones that are unavailable.
> +	 */
> +	if (!g->npins)
> +		return -ENODEV;
> +

gpiochips also have a request() hook. Can we use that before
initializing direction to make sure the GPIO is accessible?

>  	val = readl(pctrl->regs + g->ctl_reg);
>  
>  	/* 0 = output, 1 = input */
> @@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
>  
>  	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
>  	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
> -	seq_printf(s, " %s", pulls[pull]);
> +	seq_printf(s, " %s\n", pulls[pull]);
>  }
>  
>  static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
> @@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>  	unsigned gpio = chip->base;
>  	unsigned i;
>  
> -	for (i = 0; i < chip->ngpio; i++, gpio++) {
> +	for (i = 0; i < chip->ngpio; i++, gpio++)
>  		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
> -		seq_puts(s, "\n");
> -	}
>  }

Were these two hunks necessary? Looks like noise.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 11:44 AM, Bjorn Andersson wrote:
> We would have to drop the "const" on the groups arrays of the other
> platform in order to use this, but I don't have a better suggestion at
> this time.

Why?  I don't modify any data in this patch, and I build just fine with 
these options enabled:

CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_MSM8994=y
CONFIG_PINCTRL_MSM8996=y
CONFIG_PINCTRL_QDF2XXX=m

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 11:44 AM, Bjorn Andersson wrote:
> We would have to drop the "const" on the groups arrays of the other
> platform in order to use this, but I don't have a better suggestion at
> this time.

Why?  I don't modify any data in this patch, and I build just fine with 
these options enabled:

CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_MSM8994=y
CONFIG_PINCTRL_MSM8996=y
CONFIG_PINCTRL_QDF2XXX=m

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Bjorn Andersson]

On Thu 13 Jul 14:52 PDT 2017, Timur Tabi wrote:

> To support sparse GPIO maps, pinctrl-msm client drivers can specify
> that a given GPIO has a pin count of zero.  These GPIOs will be
> considered "hidden".  Any attempt to claim the GPIO will fail, and they
> will not be listed in debugfs.
> 
> However, when the driver probes, it calls gpiochip_add_data() which
> wants to initialize the direction of all the GPIOs, even the ones that
> are unavailable.  Therefore, msm_gpio_get_direction() checks to make
> sure the pin is available.
> 
> Signed-off-by: Timur Tabi <timur@codeaurora.org>

We would have to drop the "const" on the groups arrays of the other
platform in order to use this, but I don't have a better suggestion at
this time.

Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> ---
>  drivers/pinctrl/qcom/pinctrl-msm.c | 34 ++++++++++++++++++++++++++++++----
>  1 file changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index 273badd..e915db4 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
>  	return 0;
>  }
>  
> +/*
> + * Request a GPIO. If the number of pins for this GPIO group is zero,
> + * then assume that the GPIO is unavailable.
> + */
> +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
> +{
> +	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> +	const struct msm_pingroup *g;
> +
> +	g = &pctrl->soc->groups[offset];
> +
> +	return g->npins ? 0 : -ENODEV;
> +}
> +
>  static const struct pinmux_ops msm_pinmux_ops = {
> +	.request		= msm_request,
>  	.get_functions_count	= msm_get_functions_count,
>  	.get_function_name	= msm_get_function_name,
>  	.get_function_groups	= msm_get_function_groups,
> @@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
>  
>  	g = &pctrl->soc->groups[offset];
>  
> +	/*
> +	 * If the GPIO is unavailable, just return error.  This is necessary
> +	 * because the GPIO layer tries to initialize the direction of all
> +	 * the GPIOs, even the ones that are unavailable.
> +	 */
> +	if (!g->npins)
> +		return -ENODEV;
> +
>  	val = readl(pctrl->regs + g->ctl_reg);
>  
>  	/* 0 = output, 1 = input */
> @@ -494,6 +517,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
>  	};
>  
>  	g = &pctrl->soc->groups[offset];
> +
> +	/* If the GPIO group has no pins, then don't show it. */
> +	if (!g->npins)
> +		return;
> +
>  	ctl_reg = readl(pctrl->regs + g->ctl_reg);
>  
>  	is_out = !!(ctl_reg & BIT(g->oe_bit));
> @@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
>  
>  	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
>  	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
> -	seq_printf(s, " %s", pulls[pull]);
> +	seq_printf(s, " %s\n", pulls[pull]);
>  }
>  
>  static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
> @@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>  	unsigned gpio = chip->base;
>  	unsigned i;
>  
> -	for (i = 0; i < chip->ngpio; i++, gpio++) {
> +	for (i = 0; i < chip->ngpio; i++, gpio++)
>  		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
> -		seq_puts(s, "\n");
> -	}
>  }
>  
>  #else
> -- 
> Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
> Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
> Code Aurora Forum, a Linux Foundation Collaborative Project.
> 

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Bjorn Andersson]

On Thu 13 Jul 14:52 PDT 2017, Timur Tabi wrote:

> To support sparse GPIO maps, pinctrl-msm client drivers can specify
> that a given GPIO has a pin count of zero.  These GPIOs will be
> considered "hidden".  Any attempt to claim the GPIO will fail, and they
> will not be listed in debugfs.
> 
> However, when the driver probes, it calls gpiochip_add_data() which
> wants to initialize the direction of all the GPIOs, even the ones that
> are unavailable.  Therefore, msm_gpio_get_direction() checks to make
> sure the pin is available.
> 
> Signed-off-by: Timur Tabi <timur@codeaurora.org>

We would have to drop the "const" on the groups arrays of the other
platform in order to use this, but I don't have a better suggestion at
this time.

Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> ---
>  drivers/pinctrl/qcom/pinctrl-msm.c | 34 ++++++++++++++++++++++++++++++----
>  1 file changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index 273badd..e915db4 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
>  	return 0;
>  }
>  
> +/*
> + * Request a GPIO. If the number of pins for this GPIO group is zero,
> + * then assume that the GPIO is unavailable.
> + */
> +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
> +{
> +	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> +	const struct msm_pingroup *g;
> +
> +	g = &pctrl->soc->groups[offset];
> +
> +	return g->npins ? 0 : -ENODEV;
> +}
> +
>  static const struct pinmux_ops msm_pinmux_ops = {
> +	.request		= msm_request,
>  	.get_functions_count	= msm_get_functions_count,
>  	.get_function_name	= msm_get_function_name,
>  	.get_function_groups	= msm_get_function_groups,
> @@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
>  
>  	g = &pctrl->soc->groups[offset];
>  
> +	/*
> +	 * If the GPIO is unavailable, just return error.  This is necessary
> +	 * because the GPIO layer tries to initialize the direction of all
> +	 * the GPIOs, even the ones that are unavailable.
> +	 */
> +	if (!g->npins)
> +		return -ENODEV;
> +
>  	val = readl(pctrl->regs + g->ctl_reg);
>  
>  	/* 0 = output, 1 = input */
> @@ -494,6 +517,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
>  	};
>  
>  	g = &pctrl->soc->groups[offset];
> +
> +	/* If the GPIO group has no pins, then don't show it. */
> +	if (!g->npins)
> +		return;
> +
>  	ctl_reg = readl(pctrl->regs + g->ctl_reg);
>  
>  	is_out = !!(ctl_reg & BIT(g->oe_bit));
> @@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
>  
>  	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
>  	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
> -	seq_printf(s, " %s", pulls[pull]);
> +	seq_printf(s, " %s\n", pulls[pull]);
>  }
>  
>  static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
> @@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>  	unsigned gpio = chip->base;
>  	unsigned i;
>  
> -	for (i = 0; i < chip->ngpio; i++, gpio++) {
> +	for (i = 0; i < chip->ngpio; i++, gpio++)
>  		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
> -		seq_puts(s, "\n");
> -	}
>  }
>  
>  #else
> -- 
> Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
> Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
> Code Aurora Forum, a Linux Foundation Collaborative Project.
> 

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

To support sparse GPIO maps, pinctrl-msm client drivers can specify
that a given GPIO has a pin count of zero.  These GPIOs will be
considered "hidden".  Any attempt to claim the GPIO will fail, and they
will not be listed in debugfs.

However, when the driver probes, it calls gpiochip_add_data() which
wants to initialize the direction of all the GPIOs, even the ones that
are unavailable.  Therefore, msm_gpio_get_direction() checks to make
sure the pin is available.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 34 ++++++++++++++++++++++++++++++----
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 273badd..e915db4 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 	return 0;
 }
 
+/*
+ * Request a GPIO. If the number of pins for this GPIO group is zero,
+ * then assume that the GPIO is unavailable.
+ */
+static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
+{
+	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	const struct msm_pingroup *g;
+
+	g = &pctrl->soc->groups[offset];
+
+	return g->npins ? 0 : -ENODEV;
+}
+
 static const struct pinmux_ops msm_pinmux_ops = {
+	.request		= msm_request,
 	.get_functions_count	= msm_get_functions_count,
 	.get_function_name	= msm_get_function_name,
 	.get_function_groups	= msm_get_function_groups,
@@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 
 	g = &pctrl->soc->groups[offset];
 
+	/*
+	 * If the GPIO is unavailable, just return error.  This is necessary
+	 * because the GPIO layer tries to initialize the direction of all
+	 * the GPIOs, even the ones that are unavailable.
+	 */
+	if (!g->npins)
+		return -ENODEV;
+
 	val = readl(pctrl->regs + g->ctl_reg);
 
 	/* 0 = output, 1 = input */
@@ -494,6 +517,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 	};
 
 	g = &pctrl->soc->groups[offset];
+
+	/* If the GPIO group has no pins, then don't show it. */
+	if (!g->npins)
+		return;
+
 	ctl_reg = readl(pctrl->regs + g->ctl_reg);
 
 	is_out = !!(ctl_reg & BIT(g->oe_bit));
@@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 
 	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
-	seq_printf(s, " %s", pulls[pull]);
+	seq_printf(s, " %s\n", pulls[pull]);
 }
 
 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
@@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 	unsigned gpio = chip->base;
 	unsigned i;
 
-	for (i = 0; i < chip->ngpio; i++, gpio++) {
+	for (i = 0; i < chip->ngpio; i++, gpio++)
 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
-		seq_puts(s, "\n");
-	}
 }
 
 #else
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

To support sparse GPIO maps, pinctrl-msm client drivers can specify
that a given GPIO has a pin count of zero.  These GPIOs will be
considered "hidden".  Any attempt to claim the GPIO will fail, and they
will not be listed in debugfs.

However, when the driver probes, it calls gpiochip_add_data() which
wants to initialize the direction of all the GPIOs, even the ones that
are unavailable.  Therefore, msm_gpio_get_direction() checks to make
sure the pin is available.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 34 ++++++++++++++++++++++++++++++----
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 273badd..e915db4 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 	return 0;
 }
 
+/*
+ * Request a GPIO. If the number of pins for this GPIO group is zero,
+ * then assume that the GPIO is unavailable.
+ */
+static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
+{
+	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	const struct msm_pingroup *g;
+
+	g = &pctrl->soc->groups[offset];
+
+	return g->npins ? 0 : -ENODEV;
+}
+
 static const struct pinmux_ops msm_pinmux_ops = {
+	.request		= msm_request,
 	.get_functions_count	= msm_get_functions_count,
 	.get_function_name	= msm_get_function_name,
 	.get_function_groups	= msm_get_function_groups,
@@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 
 	g = &pctrl->soc->groups[offset];
 
+	/*
+	 * If the GPIO is unavailable, just return error.  This is necessary
+	 * because the GPIO layer tries to initialize the direction of all
+	 * the GPIOs, even the ones that are unavailable.
+	 */
+	if (!g->npins)
+		return -ENODEV;
+
 	val = readl(pctrl->regs + g->ctl_reg);
 
 	/* 0 = output, 1 = input */
@@ -494,6 +517,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 	};
 
 	g = &pctrl->soc->groups[offset];
+
+	/* If the GPIO group has no pins, then don't show it. */
+	if (!g->npins)
+		return;
+
 	ctl_reg = readl(pctrl->regs + g->ctl_reg);
 
 	is_out = !!(ctl_reg & BIT(g->oe_bit));
@@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 
 	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
-	seq_printf(s, " %s", pulls[pull]);
+	seq_printf(s, " %s\n", pulls[pull]);
 }
 
 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
@@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 	unsigned gpio = chip->base;
 	unsigned i;
 
-	for (i = 0; i < chip->ngpio; i++, gpio++) {
+	for (i = 0; i < chip->ngpio; i++, gpio++)
 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
-		seq_puts(s, "\n");
-	}
 }
 
 #else
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.