[PATCH 0/2] pinctrl: qcom: add support for sparse GPIOs

[PATCH 0/2] pinctrl: qcom: add support for sparse GPIOs

[Timur Tabi]

First patch allows for for pinctrl-msm to understand GPIO groups with
no pins.  Such pins are "hidden" and can't be exported or accessed.

Second patch update the QDF2xxx driver to take advantage of that.

Timur Tabi (2):
  pinctrl: qcom: disable GPIO groups with no pins
  pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

 drivers/pinctrl/qcom/pinctrl-msm.c     |  36 ++++++--
 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 157 +++++++++++++++++++++++----------
 2 files changed, 142 insertions(+), 51 deletions(-)

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 0/2] pinctrl: qcom: add support for sparse GPIOs

[Timur Tabi]

First patch allows for for pinctrl-msm to understand GPIO groups with
no pins.  Such pins are "hidden" and can't be exported or accessed.

Second patch update the QDF2xxx driver to take advantage of that.

Timur Tabi (2):
  pinctrl: qcom: disable GPIO groups with no pins
  pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

 drivers/pinctrl/qcom/pinctrl-msm.c     |  36 ++++++--
 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 157 +++++++++++++++++++++++----------
 2 files changed, 142 insertions(+), 51 deletions(-)

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

To support sparse GPIO maps, pinctrl-msm client drivers can specify
that a given GPIO has a pin count of zero.  These GPIOs will be
considered "hidden".  Any attempt to claim the GPIO will fail, and they
will not be listed in debugfs.

However, when the driver probes, it calls gpiochip_add_data() which
wants to initialize the direction of all the GPIOs, even the ones that
are unavailable.  Therefore, msm_gpio_get_direction() checks to make
sure the pin is available.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 34 ++++++++++++++++++++++++++++++----
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 273badd..e915db4 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 	return 0;
 }
 
+/*
+ * Request a GPIO. If the number of pins for this GPIO group is zero,
+ * then assume that the GPIO is unavailable.
+ */
+static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
+{
+	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	const struct msm_pingroup *g;
+
+	g = &pctrl->soc->groups[offset];
+
+	return g->npins ? 0 : -ENODEV;
+}
+
 static const struct pinmux_ops msm_pinmux_ops = {
+	.request		= msm_request,
 	.get_functions_count	= msm_get_functions_count,
 	.get_function_name	= msm_get_function_name,
 	.get_function_groups	= msm_get_function_groups,
@@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 
 	g = &pctrl->soc->groups[offset];
 
+	/*
+	 * If the GPIO is unavailable, just return error.  This is necessary
+	 * because the GPIO layer tries to initialize the direction of all
+	 * the GPIOs, even the ones that are unavailable.
+	 */
+	if (!g->npins)
+		return -ENODEV;
+
 	val = readl(pctrl->regs + g->ctl_reg);
 
 	/* 0 = output, 1 = input */
@@ -494,6 +517,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 	};
 
 	g = &pctrl->soc->groups[offset];
+
+	/* If the GPIO group has no pins, then don't show it. */
+	if (!g->npins)
+		return;
+
 	ctl_reg = readl(pctrl->regs + g->ctl_reg);
 
 	is_out = !!(ctl_reg & BIT(g->oe_bit));
@@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 
 	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
-	seq_printf(s, " %s", pulls[pull]);
+	seq_printf(s, " %s\n", pulls[pull]);
 }
 
 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
@@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 	unsigned gpio = chip->base;
 	unsigned i;
 
-	for (i = 0; i < chip->ngpio; i++, gpio++) {
+	for (i = 0; i < chip->ngpio; i++, gpio++)
 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
-		seq_puts(s, "\n");
-	}
 }
 
 #else
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

To support sparse GPIO maps, pinctrl-msm client drivers can specify
that a given GPIO has a pin count of zero.  These GPIOs will be
considered "hidden".  Any attempt to claim the GPIO will fail, and they
will not be listed in debugfs.

However, when the driver probes, it calls gpiochip_add_data() which
wants to initialize the direction of all the GPIOs, even the ones that
are unavailable.  Therefore, msm_gpio_get_direction() checks to make
sure the pin is available.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 34 ++++++++++++++++++++++++++++++----
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 273badd..e915db4 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 	return 0;
 }
 
+/*
+ * Request a GPIO. If the number of pins for this GPIO group is zero,
+ * then assume that the GPIO is unavailable.
+ */
+static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
+{
+	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	const struct msm_pingroup *g;
+
+	g = &pctrl->soc->groups[offset];
+
+	return g->npins ? 0 : -ENODEV;
+}
+
 static const struct pinmux_ops msm_pinmux_ops = {
+	.request		= msm_request,
 	.get_functions_count	= msm_get_functions_count,
 	.get_function_name	= msm_get_function_name,
 	.get_function_groups	= msm_get_function_groups,
@@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 
 	g = &pctrl->soc->groups[offset];
 
+	/*
+	 * If the GPIO is unavailable, just return error.  This is necessary
+	 * because the GPIO layer tries to initialize the direction of all
+	 * the GPIOs, even the ones that are unavailable.
+	 */
+	if (!g->npins)
+		return -ENODEV;
+
 	val = readl(pctrl->regs + g->ctl_reg);
 
 	/* 0 = output, 1 = input */
@@ -494,6 +517,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 	};
 
 	g = &pctrl->soc->groups[offset];
+
+	/* If the GPIO group has no pins, then don't show it. */
+	if (!g->npins)
+		return;
+
 	ctl_reg = readl(pctrl->regs + g->ctl_reg);
 
 	is_out = !!(ctl_reg & BIT(g->oe_bit));
@@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 
 	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
-	seq_printf(s, " %s", pulls[pull]);
+	seq_printf(s, " %s\n", pulls[pull]);
 }
 
 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
@@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 	unsigned gpio = chip->base;
 	unsigned i;
 
-	for (i = 0; i < chip->ngpio; i++, gpio++) {
+	for (i = 0; i < chip->ngpio; i++, gpio++)
 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
-		seq_puts(s, "\n");
-	}
 }
 
 #else
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Bjorn Andersson]

On Thu 13 Jul 14:52 PDT 2017, Timur Tabi wrote:

> To support sparse GPIO maps, pinctrl-msm client drivers can specify
> that a given GPIO has a pin count of zero.  These GPIOs will be
> considered "hidden".  Any attempt to claim the GPIO will fail, and they
> will not be listed in debugfs.
> 
> However, when the driver probes, it calls gpiochip_add_data() which
> wants to initialize the direction of all the GPIOs, even the ones that
> are unavailable.  Therefore, msm_gpio_get_direction() checks to make
> sure the pin is available.
> 
> Signed-off-by: Timur Tabi <timur@codeaurora.org>

We would have to drop the "const" on the groups arrays of the other
platform in order to use this, but I don't have a better suggestion at
this time.

Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> ---
>  drivers/pinctrl/qcom/pinctrl-msm.c | 34 ++++++++++++++++++++++++++++++----
>  1 file changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index 273badd..e915db4 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
>  	return 0;
>  }
>  
> +/*
> + * Request a GPIO. If the number of pins for this GPIO group is zero,
> + * then assume that the GPIO is unavailable.
> + */
> +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
> +{
> +	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> +	const struct msm_pingroup *g;
> +
> +	g = &pctrl->soc->groups[offset];
> +
> +	return g->npins ? 0 : -ENODEV;
> +}
> +
>  static const struct pinmux_ops msm_pinmux_ops = {
> +	.request		= msm_request,
>  	.get_functions_count	= msm_get_functions_count,
>  	.get_function_name	= msm_get_function_name,
>  	.get_function_groups	= msm_get_function_groups,
> @@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
>  
>  	g = &pctrl->soc->groups[offset];
>  
> +	/*
> +	 * If the GPIO is unavailable, just return error.  This is necessary
> +	 * because the GPIO layer tries to initialize the direction of all
> +	 * the GPIOs, even the ones that are unavailable.
> +	 */
> +	if (!g->npins)
> +		return -ENODEV;
> +
>  	val = readl(pctrl->regs + g->ctl_reg);
>  
>  	/* 0 = output, 1 = input */
> @@ -494,6 +517,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
>  	};
>  
>  	g = &pctrl->soc->groups[offset];
> +
> +	/* If the GPIO group has no pins, then don't show it. */
> +	if (!g->npins)
> +		return;
> +
>  	ctl_reg = readl(pctrl->regs + g->ctl_reg);
>  
>  	is_out = !!(ctl_reg & BIT(g->oe_bit));
> @@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
>  
>  	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
>  	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
> -	seq_printf(s, " %s", pulls[pull]);
> +	seq_printf(s, " %s\n", pulls[pull]);
>  }
>  
>  static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
> @@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>  	unsigned gpio = chip->base;
>  	unsigned i;
>  
> -	for (i = 0; i < chip->ngpio; i++, gpio++) {
> +	for (i = 0; i < chip->ngpio; i++, gpio++)
>  		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
> -		seq_puts(s, "\n");
> -	}
>  }
>  
>  #else
> -- 
> Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
> Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
> Code Aurora Forum, a Linux Foundation Collaborative Project.
> 

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Bjorn Andersson]

On Thu 13 Jul 14:52 PDT 2017, Timur Tabi wrote:

> To support sparse GPIO maps, pinctrl-msm client drivers can specify
> that a given GPIO has a pin count of zero.  These GPIOs will be
> considered "hidden".  Any attempt to claim the GPIO will fail, and they
> will not be listed in debugfs.
> 
> However, when the driver probes, it calls gpiochip_add_data() which
> wants to initialize the direction of all the GPIOs, even the ones that
> are unavailable.  Therefore, msm_gpio_get_direction() checks to make
> sure the pin is available.
> 
> Signed-off-by: Timur Tabi <timur@codeaurora.org>

We would have to drop the "const" on the groups arrays of the other
platform in order to use this, but I don't have a better suggestion at
this time.

Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> ---
>  drivers/pinctrl/qcom/pinctrl-msm.c | 34 ++++++++++++++++++++++++++++++----
>  1 file changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index 273badd..e915db4 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
>  	return 0;
>  }
>  
> +/*
> + * Request a GPIO. If the number of pins for this GPIO group is zero,
> + * then assume that the GPIO is unavailable.
> + */
> +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
> +{
> +	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> +	const struct msm_pingroup *g;
> +
> +	g = &pctrl->soc->groups[offset];
> +
> +	return g->npins ? 0 : -ENODEV;
> +}
> +
>  static const struct pinmux_ops msm_pinmux_ops = {
> +	.request		= msm_request,
>  	.get_functions_count	= msm_get_functions_count,
>  	.get_function_name	= msm_get_function_name,
>  	.get_function_groups	= msm_get_function_groups,
> @@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
>  
>  	g = &pctrl->soc->groups[offset];
>  
> +	/*
> +	 * If the GPIO is unavailable, just return error.  This is necessary
> +	 * because the GPIO layer tries to initialize the direction of all
> +	 * the GPIOs, even the ones that are unavailable.
> +	 */
> +	if (!g->npins)
> +		return -ENODEV;
> +
>  	val = readl(pctrl->regs + g->ctl_reg);
>  
>  	/* 0 = output, 1 = input */
> @@ -494,6 +517,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
>  	};
>  
>  	g = &pctrl->soc->groups[offset];
> +
> +	/* If the GPIO group has no pins, then don't show it. */
> +	if (!g->npins)
> +		return;
> +
>  	ctl_reg = readl(pctrl->regs + g->ctl_reg);
>  
>  	is_out = !!(ctl_reg & BIT(g->oe_bit));
> @@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
>  
>  	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
>  	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
> -	seq_printf(s, " %s", pulls[pull]);
> +	seq_printf(s, " %s\n", pulls[pull]);
>  }
>  
>  static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
> @@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>  	unsigned gpio = chip->base;
>  	unsigned i;
>  
> -	for (i = 0; i < chip->ngpio; i++, gpio++) {
> +	for (i = 0; i < chip->ngpio; i++, gpio++)
>  		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
> -		seq_puts(s, "\n");
> -	}
>  }
>  
>  #else
> -- 
> Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
> Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
> Code Aurora Forum, a Linux Foundation Collaborative Project.
> 

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 11:44 AM, Bjorn Andersson wrote:
> We would have to drop the "const" on the groups arrays of the other
> platform in order to use this, but I don't have a better suggestion at
> this time.

Why?  I don't modify any data in this patch, and I build just fine with 
these options enabled:

CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_MSM8994=y
CONFIG_PINCTRL_MSM8996=y
CONFIG_PINCTRL_QDF2XXX=m

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 11:44 AM, Bjorn Andersson wrote:
> We would have to drop the "const" on the groups arrays of the other
> platform in order to use this, but I don't have a better suggestion at
> this time.

Why?  I don't modify any data in this patch, and I build just fine with 
these options enabled:

CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_MSM8994=y
CONFIG_PINCTRL_MSM8996=y
CONFIG_PINCTRL_QDF2XXX=m

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Bjorn Andersson]

On Fri 14 Jul 10:01 PDT 2017, Timur Tabi wrote:

> On 07/14/2017 11:44 AM, Bjorn Andersson wrote:
> > We would have to drop the "const" on the groups arrays of the other
> > platform in order to use this, but I don't have a better suggestion at
> > this time.
> 
> Why?  I don't modify any data in this patch, and I build just fine with
> these options enabled:
> 
> CONFIG_PINCTRL_MSM8916=y
> CONFIG_PINCTRL_MSM8994=y
> CONFIG_PINCTRL_MSM8996=y
> CONFIG_PINCTRL_QDF2XXX=m
> 

What I mean is that if we want to specify that any pin of those drivers
are locked down we would make npins = 0.

But as this is a system configuration thing this information would
preferably be injected in runtime (like you do), but the
soc_data->groups arrays are currently all const (see e.g.
msm8x74_groups), so we can't change npins in runtime.


But I think this is fine for now.

Regards,
Bjorn

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Bjorn Andersson]

On Fri 14 Jul 10:01 PDT 2017, Timur Tabi wrote:

> On 07/14/2017 11:44 AM, Bjorn Andersson wrote:
> > We would have to drop the "const" on the groups arrays of the other
> > platform in order to use this, but I don't have a better suggestion at
> > this time.
> 
> Why?  I don't modify any data in this patch, and I build just fine with
> these options enabled:
> 
> CONFIG_PINCTRL_MSM8916=y
> CONFIG_PINCTRL_MSM8994=y
> CONFIG_PINCTRL_MSM8996=y
> CONFIG_PINCTRL_QDF2XXX=m
> 

What I mean is that if we want to specify that any pin of those drivers
are locked down we would make npins = 0.

But as this is a system configuration thing this information would
preferably be injected in runtime (like you do), but the
soc_data->groups arrays are currently all const (see e.g.
msm8x74_groups), so we can't change npins in runtime.


But I think this is fine for now.

Regards,
Bjorn

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Stephen Boyd]

On 07/13, Timur Tabi wrote:
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index 273badd..e915db4 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
>  	return 0;
>  }
>  
> +/*
> + * Request a GPIO. If the number of pins for this GPIO group is zero,
> + * then assume that the GPIO is unavailable.
> + */
> +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)

These names are awful. Reminds me of the serial driver that has
functions like msm_reset(). But when in Rome this is how it goes
I suppose.

> +{
> +	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> +	const struct msm_pingroup *g;
> +
> +	g = &pctrl->soc->groups[offset];
> +
> +	return g->npins ? 0 : -ENODEV;
> +}
> +
>  static const struct pinmux_ops msm_pinmux_ops = {
> +	.request		= msm_request,
>  	.get_functions_count	= msm_get_functions_count,
>  	.get_function_name	= msm_get_function_name,
>  	.get_function_groups	= msm_get_function_groups,
> @@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
>  
>  	g = &pctrl->soc->groups[offset];
>  
> +	/*
> +	 * If the GPIO is unavailable, just return error.  This is necessary
> +	 * because the GPIO layer tries to initialize the direction of all
> +	 * the GPIOs, even the ones that are unavailable.
> +	 */
> +	if (!g->npins)
> +		return -ENODEV;
> +

gpiochips also have a request() hook. Can we use that before
initializing direction to make sure the GPIO is accessible?

>  	val = readl(pctrl->regs + g->ctl_reg);
>  
>  	/* 0 = output, 1 = input */
> @@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
>  
>  	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
>  	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
> -	seq_printf(s, " %s", pulls[pull]);
> +	seq_printf(s, " %s\n", pulls[pull]);
>  }
>  
>  static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
> @@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>  	unsigned gpio = chip->base;
>  	unsigned i;
>  
> -	for (i = 0; i < chip->ngpio; i++, gpio++) {
> +	for (i = 0; i < chip->ngpio; i++, gpio++)
>  		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
> -		seq_puts(s, "\n");
> -	}
>  }

Were these two hunks necessary? Looks like noise.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Stephen Boyd]

On 07/13, Timur Tabi wrote:
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index 273badd..e915db4 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
>  	return 0;
>  }
>  
> +/*
> + * Request a GPIO. If the number of pins for this GPIO group is zero,
> + * then assume that the GPIO is unavailable.
> + */
> +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)

These names are awful. Reminds me of the serial driver that has
functions like msm_reset(). But when in Rome this is how it goes
I suppose.

> +{
> +	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> +	const struct msm_pingroup *g;
> +
> +	g = &pctrl->soc->groups[offset];
> +
> +	return g->npins ? 0 : -ENODEV;
> +}
> +
>  static const struct pinmux_ops msm_pinmux_ops = {
> +	.request		= msm_request,
>  	.get_functions_count	= msm_get_functions_count,
>  	.get_function_name	= msm_get_function_name,
>  	.get_function_groups	= msm_get_function_groups,
> @@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
>  
>  	g = &pctrl->soc->groups[offset];
>  
> +	/*
> +	 * If the GPIO is unavailable, just return error.  This is necessary
> +	 * because the GPIO layer tries to initialize the direction of all
> +	 * the GPIOs, even the ones that are unavailable.
> +	 */
> +	if (!g->npins)
> +		return -ENODEV;
> +

gpiochips also have a request() hook. Can we use that before
initializing direction to make sure the GPIO is accessible?

>  	val = readl(pctrl->regs + g->ctl_reg);
>  
>  	/* 0 = output, 1 = input */
> @@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
>  
>  	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
>  	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
> -	seq_printf(s, " %s", pulls[pull]);
> +	seq_printf(s, " %s\n", pulls[pull]);
>  }
>  
>  static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
> @@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>  	unsigned gpio = chip->base;
>  	unsigned i;
>  
> -	for (i = 0; i < chip->ngpio; i++, gpio++) {
> +	for (i = 0; i < chip->ngpio; i++, gpio++)
>  		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
> -		seq_puts(s, "\n");
> -	}
>  }

Were these two hunks necessary? Looks like noise.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 12:11 PM, Stephen Boyd wrote:

>> +/*
>> + * Request a GPIO. If the number of pins for this GPIO group is zero,
>> + * then assume that the GPIO is unavailable.
>> + */
>> +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
> 
> These names are awful. Reminds me of the serial driver that has
> functions like msm_reset(). But when in Rome this is how it goes
> I suppose.

I can change it to msm_pinctrl_request().

>> @@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
>>   
>>   	g = &pctrl->soc->groups[offset];
>>   
>> +	/*
>> +	 * If the GPIO is unavailable, just return error.  This is necessary
>> +	 * because the GPIO layer tries to initialize the direction of all
>> +	 * the GPIOs, even the ones that are unavailable.
>> +	 */
>> +	if (!g->npins)
>> +		return -ENODEV;
>> +
> 
> gpiochips also have a request() hook. Can we use that before
> initializing direction to make sure the GPIO is accessible?

I'll try that.

>>   static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>> @@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>>   	unsigned gpio = chip->base;
>>   	unsigned i;
>>   
>> -	for (i = 0; i < chip->ngpio; i++, gpio++) {
>> +	for (i = 0; i < chip->ngpio; i++, gpio++)
>>   		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
>> -		seq_puts(s, "\n");
>> -	}
>>   }
> 
> Were these two hunks necessary? Looks like noise.

Yes, because otherwise there will be a whole bunch of blank lines for 
hidden GPIOs.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 12:11 PM, Stephen Boyd wrote:

>> +/*
>> + * Request a GPIO. If the number of pins for this GPIO group is zero,
>> + * then assume that the GPIO is unavailable.
>> + */
>> +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
> 
> These names are awful. Reminds me of the serial driver that has
> functions like msm_reset(). But when in Rome this is how it goes
> I suppose.

I can change it to msm_pinctrl_request().

>> @@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
>>   
>>   	g = &pctrl->soc->groups[offset];
>>   
>> +	/*
>> +	 * If the GPIO is unavailable, just return error.  This is necessary
>> +	 * because the GPIO layer tries to initialize the direction of all
>> +	 * the GPIOs, even the ones that are unavailable.
>> +	 */
>> +	if (!g->npins)
>> +		return -ENODEV;
>> +
> 
> gpiochips also have a request() hook. Can we use that before
> initializing direction to make sure the GPIO is accessible?

I'll try that.

>>   static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>> @@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
>>   	unsigned gpio = chip->base;
>>   	unsigned i;
>>   
>> -	for (i = 0; i < chip->ngpio; i++, gpio++) {
>> +	for (i = 0; i < chip->ngpio; i++, gpio++)
>>   		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
>> -		seq_puts(s, "\n");
>> -	}
>>   }
> 
> Were these two hunks necessary? Looks like noise.

Yes, because otherwise there will be a whole bunch of blank lines for 
hidden GPIOs.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Bjorn Andersson]

On Fri 14 Jul 10:17 PDT 2017, Timur Tabi wrote:

> On 07/14/2017 12:11 PM, Stephen Boyd wrote:
> 
> > > +/*
> > > + * Request a GPIO. If the number of pins for this GPIO group is zero,
> > > + * then assume that the GPIO is unavailable.
> > > + */
> > > +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
> > 
> > These names are awful. Reminds me of the serial driver that has
> > functions like msm_reset(). But when in Rome this is how it goes
> > I suppose.
> 
> I can change it to msm_pinctrl_request().
> 

msm_pinmux_request()

Regards,
Bjorn

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Bjorn Andersson]

On Fri 14 Jul 10:17 PDT 2017, Timur Tabi wrote:

> On 07/14/2017 12:11 PM, Stephen Boyd wrote:
> 
> > > +/*
> > > + * Request a GPIO. If the number of pins for this GPIO group is zero,
> > > + * then assume that the GPIO is unavailable.
> > > + */
> > > +static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
> > 
> > These names are awful. Reminds me of the serial driver that has
> > functions like msm_reset(). But when in Rome this is how it goes
> > I suppose.
> 
> I can change it to msm_pinctrl_request().
> 

msm_pinmux_request()

Regards,
Bjorn

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 12:11 PM, Stephen Boyd wrote:
> gpiochips also have a request() hook. Can we use that before
> initializing direction to make sure the GPIO is accessible?

So I tried it, and it didn't work:

static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
	pr_info("%s:%u offset=%u\n", __func__, __LINE__, offset);

	return 0;
}

static struct gpio_chip msm_gpio_template = {
	.request          = msm_gpio_request,
	...

msm_gpio_request() is never called when the driver loads.  In fact, I 
can't figure out when it would be called.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 12:11 PM, Stephen Boyd wrote:
> gpiochips also have a request() hook. Can we use that before
> initializing direction to make sure the GPIO is accessible?

So I tried it, and it didn't work:

static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
	pr_info("%s:%u offset=%u\n", __func__, __LINE__, offset);

	return 0;
}

static struct gpio_chip msm_gpio_template = {
	.request          = msm_gpio_request,
	...

msm_gpio_request() is never called when the driver loads.  In fact, I 
can't figure out when it would be called.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Stephen Boyd]

On 07/14, Timur Tabi wrote:
> On 07/14/2017 12:11 PM, Stephen Boyd wrote:
> >gpiochips also have a request() hook. Can we use that before
> >initializing direction to make sure the GPIO is accessible?
> 
> So I tried it, and it didn't work:
> 
> static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)
> {
> 	pr_info("%s:%u offset=%u\n", __func__, __LINE__, offset);
> 
> 	return 0;
> }
> 
> static struct gpio_chip msm_gpio_template = {
> 	.request          = msm_gpio_request,
> 	...
> 
> msm_gpio_request() is never called when the driver loads.  In fact,
> I can't figure out when it would be called.
> 

Right, the gpiolib core would need to be updated to request the
gpio in gpiochip_add_data() around the loop where it goes and
configures things. And it could ignore ones that it can't request
there.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Stephen Boyd]

On 07/14, Timur Tabi wrote:
> On 07/14/2017 12:11 PM, Stephen Boyd wrote:
> >gpiochips also have a request() hook. Can we use that before
> >initializing direction to make sure the GPIO is accessible?
> 
> So I tried it, and it didn't work:
> 
> static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)
> {
> 	pr_info("%s:%u offset=%u\n", __func__, __LINE__, offset);
> 
> 	return 0;
> }
> 
> static struct gpio_chip msm_gpio_template = {
> 	.request          = msm_gpio_request,
> 	...
> 
> msm_gpio_request() is never called when the driver loads.  In fact,
> I can't figure out when it would be called.
> 

Right, the gpiolib core would need to be updated to request the
gpio in gpiochip_add_data() around the loop where it goes and
configures things. And it could ignore ones that it can't request
there.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 04:46 PM, Stephen Boyd wrote:
> Right, the gpiolib core would need to be updated to request the
> gpio in gpiochip_add_data() around the loop where it goes and
> configures things. And it could ignore ones that it can't request
> there.

__gpiod_request already calls chip->request(), so this would need to be 
a temporary request.  It seems a bit hackish, but I'll try it.

BTW, I noticed that __gpiod_free() does this:

	if (chip->free) {
		spin_unlock_irqrestore(&gpio_lock, flags);
--->		might_sleep_if(chip->can_sleep);
		chip->free(chip, gpio_chip_hwgpio(desc));
		spin_lock_irqsave(&gpio_lock, flags);


Should __gpiod_request() also call might_sleep_if()?

	if (chip->request) {
		/* chip->request may sleep */
		spin_unlock_irqrestore(&gpio_lock, flags);
---> missing call to might_sleep_if() here?
		status = chip->request(chip, gpio_chip_hwgpio(desc));
		spin_lock_irqsave(&gpio_lock, flags);


-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/14/2017 04:46 PM, Stephen Boyd wrote:
> Right, the gpiolib core would need to be updated to request the
> gpio in gpiochip_add_data() around the loop where it goes and
> configures things. And it could ignore ones that it can't request
> there.

__gpiod_request already calls chip->request(), so this would need to be 
a temporary request.  It seems a bit hackish, but I'll try it.

BTW, I noticed that __gpiod_free() does this:

	if (chip->free) {
		spin_unlock_irqrestore(&gpio_lock, flags);
--->		might_sleep_if(chip->can_sleep);
		chip->free(chip, gpio_chip_hwgpio(desc));
		spin_lock_irqsave(&gpio_lock, flags);


Should __gpiod_request() also call might_sleep_if()?

	if (chip->request) {
		/* chip->request may sleep */
		spin_unlock_irqrestore(&gpio_lock, flags);
---> missing call to might_sleep_if() here?
		status = chip->request(chip, gpio_chip_hwgpio(desc));
		spin_lock_irqsave(&gpio_lock, flags);


-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Stephen Boyd]

On 07/14, Timur Tabi wrote:
> On 07/14/2017 04:46 PM, Stephen Boyd wrote:
> >Right, the gpiolib core would need to be updated to request the
> >gpio in gpiochip_add_data() around the loop where it goes and
> >configures things. And it could ignore ones that it can't request
> >there.
> 
> __gpiod_request already calls chip->request(), so this would need to
> be a temporary request.  It seems a bit hackish, but I'll try it.

Yeah, request, configure, free, in a loop. Unless someone is
aware why we don't do that here.

> 
> BTW, I noticed that __gpiod_free() does this:
> 
> 	if (chip->free) {
> 		spin_unlock_irqrestore(&gpio_lock, flags);
> --->		might_sleep_if(chip->can_sleep);
> 		chip->free(chip, gpio_chip_hwgpio(desc));
> 		spin_lock_irqsave(&gpio_lock, flags);
> 
> 
> Should __gpiod_request() also call might_sleep_if()?
> 
> 	if (chip->request) {
> 		/* chip->request may sleep */
> 		spin_unlock_irqrestore(&gpio_lock, flags);
> ---> missing call to might_sleep_if() here?
> 		status = chip->request(chip, gpio_chip_hwgpio(desc));
> 		spin_lock_irqsave(&gpio_lock, flags);
> 

Probably. Except we would have caught it earlier when it was
requested?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Stephen Boyd]

On 07/14, Timur Tabi wrote:
> On 07/14/2017 04:46 PM, Stephen Boyd wrote:
> >Right, the gpiolib core would need to be updated to request the
> >gpio in gpiochip_add_data() around the loop where it goes and
> >configures things. And it could ignore ones that it can't request
> >there.
> 
> __gpiod_request already calls chip->request(), so this would need to
> be a temporary request.  It seems a bit hackish, but I'll try it.

Yeah, request, configure, free, in a loop. Unless someone is
aware why we don't do that here.

> 
> BTW, I noticed that __gpiod_free() does this:
> 
> 	if (chip->free) {
> 		spin_unlock_irqrestore(&gpio_lock, flags);
> --->		might_sleep_if(chip->can_sleep);
> 		chip->free(chip, gpio_chip_hwgpio(desc));
> 		spin_lock_irqsave(&gpio_lock, flags);
> 
> 
> Should __gpiod_request() also call might_sleep_if()?
> 
> 	if (chip->request) {
> 		/* chip->request may sleep */
> 		spin_unlock_irqrestore(&gpio_lock, flags);
> ---> missing call to might_sleep_if() here?
> 		status = chip->request(chip, gpio_chip_hwgpio(desc));
> 		spin_lock_irqsave(&gpio_lock, flags);
> 

Probably. Except we would have caught it earlier when it was
requested?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Timur Tabi]

Newer versions of the firmware for the Qualcomm Datacenter Technologies
QDF2400 restricts access to a subset of the GPIOs on the TLMM.  To
prevent older kernels from accidentally accessing the restricted GPIOs,
we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
and introduce a new property "gpios".  This property is an array of
specific GPIOs that are accessible.  When an older kernel boots on
newer (restricted) firmware, it will fail to probe.

To implement the sparse GPIO map, we register all of the GPIOs, but set
the pin count for the unavailable GPIOs to zero.  The pinctrl-msm
driver will block those unavailable GPIOs from being accessed.

To allow newer kernels to support older firmware, the driver retains
support for QCOM8001.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 157 +++++++++++++++++++++++----------
 1 file changed, 111 insertions(+), 46 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
index bb3ce5c..266f2e6 100644
--- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -38,83 +38,148 @@
 /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
 #define NAME_SIZE	8
 
+enum {
+	QDF2XXX_V1,
+	QDF2XXX_V2,
+};
+
+static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
+	{"QCOM8001", QDF2XXX_V1},
+	{"QCOM8002", QDF2XXX_V2},
+	{},
+};
+MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
+
 static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
 {
+	const struct acpi_device_id *id =
+		acpi_match_device(qdf2xxx_acpi_ids, &pdev->dev);
+	struct device *dev = &pdev->dev;
 	struct pinctrl_pin_desc *pins;
 	struct msm_pingroup *groups;
 	char (*names)[NAME_SIZE];
 	unsigned int i;
-	u32 num_gpios;
+	unsigned int num_gpios; /* The number of GPIOs we support */
+	u32 max_gpios; /* The highest number GPIO that exists */
+	u16 *gpios; /* An array of supported GPIOs */
 	int ret;
 
-	/* Query the number of GPIOs from ACPI */
-	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
+	/* The total number of GPIOs that exist */
+	ret = device_property_read_u32(dev, "num-gpios", &max_gpios);
 	if (ret < 0) {
-		dev_warn(&pdev->dev, "missing num-gpios property\n");
+		dev_err(dev, "missing or invalid 'num-gpios' property\n");
 		return ret;
 	}
+	if (!max_gpios || max_gpios > MAX_GPIOS) {
+		dev_err(dev, "invalid 'num-gpios' property\n");
+		return -EINVAL;
+	}
 
-	if (!num_gpios || num_gpios > MAX_GPIOS) {
-		dev_warn(&pdev->dev, "invalid num-gpios property\n");
-		return -ENODEV;
+	/*
+	 * The QCOM8001 HID contains only the number of GPIOs, and assumes
+	 * that all of them are available.  num_gpios is the same as max_gpios.
+	 *
+	 * The QCOM8002 HID introduces the 'gpios' DSD, which lists
+	 * specific GPIOs that the driver is allowed to access.
+	 *
+	 * The make the common code simpler, in both cases we create an
+	 * array of GPIOs that are accessible.  So for QCOM8001, that would
+	 * be all of the GPIOs.
+	 */
+	if (id->driver_data == QDF2XXX_V1) {
+		num_gpios = max_gpios;
+
+		gpios = devm_kcalloc(dev, num_gpios, sizeof(u16), GFP_KERNEL);
+		if (!gpios)
+			return -ENOMEM;
+
+		for (i = 0; i < num_gpios; i++)
+			gpios[i] = i;
+	} else {
+		/* The number of GPIOs in the approved list */
+		ret = device_property_read_u16_array(dev, "gpios", NULL, 0);
+		if (ret < 0) {
+			dev_err(dev, "missing/invalid 'gpios' property\n");
+			return ret;
+		}
+		if (ret == 0) {
+			dev_warn(dev, "no GPIOs defined\n");
+			return -ENODEV;
+		}
+		num_gpios = ret;
+
+		gpios = devm_kcalloc(dev, num_gpios, sizeof(u16), GFP_KERNEL);
+		if (!gpios)
+			return -ENOMEM;
+
+		ret = device_property_read_u16_array(dev, "gpios", gpios,
+						     num_gpios);
+		if (ret < 0) {
+			dev_err(dev, "could not read list of GPIOs\n");
+			return ret;
+		}
 	}
 
-	pins = devm_kcalloc(&pdev->dev, num_gpios,
+	pins = devm_kcalloc(dev, max_gpios,
 		sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
-	groups = devm_kcalloc(&pdev->dev, num_gpios,
+	groups = devm_kcalloc(dev, max_gpios,
 		sizeof(struct msm_pingroup), GFP_KERNEL);
-	names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
+	names = devm_kcalloc(dev, num_gpios, NAME_SIZE, GFP_KERNEL);
 
 	if (!pins || !groups || !names)
 		return -ENOMEM;
 
-	for (i = 0; i < num_gpios; i++) {
-		snprintf(names[i], NAME_SIZE, "gpio%u", i);
-
+	/*
+	 * Initialize the array.  GPIOs not listed in the 'gpios' array
+	 * still need a number and a name, but nothing else.
+	 */
+	for (i = 0; i < max_gpios; i++) {
 		pins[i].number = i;
-		pins[i].name = names[i];
-
-		groups[i].npins = 1;
-		groups[i].name = names[i];
 		groups[i].pins = &pins[i].number;
+	}
 
-		groups[i].ctl_reg = 0x10000 * i;
-		groups[i].io_reg = 0x04 + 0x10000 * i;
-		groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
-		groups[i].intr_status_reg = 0x0c + 0x10000 * i;
-		groups[i].intr_target_reg = 0x08 + 0x10000 * i;
-
-		groups[i].mux_bit = 2;
-		groups[i].pull_bit = 0;
-		groups[i].drv_bit = 6;
-		groups[i].oe_bit = 9;
-		groups[i].in_bit = 0;
-		groups[i].out_bit = 1;
-		groups[i].intr_enable_bit = 0;
-		groups[i].intr_status_bit = 0;
-		groups[i].intr_target_bit = 5;
-		groups[i].intr_target_kpss_val = 1;
-		groups[i].intr_raw_status_bit = 4;
-		groups[i].intr_polarity_bit = 1;
-		groups[i].intr_detection_bit = 2;
-		groups[i].intr_detection_width = 2;
+	/* Populate the entries that are meant to be exposes as GPIOs. */
+	for (i = 0; i < num_gpios; i++) {
+		unsigned int gpio = gpios[i];
+
+		groups[gpio].npins = 1;
+		snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
+		pins[gpio].name = names[i];
+		groups[gpio].name = names[i];
+
+		groups[gpio].ctl_reg = 0x10000 * gpio;
+		groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
+		groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
+		groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
+		groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
+
+		groups[gpio].mux_bit = 2;
+		groups[gpio].pull_bit = 0;
+		groups[gpio].drv_bit = 6;
+		groups[gpio].oe_bit = 9;
+		groups[gpio].in_bit = 0;
+		groups[gpio].out_bit = 1;
+		groups[gpio].intr_enable_bit = 0;
+		groups[gpio].intr_status_bit = 0;
+		groups[gpio].intr_target_bit = 5;
+		groups[gpio].intr_target_kpss_val = 1;
+		groups[gpio].intr_raw_status_bit = 4;
+		groups[gpio].intr_polarity_bit = 1;
+		groups[gpio].intr_detection_bit = 2;
+		groups[gpio].intr_detection_width = 2;
 	}
 
+	devm_kfree(dev, gpios);
+
 	qdf2xxx_pinctrl.pins = pins;
 	qdf2xxx_pinctrl.groups = groups;
-	qdf2xxx_pinctrl.npins = num_gpios;
-	qdf2xxx_pinctrl.ngroups = num_gpios;
-	qdf2xxx_pinctrl.ngpios = num_gpios;
+	qdf2xxx_pinctrl.npins = max_gpios;
+	qdf2xxx_pinctrl.ngroups = max_gpios;
+	qdf2xxx_pinctrl.ngpios = max_gpios;
 
 	return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
 }
 
-static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
-	{"QCOM8001"},
-	{},
-};
-MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
-
 static struct platform_driver qdf2xxx_pinctrl_driver = {
 	.driver = {
 		.name = "qdf2xxx-pinctrl",
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Timur Tabi]

Newer versions of the firmware for the Qualcomm Datacenter Technologies
QDF2400 restricts access to a subset of the GPIOs on the TLMM.  To
prevent older kernels from accidentally accessing the restricted GPIOs,
we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
and introduce a new property "gpios".  This property is an array of
specific GPIOs that are accessible.  When an older kernel boots on
newer (restricted) firmware, it will fail to probe.

To implement the sparse GPIO map, we register all of the GPIOs, but set
the pin count for the unavailable GPIOs to zero.  The pinctrl-msm
driver will block those unavailable GPIOs from being accessed.

To allow newer kernels to support older firmware, the driver retains
support for QCOM8001.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 157 +++++++++++++++++++++++----------
 1 file changed, 111 insertions(+), 46 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
index bb3ce5c..266f2e6 100644
--- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -38,83 +38,148 @@
 /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
 #define NAME_SIZE	8
 
+enum {
+	QDF2XXX_V1,
+	QDF2XXX_V2,
+};
+
+static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
+	{"QCOM8001", QDF2XXX_V1},
+	{"QCOM8002", QDF2XXX_V2},
+	{},
+};
+MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
+
 static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
 {
+	const struct acpi_device_id *id =
+		acpi_match_device(qdf2xxx_acpi_ids, &pdev->dev);
+	struct device *dev = &pdev->dev;
 	struct pinctrl_pin_desc *pins;
 	struct msm_pingroup *groups;
 	char (*names)[NAME_SIZE];
 	unsigned int i;
-	u32 num_gpios;
+	unsigned int num_gpios; /* The number of GPIOs we support */
+	u32 max_gpios; /* The highest number GPIO that exists */
+	u16 *gpios; /* An array of supported GPIOs */
 	int ret;
 
-	/* Query the number of GPIOs from ACPI */
-	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
+	/* The total number of GPIOs that exist */
+	ret = device_property_read_u32(dev, "num-gpios", &max_gpios);
 	if (ret < 0) {
-		dev_warn(&pdev->dev, "missing num-gpios property\n");
+		dev_err(dev, "missing or invalid 'num-gpios' property\n");
 		return ret;
 	}
+	if (!max_gpios || max_gpios > MAX_GPIOS) {
+		dev_err(dev, "invalid 'num-gpios' property\n");
+		return -EINVAL;
+	}
 
-	if (!num_gpios || num_gpios > MAX_GPIOS) {
-		dev_warn(&pdev->dev, "invalid num-gpios property\n");
-		return -ENODEV;
+	/*
+	 * The QCOM8001 HID contains only the number of GPIOs, and assumes
+	 * that all of them are available.  num_gpios is the same as max_gpios.
+	 *
+	 * The QCOM8002 HID introduces the 'gpios' DSD, which lists
+	 * specific GPIOs that the driver is allowed to access.
+	 *
+	 * The make the common code simpler, in both cases we create an
+	 * array of GPIOs that are accessible.  So for QCOM8001, that would
+	 * be all of the GPIOs.
+	 */
+	if (id->driver_data == QDF2XXX_V1) {
+		num_gpios = max_gpios;
+
+		gpios = devm_kcalloc(dev, num_gpios, sizeof(u16), GFP_KERNEL);
+		if (!gpios)
+			return -ENOMEM;
+
+		for (i = 0; i < num_gpios; i++)
+			gpios[i] = i;
+	} else {
+		/* The number of GPIOs in the approved list */
+		ret = device_property_read_u16_array(dev, "gpios", NULL, 0);
+		if (ret < 0) {
+			dev_err(dev, "missing/invalid 'gpios' property\n");
+			return ret;
+		}
+		if (ret == 0) {
+			dev_warn(dev, "no GPIOs defined\n");
+			return -ENODEV;
+		}
+		num_gpios = ret;
+
+		gpios = devm_kcalloc(dev, num_gpios, sizeof(u16), GFP_KERNEL);
+		if (!gpios)
+			return -ENOMEM;
+
+		ret = device_property_read_u16_array(dev, "gpios", gpios,
+						     num_gpios);
+		if (ret < 0) {
+			dev_err(dev, "could not read list of GPIOs\n");
+			return ret;
+		}
 	}
 
-	pins = devm_kcalloc(&pdev->dev, num_gpios,
+	pins = devm_kcalloc(dev, max_gpios,
 		sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
-	groups = devm_kcalloc(&pdev->dev, num_gpios,
+	groups = devm_kcalloc(dev, max_gpios,
 		sizeof(struct msm_pingroup), GFP_KERNEL);
-	names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
+	names = devm_kcalloc(dev, num_gpios, NAME_SIZE, GFP_KERNEL);
 
 	if (!pins || !groups || !names)
 		return -ENOMEM;
 
-	for (i = 0; i < num_gpios; i++) {
-		snprintf(names[i], NAME_SIZE, "gpio%u", i);
-
+	/*
+	 * Initialize the array.  GPIOs not listed in the 'gpios' array
+	 * still need a number and a name, but nothing else.
+	 */
+	for (i = 0; i < max_gpios; i++) {
 		pins[i].number = i;
-		pins[i].name = names[i];
-
-		groups[i].npins = 1;
-		groups[i].name = names[i];
 		groups[i].pins = &pins[i].number;
+	}
 
-		groups[i].ctl_reg = 0x10000 * i;
-		groups[i].io_reg = 0x04 + 0x10000 * i;
-		groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
-		groups[i].intr_status_reg = 0x0c + 0x10000 * i;
-		groups[i].intr_target_reg = 0x08 + 0x10000 * i;
-
-		groups[i].mux_bit = 2;
-		groups[i].pull_bit = 0;
-		groups[i].drv_bit = 6;
-		groups[i].oe_bit = 9;
-		groups[i].in_bit = 0;
-		groups[i].out_bit = 1;
-		groups[i].intr_enable_bit = 0;
-		groups[i].intr_status_bit = 0;
-		groups[i].intr_target_bit = 5;
-		groups[i].intr_target_kpss_val = 1;
-		groups[i].intr_raw_status_bit = 4;
-		groups[i].intr_polarity_bit = 1;
-		groups[i].intr_detection_bit = 2;
-		groups[i].intr_detection_width = 2;
+	/* Populate the entries that are meant to be exposes as GPIOs. */
+	for (i = 0; i < num_gpios; i++) {
+		unsigned int gpio = gpios[i];
+
+		groups[gpio].npins = 1;
+		snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
+		pins[gpio].name = names[i];
+		groups[gpio].name = names[i];
+
+		groups[gpio].ctl_reg = 0x10000 * gpio;
+		groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
+		groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
+		groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
+		groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
+
+		groups[gpio].mux_bit = 2;
+		groups[gpio].pull_bit = 0;
+		groups[gpio].drv_bit = 6;
+		groups[gpio].oe_bit = 9;
+		groups[gpio].in_bit = 0;
+		groups[gpio].out_bit = 1;
+		groups[gpio].intr_enable_bit = 0;
+		groups[gpio].intr_status_bit = 0;
+		groups[gpio].intr_target_bit = 5;
+		groups[gpio].intr_target_kpss_val = 1;
+		groups[gpio].intr_raw_status_bit = 4;
+		groups[gpio].intr_polarity_bit = 1;
+		groups[gpio].intr_detection_bit = 2;
+		groups[gpio].intr_detection_width = 2;
 	}
 
+	devm_kfree(dev, gpios);
+
 	qdf2xxx_pinctrl.pins = pins;
 	qdf2xxx_pinctrl.groups = groups;
-	qdf2xxx_pinctrl.npins = num_gpios;
-	qdf2xxx_pinctrl.ngroups = num_gpios;
-	qdf2xxx_pinctrl.ngpios = num_gpios;
+	qdf2xxx_pinctrl.npins = max_gpios;
+	qdf2xxx_pinctrl.ngroups = max_gpios;
+	qdf2xxx_pinctrl.ngpios = max_gpios;
 
 	return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
 }
 
-static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
-	{"QCOM8001"},
-	{},
-};
-MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
-
 static struct platform_driver qdf2xxx_pinctrl_driver = {
 	.driver = {
 		.name = "qdf2xxx-pinctrl",
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Bjorn Andersson]

On Thu 13 Jul 14:52 PDT 2017, Timur Tabi wrote:

> Newer versions of the firmware for the Qualcomm Datacenter Technologies
> QDF2400 restricts access to a subset of the GPIOs on the TLMM.  To
> prevent older kernels from accidentally accessing the restricted GPIOs,
> we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
> and introduce a new property "gpios".  This property is an array of
> specific GPIOs that are accessible.  When an older kernel boots on
> newer (restricted) firmware, it will fail to probe.
> 
> To implement the sparse GPIO map, we register all of the GPIOs, but set
> the pin count for the unavailable GPIOs to zero.  The pinctrl-msm
> driver will block those unavailable GPIOs from being accessed.
> 
> To allow newer kernels to support older firmware, the driver retains
> support for QCOM8001.
> 

This approach looks sane.

> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---
>  drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 157 +++++++++++++++++++++++----------
>  1 file changed, 111 insertions(+), 46 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> index bb3ce5c..266f2e6 100644
> --- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> @@ -38,83 +38,148 @@
>  /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
>  #define NAME_SIZE	8
>  
> +enum {
> +	QDF2XXX_V1,
> +	QDF2XXX_V2,
> +};
> +
> +static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
> +	{"QCOM8001", QDF2XXX_V1},
> +	{"QCOM8002", QDF2XXX_V2},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);

NB. too bad there doesn't seem to be an equivalent of
of_device_get_match_data().

> +
>  static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
>  {
> +	const struct acpi_device_id *id =
> +		acpi_match_device(qdf2xxx_acpi_ids, &pdev->dev);
> +	struct device *dev = &pdev->dev;
>  	struct pinctrl_pin_desc *pins;
>  	struct msm_pingroup *groups;
>  	char (*names)[NAME_SIZE];
>  	unsigned int i;

The result of the patch looks fine, but unfortunately there's some noise
in the patch due to the transition from &pdev->dev to dev and num_gpios
to max_gpios.

> -	u32 num_gpios;
> +	unsigned int num_gpios; /* The number of GPIOs we support */
> +	u32 max_gpios; /* The highest number GPIO that exists */

Could you please keep the "num_gpios" naming and name the new variable
"avail_gpios" or something similar.

> +	u16 *gpios; /* An array of supported GPIOs */
>  	int ret;

>  
> -	/* Query the number of GPIOs from ACPI */
> -	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
> +	/* The total number of GPIOs that exist */
> +	ret = device_property_read_u32(dev, "num-gpios", &max_gpios);
>  	if (ret < 0) {
> -		dev_warn(&pdev->dev, "missing num-gpios property\n");
> +		dev_err(dev, "missing or invalid 'num-gpios' property\n");

While this makes sense it's not entirely related to this patch. My
suggestion is that you prepend a patch transitioning &pdev->dev to dev
and change these to dev_err in the same.

Regards,
Bjorn

[PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Bjorn Andersson]

On Thu 13 Jul 14:52 PDT 2017, Timur Tabi wrote:

> Newer versions of the firmware for the Qualcomm Datacenter Technologies
> QDF2400 restricts access to a subset of the GPIOs on the TLMM.  To
> prevent older kernels from accidentally accessing the restricted GPIOs,
> we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
> and introduce a new property "gpios".  This property is an array of
> specific GPIOs that are accessible.  When an older kernel boots on
> newer (restricted) firmware, it will fail to probe.
> 
> To implement the sparse GPIO map, we register all of the GPIOs, but set
> the pin count for the unavailable GPIOs to zero.  The pinctrl-msm
> driver will block those unavailable GPIOs from being accessed.
> 
> To allow newer kernels to support older firmware, the driver retains
> support for QCOM8001.
> 

This approach looks sane.

> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---
>  drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 157 +++++++++++++++++++++++----------
>  1 file changed, 111 insertions(+), 46 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> index bb3ce5c..266f2e6 100644
> --- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> @@ -38,83 +38,148 @@
>  /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
>  #define NAME_SIZE	8
>  
> +enum {
> +	QDF2XXX_V1,
> +	QDF2XXX_V2,
> +};
> +
> +static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
> +	{"QCOM8001", QDF2XXX_V1},
> +	{"QCOM8002", QDF2XXX_V2},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);

NB. too bad there doesn't seem to be an equivalent of
of_device_get_match_data().

> +
>  static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
>  {
> +	const struct acpi_device_id *id =
> +		acpi_match_device(qdf2xxx_acpi_ids, &pdev->dev);
> +	struct device *dev = &pdev->dev;
>  	struct pinctrl_pin_desc *pins;
>  	struct msm_pingroup *groups;
>  	char (*names)[NAME_SIZE];
>  	unsigned int i;

The result of the patch looks fine, but unfortunately there's some noise
in the patch due to the transition from &pdev->dev to dev and num_gpios
to max_gpios.

> -	u32 num_gpios;
> +	unsigned int num_gpios; /* The number of GPIOs we support */
> +	u32 max_gpios; /* The highest number GPIO that exists */

Could you please keep the "num_gpios" naming and name the new variable
"avail_gpios" or something similar.

> +	u16 *gpios; /* An array of supported GPIOs */
>  	int ret;

>  
> -	/* Query the number of GPIOs from ACPI */
> -	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
> +	/* The total number of GPIOs that exist */
> +	ret = device_property_read_u32(dev, "num-gpios", &max_gpios);
>  	if (ret < 0) {
> -		dev_warn(&pdev->dev, "missing num-gpios property\n");
> +		dev_err(dev, "missing or invalid 'num-gpios' property\n");

While this makes sense it's not entirely related to this patch. My
suggestion is that you prepend a patch transitioning &pdev->dev to dev
and change these to dev_err in the same.

Regards,
Bjorn

Re: [PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Timur Tabi]

On 07/14/2017 12:21 PM, Bjorn Andersson wrote:

>> +enum {
>> +	QDF2XXX_V1,
>> +	QDF2XXX_V2,
>> +};
>> +
>> +static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
>> +	{"QCOM8001", QDF2XXX_V1},
>> +	{"QCOM8002", QDF2XXX_V2},
>> +	{},
>> +};
>> +MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
> 
> NB. too bad there doesn't seem to be an equivalent of
> of_device_get_match_data().

There's acpi_match_device(), which I use.

> 
>> +
>>   static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
>>   {
>> +	const struct acpi_device_id *id =
>> +		acpi_match_device(qdf2xxx_acpi_ids, &pdev->dev);
>> +	struct device *dev = &pdev->dev;
>>   	struct pinctrl_pin_desc *pins;
>>   	struct msm_pingroup *groups;
>>   	char (*names)[NAME_SIZE];
>>   	unsigned int i;
> 
> The result of the patch looks fine, but unfortunately there's some noise
> in the patch due to the transition from &pdev->dev to dev and num_gpios
> to max_gpios.

I did that to shrink the line lengths.  I can put it back if you want.

> 
>> -	u32 num_gpios;
>> +	unsigned int num_gpios; /* The number of GPIOs we support */
>> +	u32 max_gpios; /* The highest number GPIO that exists */
> 
> Could you please keep the "num_gpios" naming and name the new variable
> "avail_gpios" or something similar.

Sure.

> 
>> +	u16 *gpios; /* An array of supported GPIOs */
>>   	int ret;
> 
>>   
>> -	/* Query the number of GPIOs from ACPI */
>> -	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
>> +	/* The total number of GPIOs that exist */
>> +	ret = device_property_read_u32(dev, "num-gpios", &max_gpios);
>>   	if (ret < 0) {
>> -		dev_warn(&pdev->dev, "missing num-gpios property\n");
>> +		dev_err(dev, "missing or invalid 'num-gpios' property\n");
> 
> While this makes sense it's not entirely related to this patch. My
> suggestion is that you prepend a patch transitioning &pdev->dev to dev
> and change these to dev_err in the same.

I'd rather put pdev->dev back.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 2/2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Timur Tabi]

On 07/14/2017 12:21 PM, Bjorn Andersson wrote:

>> +enum {
>> +	QDF2XXX_V1,
>> +	QDF2XXX_V2,
>> +};
>> +
>> +static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
>> +	{"QCOM8001", QDF2XXX_V1},
>> +	{"QCOM8002", QDF2XXX_V2},
>> +	{},
>> +};
>> +MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
> 
> NB. too bad there doesn't seem to be an equivalent of
> of_device_get_match_data().

There's acpi_match_device(), which I use.

> 
>> +
>>   static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
>>   {
>> +	const struct acpi_device_id *id =
>> +		acpi_match_device(qdf2xxx_acpi_ids, &pdev->dev);
>> +	struct device *dev = &pdev->dev;
>>   	struct pinctrl_pin_desc *pins;
>>   	struct msm_pingroup *groups;
>>   	char (*names)[NAME_SIZE];
>>   	unsigned int i;
> 
> The result of the patch looks fine, but unfortunately there's some noise
> in the patch due to the transition from &pdev->dev to dev and num_gpios
> to max_gpios.

I did that to shrink the line lengths.  I can put it back if you want.

> 
>> -	u32 num_gpios;
>> +	unsigned int num_gpios; /* The number of GPIOs we support */
>> +	u32 max_gpios; /* The highest number GPIO that exists */
> 
> Could you please keep the "num_gpios" naming and name the new variable
> "avail_gpios" or something similar.

Sure.

> 
>> +	u16 *gpios; /* An array of supported GPIOs */
>>   	int ret;
> 
>>   
>> -	/* Query the number of GPIOs from ACPI */
>> -	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
>> +	/* The total number of GPIOs that exist */
>> +	ret = device_property_read_u32(dev, "num-gpios", &max_gpios);
>>   	if (ret < 0) {
>> -		dev_warn(&pdev->dev, "missing num-gpios property\n");
>> +		dev_err(dev, "missing or invalid 'num-gpios' property\n");
> 
> While this makes sense it's not entirely related to this patch. My
> suggestion is that you prepend a patch transitioning &pdev->dev to dev
> and change these to dev_err in the same.

I'd rather put pdev->dev back.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

To support sparse GPIO maps, pinctrl-msm client drivers can specify
that a given GPIO has a pin count of zero.  These GPIOs will be
considered "hidden".  Any attempt to claim the GPIO will fail, and they
will not be listed in debugfs.

However, when the driver probes, it calls gpiochip_add_data() which
wants to initialize the direction of all the GPIOs, even the ones that
are unavailable.  Therefore, msm_gpio_get_direction() checks to make
sure the pin is available.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 34 ++++++++++++++++++++++++++++++----
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 273badd..e915db4 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 	return 0;
 }
 
+/*
+ * Request a GPIO. If the number of pins for this GPIO group is zero,
+ * then assume that the GPIO is unavailable.
+ */
+static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
+{
+	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	const struct msm_pingroup *g;
+
+	g = &pctrl->soc->groups[offset];
+
+	return g->npins ? 0 : -ENODEV;
+}
+
 static const struct pinmux_ops msm_pinmux_ops = {
+	.request		= msm_request,
 	.get_functions_count	= msm_get_functions_count,
 	.get_function_name	= msm_get_function_name,
 	.get_function_groups	= msm_get_function_groups,
@@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 
 	g = &pctrl->soc->groups[offset];
 
+	/*
+	 * If the GPIO is unavailable, just return error.  This is necessary
+	 * because the GPIO layer tries to initialize the direction of all
+	 * the GPIOs, even the ones that are unavailable.
+	 */
+	if (!g->npins)
+		return -ENODEV;
+
 	val = readl(pctrl->regs + g->ctl_reg);
 
 	/* 0 = output, 1 = input */
@@ -494,6 +517,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 	};
 
 	g = &pctrl->soc->groups[offset];
+
+	/* If the GPIO group has no pins, then don't show it. */
+	if (!g->npins)
+		return;
+
 	ctl_reg = readl(pctrl->regs + g->ctl_reg);
 
 	is_out = !!(ctl_reg & BIT(g->oe_bit));
@@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 
 	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
-	seq_printf(s, " %s", pulls[pull]);
+	seq_printf(s, " %s\n", pulls[pull]);
 }
 
 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
@@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 	unsigned gpio = chip->base;
 	unsigned i;
 
-	for (i = 0; i < chip->ngpio; i++, gpio++) {
+	for (i = 0; i < chip->ngpio; i++, gpio++)
 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
-		seq_puts(s, "\n");
-	}
 }
 
 #else
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/2] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

To support sparse GPIO maps, pinctrl-msm client drivers can specify
that a given GPIO has a pin count of zero.  These GPIOs will be
considered "hidden".  Any attempt to claim the GPIO will fail, and they
will not be listed in debugfs.

However, when the driver probes, it calls gpiochip_add_data() which
wants to initialize the direction of all the GPIOs, even the ones that
are unavailable.  Therefore, msm_gpio_get_direction() checks to make
sure the pin is available.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 34 ++++++++++++++++++++++++++++++----
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 273badd..e915db4 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -165,7 +165,22 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 	return 0;
 }
 
+/*
+ * Request a GPIO. If the number of pins for this GPIO group is zero,
+ * then assume that the GPIO is unavailable.
+ */
+static int msm_request(struct pinctrl_dev *pctldev, unsigned int offset)
+{
+	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+	const struct msm_pingroup *g;
+
+	g = &pctrl->soc->groups[offset];
+
+	return g->npins ? 0 : -ENODEV;
+}
+
 static const struct pinmux_ops msm_pinmux_ops = {
+	.request		= msm_request,
 	.get_functions_count	= msm_get_functions_count,
 	.get_function_name	= msm_get_function_name,
 	.get_function_groups	= msm_get_function_groups,
@@ -430,6 +445,14 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 
 	g = &pctrl->soc->groups[offset];
 
+	/*
+	 * If the GPIO is unavailable, just return error.  This is necessary
+	 * because the GPIO layer tries to initialize the direction of all
+	 * the GPIOs, even the ones that are unavailable.
+	 */
+	if (!g->npins)
+		return -ENODEV;
+
 	val = readl(pctrl->regs + g->ctl_reg);
 
 	/* 0 = output, 1 = input */
@@ -494,6 +517,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 	};
 
 	g = &pctrl->soc->groups[offset];
+
+	/* If the GPIO group has no pins, then don't show it. */
+	if (!g->npins)
+		return;
+
 	ctl_reg = readl(pctrl->regs + g->ctl_reg);
 
 	is_out = !!(ctl_reg & BIT(g->oe_bit));
@@ -503,7 +531,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 
 	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
-	seq_printf(s, " %s", pulls[pull]);
+	seq_printf(s, " %s\n", pulls[pull]);
 }
 
 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
@@ -511,10 +539,8 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 	unsigned gpio = chip->base;
 	unsigned i;
 
-	for (i = 0; i < chip->ngpio; i++, gpio++) {
+	for (i = 0; i < chip->ngpio; i++, gpio++)
 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
-		seq_puts(s, "\n");
-	}
 }
 
 #else
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.