Re: [Qemu-devel] [PATCH 0/14] target/mips: Add Enhanced Virtual Addressing (EVA) support

[no-reply@patchew.org]

Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH 0/14] target/mips: Add Enhanced Virtual Addressing (EVA) support
Message-id: cover.34f8428dbbcaa0611cef759667d281ae508ac91d.1500378931.git-series.james.hogan@imgtec.com
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
888a8b3 target/mips: Enable CP0_EBase.WG on MIPS64 CPUs
ff13d16 target/mips: Add EVA support to P5600
3edc7b0 target/mips: Implement segmentation control
796fdf5 target/mips: Add segmentation control registers
f72fe25 target/mips: Add an MMU mode for ERL
0bcefc0 target/mips: Abstract mmu_idx from hflags
39dc7d8 target/mips: Check memory permissions with mem_idx
d75cb8a target/mips: Decode microMIPS EVA load & store instructions
d92ac8c target/mips: Decode MIPS32 EVA load & store instructions
4f20958 target/mips: Prepare loads/stores for EVA
b99a507 target/mips: Add CP0_Ebase.WG (write gate) support
97df4ad target/mips: Weaken TLB flush on UX, SX, KX, ASID changes
4c8f539 target/mips: Fix TLBWI shadow flush for EHINV, XI, RI
57afc02 target/mips: Fix MIPS64 MFC0 UserLocal on BE host

=== OUTPUT BEGIN ===
Checking PATCH 1/14: target/mips: Fix MIPS64 MFC0 UserLocal on BE host...
Checking PATCH 2/14: target/mips: Fix TLBWI shadow flush for EHINV, XI, RI...
ERROR: space prohibited after that '&' (ctx:WxW)
#44: FILE: target/mips/op_helper.c:2045:
+    XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
                                             ^

ERROR: space prohibited after that '&' (ctx:WxW)
#45: FILE: target/mips/op_helper.c:2046:
+    RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
                                             ^

ERROR: space prohibited after that '&' (ctx:WxW)
#48: FILE: target/mips/op_helper.c:2049:
+    XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
                                             ^

ERROR: space prohibited after that '&' (ctx:WxW)
#49: FILE: target/mips/op_helper.c:2050:
+    RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
                                             ^

total: 4 errors, 0 warnings, 34 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 3/14: target/mips: Weaken TLB flush on UX, SX, KX, ASID changes...
Checking PATCH 4/14: target/mips: Add CP0_Ebase.WG (write gate) support...
ERROR: space prohibited after that '&' (ctx:WxW)
#114: FILE: target/mips/op_helper.c:1519:
+    if (arg1 & (1 << CP0EBase_WG) & mask) {
                                   ^

ERROR: space prohibited after that '&' (ctx:WxW)
#126: FILE: target/mips/op_helper.c:1530:
+    if (arg1 & (1 << CP0EBase_WG) & mask) {
                                   ^

total: 2 errors, 0 warnings, 126 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 5/14: target/mips: Prepare loads/stores for EVA...
Checking PATCH 6/14: target/mips: Decode MIPS32 EVA load & store instructions...
Checking PATCH 7/14: target/mips: Decode microMIPS EVA load & store instructions...
Checking PATCH 8/14: target/mips: Check memory permissions with mem_idx...
Checking PATCH 9/14: target/mips: Abstract mmu_idx from hflags...
Checking PATCH 10/14: target/mips: Add an MMU mode for ERL...
ERROR: trailing statements should be on next line
#94: FILE: target/mips/op_helper.c:98:
+    case 3: cpu_##insn##_error_ra(env, addr, val, retaddr); break;      \

ERROR: trailing statements should be on next line
#102: FILE: target/mips/op_helper.c:1456:
+        case 3: qemu_log(", ERL\n"); break;

ERROR: trailing statements should be on next line
#110: FILE: target/mips/op_helper.c:2251:
+        case 3: qemu_log(", ERL\n"); break;

total: 3 errors, 0 warnings, 79 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 11/14: target/mips: Add segmentation control registers...
Checking PATCH 12/14: target/mips: Implement segmentation control...
ERROR: braces {} are necessary for all arms of this statement
#246: FILE: target/mips/helper.c:836:
+            if ((R != 0 || UX) && (R != 3 || KX) &&
[...]

ERROR: braces {} are necessary for all arms of this statement
#258: FILE: target/mips/helper.c:854:
+            if ((R != 0 || UX) && (R != 3 || KX) &&
[...]

total: 2 errors, 0 warnings, 234 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 13/14: target/mips: Add EVA support to P5600...
Checking PATCH 14/14: target/mips: Enable CP0_EBase.WG on MIPS64 CPUs...
=== OUTPUT END ===

Test command exited with code: 1


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