All of lore.kernel.org
 help / color / mirror / Atom feed
From: James Hogan <james.hogan@imgtec.com>
To: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: qemu-devel@nongnu.org, James Hogan <james.hogan@imgtec.com>,
	Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH 8/14] target/mips: Check memory permissions with mem_idx
Date: Tue, 18 Jul 2017 12:55:53 +0100	[thread overview]
Message-ID: <22d40c9833292f00f0d4ccaf3317aa57a4d905a6.1500378931.git-series.james.hogan@imgtec.com> (raw)
In-Reply-To: <cover.34f8428dbbcaa0611cef759667d281ae508ac91d.1500378931.git-series.james.hogan@imgtec.com>

When performing virtual to physical address translation, check the
required privilege level based on the mem_idx rather than the mode in
the hflags. This will allow EVA loads & stores to operate safely only on
user memory from kernel mode.

For the cases where the mmu_idx doesn't need to be overridden
(mips_cpu_get_phys_page_debug() and cpu_mips_translate_address()), we
calculate the required mmu_idx using cpu_mmu_index(). Note that this
only tests the MIPS_HFLAG_KSU bits rather than MIPS_HFLAG_MODE, so we
don't test the debug mode hflag MIPS_HFLAG_DM any longer. This should be
fine as get_physical_address() only compares against MIPS_HFLAG_UM and
MIPS_HFLAG_SM, neither of which should get set by compute_hflags() when
MIPS_HFLAG_DM is set.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
---
 target/mips/helper.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/target/mips/helper.c b/target/mips/helper.c
index cd07995eedb2..f78d151d2583 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -109,11 +109,11 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 
 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
                                 int *prot, target_ulong real_address,
-                                int rw, int access_type)
+                                int rw, int access_type, int mmu_idx)
 {
     /* User mode can only access useg/xuseg */
-    int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
-    int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
+    int user_mode = mmu_idx == MIPS_HFLAG_UM;
+    int supervisor_mode = mmu_idx == MIPS_HFLAG_SM;
     int kernel_mode = !user_mode && !supervisor_mode;
 #if defined(TARGET_MIPS64)
     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
@@ -413,11 +413,12 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 {
     MIPSCPU *cpu = MIPS_CPU(cs);
+    CPUMIPSState *env = &cpu->env;
     hwaddr phys_addr;
     int prot;
 
-    if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
-                             ACCESS_INT) != 0) {
+    if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT,
+                             cpu_mmu_index(env, false)) != 0) {
         return -1;
     }
     return phys_addr;
@@ -449,7 +450,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
        correctly */
     access_type = ACCESS_INT;
     ret = get_physical_address(env, &physical, &prot,
-                               address, rw, access_type);
+                               address, rw, access_type, mmu_idx);
     switch (ret) {
     case TLBRET_MATCH:
         qemu_log_mask(CPU_LOG_MMU,
@@ -487,8 +488,8 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int r
 
     /* data access */
     access_type = ACCESS_INT;
-    ret = get_physical_address(env, &physical, &prot,
-                               address, rw, access_type);
+    ret = get_physical_address(env, &physical, &prot, address, rw, access_type,
+                               cpu_mmu_index(env, false));
     if (ret != TLBRET_MATCH) {
         raise_mmu_exception(env, address, rw, ret);
         return -1LL;
-- 
git-series 0.8.10

  parent reply	other threads:[~2017-07-18 11:56 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-18 11:55 [Qemu-devel] [PATCH 0/14] target/mips: Add Enhanced Virtual Addressing (EVA) support James Hogan
2017-07-18 11:55 ` [Qemu-devel] [PATCH 1/14] target/mips: Fix MIPS64 MFC0 UserLocal on BE host James Hogan
2017-07-18 14:37   ` Yongbok Kim
2017-07-19 10:27   ` Aurelien Jarno
2017-07-19 13:44     ` James Hogan
2017-07-19 16:26       ` Aurelien Jarno
2017-07-18 11:55 ` [Qemu-devel] [PATCH 2/14] target/mips: Fix TLBWI shadow flush for EHINV, XI, RI James Hogan
2017-07-20 15:16   ` Yongbok Kim
2017-07-18 11:55 ` [Qemu-devel] [PATCH 3/14] target/mips: Weaken TLB flush on UX, SX, KX, ASID changes James Hogan
2017-07-20 15:17   ` Yongbok Kim
2017-07-18 11:55 ` [Qemu-devel] [PATCH 4/14] target/mips: Add CP0_Ebase.WG (write gate) support James Hogan
2017-07-19 14:54   ` Yongbok Kim
2017-07-19 15:02     ` James Hogan
2017-07-18 11:55 ` [Qemu-devel] [PATCH 5/14] target/mips: Prepare loads/stores for EVA James Hogan
2017-07-18 11:55 ` [Qemu-devel] [PATCH 6/14] target/mips: Decode MIPS32 EVA load & store instructions James Hogan
2017-07-18 15:43   ` Yongbok Kim
2017-07-18 11:55 ` [Qemu-devel] [PATCH 7/14] target/mips: Decode microMIPS " James Hogan
2017-07-18 16:07   ` Yongbok Kim
2017-07-18 11:55 ` James Hogan [this message]
2017-07-18 11:55 ` [Qemu-devel] [PATCH 9/14] target/mips: Abstract mmu_idx from hflags James Hogan
2017-07-18 11:55 ` [Qemu-devel] [PATCH 10/14] target/mips: Add an MMU mode for ERL James Hogan
2017-07-18 11:55 ` [Qemu-devel] [PATCH 11/14] target/mips: Add segmentation control registers James Hogan
2017-07-18 22:01   ` Yongbok Kim
2017-07-18 11:55 ` [Qemu-devel] [PATCH 12/14] target/mips: Implement segmentation control James Hogan
2017-07-20 13:08   ` Yongbok Kim
2017-07-18 11:55 ` [Qemu-devel] [PATCH 13/14] target/mips: Add EVA support to P5600 James Hogan
2017-07-18 11:55 ` [Qemu-devel] [PATCH 14/14] target/mips: Enable CP0_EBase.WG on MIPS64 CPUs James Hogan
2017-07-20 13:12   ` Yongbok Kim
2017-07-18 21:21 ` [Qemu-devel] [PATCH 0/14] target/mips: Add Enhanced Virtual Addressing (EVA) support no-reply
2017-07-19  9:02   ` James Hogan

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=22d40c9833292f00f0d4ccaf3317aa57a4d905a6.1500378931.git-series.james.hogan@imgtec.com \
    --to=james.hogan@imgtec.com \
    --cc=aurelien@aurel32.net \
    --cc=qemu-devel@nongnu.org \
    --cc=yongbok.kim@imgtec.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.