From: Varadarajan Narayanan <varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> To: bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, svarbanov-NEYub+7Iv8PQT0dZR+AlfA@public.gmane.org, kishon-l0cyMroinI0@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, fengguang.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, weiyongjun1-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: Varadarajan Narayanan <varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Subject: [PATCH v6 1/7] dt-bindings: phy: qmp: Add output-clock-names Date: Mon, 31 Jul 2017 12:04:11 +0530 [thread overview] Message-ID: <1501482857-14100-2-git-send-email-varada@codeaurora.org> (raw) In-Reply-To: <1501482857-14100-1-git-send-email-varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> The phy outputs a clock that will act as the parent for the phy's pipe clock. Add the name of this clock to the lane's DT node. Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> Signed-off-by: Varadarajan Narayanan <varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> --- Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index e11c563..5d7a51f 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -60,6 +60,8 @@ Required properties for child node: one for each entry in clock-names. - clock-names: Must contain following for pcie and usb qmp phys: "pipe<lane-number>" for pipe clock specific to each lane. + - clock-output-names: Name of the phy clock that will be the parent for + the above pipe clock. - resets: a list of phandles and reset controller specifier pairs, one for each entry in reset-names. @@ -96,6 +98,7 @@ Example: clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "pipe0"; + clock-output-names = "pcie_0_pipe_clk_src"; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "lane0"; }; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
WARNING: multiple messages have this Message-ID (diff)
From: Varadarajan Narayanan <varada@codeaurora.org> To: bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, svarbanov@mm-sol.com, kishon@ti.com, sboyd@codeaurora.org, vivek.gautam@codeaurora.org, fengguang.wu@intel.com, weiyongjun1@huawei.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Varadarajan Narayanan <varada@codeaurora.org> Subject: [PATCH v6 1/7] dt-bindings: phy: qmp: Add output-clock-names Date: Mon, 31 Jul 2017 12:04:11 +0530 [thread overview] Message-ID: <1501482857-14100-2-git-send-email-varada@codeaurora.org> (raw) In-Reply-To: <1501482857-14100-1-git-send-email-varada@codeaurora.org> The phy outputs a clock that will act as the parent for the phy's pipe clock. Add the name of this clock to the lane's DT node. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> --- Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index e11c563..5d7a51f 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -60,6 +60,8 @@ Required properties for child node: one for each entry in clock-names. - clock-names: Must contain following for pcie and usb qmp phys: "pipe<lane-number>" for pipe clock specific to each lane. + - clock-output-names: Name of the phy clock that will be the parent for + the above pipe clock. - resets: a list of phandles and reset controller specifier pairs, one for each entry in reset-names. @@ -96,6 +98,7 @@ Example: clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "pipe0"; + clock-output-names = "pcie_0_pipe_clk_src"; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "lane0"; }; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2017-07-31 6:34 UTC|newest] Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-07-31 6:34 [PATCH v6 0/7] Add support for IPQ8074 PCIe phy and controller Varadarajan Narayanan [not found] ` <1501482857-14100-1-git-send-email-varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2017-07-31 6:34 ` Varadarajan Narayanan [this message] 2017-07-31 6:34 ` [PATCH v6 1/7] dt-bindings: phy: qmp: Add output-clock-names Varadarajan Narayanan 2017-08-03 23:04 ` Bjorn Helgaas 2017-07-31 6:34 ` [PATCH v6 3/7] phy: qcom-qmp: Fix phy pipe clock name Varadarajan Narayanan 2017-07-31 6:34 ` Varadarajan Narayanan 2017-07-31 6:34 ` [PATCH v6 2/7] dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074 Varadarajan Narayanan 2017-08-03 23:05 ` Bjorn Helgaas 2017-08-03 23:38 ` Rob Herring 2017-07-31 6:34 ` [PATCH v6 4/7] phy: qcom-qmp: Add support for IPQ8074 Varadarajan Narayanan 2017-07-31 6:34 ` [PATCH v6 5/7] PCI: dwc: qcom: Use block IP version for operations Varadarajan Narayanan [not found] ` <1501482857-14100-6-git-send-email-varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2017-08-02 18:34 ` Stanimir Varbanov 2017-08-02 18:34 ` Stanimir Varbanov 2017-07-31 6:34 ` [PATCH v6 6/7] dt-bindings: pci: qcom: Add support for IPQ8074 Varadarajan Narayanan 2017-08-03 23:39 ` Rob Herring 2017-07-31 6:34 ` [PATCH v6 7/7] PCI: dwc: qcom: Add support for IPQ8074 PCIe controller Varadarajan Narayanan 2017-08-02 20:40 ` Stanimir Varbanov 2017-08-17 8:31 ` Varadarajan Narayanan 2017-08-02 5:08 ` [PATCH v6 0/7] Add support for IPQ8074 PCIe phy and controller Kishon Vijay Abraham I 2017-08-02 5:08 ` Kishon Vijay Abraham I 2017-08-03 23:07 ` Bjorn Helgaas 2017-08-20 10:58 ` Kishon Vijay Abraham I 2017-08-20 10:58 ` Kishon Vijay Abraham I
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