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* [PATCH v3 1/2] drm/i915: Introduce INTEL_GEN_MASK
@ 2017-09-11  7:57 Joonas Lahtinen
  2017-09-11  7:57 ` [PATCH v3 2/2] drm/i915: Simplify i915_reg_read_ioctl Joonas Lahtinen
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Joonas Lahtinen @ 2017-09-11  7:57 UTC (permalink / raw)
  To: Intel graphics driver community testing & development
  Cc: Jani Nikula, Rodrigo Vivi

Split INTEL_GEN_MASK out of IS_GEN macro, and make it usable
within static declarations (unlike combound statements).

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.h | 22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 63ca2ffcafef..c3f9d7d7b146 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2873,23 +2873,21 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
 
 #define GEN_FOREVER (0)
+
+#define INTEL_GEN_MASK(s, e) ( \
+        BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
+        BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
+        GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
+	        (s) != GEN_FOREVER ? (s) - 1 : 0) \
+)
+
 /*
  * Returns true if Gen is in inclusive range [Start, End].
  *
  * Use GEN_FOREVER for unbound start and or end.
  */
-#define IS_GEN(dev_priv, s, e) ({ \
-	unsigned int __s = (s), __e = (e); \
-	BUILD_BUG_ON(!__builtin_constant_p(s)); \
-	BUILD_BUG_ON(!__builtin_constant_p(e)); \
-	if ((__s) != GEN_FOREVER) \
-		__s = (s) - 1; \
-	if ((__e) == GEN_FOREVER) \
-		__e = BITS_PER_LONG - 1; \
-	else \
-		__e = (e) - 1; \
-	!!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
-})
+#define IS_GEN(dev_priv, s, e) \
+	(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
 
 /*
  * Return true if revision is in range [since,until] inclusive.
-- 
2.13.5

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH v3 2/2] drm/i915: Simplify i915_reg_read_ioctl
  2017-09-11  7:57 [PATCH v3 1/2] drm/i915: Introduce INTEL_GEN_MASK Joonas Lahtinen
@ 2017-09-11  7:57 ` Joonas Lahtinen
  2017-09-11  9:18   ` Chris Wilson
  2017-09-11  8:24 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915: Introduce INTEL_GEN_MASK Patchwork
  2017-09-11  9:23 ` ✓ Fi.CI.IGT: " Patchwork
  2 siblings, 1 reply; 6+ messages in thread
From: Joonas Lahtinen @ 2017-09-11  7:57 UTC (permalink / raw)
  To: Intel graphics driver community testing & development
  Cc: Jani Nikula, Rodrigo Vivi

Convert to use the freshly available made INTEL_GEN_MASK for easier
grepping and improve function readability and clarify the UABI
documentation.

No functional changes.

v2:
- Lift GEM_BUG_ONs and use is_power_of_2 (Chris)
- Retain -EINVAL on bad flags behavior (Chris)

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 93 +++++++++++++++++--------------------
 include/uapi/drm/i915_drm.h         |  6 ++-
 2 files changed, 46 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 1b38eb94d461..647bacd7c56b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1292,72 +1292,63 @@ void intel_uncore_fini(struct drm_i915_private *dev_priv)
 	intel_uncore_forcewake_reset(dev_priv, false);
 }
 
-#define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
-
-static const struct register_whitelist {
-	i915_reg_t offset_ldw, offset_udw;
-	uint32_t size;
-	/* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
-	uint32_t gen_bitmask;
-} whitelist[] = {
-	{ .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
-	  .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
-	  .size = 8, .gen_bitmask = GEN_RANGE(4, 10) },
-};
+static const struct reg_whitelist {
+	i915_reg_t offset_ldw;
+	i915_reg_t offset_udw;
+	unsigned long gen_mask;
+	u8 size;
+} reg_read_whitelist[] = {{
+	.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
+	.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
+	.gen_mask = INTEL_GEN_MASK(4, 10),
+	.size = 8
+}};
 
 int i915_reg_read_ioctl(struct drm_device *dev,
 			void *data, struct drm_file *file)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct drm_i915_reg_read *reg = data;
-	struct register_whitelist const *entry = whitelist;
-	unsigned size;
-	i915_reg_t offset_ldw, offset_udw;
-	int i, ret = 0;
-
-	for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
-		if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
-		    (INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask))
+	struct reg_whitelist const *entry;
+	unsigned flags;
+	int remain;
+	int ret = 0;
+
+	entry = reg_read_whitelist;
+	remain = ARRAY_SIZE(reg_read_whitelist);
+	while (remain) {
+		GEM_BUG_ON(!is_power_of_2(entry->size));
+		GEM_BUG_ON(entry->size > 8);
+
+		if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask &&
+		    i915_mmio_reg_offset(entry->offset_ldw) ==
+			    (reg->offset & -entry->size))
 			break;
+		entry++;
+		remain--;
 	}
 
-	if (i == ARRAY_SIZE(whitelist))
+	if (!remain)
 		return -EINVAL;
 
-	/* We use the low bits to encode extra flags as the register should
-	 * be naturally aligned (and those that are not so aligned merely
-	 * limit the available flags for that register).
-	 */
-	offset_ldw = entry->offset_ldw;
-	offset_udw = entry->offset_udw;
-	size = entry->size;
-	size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
+	flags = reg->offset & ~i915_mmio_reg_offset(entry->offset_ldw);
 
 	intel_runtime_pm_get(dev_priv);
-
-	switch (size) {
-	case 8 | 1:
-		reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
-		break;
-	case 8:
-		reg->val = I915_READ64(offset_ldw);
-		break;
-	case 4:
-		reg->val = I915_READ(offset_ldw);
-		break;
-	case 2:
-		reg->val = I915_READ16(offset_ldw);
-		break;
-	case 1:
-		reg->val = I915_READ8(offset_ldw);
-		break;
-	default:
+	if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
+		reg->val = I915_READ64_2x32(entry->offset_ldw,
+					    entry->offset_udw);
+	else if (entry->size == 8 && flags == 0)
+		reg->val = I915_READ64(entry->offset_ldw);
+	else if (entry->size == 4 && flags == 0)
+		reg->val = I915_READ(entry->offset_ldw);
+	else if (entry->size == 2 && flags == 0)
+		reg->val = I915_READ16(entry->offset_ldw);
+	else if (entry->size == 1 && flags == 0)
+		reg->val = I915_READ8(entry->offset_ldw);
+	else
 		ret = -EINVAL;
-		goto out;
-	}
-
-out:
 	intel_runtime_pm_put(dev_priv);
+
 	return ret;
 }
 
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index d8d10d932759..b4505d55990d 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1308,14 +1308,16 @@ struct drm_i915_reg_read {
 	 * be specified
 	 */
 	__u64 offset;
+#define I915_REG_READ_8B_WA BIT(0)
+
 	__u64 val; /* Return value */
 };
 /* Known registers:
  *
  * Render engine timestamp - 0x2358 + 64bit - gen7+
  * - Note this register returns an invalid value if using the default
- *   single instruction 8byte read, in order to workaround that use
- *   offset (0x2538 | 1) instead.
+ *   single instruction 8byte read, in order to workaround that pass
+ *   flag I915_REG_READ_8B_WA in offset field.
  *
  */
 
-- 
2.13.5

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915: Introduce INTEL_GEN_MASK
  2017-09-11  7:57 [PATCH v3 1/2] drm/i915: Introduce INTEL_GEN_MASK Joonas Lahtinen
  2017-09-11  7:57 ` [PATCH v3 2/2] drm/i915: Simplify i915_reg_read_ioctl Joonas Lahtinen
@ 2017-09-11  8:24 ` Patchwork
  2017-09-11  9:23 ` ✓ Fi.CI.IGT: " Patchwork
  2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-09-11  8:24 UTC (permalink / raw)
  To: Joonas Lahtinen; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v3,1/2] drm/i915: Introduce INTEL_GEN_MASK
URL   : https://patchwork.freedesktop.org/series/30103/
State : success

== Summary ==

Series 30103v1 series starting with [v3,1/2] drm/i915: Introduce INTEL_GEN_MASK
https://patchwork.freedesktop.org/api/1.0/series/30103/revisions/1/mbox/

Test chamelium:
        Subgroup dp-crc-fast:
                pass       -> FAIL       (fi-kbl-7500u) fdo#102514
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-atomic:
                pass       -> FAIL       (fi-snb-2600) fdo#100215 +1
Test kms_flip:
        Subgroup basic-flip-vs-modeset:
                pass       -> SKIP       (fi-skl-x1585l) fdo#101781

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:444s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:464s
fi-blb-e6850     total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  time:377s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:539s
fi-bwr-2160      total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 time:269s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:507s
fi-byt-j1900     total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  time:505s
fi-byt-n2820     total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  time:498s
fi-cfl-s         total:289  pass:250  dwarn:4   dfail:0   fail:0   skip:35  time:453s
fi-elk-e7500     total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  time:452s
fi-glk-2a        total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:598s
fi-hsw-4770      total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:429s
fi-hsw-4770r     total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:412s
fi-ilk-650       total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:444s
fi-ivb-3520m     total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:483s
fi-ivb-3770      total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:458s
fi-kbl-7500u     total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  time:481s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:581s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:587s
fi-pnv-d510      total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:555s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:457s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:519s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:503s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:466s
fi-skl-x1585l    total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:474s
fi-snb-2520m     total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  time:565s
fi-snb-2600      total:289  pass:248  dwarn:0   dfail:0   fail:2   skip:39  time:426s

9ef5732ddf6924e98a5c5d034a3535cff14f72bf drm-tip: 2017y-09m-10d-21h-59m-53s UTC integration manifest
9edbbb496ff4 drm/i915: Simplify i915_reg_read_ioctl
6184fa0370e2 drm/i915: Introduce INTEL_GEN_MASK

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5633/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v3 2/2] drm/i915: Simplify i915_reg_read_ioctl
  2017-09-11  7:57 ` [PATCH v3 2/2] drm/i915: Simplify i915_reg_read_ioctl Joonas Lahtinen
@ 2017-09-11  9:18   ` Chris Wilson
  2017-09-11  9:32     ` Chris Wilson
  0 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2017-09-11  9:18 UTC (permalink / raw)
  To: Joonas Lahtinen,
	Intel graphics driver community testing & development
  Cc: Jani Nikula, Rodrigo Vivi

Quoting Joonas Lahtinen (2017-09-11 08:57:19)
> Convert to use the freshly available made INTEL_GEN_MASK for easier
> grepping and improve function readability and clarify the UABI
> documentation.
> 
> No functional changes.
> 
> v2:
> - Lift GEM_BUG_ONs and use is_power_of_2 (Chris)
> - Retain -EINVAL on bad flags behavior (Chris)
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 93 +++++++++++++++++--------------------
>  include/uapi/drm/i915_drm.h         |  6 ++-
>  2 files changed, 46 insertions(+), 53 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 1b38eb94d461..647bacd7c56b 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1292,72 +1292,63 @@ void intel_uncore_fini(struct drm_i915_private *dev_priv)
>         intel_uncore_forcewake_reset(dev_priv, false);
>  }
>  
> -#define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
> -
> -static const struct register_whitelist {
> -       i915_reg_t offset_ldw, offset_udw;
> -       uint32_t size;
> -       /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
> -       uint32_t gen_bitmask;
> -} whitelist[] = {
> -       { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
> -         .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
> -         .size = 8, .gen_bitmask = GEN_RANGE(4, 10) },
> -};
> +static const struct reg_whitelist {
> +       i915_reg_t offset_ldw;
> +       i915_reg_t offset_udw;
> +       unsigned long gen_mask;
> +       u8 size;
> +} reg_read_whitelist[] = {{
> +       .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
> +       .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
> +       .gen_mask = INTEL_GEN_MASK(4, 10),
> +       .size = 8
> +}};
>  
>  int i915_reg_read_ioctl(struct drm_device *dev,
>                         void *data, struct drm_file *file)
>  {
>         struct drm_i915_private *dev_priv = to_i915(dev);
>         struct drm_i915_reg_read *reg = data;
> -       struct register_whitelist const *entry = whitelist;
> -       unsigned size;
> -       i915_reg_t offset_ldw, offset_udw;
> -       int i, ret = 0;
> -
> -       for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
> -               if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
> -                   (INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask))
> +       struct reg_whitelist const *entry;
> +       unsigned flags;
> +       int remain;
> +       int ret = 0;
> +
> +       entry = reg_read_whitelist;
> +       remain = ARRAY_SIZE(reg_read_whitelist);
> +       while (remain) {
> +               GEM_BUG_ON(!is_power_of_2(entry->size));
> +               GEM_BUG_ON(entry->size > 8);
> +
> +               if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask &&
> +                   i915_mmio_reg_offset(entry->offset_ldw) ==
> +                           (reg->offset & -entry->size))
>                         break;
> +               entry++;
> +               remain--;
>         }
>  
> -       if (i == ARRAY_SIZE(whitelist))
> +       if (!remain)
>                 return -EINVAL;
>  
> -       /* We use the low bits to encode extra flags as the register should
> -        * be naturally aligned (and those that are not so aligned merely
> -        * limit the available flags for that register).
> -        */
> -       offset_ldw = entry->offset_ldw;
> -       offset_udw = entry->offset_udw;
> -       size = entry->size;
> -       size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
> +       flags = reg->offset & ~i915_mmio_reg_offset(entry->offset_ldw);

The mmio offset is not a mask, so ~not_a_mask is an interesting mix of
bits. So I still think ^ is clearer to extract the bits that differ in
the user offset. If you want to enunciate the interface clearly then
use flags = reg->offset & (entry->size - 1);

>  
>         intel_runtime_pm_get(dev_priv);
> -
> -       switch (size) {
> -       case 8 | 1:
> -               reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
> -               break;
> -       case 8:
> -               reg->val = I915_READ64(offset_ldw);
> -               break;
> -       case 4:
> -               reg->val = I915_READ(offset_ldw);
> -               break;
> -       case 2:
> -               reg->val = I915_READ16(offset_ldw);
> -               break;
> -       case 1:
> -               reg->val = I915_READ8(offset_ldw);
> -               break;
> -       default:
> +       if (entry->size == 8 && flags == I915_REG_READ_8B_WA)

* sheds a tear for the loss of aesthetic beauty ;)

With a second take on flags = offset & blah,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [v3,1/2] drm/i915: Introduce INTEL_GEN_MASK
  2017-09-11  7:57 [PATCH v3 1/2] drm/i915: Introduce INTEL_GEN_MASK Joonas Lahtinen
  2017-09-11  7:57 ` [PATCH v3 2/2] drm/i915: Simplify i915_reg_read_ioctl Joonas Lahtinen
  2017-09-11  8:24 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915: Introduce INTEL_GEN_MASK Patchwork
@ 2017-09-11  9:23 ` Patchwork
  2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-09-11  9:23 UTC (permalink / raw)
  To: Joonas Lahtinen; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v3,1/2] drm/i915: Introduce INTEL_GEN_MASK
URL   : https://patchwork.freedesktop.org/series/30103/
State : success

== Summary ==

Test perf:
        Subgroup polling:
                pass       -> FAIL       (shard-hsw) fdo#102252
Test kms_setmode:
        Subgroup basic:
                pass       -> FAIL       (shard-hsw) fdo#99912

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912

shard-hsw        total:2302 pass:1237 dwarn:0   dfail:0   fail:13  skip:1052 time:9451s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5633/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v3 2/2] drm/i915: Simplify i915_reg_read_ioctl
  2017-09-11  9:18   ` Chris Wilson
@ 2017-09-11  9:32     ` Chris Wilson
  0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2017-09-11  9:32 UTC (permalink / raw)
  To: Joonas Lahtinen,
	Intel graphics driver community testing & development
  Cc: Jani Nikula, Rodrigo Vivi

Quoting Chris Wilson (2017-09-11 10:18:51)
> Quoting Joonas Lahtinen (2017-09-11 08:57:19)
> > +       entry = reg_read_whitelist;
> > +       remain = ARRAY_SIZE(reg_read_whitelist);
> > +       while (remain) {
> > +               GEM_BUG_ON(!is_power_of_2(entry->size));
> > +               GEM_BUG_ON(entry->size > 8);
> > +
> > +               if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask &&
> > +                   i915_mmio_reg_offset(entry->offset_ldw) ==
> > +                           (reg->offset & -entry->size))
> >                         break;
> > +               entry++;
> > +               remain--;
> >         }
> >  
> > -       if (i == ARRAY_SIZE(whitelist))
> > +       if (!remain)
> >                 return -EINVAL;
> >  
> > -       /* We use the low bits to encode extra flags as the register should
> > -        * be naturally aligned (and those that are not so aligned merely
> > -        * limit the available flags for that register).
> > -        */
> > -       offset_ldw = entry->offset_ldw;
> > -       offset_udw = entry->offset_udw;
> > -       size = entry->size;
> > -       size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
> > +       flags = reg->offset & ~i915_mmio_reg_offset(entry->offset_ldw);
> 
> The mmio offset is not a mask, so ~not_a_mask is an interesting mix of
> bits. So I still think ^ is clearer to extract the bits that differ in
> the user offset. If you want to enunciate the interface clearly then
> use flags = reg->offset & (entry->size - 1);

With a GEM_BUG_ON(entry->offset_ldw & -entry->size); for sanity.
-Chris
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^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-09-11  9:33 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-09-11  7:57 [PATCH v3 1/2] drm/i915: Introduce INTEL_GEN_MASK Joonas Lahtinen
2017-09-11  7:57 ` [PATCH v3 2/2] drm/i915: Simplify i915_reg_read_ioctl Joonas Lahtinen
2017-09-11  9:18   ` Chris Wilson
2017-09-11  9:32     ` Chris Wilson
2017-09-11  8:24 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915: Introduce INTEL_GEN_MASK Patchwork
2017-09-11  9:23 ` ✓ Fi.CI.IGT: " Patchwork

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