From: David Wu <david.wu@rock-chips.com> To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Cc: huangtao@rock-chips.com, u-boot@lists.denx.de, zhangqing@rock-chips.com, linux-rockchip@lists.infradead.org, p.marczak@samsung.com, David Wu <david.wu@rock-chips.com>, andy.yan@rock-chips.com, chenjh@rock-chips.com Subject: [PATCH 3/8] clk: rockchip: Add rv1108 Saradc clock support Date: Wed, 13 Sep 2017 18:09:34 +0800 [thread overview] Message-ID: <1505297379-12638-4-git-send-email-david.wu@rock-chips.com> (raw) In-Reply-To: <1505297379-12638-1-git-send-email-david.wu@rock-chips.com> Signed-off-by: David Wu <david.wu@rock-chips.com> --- arch/arm/include/asm/arch-rockchip/cru_rv1108.h | 5 ++++ drivers/clk/rockchip/clk_rv1108.c | 35 +++++++++++++++++++++++++ include/dt-bindings/clock/rv1108-cru.h | 2 ++ 3 files changed, 42 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h index 2a1ae69..b134559 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h @@ -90,6 +90,11 @@ enum { CORE_CLK_DIV_SHIFT = 0, CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, + /* CLKSEL_CON22 */ + CLK_SARADC_DIV_CON_SHIFT= 0, + CLK_SARADC_DIV_CON_MASK = 0x3ff << CLK_SARADC_DIV_CON_SHIFT, + CLK_SARADC_DIV_CON_WIDTH= 10, + /* CLKSEL24_CON */ MAC_PLL_SEL_SHIFT = 12, MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index cf966bb..aa989c6 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -36,6 +36,11 @@ enum { #hz "Hz cannot be hit with PLL "\ "divisors on line " __stringify(__LINE__)); +static inline u32 extract_bits(u32 val, unsigned width, unsigned shift) +{ + return (val >> shift) & ((1 << width) - 1); +} + /* use interge mode*/ static inline int rv1108_pll_id(enum rk_clk_id clk_id) { @@ -130,6 +135,31 @@ static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate) return DIV_TO_RATE(pll_rate, div); } +static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[22]); + div = extract_bits(val, CLK_SARADC_DIV_CON_WIDTH, + CLK_SARADC_DIV_CON_SHIFT); + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz) +{ + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; + assert(src_clk_div < 128); + + rk_clrsetreg(&cru->clksel_con[22], + CLK_SARADC_DIV_CON_MASK, + src_clk_div << CLK_SARADC_DIV_CON_SHIFT); + + return rv1108_saradc_get_clk(cru); +} + static ulong rv1108_clk_get_rate(struct clk *clk) { struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); @@ -137,6 +167,8 @@ static ulong rv1108_clk_get_rate(struct clk *clk) switch (clk->id) { case 0 ... 63: return rkclk_pll_get_rate(priv->cru, clk->id); + case SCLK_SARADC: + return rv1108_saradc_get_clk(priv->cru); default: return -ENOENT; } @@ -154,6 +186,9 @@ static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SFC: new_rate = rv1108_sfc_set_clk(priv->cru, rate); break; + case SCLK_SARADC: + new_rate = rv1108_saradc_set_clk(priv->cru, rate); + break; default: return -ENOENT; } diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h index d2ad3bb..7defc6b 100644 --- a/include/dt-bindings/clock/rv1108-cru.h +++ b/include/dt-bindings/clock/rv1108-cru.h @@ -39,6 +39,7 @@ #define SCLK_MAC_TX 88 #define SCLK_MACREF 89 #define SCLK_MACREF_OUT 90 +#define SCLK_SARADC 91 /* aclk gates */ @@ -67,6 +68,7 @@ #define PCLK_TIMER 270 #define PCLK_PERI 271 #define PCLK_GMAC 272 +#define PCLK_SARADC 273 /* hclk gates */ #define HCLK_I2S0_8CH 320 -- 2.7.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
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From: David Wu <david.wu@rock-chips.com> To: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 3/8] clk: rockchip: Add rv1108 Saradc clock support Date: Wed, 13 Sep 2017 18:09:34 +0800 [thread overview] Message-ID: <1505297379-12638-4-git-send-email-david.wu@rock-chips.com> (raw) In-Reply-To: <1505297379-12638-1-git-send-email-david.wu@rock-chips.com> Signed-off-by: David Wu <david.wu@rock-chips.com> --- arch/arm/include/asm/arch-rockchip/cru_rv1108.h | 5 ++++ drivers/clk/rockchip/clk_rv1108.c | 35 +++++++++++++++++++++++++ include/dt-bindings/clock/rv1108-cru.h | 2 ++ 3 files changed, 42 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h index 2a1ae69..b134559 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h @@ -90,6 +90,11 @@ enum { CORE_CLK_DIV_SHIFT = 0, CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, + /* CLKSEL_CON22 */ + CLK_SARADC_DIV_CON_SHIFT= 0, + CLK_SARADC_DIV_CON_MASK = 0x3ff << CLK_SARADC_DIV_CON_SHIFT, + CLK_SARADC_DIV_CON_WIDTH= 10, + /* CLKSEL24_CON */ MAC_PLL_SEL_SHIFT = 12, MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index cf966bb..aa989c6 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -36,6 +36,11 @@ enum { #hz "Hz cannot be hit with PLL "\ "divisors on line " __stringify(__LINE__)); +static inline u32 extract_bits(u32 val, unsigned width, unsigned shift) +{ + return (val >> shift) & ((1 << width) - 1); +} + /* use interge mode*/ static inline int rv1108_pll_id(enum rk_clk_id clk_id) { @@ -130,6 +135,31 @@ static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate) return DIV_TO_RATE(pll_rate, div); } +static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[22]); + div = extract_bits(val, CLK_SARADC_DIV_CON_WIDTH, + CLK_SARADC_DIV_CON_SHIFT); + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz) +{ + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; + assert(src_clk_div < 128); + + rk_clrsetreg(&cru->clksel_con[22], + CLK_SARADC_DIV_CON_MASK, + src_clk_div << CLK_SARADC_DIV_CON_SHIFT); + + return rv1108_saradc_get_clk(cru); +} + static ulong rv1108_clk_get_rate(struct clk *clk) { struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); @@ -137,6 +167,8 @@ static ulong rv1108_clk_get_rate(struct clk *clk) switch (clk->id) { case 0 ... 63: return rkclk_pll_get_rate(priv->cru, clk->id); + case SCLK_SARADC: + return rv1108_saradc_get_clk(priv->cru); default: return -ENOENT; } @@ -154,6 +186,9 @@ static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SFC: new_rate = rv1108_sfc_set_clk(priv->cru, rate); break; + case SCLK_SARADC: + new_rate = rv1108_saradc_set_clk(priv->cru, rate); + break; default: return -ENOENT; } diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h index d2ad3bb..7defc6b 100644 --- a/include/dt-bindings/clock/rv1108-cru.h +++ b/include/dt-bindings/clock/rv1108-cru.h @@ -39,6 +39,7 @@ #define SCLK_MAC_TX 88 #define SCLK_MACREF 89 #define SCLK_MACREF_OUT 90 +#define SCLK_SARADC 91 /* aclk gates */ @@ -67,6 +68,7 @@ #define PCLK_TIMER 270 #define PCLK_PERI 271 #define PCLK_GMAC 272 +#define PCLK_SARADC 273 /* hclk gates */ #define HCLK_I2S0_8CH 320 -- 2.7.4
next prev parent reply other threads:[~2017-09-13 10:09 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-09-13 10:09 [PATCH 0/8] Add rockchip Saradc support David Wu 2017-09-13 10:09 ` [U-Boot] " David Wu [not found] ` <1505297379-12638-1-git-send-email-david.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2017-09-13 10:09 ` [PATCH 1/8] adc: Add driver for Rockchip Saradc David Wu 2017-09-13 10:09 ` [U-Boot] " David Wu [not found] ` <1505297379-12638-2-git-send-email-david.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2017-09-13 20:07 ` [U-Boot,1/8] " Philipp Tomsich 2017-09-13 20:07 ` [U-Boot] " Philipp Tomsich 2017-09-13 20:40 ` Philipp Tomsich 2017-09-13 20:40 ` [U-Boot] " Philipp Tomsich 2017-09-13 10:09 ` [PATCH 2/8] configs: rockchip: Enable the ROCKCHIP_SARADC config David Wu 2017-09-13 10:09 ` [U-Boot] " David Wu 2017-09-13 10:20 ` Dr. Philipp Tomsich 2017-09-13 10:20 ` [U-Boot] " Dr. Philipp Tomsich 2017-09-13 10:09 ` [PATCH 4/8] clk: rockchip: Add Saradc clock support for rk3288 David Wu 2017-09-13 10:09 ` [U-Boot] " David Wu 2017-09-13 10:24 ` Dr. Philipp Tomsich 2017-09-13 10:24 ` [U-Boot] " Dr. Philipp Tomsich 2017-09-13 10:26 ` Dr. Philipp Tomsich 2017-09-13 10:26 ` [U-Boot] " Dr. Philipp Tomsich [not found] ` <1505297379-12638-5-git-send-email-david.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2017-09-13 20:07 ` [U-Boot,4/8] " Philipp Tomsich 2017-09-13 20:07 ` [U-Boot] [U-Boot, 4/8] " Philipp Tomsich 2017-09-13 10:52 ` [PATCH 5/8] clk: rockchip: Add rk3328 Saradc clock support David Wu 2017-09-13 10:52 ` [U-Boot] " David Wu [not found] ` <1505299969-13329-1-git-send-email-david.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2017-09-13 20:07 ` [U-Boot,5/8] " Philipp Tomsich 2017-09-13 20:07 ` [U-Boot] [U-Boot, 5/8] " Philipp Tomsich 2017-09-13 20:44 ` Philipp Tomsich 2017-09-13 20:44 ` [U-Boot] " Philipp Tomsich 2017-09-13 10:09 ` David Wu [this message] 2017-09-13 10:09 ` [U-Boot] [PATCH 3/8] clk: rockchip: Add rv1108 " David Wu [not found] ` <1505297379-12638-4-git-send-email-david.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2017-09-13 20:07 ` [U-Boot,3/8] " Philipp Tomsich 2017-09-13 20:07 ` [U-Boot] [U-Boot, 3/8] " Philipp Tomsich 2017-09-13 20:45 ` Philipp Tomsich 2017-09-13 20:45 ` [U-Boot] " Philipp Tomsich 2017-09-13 11:32 ` [U-Boot] [PATCH 6/8] clk: rockchip: Add rk3368 " David Wu 2017-09-13 20:07 ` [U-Boot] [U-Boot, " Philipp Tomsich 2017-09-13 20:41 ` Philipp Tomsich 2017-09-13 20:44 ` Dr. Philipp Tomsich 2017-09-14 11:17 ` David.Wu 2017-09-14 14:55 ` Dr. Philipp Tomsich 2017-09-13 11:33 ` [U-Boot] [PATCH 7/8] clk: rockchip: Add rk3399 " David Wu 2017-09-13 20:07 ` [U-Boot] [U-Boot, " Philipp Tomsich 2017-09-13 20:42 ` Philipp Tomsich 2017-09-13 11:35 ` [U-Boot] [PATCH 8/8] arm: dts: rv1108: Add Saradc node at dtsi level David Wu 2017-09-13 20:07 ` [U-Boot] [U-Boot, " Philipp Tomsich 2017-09-13 20:08 ` Philipp Tomsich
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