From: Dave Martin <Dave.Martin@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: "Catalin Marinas" <catalin.marinas@arm.com>, "Will Deacon" <will.deacon@arm.com>, "Ard Biesheuvel" <ard.biesheuvel@linaro.org>, "Alex Bennée" <alex.bennee@linaro.org>, "Szabolcs Nagy" <szabolcs.nagy@arm.com>, "Richard Sandiford" <richard.sandiford@arm.com>, "Okamoto Takayuki" <tokamoto@jp.fujitsu.com>, kvmarm@lists.cs.columbia.edu, libc-alpha@sourceware.org, linux-arch@vger.kernel.org Subject: [PATCH v3 07/28] arm64/sve: Low-level SVE architectural state manipulation functions Date: Tue, 10 Oct 2017 19:38:24 +0100 [thread overview] Message-ID: <1507660725-7986-8-git-send-email-Dave.Martin@arm.com> (raw) In-Reply-To: <1507660725-7986-1-git-send-email-Dave.Martin@arm.com> Manipulating the SVE architectural state, including the vector and predicate registers, first-fault register and the vector length, requires the use of dedicated instructions added by SVE. This patch adds suitable assembly functions for saving and restoring the SVE registers and querying the vector length. Setting of the vector length is done as part of register restore. Since people building kernels may not all get an SVE-enabled toolchain for a while, this patch uses macros that generate explicit opcodes in place of assembler mnemonics. Signed-off-by: Dave Martin <Dave.Martin@arm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> --- arch/arm64/include/asm/fpsimd.h | 5 ++ arch/arm64/include/asm/fpsimdmacros.h | 148 ++++++++++++++++++++++++++++++++++ arch/arm64/kernel/entry-fpsimd.S | 17 ++++ 3 files changed, 170 insertions(+) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h index 410c481..026a7c7 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -67,6 +67,11 @@ extern void fpsimd_update_current_state(struct fpsimd_state *state); extern void fpsimd_flush_task_state(struct task_struct *target); +extern void sve_save_state(void *state, u32 *pfpsr); +extern void sve_load_state(void const *state, u32 const *pfpsr, + unsigned long vq_minus_1); +extern unsigned int sve_get_vl(void); + /* For use by EFI runtime services calls only */ extern void __efi_fpsimd_begin(void); extern void __efi_fpsimd_end(void); diff --git a/arch/arm64/include/asm/fpsimdmacros.h b/arch/arm64/include/asm/fpsimdmacros.h index 0f5fdd3..e050d76 100644 --- a/arch/arm64/include/asm/fpsimdmacros.h +++ b/arch/arm64/include/asm/fpsimdmacros.h @@ -75,3 +75,151 @@ ldr w\tmpnr, [\state, #16 * 2 + 4] fpsimd_restore_fpcr x\tmpnr, \state .endm + +/* Sanity-check macros to help avoid encoding garbage instructions */ + +.macro _check_general_reg nr + .if (\nr) < 0 || (\nr) > 30 + .error "Bad register number \nr." + .endif +.endm + +.macro _sve_check_zreg znr + .if (\znr) < 0 || (\znr) > 31 + .error "Bad Scalable Vector Extension vector register number \znr." + .endif +.endm + +.macro _sve_check_preg pnr + .if (\pnr) < 0 || (\pnr) > 15 + .error "Bad Scalable Vector Extension predicate register number \pnr." + .endif +.endm + +.macro _check_num n, min, max + .if (\n) < (\min) || (\n) > (\max) + .error "Number \n out of range [\min,\max]" + .endif +.endm + +/* SVE instruction encodings for non-SVE-capable assemblers */ + +/* STR (vector): STR Z\nz, [X\nxbase, #\offset, MUL VL] */ +.macro _sve_str_v nz, nxbase, offset=0 + _sve_check_zreg \nz + _check_general_reg \nxbase + _check_num (\offset), -0x100, 0xff + .inst 0xe5804000 \ + | (\nz) \ + | ((\nxbase) << 5) \ + | (((\offset) & 7) << 10) \ + | (((\offset) & 0x1f8) << 13) +.endm + +/* LDR (vector): LDR Z\nz, [X\nxbase, #\offset, MUL VL] */ +.macro _sve_ldr_v nz, nxbase, offset=0 + _sve_check_zreg \nz + _check_general_reg \nxbase + _check_num (\offset), -0x100, 0xff + .inst 0x85804000 \ + | (\nz) \ + | ((\nxbase) << 5) \ + | (((\offset) & 7) << 10) \ + | (((\offset) & 0x1f8) << 13) +.endm + +/* STR (predicate): STR P\np, [X\nxbase, #\offset, MUL VL] */ +.macro _sve_str_p np, nxbase, offset=0 + _sve_check_preg \np + _check_general_reg \nxbase + _check_num (\offset), -0x100, 0xff + .inst 0xe5800000 \ + | (\np) \ + | ((\nxbase) << 5) \ + | (((\offset) & 7) << 10) \ + | (((\offset) & 0x1f8) << 13) +.endm + +/* LDR (predicate): LDR P\np, [X\nxbase, #\offset, MUL VL] */ +.macro _sve_ldr_p np, nxbase, offset=0 + _sve_check_preg \np + _check_general_reg \nxbase + _check_num (\offset), -0x100, 0xff + .inst 0x85800000 \ + | (\np) \ + | ((\nxbase) << 5) \ + | (((\offset) & 7) << 10) \ + | (((\offset) & 0x1f8) << 13) +.endm + +/* RDVL X\nx, #\imm */ +.macro _sve_rdvl nx, imm + _check_general_reg \nx + _check_num (\imm), -0x20, 0x1f + .inst 0x04bf5000 \ + | (\nx) \ + | (((\imm) & 0x3f) << 5) +.endm + +/* RDFFR (unpredicated): RDFFR P\np.B */ +.macro _sve_rdffr np + _sve_check_preg \np + .inst 0x2519f000 \ + | (\np) +.endm + +/* WRFFR P\np.B */ +.macro _sve_wrffr np + _sve_check_preg \np + .inst 0x25289000 \ + | ((\np) << 5) +.endm + +.macro __for from:req, to:req + .if (\from) == (\to) + _for__body \from + .else + __for \from, (\from) + ((\to) - (\from)) / 2 + __for (\from) + ((\to) - (\from)) / 2 + 1, \to + .endif +.endm + +.macro _for var:req, from:req, to:req, insn:vararg + .macro _for__body \var:req + \insn + .endm + + __for \from, \to + + .purgem _for__body +.endm + +.macro sve_save nxbase, xpfpsr, nxtmp + _for n, 0, 31, _sve_str_v \n, \nxbase, \n - 34 + _for n, 0, 15, _sve_str_p \n, \nxbase, \n - 16 + _sve_rdffr 0 + _sve_str_p 0, \nxbase + _sve_ldr_p 0, \nxbase, -16 + + mrs x\nxtmp, fpsr + str w\nxtmp, [\xpfpsr] + mrs x\nxtmp, fpcr + str w\nxtmp, [\xpfpsr, #4] +.endm + +.macro sve_load nxbase, xpfpsr, xvqminus1, nxtmp + mrs_s x\nxtmp, SYS_ZCR_EL1 + bic x\nxtmp, x\nxtmp, ZCR_ELx_LEN_MASK + orr x\nxtmp, x\nxtmp, \xvqminus1 + msr_s SYS_ZCR_EL1, x\nxtmp // self-synchronising + + _for n, 0, 31, _sve_ldr_v \n, \nxbase, \n - 34 + _sve_ldr_p 0, \nxbase + _sve_wrffr 0 + _for n, 0, 15, _sve_ldr_p \n, \nxbase, \n - 16 + + ldr w\nxtmp, [\xpfpsr] + msr fpsr, x\nxtmp + ldr w\nxtmp, [\xpfpsr, #4] + msr fpcr, x\nxtmp +.endm diff --git a/arch/arm64/kernel/entry-fpsimd.S b/arch/arm64/kernel/entry-fpsimd.S index 6a27cd6..73f17bf 100644 --- a/arch/arm64/kernel/entry-fpsimd.S +++ b/arch/arm64/kernel/entry-fpsimd.S @@ -41,3 +41,20 @@ ENTRY(fpsimd_load_state) fpsimd_restore x0, 8 ret ENDPROC(fpsimd_load_state) + +#ifdef CONFIG_ARM64_SVE +ENTRY(sve_save_state) + sve_save 0, x1, 2 + ret +ENDPROC(sve_save_state) + +ENTRY(sve_load_state) + sve_load 0, x1, x2, 3 + ret +ENDPROC(sve_load_state) + +ENTRY(sve_get_vl) + _sve_rdvl 0, 1 + ret +ENDPROC(sve_get_vl) +#endif /* CONFIG_ARM64_SVE */ -- 2.1.4
WARNING: multiple messages have this Message-ID (diff)
From: Dave.Martin@arm.com (Dave Martin) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 07/28] arm64/sve: Low-level SVE architectural state manipulation functions Date: Tue, 10 Oct 2017 19:38:24 +0100 [thread overview] Message-ID: <1507660725-7986-8-git-send-email-Dave.Martin@arm.com> (raw) In-Reply-To: <1507660725-7986-1-git-send-email-Dave.Martin@arm.com> Manipulating the SVE architectural state, including the vector and predicate registers, first-fault register and the vector length, requires the use of dedicated instructions added by SVE. This patch adds suitable assembly functions for saving and restoring the SVE registers and querying the vector length. Setting of the vector length is done as part of register restore. Since people building kernels may not all get an SVE-enabled toolchain for a while, this patch uses macros that generate explicit opcodes in place of assembler mnemonics. Signed-off-by: Dave Martin <Dave.Martin@arm.com> Reviewed-by: Alex Benn?e <alex.bennee@linaro.org> --- arch/arm64/include/asm/fpsimd.h | 5 ++ arch/arm64/include/asm/fpsimdmacros.h | 148 ++++++++++++++++++++++++++++++++++ arch/arm64/kernel/entry-fpsimd.S | 17 ++++ 3 files changed, 170 insertions(+) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h index 410c481..026a7c7 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -67,6 +67,11 @@ extern void fpsimd_update_current_state(struct fpsimd_state *state); extern void fpsimd_flush_task_state(struct task_struct *target); +extern void sve_save_state(void *state, u32 *pfpsr); +extern void sve_load_state(void const *state, u32 const *pfpsr, + unsigned long vq_minus_1); +extern unsigned int sve_get_vl(void); + /* For use by EFI runtime services calls only */ extern void __efi_fpsimd_begin(void); extern void __efi_fpsimd_end(void); diff --git a/arch/arm64/include/asm/fpsimdmacros.h b/arch/arm64/include/asm/fpsimdmacros.h index 0f5fdd3..e050d76 100644 --- a/arch/arm64/include/asm/fpsimdmacros.h +++ b/arch/arm64/include/asm/fpsimdmacros.h @@ -75,3 +75,151 @@ ldr w\tmpnr, [\state, #16 * 2 + 4] fpsimd_restore_fpcr x\tmpnr, \state .endm + +/* Sanity-check macros to help avoid encoding garbage instructions */ + +.macro _check_general_reg nr + .if (\nr) < 0 || (\nr) > 30 + .error "Bad register number \nr." + .endif +.endm + +.macro _sve_check_zreg znr + .if (\znr) < 0 || (\znr) > 31 + .error "Bad Scalable Vector Extension vector register number \znr." + .endif +.endm + +.macro _sve_check_preg pnr + .if (\pnr) < 0 || (\pnr) > 15 + .error "Bad Scalable Vector Extension predicate register number \pnr." + .endif +.endm + +.macro _check_num n, min, max + .if (\n) < (\min) || (\n) > (\max) + .error "Number \n out of range [\min,\max]" + .endif +.endm + +/* SVE instruction encodings for non-SVE-capable assemblers */ + +/* STR (vector): STR Z\nz, [X\nxbase, #\offset, MUL VL] */ +.macro _sve_str_v nz, nxbase, offset=0 + _sve_check_zreg \nz + _check_general_reg \nxbase + _check_num (\offset), -0x100, 0xff + .inst 0xe5804000 \ + | (\nz) \ + | ((\nxbase) << 5) \ + | (((\offset) & 7) << 10) \ + | (((\offset) & 0x1f8) << 13) +.endm + +/* LDR (vector): LDR Z\nz, [X\nxbase, #\offset, MUL VL] */ +.macro _sve_ldr_v nz, nxbase, offset=0 + _sve_check_zreg \nz + _check_general_reg \nxbase + _check_num (\offset), -0x100, 0xff + .inst 0x85804000 \ + | (\nz) \ + | ((\nxbase) << 5) \ + | (((\offset) & 7) << 10) \ + | (((\offset) & 0x1f8) << 13) +.endm + +/* STR (predicate): STR P\np, [X\nxbase, #\offset, MUL VL] */ +.macro _sve_str_p np, nxbase, offset=0 + _sve_check_preg \np + _check_general_reg \nxbase + _check_num (\offset), -0x100, 0xff + .inst 0xe5800000 \ + | (\np) \ + | ((\nxbase) << 5) \ + | (((\offset) & 7) << 10) \ + | (((\offset) & 0x1f8) << 13) +.endm + +/* LDR (predicate): LDR P\np, [X\nxbase, #\offset, MUL VL] */ +.macro _sve_ldr_p np, nxbase, offset=0 + _sve_check_preg \np + _check_general_reg \nxbase + _check_num (\offset), -0x100, 0xff + .inst 0x85800000 \ + | (\np) \ + | ((\nxbase) << 5) \ + | (((\offset) & 7) << 10) \ + | (((\offset) & 0x1f8) << 13) +.endm + +/* RDVL X\nx, #\imm */ +.macro _sve_rdvl nx, imm + _check_general_reg \nx + _check_num (\imm), -0x20, 0x1f + .inst 0x04bf5000 \ + | (\nx) \ + | (((\imm) & 0x3f) << 5) +.endm + +/* RDFFR (unpredicated): RDFFR P\np.B */ +.macro _sve_rdffr np + _sve_check_preg \np + .inst 0x2519f000 \ + | (\np) +.endm + +/* WRFFR P\np.B */ +.macro _sve_wrffr np + _sve_check_preg \np + .inst 0x25289000 \ + | ((\np) << 5) +.endm + +.macro __for from:req, to:req + .if (\from) == (\to) + _for__body \from + .else + __for \from, (\from) + ((\to) - (\from)) / 2 + __for (\from) + ((\to) - (\from)) / 2 + 1, \to + .endif +.endm + +.macro _for var:req, from:req, to:req, insn:vararg + .macro _for__body \var:req + \insn + .endm + + __for \from, \to + + .purgem _for__body +.endm + +.macro sve_save nxbase, xpfpsr, nxtmp + _for n, 0, 31, _sve_str_v \n, \nxbase, \n - 34 + _for n, 0, 15, _sve_str_p \n, \nxbase, \n - 16 + _sve_rdffr 0 + _sve_str_p 0, \nxbase + _sve_ldr_p 0, \nxbase, -16 + + mrs x\nxtmp, fpsr + str w\nxtmp, [\xpfpsr] + mrs x\nxtmp, fpcr + str w\nxtmp, [\xpfpsr, #4] +.endm + +.macro sve_load nxbase, xpfpsr, xvqminus1, nxtmp + mrs_s x\nxtmp, SYS_ZCR_EL1 + bic x\nxtmp, x\nxtmp, ZCR_ELx_LEN_MASK + orr x\nxtmp, x\nxtmp, \xvqminus1 + msr_s SYS_ZCR_EL1, x\nxtmp // self-synchronising + + _for n, 0, 31, _sve_ldr_v \n, \nxbase, \n - 34 + _sve_ldr_p 0, \nxbase + _sve_wrffr 0 + _for n, 0, 15, _sve_ldr_p \n, \nxbase, \n - 16 + + ldr w\nxtmp, [\xpfpsr] + msr fpsr, x\nxtmp + ldr w\nxtmp, [\xpfpsr, #4] + msr fpcr, x\nxtmp +.endm diff --git a/arch/arm64/kernel/entry-fpsimd.S b/arch/arm64/kernel/entry-fpsimd.S index 6a27cd6..73f17bf 100644 --- a/arch/arm64/kernel/entry-fpsimd.S +++ b/arch/arm64/kernel/entry-fpsimd.S @@ -41,3 +41,20 @@ ENTRY(fpsimd_load_state) fpsimd_restore x0, 8 ret ENDPROC(fpsimd_load_state) + +#ifdef CONFIG_ARM64_SVE +ENTRY(sve_save_state) + sve_save 0, x1, 2 + ret +ENDPROC(sve_save_state) + +ENTRY(sve_load_state) + sve_load 0, x1, x2, 3 + ret +ENDPROC(sve_load_state) + +ENTRY(sve_get_vl) + _sve_rdvl 0, 1 + ret +ENDPROC(sve_get_vl) +#endif /* CONFIG_ARM64_SVE */ -- 2.1.4
next prev parent reply other threads:[~2017-10-10 18:39 UTC|newest] Thread overview: 253+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-10-10 18:38 [PATCH v3 00/28] ARM Scalable Vector Extension (SVE) Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` [PATCH v3 01/28] regset: Add support for dynamically sized regsets Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 14:14 ` Catalin Marinas 2017-10-11 14:14 ` Catalin Marinas 2017-10-11 14:14 ` Catalin Marinas 2017-10-11 14:45 ` Dave Martin 2017-10-11 14:45 ` Dave Martin 2017-10-11 14:45 ` Dave Martin 2017-10-11 14:45 ` Dave Martin 2017-10-10 18:38 ` [PATCH v3 02/28] arm64: KVM: Hide unsupported AArch64 CPU features from guests Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 14:14 ` Catalin Marinas 2017-10-11 14:14 ` Catalin Marinas 2017-10-11 16:21 ` Marc Zyngier 2017-10-11 16:21 ` Marc Zyngier 2017-10-17 13:51 ` Christoffer Dall 2017-10-17 13:51 ` Christoffer Dall 2017-10-17 14:08 ` Marc Zyngier 2017-10-17 14:08 ` Marc Zyngier 2017-10-18 13:20 ` Christoffer Dall 2017-10-18 13:20 ` Christoffer Dall 2017-10-18 14:45 ` Dave Martin 2017-10-18 14:45 ` Dave Martin 2017-10-18 19:19 ` Christoffer Dall 2017-10-18 19:19 ` Christoffer Dall 2017-10-10 18:38 ` [PATCH v3 03/28] arm64: efi: Add missing Kconfig dependency on KERNEL_MODE_NEON Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 14:16 ` Catalin Marinas 2017-10-11 14:16 ` Catalin Marinas 2017-10-11 14:35 ` Dave Martin 2017-10-11 14:35 ` Dave Martin 2017-10-10 18:38 ` [PATCH v3 04/28] arm64: Port deprecated instruction emulation to new sysctl interface Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 14:17 ` Catalin Marinas 2017-10-11 14:17 ` Catalin Marinas 2017-10-10 18:38 ` [PATCH v3 05/28] arm64: fpsimd: Simplify uses of {set, clear}_ti_thread_flag() Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` [PATCH v3 05/28] arm64: fpsimd: Simplify uses of {set,clear}_ti_thread_flag() Dave Martin 2017-10-11 14:19 ` [PATCH v3 05/28] arm64: fpsimd: Simplify uses of {set, clear}_ti_thread_flag() Catalin Marinas 2017-10-11 14:19 ` Catalin Marinas 2017-10-10 18:38 ` [PATCH v3 06/28] arm64/sve: System register and exception syndrome definitions Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 14:20 ` Catalin Marinas 2017-10-11 14:20 ` Catalin Marinas 2017-10-10 18:38 ` Dave Martin [this message] 2017-10-10 18:38 ` [PATCH v3 07/28] arm64/sve: Low-level SVE architectural state manipulation functions Dave Martin 2017-10-11 14:28 ` Catalin Marinas 2017-10-11 14:28 ` Catalin Marinas 2017-10-11 14:28 ` Catalin Marinas 2017-10-11 14:39 ` Dave Martin 2017-10-11 14:39 ` Dave Martin 2017-10-10 18:38 ` [PATCH v3 08/28] arm64/sve: Kconfig update and conditional compilation support Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 14:29 ` Catalin Marinas 2017-10-11 14:29 ` Catalin Marinas 2017-10-11 14:29 ` Catalin Marinas 2017-10-10 18:38 ` [PATCH v3 09/28] arm64/sve: Signal frame and context structure definition Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 14:29 ` Catalin Marinas 2017-10-11 14:29 ` Catalin Marinas 2017-10-11 14:29 ` Catalin Marinas 2017-10-10 18:38 ` [PATCH v3 10/28] arm64/sve: Low-level CPU setup Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 14:30 ` Catalin Marinas 2017-10-11 14:30 ` Catalin Marinas 2017-10-10 18:38 ` [PATCH v3 11/28] arm64/sve: Core task context handling Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 16:15 ` Catalin Marinas 2017-10-11 16:15 ` Catalin Marinas 2017-10-12 16:05 ` Dave Martin 2017-10-12 16:05 ` Dave Martin 2017-10-13 13:57 ` Catalin Marinas 2017-10-13 13:57 ` Catalin Marinas 2017-10-13 17:53 ` Dave Martin 2017-10-13 17:53 ` Dave Martin 2017-10-10 18:38 ` [PATCH v3 12/28] arm64/sve: Support vector length resetting for new processes Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 16:16 ` Catalin Marinas 2017-10-11 16:16 ` Catalin Marinas 2017-10-11 16:16 ` Catalin Marinas 2017-10-10 18:38 ` [PATCH v3 13/28] arm64/sve: Signal handling support Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 16:40 ` Catalin Marinas 2017-10-11 16:40 ` Catalin Marinas 2017-10-12 16:11 ` Dave Martin 2017-10-12 16:11 ` Dave Martin 2017-10-13 11:17 ` Catalin Marinas 2017-10-13 11:17 ` Catalin Marinas 2017-10-13 11:17 ` Catalin Marinas 2017-10-13 14:26 ` Dave Martin 2017-10-13 14:26 ` Dave Martin 2017-10-10 18:38 ` [PATCH v3 14/28] arm64/sve: Backend logic for setting the vector length Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 16:43 ` Catalin Marinas 2017-10-11 16:43 ` Catalin Marinas 2017-10-10 18:38 ` [PATCH v3 15/28] arm64: cpufeature: Move sys_caps_initialised declarations Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 16:50 ` Catalin Marinas 2017-10-11 16:50 ` Catalin Marinas 2017-10-10 18:38 ` [PATCH v3 16/28] arm64/sve: Probe SVE capabilities and usable vector lengths Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 16:55 ` Catalin Marinas 2017-10-11 16:55 ` Catalin Marinas 2017-10-12 12:56 ` Suzuki K Poulose 2017-10-12 12:56 ` Suzuki K Poulose 2017-10-16 15:46 ` Dave Martin 2017-10-16 15:46 ` Dave Martin 2017-10-16 16:27 ` Suzuki K Poulose 2017-10-16 16:27 ` Suzuki K Poulose 2017-10-16 16:27 ` Suzuki K Poulose 2017-10-16 16:44 ` Dave Martin 2017-10-16 16:44 ` Dave Martin 2017-10-16 16:47 ` Suzuki K Poulose 2017-10-16 16:47 ` Suzuki K Poulose 2017-10-16 16:47 ` Suzuki K Poulose 2017-10-16 16:55 ` Dave Martin 2017-10-16 16:55 ` Dave Martin 2017-10-16 16:58 ` Suzuki K Poulose 2017-10-16 16:58 ` Suzuki K Poulose 2017-10-10 18:38 ` [PATCH v3 17/28] arm64/sve: Preserve SVE registers around kernel-mode NEON use Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-12 10:15 ` Catalin Marinas 2017-10-12 10:15 ` Catalin Marinas 2017-10-10 18:38 ` [PATCH v3 18/28] arm64/sve: Preserve SVE registers around EFI runtime service calls Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-12 10:57 ` Catalin Marinas 2017-10-12 10:57 ` Catalin Marinas 2017-10-12 10:57 ` Catalin Marinas 2017-10-10 18:38 ` [PATCH v3 19/28] arm64/sve: ptrace and ELF coredump support Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-12 17:06 ` Catalin Marinas 2017-10-12 17:06 ` Catalin Marinas 2017-10-13 16:16 ` Dave Martin 2017-10-13 16:16 ` Dave Martin 2017-10-13 16:16 ` Dave Martin 2017-10-18 10:32 ` Catalin Marinas 2017-10-18 10:32 ` Catalin Marinas 2017-10-18 16:02 ` Dave Martin 2017-10-18 16:02 ` Dave Martin 2017-10-10 18:38 ` [PATCH v3 20/28] arm64/sve: Add prctl controls for userspace vector length management Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-12 17:11 ` Catalin Marinas 2017-10-12 17:11 ` Catalin Marinas 2017-10-10 18:38 ` [PATCH v3 21/28] arm64/sve: Add sysctl to set the default vector length for new processes Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-12 17:11 ` Catalin Marinas 2017-10-12 17:11 ` Catalin Marinas 2017-10-10 18:38 ` [PATCH v3 22/28] arm64/sve: KVM: Prevent guests from using SVE Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 16:28 ` Marc Zyngier 2017-10-11 16:28 ` Marc Zyngier 2017-10-12 11:04 ` Dave Martin 2017-10-12 11:04 ` Dave Martin 2017-10-12 11:28 ` Marc Zyngier 2017-10-12 11:28 ` Marc Zyngier 2017-10-13 14:15 ` Dave Martin 2017-10-13 14:15 ` Dave Martin 2017-10-13 14:21 ` Marc Zyngier 2017-10-13 14:21 ` Marc Zyngier 2017-10-13 16:47 ` Dave Martin 2017-10-13 16:47 ` Dave Martin 2017-10-12 17:13 ` Catalin Marinas 2017-10-12 17:13 ` Catalin Marinas 2017-10-17 11:50 ` Christoffer Dall 2017-10-17 11:50 ` Christoffer Dall 2017-10-17 11:50 ` Christoffer Dall 2017-10-17 11:50 ` Christoffer Dall 2017-10-17 14:31 ` Dave Martin 2017-10-17 14:31 ` Dave Martin 2017-10-18 13:23 ` Christoffer Dall 2017-10-18 13:23 ` Christoffer Dall 2017-10-18 15:00 ` Dave Martin 2017-10-18 15:00 ` Dave Martin 2017-10-18 19:22 ` Christoffer Dall 2017-10-18 19:22 ` Christoffer Dall 2017-10-10 18:38 ` [PATCH v3 23/28] arm64/sve: KVM: Treat guest SVE use as undefined instruction execution Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-12 17:13 ` Catalin Marinas 2017-10-12 17:13 ` Catalin Marinas 2017-10-17 13:58 ` Christoffer Dall 2017-10-17 13:58 ` Christoffer Dall 2017-10-10 18:38 ` [PATCH v3 24/28] arm64/sve: KVM: Hide SVE from CPU features exposed to guests Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 16:31 ` Marc Zyngier 2017-10-11 16:31 ` Marc Zyngier 2017-10-12 17:13 ` Catalin Marinas 2017-10-12 17:13 ` Catalin Marinas 2017-10-17 13:58 ` Christoffer Dall 2017-10-17 13:58 ` Christoffer Dall 2017-10-17 14:07 ` Dave Martin 2017-10-17 14:07 ` Dave Martin 2017-10-17 14:29 ` Marc Zyngier 2017-10-17 14:29 ` Marc Zyngier 2017-10-17 14:29 ` Marc Zyngier 2017-10-17 15:47 ` Dave Martin 2017-10-17 15:47 ` Dave Martin 2017-10-18 13:21 ` Christoffer Dall 2017-10-18 13:21 ` Christoffer Dall 2017-10-18 15:01 ` Dave Martin 2017-10-18 15:01 ` Dave Martin 2017-10-18 16:49 ` Christoffer Dall 2017-10-18 16:49 ` Christoffer Dall 2017-10-10 18:38 ` [PATCH v3 25/28] arm64/sve: Detect SVE and activate runtime support Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 17:11 ` Suzuki K Poulose 2017-10-11 17:11 ` Suzuki K Poulose 2017-10-12 17:14 ` Catalin Marinas 2017-10-12 17:14 ` Catalin Marinas 2017-10-12 17:14 ` Catalin Marinas 2017-10-10 18:38 ` [PATCH v3 26/28] arm64/sve: Add documentation Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 9:50 ` Szabolcs Nagy 2017-10-11 9:50 ` Szabolcs Nagy [not found] ` <59DDE958.4080605-5wv7dgnIgG8@public.gmane.org> 2017-10-11 11:08 ` Dave Martin 2017-10-11 11:08 ` Dave Martin 2017-10-11 11:08 ` Dave Martin [not found] ` <20171011110811.GB19485-M5GwZQ6tE7x5pKCnmE3YQBJ8xKzm50AiAL8bYrjMMd8@public.gmane.org> 2017-10-11 11:30 ` Szabolcs Nagy 2017-10-11 11:30 ` Szabolcs Nagy 2017-10-11 11:30 ` Szabolcs Nagy 2017-10-13 14:24 ` Catalin Marinas 2017-10-13 14:24 ` Catalin Marinas 2017-10-13 17:17 ` Dave Martin 2017-10-13 17:17 ` Dave Martin [not found] ` <20171013171758.GO19485-M5GwZQ6tE7x5pKCnmE3YQBJ8xKzm50AiAL8bYrjMMd8@public.gmane.org> 2017-10-18 9:32 ` Catalin Marinas 2017-10-18 9:32 ` Catalin Marinas 2017-10-18 9:32 ` Catalin Marinas [not found] ` <20171013142421.j32jzisukewxtosx-+1aNUgJU5qkijLcmloz0ER/iLCjYCKR+VpNB7YpNyf8@public.gmane.org> 2017-10-13 17:35 ` Dave Martin 2017-10-13 17:35 ` Dave Martin 2017-10-13 17:35 ` Dave Martin 2017-10-10 18:38 ` [RFC PATCH v3 27/28] arm64: signal: Report signal frame size to userspace via auxv Dave Martin 2017-10-10 18:38 ` Dave Martin 2017-10-11 10:19 ` Szabolcs Nagy 2017-10-11 10:19 ` Szabolcs Nagy 2017-10-11 13:14 ` Dave P Martin 2017-10-11 13:14 ` Dave P Martin 2017-10-10 18:38 ` [RFC PATCH v3 28/28] arm64/sve: signal: Include SVE when computing AT_MINSIGSTKSZ Dave Martin 2017-10-10 18:38 ` Dave Martin
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