[U-Boot] [PATCH v4 00/20] Add FPGA, SDRAM, SPL loadfs U-boot & booting to console

[U-Boot] [PATCH v4 00/20] Add FPGA, SDRAM, SPL loadfs U-boot & booting to console

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

This patchset adding FPGA and SDRAM drivers, enable fpga loadfs to program FPGA
, SPL loading U-boot and booting to U-boot console. This version mainly resolved
comments from Dinh and Marek in [v3].
This series is working on top of u-boot-socfpga.git -
 http://git.denx.de/u-boot-socfpga.git .

[v3]: https://www.mail-archive.com/u-boot at lists.denx.de/msg266981.html

v3 -> v4 changes:
-----------------
- Created and improving generic firmware loader
- Improved commit messages and header.
- Fixed typo.
- Changed unsigned long long to u64
- Changed printf to puts and error.

Patchset history
----------------
[v1]: https://www.mail-archive.com/u-boot at lists.denx.de/msg261831.html
[v2]: https://www.mail-archive.com/u-boot at lists.denx.de/msg265192.html

Tien Fong Chee (20):
  ARM: socfpga: Description on FPGA RBF properties at Arria 10 FPGA
    manager
  dts: Add FPGA bitstream properties to Arria 10 DTS
  arm: socfpga: Add Arria 10 SoCFPGA programming interface
  dts: Enable fpga-mgr node build for Arria 10 SPL
  fs: Enable generic filesystems interface support in SPL.
  common: Generic firmware loader for file system
  arm: socfpga: Fix with the correct polling on bit is set
  arm: socfpga: Add FPGA drivers for Arria 10 FPGA loadfs
  arm: socfpga: Rename the gen5 sdram driver to more specific name
  arm: socfpga: Add DRAM bank size initialization function
  arm: socfpga: Add DDR driver for Arria 10
  configs: Add DDR Kconfig support for Arria 10
  arm: socfpga: Enable SPL memory allocation
  arm: socfpga: Improve comments for Intel SoCFPGA program header
  arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10
  arm: socfpga: Adding clock frequency info for U-Boot
  arm: socfpga: Adding SoCFPGA info for both SPL and U-Boot
  arm: socfpga: Remove static declaration on spl_mmc_find_device
    function
  arm: socfpga: Enable DDR working
  arm: socfpga: Enable SPL booting U-boot

 arch/arm/dts/socfpga_arria10.dtsi                  |   6 +
 arch/arm/mach-socfpga/Kconfig                      |   1 +
 arch/arm/mach-socfpga/Makefile                     |   1 +
 arch/arm/mach-socfpga/board.c                      |  18 +
 arch/arm/mach-socfpga/fpga_manager_arria10.c       | 132 ++++
 arch/arm/mach-socfpga/include/mach/boot0.h         |  11 +-
 .../include/mach/fpga_manager_arria10.h            |  32 +
 arch/arm/mach-socfpga/include/mach/sdram.h         | 434 +-----------
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h |   2 +
 .../include/mach/{sdram.h => sdram_gen5.h}         |   6 +-
 arch/arm/mach-socfpga/misc_arria10.c               |   5 -
 arch/arm/mach-socfpga/spl.c                        |  54 ++
 cmd/fpga.c                                         |   2 +-
 common/Makefile                                    |   7 +-
 common/spl/Kconfig                                 |   8 +
 common/spl/spl_mmc.c                               |   2 +-
 common/splash_source.c                             | 110 +++-
 configs/socfpga_arria10_defconfig                  |  58 +-
 doc/README.SPL                                     |   1 +
 .../fpga/altera-socfpga-a10-fpga-mgr.txt           |  11 +
 drivers/ddr/altera/Kconfig                         |   2 +-
 drivers/ddr/altera/Makefile                        |   3 +-
 drivers/ddr/altera/sdram_arria10.c                 | 733 +++++++++++++++++++++
 drivers/ddr/altera/{sdram.c => sdram_gen5.c}       |   0
 drivers/fpga/altera.c                              |  40 +-
 drivers/fpga/fpga.c                                |   8 +
 drivers/fpga/socfpga_arria10.c                     | 337 +++++++++-
 fs/Makefile                                        |   1 +
 include/altera.h                                   |   6 +
 include/configs/socfpga_arria10_socdk.h            |   3 +
 include/configs/socfpga_common.h                   |  23 +-
 include/fpga.h                                     |   2 +
 include/spl.h                                      |   2 +
 include/splash.h                                   |   3 +
 34 files changed, 1575 insertions(+), 489 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/fpga_manager_arria10.c
 copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%)
 create mode 100644 drivers/ddr/altera/sdram_arria10.c
 rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)

-- 
2.2.0

[U-Boot] [PATCH v4 01/20] ARM: socfpga: Description on FPGA RBF properties at Arria 10 FPGA manager

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

This patch adds description on properties about location of FPGA RBFs are
stored, type and functionality of RBF used to configure FPGA.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
index 2fd8e7a..47c695b 100644
--- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
@@ -7,6 +7,14 @@ Required properties:
                - The second index is for writing FPGA configuration data.
 - resets     : Phandle and reset specifier for the device's reset.
 - clocks     : Clocks used by the device.
+- altr,bitstream_periph : FPGA peripheral raw binary file which is used to
+                          initialize FPGA IOs, PLL, IO48 and DDR.
+- altr,bitstream_core : FPGA core raw binary file contains FPGA design which is
+			used to program FPGA CRAM and ERAM.
+- altr,bitstream_devpart : Partition of flash device where bitstream files are
+		           stored.
+                           <dev[:part]> - dev is flash device number, part is
+					  flash device partition.
 
 Example:
 
@@ -16,4 +24,7 @@ Example:
 		       0xffcfe400 0x20>;
 		clocks = <&l4_mp_clk>;
 		resets = <&rst FPGAMGR_RESET>;
+		altr,bitstream_periph = "ghrd_10as066n2.periph.rbf.mkimage";
+		altr,bitstream_core = "ghrd_10as066n2.core.rbf.mkimage";
+		altr,bitstream_devpart = "0:1";
 	};
-- 
2.2.0

[U-Boot] [PATCH v4 02/20] dts: Add FPGA bitstream properties to Arria 10 DTS

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

These FPGA bitstream properties would help bootloader to understand
how to configure FPGA and where to look the FPGA RBF files during
booting.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/dts/socfpga_arria10.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index 377700d..aeb2be8 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -538,6 +538,11 @@
 			clocks = <&l4_mp_clk>;
 			resets = <&rst FPGAMGR_RESET>;
 			reset-names = "fpgamgr";
+			altr,bitstream_periph =
+			 "ghrd_10as066n2.periph.rbf.mkimage";
+			altr,bitstream_core =
+			 "ghrd_10as066n2.core.rbf.mkimage";
+			altr,bitstream_devpart = "0:1";
 		};
 
 		i2c0: i2c at ffc02200 {
-- 
2.2.0

[U-Boot] [PATCH v4 04/20] dts: Enable fpga-mgr node build for Arria 10 SPL

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

fpga-mgr node is required in SPL, because SPL needs information
from the node to configure FPGA in Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/dts/socfpga_arria10.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index aeb2be8..1848710 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -532,6 +532,7 @@
 		};
 
 		fpga_mgr: fpga-mgr at ffd03000 {
+			u-boot,dm-pre-reloc;
 			compatible = "altr,socfpga-a10-fpga-mgr";
 			reg = <0xffd03000 0x100
 			       0xffcfe400 0x20>;
-- 
2.2.0

[U-Boot] [PATCH v4 05/20] fs: Enable generic filesystems interface support in SPL.

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Enable generic filesystem interface drivers(fs.c and fat/) build
for SPL. This would allow generic filesystem being used in SPL.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 common/spl/Kconfig | 8 ++++++++
 doc/README.SPL     | 1 +
 fs/Makefile        | 1 +
 3 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index b05ec21..ca25a2d 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -304,6 +304,14 @@ config SPL_ETH_SUPPORT
 	  is required since the network stack uses a number of environment
 	  variables. See also SPL_NET_SUPPORT.
 
+config SPL_FS_GENERIC
+	bool "Support Generic filesystems interface driver"
+	help
+	  Enable support for generic filesystems interface with SPL. This
+	  permits U-Boot (or Linux in Falcon mode) to be loaded from a generic
+	  filesystem from within SPL. Support for the underlying block
+	  device (e.g. MMC or USB) must be enabled separately.
+
 config SPL_EXT_SUPPORT
 	bool "Support EXT filesystems"
 	help
diff --git a/doc/README.SPL b/doc/README.SPL
index 3ba313c..32628a4 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -55,6 +55,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o)
 CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o)
 CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
 CONFIG_SPL_EXT_SUPPORT
+CONFIG_SPL_FS_GENERIC (fs/fs.o fat/)
 CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
 CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
 CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
diff --git a/fs/Makefile b/fs/Makefile
index 5770f41..fdacac8 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -7,6 +7,7 @@
 #
 
 ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_FS_GENERIC) += fs.o fat/
 obj-$(CONFIG_SPL_FAT_SUPPORT) += fat/
 obj-$(CONFIG_SPL_EXT_SUPPORT) += ext4/
 else
-- 
2.2.0

[U-Boot] [PATCH v4 07/20] arm: socfpga: Fix with the correct polling on bit is set

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Commit 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10")
Polling on wrong cleared bit. Fix with correct polling on bit is set.

Fixes: 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10")

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 drivers/fpga/socfpga_arria10.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 5c1a68a..e076bda 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -112,13 +112,14 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void)
 	unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
 				ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
 
-	/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
-	 * timeout at 1000ms
+	/*
+	 * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
+	 * de-asserted, timeout at 1000ms
 	 */
 	return wait_for_bit(__func__,
 			    &fpga_manager_base->imgcfg_stat,
 			    mask,
-			    false, FPGA_TIMEOUT_MSEC, false);
+			    true, FPGA_TIMEOUT_MSEC, false);
 }
 
 static int wait_for_f2s_nstatus_pin(unsigned long value)
-- 
2.2.0

[U-Boot] [PATCH v4 09/20] arm: socfpga: Rename the gen5 sdram driver to more specific name

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Current sdram driver is only applied to gen5 device, hence it is better
to rename sdram driver to more specific name which is related to gen5
device.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/include/mach/sdram.h         | 432 +--------------------
 .../include/mach/{sdram.h => sdram_gen5.h}         |   6 +-
 drivers/ddr/altera/Makefile                        |   2 +-
 drivers/ddr/altera/{sdram.c => sdram_gen5.c}       |   0
 4 files changed, 7 insertions(+), 433 deletions(-)
 copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%)
 rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index b11228f..137e073 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -8,435 +8,9 @@
 
 #ifndef __ASSEMBLY__
 
-unsigned long sdram_calculate_size(void);
-int sdram_mmr_init_full(unsigned int sdr_phy_reg);
-int sdram_calibration_full(void);
-
-const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
-
-void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
-void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
-const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
-const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
-const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
-
-#define SDR_CTRLGRP_ADDRESS	(SOCFPGA_SDR_ADDRESS | 0x5000)
-
-struct socfpga_sdr_ctrl {
-	u32	ctrl_cfg;
-	u32	dram_timing1;
-	u32	dram_timing2;
-	u32	dram_timing3;
-	u32	dram_timing4;	/* 0x10 */
-	u32	lowpwr_timing;
-	u32	dram_odt;
-	u32	extratime1;
-	u32	__padding0[3];
-	u32	dram_addrw;	/* 0x2c */
-	u32	dram_if_width;	/* 0x30 */
-	u32	dram_dev_width;
-	u32	dram_sts;
-	u32	dram_intr;
-	u32	sbe_count;	/* 0x40 */
-	u32	dbe_count;
-	u32	err_addr;
-	u32	drop_count;
-	u32	drop_addr;	/* 0x50 */
-	u32	lowpwr_eq;
-	u32	lowpwr_ack;
-	u32	static_cfg;
-	u32	ctrl_width;	/* 0x60 */
-	u32	cport_width;
-	u32	cport_wmap;
-	u32	cport_rmap;
-	u32	rfifo_cmap;	/* 0x70 */
-	u32	wfifo_cmap;
-	u32	cport_rdwr;
-	u32	port_cfg;
-	u32	fpgaport_rst;	/* 0x80 */
-	u32	__padding1;
-	u32	fifo_cfg;
-	u32	protport_default;
-	u32	prot_rule_addr;	/* 0x90 */
-	u32	prot_rule_id;
-	u32	prot_rule_data;
-	u32	prot_rule_rdwr;
-	u32	__padding2[3];
-	u32	mp_priority;	/* 0xac */
-	u32	mp_weight0;	/* 0xb0 */
-	u32	mp_weight1;
-	u32	mp_weight2;
-	u32	mp_weight3;
-	u32	mp_pacing0;	/* 0xc0 */
-	u32	mp_pacing1;
-	u32	mp_pacing2;
-	u32	mp_pacing3;
-	u32	mp_threshold0;	/* 0xd0 */
-	u32	mp_threshold1;
-	u32	mp_threshold2;
-	u32	__padding3[29];
-	u32	phy_ctrl0;	/* 0x150 */
-	u32	phy_ctrl1;
-	u32	phy_ctrl2;
-};
-
-/* SDRAM configuration structure for the SPL. */
-struct socfpga_sdram_config {
-	u32	ctrl_cfg;
-	u32	dram_timing1;
-	u32	dram_timing2;
-	u32	dram_timing3;
-	u32	dram_timing4;
-	u32	lowpwr_timing;
-	u32	dram_odt;
-	u32	extratime1;
-	u32	dram_addrw;
-	u32	dram_if_width;
-	u32	dram_dev_width;
-	u32	dram_intr;
-	u32	lowpwr_eq;
-	u32	static_cfg;
-	u32	ctrl_width;
-	u32	cport_width;
-	u32	cport_wmap;
-	u32	cport_rmap;
-	u32	rfifo_cmap;
-	u32	wfifo_cmap;
-	u32	cport_rdwr;
-	u32	port_cfg;
-	u32	fpgaport_rst;
-	u32	fifo_cfg;
-	u32	mp_priority;
-	u32	mp_weight0;
-	u32	mp_weight1;
-	u32	mp_weight2;
-	u32	mp_weight3;
-	u32	mp_pacing0;
-	u32	mp_pacing1;
-	u32	mp_pacing2;
-	u32	mp_pacing3;
-	u32	mp_threshold0;
-	u32	mp_threshold1;
-	u32	mp_threshold2;
-	u32	phy_ctrl0;
-};
-
-struct socfpga_sdram_rw_mgr_config {
-	u8	activate_0_and_1;
-	u8	activate_0_and_1_wait1;
-	u8	activate_0_and_1_wait2;
-	u8	activate_1;
-	u8	clear_dqs_enable;
-	u8	guaranteed_read;
-	u8	guaranteed_read_cont;
-	u8	guaranteed_write;
-	u8	guaranteed_write_wait0;
-	u8	guaranteed_write_wait1;
-	u8	guaranteed_write_wait2;
-	u8	guaranteed_write_wait3;
-	u8	idle;
-	u8	idle_loop1;
-	u8	idle_loop2;
-	u8	init_reset_0_cke_0;
-	u8	init_reset_1_cke_0;
-	u8	lfsr_wr_rd_bank_0;
-	u8	lfsr_wr_rd_bank_0_data;
-	u8	lfsr_wr_rd_bank_0_dqs;
-	u8	lfsr_wr_rd_bank_0_nop;
-	u8	lfsr_wr_rd_bank_0_wait;
-	u8	lfsr_wr_rd_bank_0_wl_1;
-	u8	lfsr_wr_rd_dm_bank_0;
-	u8	lfsr_wr_rd_dm_bank_0_data;
-	u8	lfsr_wr_rd_dm_bank_0_dqs;
-	u8	lfsr_wr_rd_dm_bank_0_nop;
-	u8	lfsr_wr_rd_dm_bank_0_wait;
-	u8	lfsr_wr_rd_dm_bank_0_wl_1;
-	u8	mrs0_dll_reset;
-	u8	mrs0_dll_reset_mirr;
-	u8	mrs0_user;
-	u8	mrs0_user_mirr;
-	u8	mrs1;
-	u8	mrs1_mirr;
-	u8	mrs2;
-	u8	mrs2_mirr;
-	u8	mrs3;
-	u8	mrs3_mirr;
-	u8	precharge_all;
-	u8	read_b2b;
-	u8	read_b2b_wait1;
-	u8	read_b2b_wait2;
-	u8	refresh_all;
-	u8	rreturn;
-	u8	sgle_read;
-	u8	zqcl;
-
-	u8	true_mem_data_mask_width;
-	u8	mem_address_mirroring;
-	u8	mem_data_mask_width;
-	u8	mem_data_width;
-	u8	mem_dq_per_read_dqs;
-	u8	mem_dq_per_write_dqs;
-	u8	mem_if_read_dqs_width;
-	u8	mem_if_write_dqs_width;
-	u8	mem_number_of_cs_per_dimm;
-	u8	mem_number_of_ranks;
-	u8	mem_virtual_groups_per_read_dqs;
-	u8	mem_virtual_groups_per_write_dqs;
-};
-
-struct socfpga_sdram_io_config {
-	u16	delay_per_opa_tap;
-	u8	delay_per_dchain_tap;
-	u8	delay_per_dqs_en_dchain_tap;
-	u8	dll_chain_length;
-	u8	dqdqs_out_phase_max;
-	u8	dqs_en_delay_max;
-	u8	dqs_en_delay_offset;
-	u8	dqs_en_phase_max;
-	u8	dqs_in_delay_max;
-	u8	dqs_in_reserve;
-	u8	dqs_out_reserve;
-	u8	io_in_delay_max;
-	u8	io_out1_delay_max;
-	u8	io_out2_delay_max;
-	u8	shift_dqs_en_when_shift_dqs;
-};
-
-struct socfpga_sdram_misc_config {
-	u32	reg_file_init_seq_signature;
-	u8	afi_rate_ratio;
-	u8	calib_lfifo_offset;
-	u8	calib_vfifo_offset;
-	u8	enable_super_quick_calibration;
-	u8	max_latency_count_width;
-	u8	read_valid_fifo_size;
-	u8	tinit_cntr0_val;
-	u8	tinit_cntr1_val;
-	u8	tinit_cntr2_val;
-	u8	treset_cntr0_val;
-	u8	treset_cntr1_val;
-	u8	treset_cntr2_val;
-};
-
-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
-#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
-#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
-#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
-#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
-/* Register template: sdr::ctrlgrp::dramtiming1                            */
-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
-#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
-#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
-#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
-#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramtiming2                            */
-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
-#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
-#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
-#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
-#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
-/* Register template: sdr::ctrlgrp::dramtiming3                            */
-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
-#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
-#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramtiming4                            */
-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::lowpwrtiming                           */
-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
-/* Register template: sdr::ctrlgrp::dramaddrw                              */
-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
-/* Register template: sdr::ctrlgrp::dramifwidth                            */
-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
-/* Register template: sdr::ctrlgrp::dramdevwidth                           */
-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramintr                               */
-#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
-#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
-#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
-#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
-/* Register template: sdr::ctrlgrp::staticcfg                              */
-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
-#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
-#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
-/* Register template: sdr::ctrlgrp::ctrlwidth                              */
-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
-/* Register template: sdr::ctrlgrp::cportwidth                             */
-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
-/* Register template: sdr::ctrlgrp::cportwmap                              */
-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::cportrmap                              */
-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::rfifocmap                              */
-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::wfifocmap                              */
-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::cportrdwr                              */
-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
-/* Register template: sdr::ctrlgrp::portcfg                                */
-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::fifocfg                                */
-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::mppriority                             */
-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_0                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_1                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_2                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_3                   */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_0                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_1                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_2                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_3                   */
-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0       */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
-#define  \
-SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
-0xffffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1       */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
-0xffffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2       */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
-0x0000ffff
-/* Register template: sdr::ctrlgrp::remappriority                          */
-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0                     */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
- (((x) << 12) & 0xfffff000)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
- (((x) << 10) & 0x00000c00)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
- (((x) << 6) & 0x000000c0)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
- (((x) << 8) & 0x00000100)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
- (((x) << 9) & 0x00000200)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
- (((x) << 4) & 0x00000030)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
- (((x) << 2) & 0x0000000c)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
- (((x) << 0) & 0x00000003)
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1                     */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
- (((x) << 12) & 0xfffff000)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
- (((x) << 0) & 0x00000fff)
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2                     */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
- (((x) << 0) & 0x00000fff)
-/* Register template: sdr::ctrlgrp::dramodt                                */
-#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
-#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
-#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
-#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
-/* Field instance: sdr::ctrlgrp::dramsts                                   */
-#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
-#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
-/* Register template: sdr::ctrlgrp::extratime1                             */
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
-
-/* SDRAM width macro for configuration with ECC */
-#define SDRAM_WIDTH_32BIT_WITH_ECC	40
-#define SDRAM_WIDTH_16BIT_WITH_ECC	24
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/sdram_gen5.h>
+#endif
 
 #endif
 #endif /* _SDRAM_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
similarity index 99%
copy from arch/arm/mach-socfpga/include/mach/sdram.h
copy to arch/arm/mach-socfpga/include/mach/sdram_gen5.h
index b11228f..b16d776 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-#ifndef	_SDRAM_H_
-#define	_SDRAM_H_
+#ifndef	_SOCFPGA_SDRAM_GEN5_H_
+#define	_SOCFPGA_SDRAM_GEN5_H_
 
 #ifndef __ASSEMBLY__
 
@@ -439,4 +439,4 @@ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
 #define SDRAM_WIDTH_16BIT_WITH_ECC	24
 
 #endif
-#endif /* _SDRAM_H_ */
+#endif /* _SOCFPGA_SDRAM_GEN5_H_ */
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index bdd2872..ac4ab85 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -9,5 +9,5 @@
 #
 
 ifdef CONFIG_ALTERA_SDRAM
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
 endif
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram_gen5.c
similarity index 100%
rename from drivers/ddr/altera/sdram.c
rename to drivers/ddr/altera/sdram_gen5.c
-- 
2.2.0

[U-Boot] [PATCH v4 10/20] arm: socfpga: Add DRAM bank size initialization function

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Add function for both multiple DRAM bank and single DRAM bank size
initialization. This common functionality could be used by every single
SOCFPGA board.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Tested-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/board.c    | 7 +++++++
 include/configs/socfpga_common.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index a41d089..965f9dc 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -29,6 +29,13 @@ int board_init(void)
 	return 0;
 }
 
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
 #ifdef CONFIG_USB_GADGET
 struct dwc2_plat_otg_data socfpga_otg_data = {
 	.usb_gusbcfg	= 0x1417,
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 7b5417a..0d1cde6 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -43,6 +43,7 @@
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_1_SIZE
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TEXT_BASE		0x08000040
 #else
-- 
2.2.0

[U-Boot] [PATCH v4 11/20] arm: socfpga: Add DDR driver for Arria 10

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Add DDR driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/include/mach/sdram.h         |   2 +
 arch/arm/mach-socfpga/include/mach/sdram_arria10.h |   2 +
 drivers/ddr/altera/Makefile                        |   1 +
 drivers/ddr/altera/sdram_arria10.c                 | 733 +++++++++++++++++++++
 4 files changed, 738 insertions(+)
 create mode 100644 drivers/ddr/altera/sdram_arria10.c

diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index 137e073..33f830b 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -10,6 +10,8 @@
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include <asm/arch/sdram_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/sdram_arria10.h>
 #endif
 
 #endif
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
index 1d7b7c1..e7a2503 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
@@ -8,6 +8,7 @@
 #define _SOCFPGA_SDRAM_ARRIA10_H_
 
 #ifndef __ASSEMBLY__
+int ddr_calibration_sequence(void);
 
 struct socfpga_ecc_hmc {
 	u32 ip_rev_id;
@@ -204,6 +205,7 @@ struct socfpga_io48_mmr {
 	u32 niosreserve1;
 	u32 niosreserve2;
 };
+
 #endif /*__ASSEMBLY__*/
 
 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK		0x1F000000
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index ac4ab85..02f8b7c 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -10,4 +10,5 @@
 
 ifdef CONFIG_ALTERA_SDRAM
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
 endif
diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
new file mode 100644
index 0000000..7e12d14
--- /dev/null
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -0,0 +1,733 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <wait_bit.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/sdram.h>
+#include <linux/kernel.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_mmr_init(void);
+static u64 sdram_size_calc(void);
+
+/* FAWBANK - Number of Bank of a given device involved in the FAW period. */
+#define ARRIA10_SDR_ACTIVATE_FAWBANK	(0x1)
+
+#define ARRIA_DDR_CONFIG(A, B, C, R) \
+	(((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
+#define DDR_CONFIG_ELEMENTS	ARRAY_SIZE(ddr_config)
+#define DDR_REG_SEQ2CORE        0xFFD0507C
+#define DDR_REG_CORE2SEQ        0xFFD05078
+#define DDR_READ_LATENCY_DELAY	40
+#define DDR_SIZE_2GB_HEX	0x80000000
+#define DDR_MAX_TRIES		0x00100000
+
+#define IO48_MMR_DRAMSTS	0xFFCFA0EC
+#define IO48_MMR_NIOS2_RESERVE0	0xFFCFA110
+#define IO48_MMR_NIOS2_RESERVE1	0xFFCFA114
+#define IO48_MMR_NIOS2_RESERVE2	0xFFCFA118
+
+#define SEQ2CORE_MASK		0xF
+#define CORE2SEQ_INT_REQ	0xF
+#define SEQ2CORE_INT_RESP_BIT	3
+
+static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
+		(void *)SOCFPGA_SDR_ADDRESS;
+static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
+		(void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
+static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
+		*socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
+		(void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
+		(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
+		(void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
+
+/* The following are the supported configurations */
+static u32 ddr_config[] = {
+	/* Chip - Row - Bank - Column Style */
+	/* All Types */
+	ARRIA_DDR_CONFIG(0, 3, 10, 12),
+	ARRIA_DDR_CONFIG(0, 3, 10, 13),
+	ARRIA_DDR_CONFIG(0, 3, 10, 14),
+	ARRIA_DDR_CONFIG(0, 3, 10, 15),
+	ARRIA_DDR_CONFIG(0, 3, 10, 16),
+	ARRIA_DDR_CONFIG(0, 3, 10, 17),
+	/* LPDDR x16 */
+	ARRIA_DDR_CONFIG(0, 3, 11, 14),
+	ARRIA_DDR_CONFIG(0, 3, 11, 15),
+	ARRIA_DDR_CONFIG(0, 3, 11, 16),
+	ARRIA_DDR_CONFIG(0, 3, 12, 15),
+	/* DDR4 Only */
+	ARRIA_DDR_CONFIG(0, 4, 10, 14),
+	ARRIA_DDR_CONFIG(0, 4, 10, 15),
+	ARRIA_DDR_CONFIG(0, 4, 10, 16),
+	ARRIA_DDR_CONFIG(0, 4, 10, 17),	/* 14 */
+	/* Chip - Bank - Row - Column Style */
+	ARRIA_DDR_CONFIG(1, 3, 10, 12),
+	ARRIA_DDR_CONFIG(1, 3, 10, 13),
+	ARRIA_DDR_CONFIG(1, 3, 10, 14),
+	ARRIA_DDR_CONFIG(1, 3, 10, 15),
+	ARRIA_DDR_CONFIG(1, 3, 10, 16),
+	ARRIA_DDR_CONFIG(1, 3, 10, 17),
+	ARRIA_DDR_CONFIG(1, 3, 11, 14),
+	ARRIA_DDR_CONFIG(1, 3, 11, 15),
+	ARRIA_DDR_CONFIG(1, 3, 11, 16),
+	ARRIA_DDR_CONFIG(1, 3, 12, 15),
+	/* DDR4 Only */
+	ARRIA_DDR_CONFIG(1, 4, 10, 14),
+	ARRIA_DDR_CONFIG(1, 4, 10, 15),
+	ARRIA_DDR_CONFIG(1, 4, 10, 16),
+	ARRIA_DDR_CONFIG(1, 4, 10, 17),
+};
+
+static int match_ddr_conf(u32 ddr_conf)
+{
+	int i;
+
+	for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
+		if (ddr_conf == ddr_config[i])
+			return i;
+	}
+	return 0;
+}
+
+/* Check whether SDRAM is successfully Calibrated */
+static int is_sdram_cal_success(void)
+{
+	return readl(&socfpga_ecc_hmc_base->ddrcalstat);
+}
+
+static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
+{
+	u32 reg = readl(ereg);
+
+	return (reg & BIT(bit)) ? 1 : 0;
+}
+
+static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
+			   u32 expected, u32 timeout_usec)
+{
+	u32 tmr;
+
+	for (tmr = 0; tmr < timeout_usec; tmr += 100) {
+		udelay(100);
+		WATCHDOG_RESET();
+		if (ddr_get_bit(ereg, bit) == expected)
+			return 0;
+	}
+
+	return 1;
+}
+
+static int emif_clear(void)
+{
+	u32 i = DDR_MAX_TRIES;
+	u8 ret = 0;
+
+	writel(0, DDR_REG_CORE2SEQ);
+
+	do {
+		ret = !wait_for_bit(__func__, (u32 *)DDR_REG_SEQ2CORE,
+				   SEQ2CORE_MASK, 1, 50, 0);
+	} while (ret && (--i > 0));
+
+	return !i;
+}
+
+static int emif_reset(void)
+{
+	u32 c2s, s2c;
+
+	c2s = readl(DDR_REG_CORE2SEQ);
+	s2c = readl(DDR_REG_SEQ2CORE);
+
+	debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
+	     c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
+	     readl(IO48_MMR_NIOS2_RESERVE1),
+	     readl(IO48_MMR_NIOS2_RESERVE2),
+	     readl(IO48_MMR_DRAMSTS));
+
+	if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
+		debug("failed emif_clear()\n");
+		return -EPERM;
+	}
+
+	writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
+
+	if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
+		debug("emif_reset failed to see interrupt acknowledge\n");
+		return -EPERM;
+	} else {
+		debug("emif_reset interrupt acknowledged\n");
+	}
+
+	if (emif_clear()) {
+		debug("emif_clear() failed\n");
+		return -EPERM;
+	}
+	debug("emif_reset interrupt cleared\n");
+
+	debug("nr0=%08x nr1=%08x nr2=%08x\n",
+	     readl(IO48_MMR_NIOS2_RESERVE0),
+	     readl(IO48_MMR_NIOS2_RESERVE1),
+	     readl(IO48_MMR_NIOS2_RESERVE2));
+
+	return 0;
+}
+
+static int ddr_setup(void)
+{
+	int i, j, ddr_setup_complete = 0;
+
+	/* Try 3 times to do a calibration */
+	for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
+		WATCHDOG_RESET();
+
+		/* A delay to wait for calibration bit to set */
+		for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
+			mdelay(500);
+			ddr_setup_complete = is_sdram_cal_success();
+		}
+
+		if (!ddr_setup_complete)
+			if (emif_reset())
+				puts("Error: Failed to reset EMIF\n");
+	}
+
+	/* After 3 times trying calibration */
+	if (!ddr_setup_complete) {
+		puts("Error: Could Not Calibrate SDRAM\n");
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+/* Function to startup the SDRAM*/
+static int sdram_startup(void)
+{
+	/* Release NOC ddr scheduler from reset */
+	socfpga_reset_deassert_noc_ddr_scheduler();
+
+	/* Bringup the DDR (calibration and configuration) */
+	return ddr_setup();
+}
+
+static u64 sdram_size_calc(void)
+{
+	u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
+
+	u64 size = BIT(((dramaddrw &
+		IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
+		IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
+		((dramaddrw &
+		IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
+		IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
+		((dramaddrw &
+		IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
+		IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
+		((dramaddrw &
+		IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
+		IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
+		(dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
+
+	size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
+		       ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
+
+	debug("SDRAM size=%llu", size);
+
+	return size;
+}
+
+/* Function to initialize SDRAM MMR and NOC DDR scheduler*/
+static void sdram_mmr_init(void)
+{
+	u32 update_value, io48_value;
+	u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
+	u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
+	u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
+	u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
+	u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
+	u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
+	u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
+	u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
+	u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
+	u32 ddrioctl;
+
+	/*
+	 * Configure the DDR IO size [0xFFCFB008]
+	 * niosreserve0: Used to indicate DDR width &
+	 *	bit[7:0] = Number of data bits (0x20 for 32bit)
+	 *	bit[8]   = 1 if user-mode OCT is present
+	 *	bit[9]   = 1 if warm reset compiled into EMIF Cal Code
+	 *	bit[10]  = 1 if warm reset is on during generation in EMIF Cal
+	 * niosreserve1: IP ADCDS version encoded as 16 bit value
+	 *	bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
+	 *			    3=EAP, 4-6 are reserved)
+	 *	bit[5:3] = Service Pack # (e.g. 1)
+	 *	bit[9:6] = Minor Release #
+	 *	bit[14:10] = Major Release #
+	 */
+	if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {
+		update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
+		writel(((update_value & 0xFF) >> 5),
+		       &socfpga_ecc_hmc_base->ddrioctrl);
+	}
+
+	ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
+
+	/* Set the DDR Configuration [0xFFD12400] */
+	io48_value = ARRIA_DDR_CONFIG(
+			((ctrlcfg1 &
+			IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
+			IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
+			((dramaddrw &
+			IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
+			IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
+			((dramaddrw &
+			IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
+			IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
+			(dramaddrw &
+			IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
+			((dramaddrw &
+			IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
+			IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
+
+	update_value = match_ddr_conf(io48_value);
+	if (update_value)
+		writel(update_value,
+		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
+
+	/*
+	 * Configure DDR timing [0xFFD1240C]
+	 *  RDTOMISS = tRTP + tRP + tRCD - BL/2
+	 *  WRTOMISS = WL + tWR + tRP + tRCD and
+	 *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
+	 *  First part of equation is in memory clock units so divide by 2
+	 *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
+	 *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
+	 */
+	u32 ctrlcfg0_cfg_ctrl_burst_len =
+		(ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
+		IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
+
+	u32 caltim0_cfg_act_to_rdwr = caltim0 &
+		IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
+
+	u32 caltim0_cfg_act_to_act =
+		(caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
+		IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
+
+	u32 caltim0_cfg_act_to_act_db =
+		(caltim0 &
+		IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
+		IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
+
+	u32 caltim1_cfg_rd_to_wr =
+		(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
+		IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
+
+	u32 caltim1_cfg_rd_to_rd_dc =
+		(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
+		IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
+
+	u32 caltim1_cfg_rd_to_wr_dc =
+		(caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
+		IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
+
+	u32 caltim2_cfg_rd_to_pch =
+		(caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
+		IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
+
+	u32 caltim3_cfg_wr_to_rd =
+		(caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
+		IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
+
+	u32 caltim3_cfg_wr_to_rd_dc =
+		(caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
+		IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
+
+	u32 caltim4_cfg_pch_to_valid =
+		(caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
+		IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
+
+	u32 caltim9_cfg_4_act_to_act = caltim9 &
+		IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
+
+	update_value = (caltim2_cfg_rd_to_pch +  caltim4_cfg_pch_to_valid +
+			caltim0_cfg_act_to_rdwr -
+			(ctrlcfg0_cfg_ctrl_burst_len >> 2));
+
+	io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &
+		      ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
+		      (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
+		      /* Up to here was in memory cycles so divide by 2 */
+		      caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
+		      caltim4_cfg_pch_to_valid);
+
+	writel(((caltim0_cfg_act_to_act <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
+		(update_value <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
+		(io48_value <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
+		((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
+		(caltim1_cfg_rd_to_wr <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
+		(caltim3_cfg_wr_to_rd <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
+		(((ddrioctl == 1) ? 1 : 0) <<
+			ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
+		&socfpga_noc_ddr_scheduler_base->
+			ddr_t_main_scheduler_ddrtiming);
+
+	/* Configure DDR mode [0xFFD12410] [precharge = 0] */
+	writel(((ddrioctl ? 0 : 1) <<
+		ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
+		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
+
+	/* Configure the read latency [0xFFD12414] */
+	writel(((socfpga_io48_mmr_base->dramtiming0 &
+		ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
+		DDR_READ_LATENCY_DELAY,
+		&socfpga_noc_ddr_scheduler_base->
+			ddr_t_main_scheduler_readlatency);
+
+	/*
+	 * Configuring timing values concerning activate commands
+	 * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
+	 */
+	writel(((caltim0_cfg_act_to_act_db <<
+			ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
+		(caltim9_cfg_4_act_to_act <<
+			ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
+		(ARRIA10_SDR_ACTIVATE_FAWBANK <<
+			ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
+		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
+
+	/*
+	 * Configuring timing values concerning device to device data bus
+	 * ownership change [0xFFD1243C]
+	 */
+	writel(((caltim1_cfg_rd_to_rd_dc <<
+			ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
+		(caltim1_cfg_rd_to_wr_dc <<
+			ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
+		(caltim3_cfg_wr_to_rd_dc <<
+			ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
+		&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
+
+	/* Enable or disable the SDRAM ECC */
+	if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
+		setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+			     (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
+		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+			     (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
+		setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
+			     (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
+	} else {
+		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
+			     (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
+		clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
+			     (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
+			      ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
+	}
+}
+
+struct firewall_entry {
+	const char *prop_name;
+	const u32 cfg_addr;
+	const u32 en_addr;
+	const u32 en_bit;
+};
+#define FW_MPU_FPGA_ADDRESS \
+	((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
+	SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
+
+#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
+		(SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
+		offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
+
+#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
+		(SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
+		offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
+
+const struct firewall_entry firewall_table[] = {
+	{
+		"altr,mpu0",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
+	},
+	{
+		"altr,mpu1",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
+	},
+	{
+		"altr,mpu2",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
+	},
+	{
+		"altr,mpu3",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
+	},
+	{
+		"altr,l3-0",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
+	},
+	{
+		"altr,l3-1",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
+	},
+	{
+		"altr,l3-2",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
+	},
+	{
+		"altr,l3-3",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
+	},
+	{
+		"altr,l3-4",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
+	},
+	{
+		"altr,l3-5",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
+	},
+	{
+		"altr,l3-6",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
+	},
+	{
+		"altr,l3-7",
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
+		SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram0-0",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram0region0addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram0-1",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram0region1addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram0-2",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram0region2addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram0-3",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram0region3addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram1-0",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram1region0addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram1-1",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram1region1addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram1-2",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram1region2addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram1-3",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram1region3addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram2-0",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram2region0addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram2-1",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram2region1addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram2-2",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram2region2addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
+	},
+	{
+		"altr,fpga2sdram2-3",
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
+		(fpga2sdram2region3addr),
+		SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
+		ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
+	},
+
+};
+
+static int of_sdram_firewall_setup(const void *blob)
+{
+	int child, i, node;
+	u32 start_end[2];
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
+	if (node < 0)
+		return -ENXIO;
+
+	child = fdt_first_subnode(blob, node);
+	if (child < 0)
+		return -ENXIO;
+
+	/* set to default state */
+	writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
+	writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
+
+
+	for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
+		if (!fdtdec_get_int_array(blob, child,
+					  firewall_table[i].prop_name,
+					  start_end, 2)) {
+			writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
+				(start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
+				 firewall_table[i].cfg_addr);
+			setbits_le32(firewall_table[i].en_addr,
+				     firewall_table[i].en_bit);
+		}
+	}
+
+	return 0;
+}
+
+int ddr_calibration_sequence(void)
+{
+	WATCHDOG_RESET();
+
+	/* Check to see if SDRAM cal was success */
+	if (sdram_startup()) {
+		puts("DDRCAL: Failed\n");
+		return -EPERM;
+	}
+
+	puts("DDRCAL: Success\n");
+
+	WATCHDOG_RESET();
+
+	/* initialize the MMR register */
+	sdram_mmr_init();
+
+	/* assigning the SDRAM size */
+	u64 size = sdram_size_calc();
+
+	/*
+	 * If size is less than zero, this is invalid/weird value from
+	 * calculation, use default Config size.
+	 * Up to 2GB is supported, 2GB would be used if more than that.
+	 */
+	if (size <= 0)
+		gd->ram_size = PHYS_SDRAM_1_SIZE;
+	else if (DDR_SIZE_2GB_HEX <= size)
+		gd->ram_size = DDR_SIZE_2GB_HEX;
+	else
+		gd->ram_size = (u32)size;
+
+	/* setup the dram info within bd */
+	dram_init_banksize();
+
+	if (of_sdram_firewall_setup(gd->fdt_blob))
+		puts("FW: Error Configuring Firewall\n");
+
+	return 0;
+}
+
+void dram_bank_mmu_setup(int bank)
+{
+	bd_t *bd = gd->bd;
+	int	i;
+
+	debug("%s: bank: %d\n", __func__, bank);
+	for (i = bd->bi_dram[bank].start >> 20;
+	     i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
+	     i++) {
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+		set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+		set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
+	}
+
+	/* same as above but just that we would want cacheable for ocram too */
+	i = CONFIG_SYS_INIT_RAM_ADDR >> 20;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+	set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+	set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
+}
-- 
2.2.0

[U-Boot] [PATCH v4 12/20] configs: Add DDR Kconfig support for Arria 10

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

This patch enables DDR Kconfig support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
---
 arch/arm/mach-socfpga/Kconfig | 1 +
 drivers/ddr/altera/Kconfig    | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 45e5379..3e7a68a 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -40,6 +40,7 @@ config TARGET_SOCFPGA_ARRIA5
 config TARGET_SOCFPGA_ARRIA10
 	bool
 	select SPL_BOARD_INIT if SPL
+	select ALTERA_SDRAM
 
 config TARGET_SOCFPGA_CYCLONE5
 	bool
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 021ec1d..2b28a97 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,5 +1,5 @@
 config ALTERA_SDRAM
 	bool "SoCFPGA DDR SDRAM driver"
-	depends on TARGET_SOCFPGA_GEN5
+	depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	help
 	  Enable DDR SDRAM controller for the SoCFPGA devices.
-- 
2.2.0

[U-Boot] [PATCH v4 13/20] arm: socfpga: Enable SPL memory allocation

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Enable memory allocation in SPL for preparation to enable FAT
in SPL. Memory allocation is needed by FAT to work properly.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
---
 include/configs/socfpga_common.h | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 0d1cde6..218eb05 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -274,17 +274,33 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * SPL
  *
- * SRAM Memory layout:
+ * SRAM Memory layout for gen 5:
  *
  * 0xFFFF_0000 ...... Start of SRAM
  * 0xFFFF_xxxx ...... Top of stack (grows down)
  * 0xFFFF_yyyy ...... Malloc area
  * 0xFFFF_zzzz ...... Global Data
  * 0xFFFF_FF00 ...... End of SRAM
+ *
+ * SRAM Memory layout for Arria 10:
+ * 0xFFE0_0000 ...... Start of SRAM (bottom)
+ * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
+ * 0xFFEy_yyyy ...... Global Data
+ * 0xFFEz_zzzz ...... Malloc area (grows up to top)
+ * 0xFFE3_FFFF ...... End of SRAM (top)
  */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+/* SPL memory allocation configuration, this is for FAT implementation */
+#ifndef CONFIG_SYS_SPL_MALLOC_START
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00010000
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 CONFIG_SYS_SPL_MALLOC_SIZE + \
+					 CONFIG_SYS_INIT_RAM_ADDR)
+#endif
+#endif
 
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT
@@ -314,7 +330,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /*
  * Stack setup
  */
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SPL_STACK		CONFIG_SYS_SPL_MALLOC_START
+#endif
 
 /* Extra Environment */
 #ifndef CONFIG_SPL_BUILD
-- 
2.2.0

[U-Boot] [PATCH v4 14/20] arm: socfpga: Improve comments for Intel SoCFPGA program header

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Adding some details about size in bytes to each section.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
---
 arch/arm/mach-socfpga/include/mach/boot0.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h
index 22d9e7f..e06b548 100644
--- a/arch/arm/mach-socfpga/include/mach/boot0.h
+++ b/arch/arm/mach-socfpga/include/mach/boot0.h
@@ -11,8 +11,8 @@
 	.balignl 64,0xf33db33f;
 
 	.word	0x1337c0d3;	/* SoCFPGA preloader validation word */
-	.word	0xc01df00d;	/* Version, flags, length */
-	.word	0xcafec0d3;	/* Checksum, zero-pad */
+	.word	0xc01df00d;	/* Header length(2B),flags(1B),version(1B) */
+	.word	0xcafec0d3;	/* Simple checksum(2B),spare offset(2B) */
 	nop;
 
 	b reset;		/* SoCFPGA jumps here */
-- 
2.2.0

[U-Boot] [PATCH v4 15/20] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Enhance preloader header with both additional program length and program
entry offset attributes, which offset is relative to the start of program
header.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
---
 arch/arm/mach-socfpga/include/mach/boot0.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h
index e06b548..b21b871 100644
--- a/arch/arm/mach-socfpga/include/mach/boot0.h
+++ b/arch/arm/mach-socfpga/include/mach/boot0.h
@@ -12,6 +12,13 @@
 
 	.word	0x1337c0d3;	/* SoCFPGA preloader validation word */
 	.word	0xc01df00d;	/* Header length(2B),flags(1B),version(1B) */
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+	.word	0xfeedface;	/* Program length(4B) */
+	.word	0xf00dcafe;	/*
+				 * Program entry offset(4B),relative to
+				 * the start of program header
+				 */
+#endif
 	.word	0xcafec0d3;	/* Simple checksum(2B),spare offset(2B) */
 	nop;
 
-- 
2.2.0

[U-Boot] [PATCH v4 16/20] arm: socfpga: Adding clock frequency info for U-Boot

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Clock frequency info is required in U-Boot because info would be erased
when transition from SPL to U-Boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/board.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 965f9dc..8d3b515 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -8,7 +8,9 @@
 
 #include <common.h>
 #include <errno.h>
+#include <fdtdec.h>
 #include <asm/arch/reset_manager.h>
+#include <asm/arch/clock_manager.h>
 #include <asm/io.h>
 
 #include <usb.h>
@@ -26,6 +28,11 @@ int board_init(void)
 	/* Address of boot parameters for ATAG (if ATAG is used) */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+	/* configuring the clock based on handoff */
+	cm_basic_init(gd->fdt_blob);
+#endif
+
 	return 0;
 }
 
-- 
2.2.0

[U-Boot] [PATCH v4 17/20] arm: socfpga: Adding SoCFPGA info for both SPL and U-Boot

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

SoC FPGA info is required in both SPL and U-Boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/board.c        | 4 ++++
 arch/arm/mach-socfpga/misc_arria10.c | 5 -----
 arch/arm/mach-socfpga/spl.c          | 6 ++++++
 3 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 8d3b515..7beb347 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -11,6 +11,7 @@
 #include <fdtdec.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/clock_manager.h>
+#include <asm/arch/misc.h>
 #include <asm/io.h>
 
 #include <usb.h>
@@ -31,6 +32,9 @@ int board_init(void)
 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 	/* configuring the clock based on handoff */
 	cm_basic_init(gd->fdt_blob);
+
+	/* Add device descriptor to FPGA device table */
+	socfpga_fpga_add();
 #endif
 
 	return 0;
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index 9d751f6..8760ac9 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -94,11 +94,6 @@ int arch_early_init_r(void)
 	/* assert reset to all except L4WD0 and L4TIMER0 */
 	socfpga_per_reset_all();
 
-	/* configuring the clock based on handoff */
-	/* TODO: Add call to cm_basic_init() */
-
-	/* Add device descriptor to FPGA device table */
-	socfpga_fpga_add();
 	return 0;
 }
 #else
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 71bae82..aba116d 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -15,6 +15,7 @@
 #include <asm/arch/system_manager.h>
 #include <asm/arch/freeze_controller.h>
 #include <asm/arch/clock_manager.h>
+#include <asm/arch/misc.h>
 #include <asm/arch/scan_manager.h>
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>
@@ -208,6 +209,11 @@ void spl_board_init(void)
 
 	/* enable console uart printing */
 	preloader_console_init();
+
+	WATCHDOG_RESET();
+
+	/* Add device descriptor to FPGA device table */
+	socfpga_fpga_add();
 }
 
 void board_init_f(ulong dummy)
-- 
2.2.0

[U-Boot] [PATCH v4 18/20] arm: socfpga: Remove static declaration on spl_mmc_find_device function

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

This patch removes the static declation on spl_mmc_find_device_function
so this function is accessible by the caller from other file. This patch
is required for later patch.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 common/spl/spl_mmc.c | 2 +-
 include/spl.h        | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index b2cccc6..159443f 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -113,7 +113,7 @@ static int spl_mmc_get_device_index(u32 boot_device)
 	return -ENODEV;
 }
 
-static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
+int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
 {
 #if CONFIG_IS_ENABLED(DM_MMC)
 	struct udevice *dev;
diff --git a/include/spl.h b/include/spl.h
index ce4cf0a..e24433d 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -10,6 +10,7 @@
 /* Platform-specific defines */
 #include <linux/compiler.h>
 #include <asm/spl.h>
+#include <mmc.h>
 
 /* Value in r0 indicates we booted from U-Boot */
 #define UBOOT_NOT_LOADED_FROM_SPL	0x13578642
@@ -68,6 +69,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 void preloader_console_init(void);
 u32 spl_boot_device(void);
 u32 spl_boot_mode(const u32 boot_device);
+int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device);
 
 /**
  * spl_set_header_raw_uboot() - Set up a standard SPL image structure
-- 
2.2.0

[U-Boot] [PATCH v4 19/20] arm: socfpga: Enable DDR working

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

SPL configures DDR by programming peripheral raw binary file
and calibrating DDR.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/spl.c       | 48 +++++++++++++++++++++++++++++++++++++++
 configs/socfpga_arria10_defconfig | 15 +++++++++---
 2 files changed, 60 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index aba116d..4529b12 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -15,6 +15,7 @@
 #include <asm/arch/system_manager.h>
 #include <asm/arch/freeze_controller.h>
 #include <asm/arch/clock_manager.h>
+#include <asm/arch/fpga_manager.h>
 #include <asm/arch/misc.h>
 #include <asm/arch/scan_manager.h>
 #include <asm/arch/sdram.h>
@@ -22,6 +23,10 @@
 #include <asm/arch/nic301.h>
 #include <asm/sections.h>
 #include <fdtdec.h>
+#include <fat.h>
+#include <fs.h>
+#include <linux/ctype.h>
+#include <mmc.h>
 #include <watchdog.h>
 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include <asm/arch/pinmux.h>
@@ -29,6 +34,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define BSIZE	4096
+#define PERIPH_RBF	0
+
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -197,6 +205,12 @@ void board_init_f(ulong dummy)
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 void spl_board_init(void)
 {
+	int rval = 0;
+	int len = 0;
+	u32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);
+	struct spl_boot_device bootdev;
+	fpga_fs_info fpga_fsinfo;
+
 	/* configuring the clock based on handoff */
 	cm_basic_init(gd->fdt_blob);
 	WATCHDOG_RESET();
@@ -214,6 +228,40 @@ void spl_board_init(void)
 
 	/* Add device descriptor to FPGA device table */
 	socfpga_fpga_add();
+
+	bootdev.boot_device = spl_boot_device();
+
+	if (BOOT_DEVICE_MMC1 == bootdev.boot_device) {
+		struct mmc *mmc = NULL;
+		int err = 0;
+
+		spl_mmc_find_device(&mmc, bootdev.boot_device);
+
+		err = mmc_init(mmc);
+
+		if (err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+			error("spl: mmc init failed with error: %d\n", err);
+#endif
+			return;
+		}
+
+		fpga_fsinfo.interface = "mmc";
+		fpga_fsinfo.fstype = FS_TYPE_FAT;
+	}
+
+	fpga_fsinfo.filename = (char *)get_cff_filename(gd->fdt_blob,
+							 &len,
+							 PERIPH_RBF);
+
+	/* Program peripheral RBF */
+	rval = fpga_fsload(0, buffer, BSIZE, &fpga_fsinfo);
+
+	if (!rval) {
+		config_pins(gd->fdt_blob, "shared");
+
+		ddr_calibration_sequence();
+	}
 }
 
 void board_init_f(ulong dummy)
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 2db34b5..14adbd8 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -8,29 +8,38 @@ CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200"
 CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
 CONFIG_FIT=y
+CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_FIT=y
 CONFIG_SPL=y
 CONFIG_SPL_FPGA_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=32768
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
 CONFIG_DOS_PARTITION=y
-# CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_DOS_PARTITION=y
+CONFIG_SPL_FS_GENERIC=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
 CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_SPL_MMC_SUPPORT=y
-- 
2.2.0

[U-Boot] [PATCH v4 20/20] arm: socfpga: Enable SPL booting U-boot

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Enable SPL successfully boot to U-boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 configs/socfpga_arria10_defconfig | 41 ++++++++++++++++++++++++++++++++++-----
 1 file changed, 36 insertions(+), 5 deletions(-)

diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 14adbd8..5211b99 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -1,16 +1,18 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
 CONFIG_IDENT_STRING="socfpga_arria10"
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200"
 CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
 CONFIG_FIT=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_FIT=y
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
 CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_SPL_FAT_SUPPORT=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=32768
@@ -19,14 +21,22 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_CMD_PART=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SPL_DOS_PARTITION=y
 CONFIG_SPL_FS_GENERIC=y
 CONFIG_CMD_FAT=y
@@ -39,7 +49,28 @@ CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_DW=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="altera"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
-- 
2.2.0